FPGA-based adaptive frequency measurement device and test method

Abstract

The application aims to provide a FPGA-based adaptive frequency measurement device and test method with higher adaptability, multiple measurement ranges, improved measurement accuracy and controlled measurement time. The application comprises a high-speed voltage comparator, a FPGA frequency measurement module and an operation unit connected in sequence, the high-speed voltage comparator is connected to a measured signal, the high-speed voltage comparator converts the measured signal into a digital pulse, the FPGA frequency measurement module performs measurement counting to obtain a counting result of the measured signal and a reference clock counting result, and the operation unit calculates the frequency of the measured signal. The application is applied to the technical field of digital frequency measurement.

Description

Technical Field

[0001] This invention relates to the technical field of digital frequency measurement, and particularly to an FPGA-based adaptive frequency measurement device and testing method. Background Technology

[0002] There are three methods for digital frequency measurement: direct measurement, indirect measurement, and equal precision measurement.

[0003] The direct measurement method generates a gate signal by counting a reference clock. Within the gate signal time, the periods of the signal under test are counted, and the frequency of the signal under test is determined according to the ratio of the reference clock frequency, the number of reference clock cycles, and the number of periods of the signal under test. However, the direct measurement method, by timing and counting the signal under test using a reference clock, introduces a measurement error originating from ±1 period of the signal under test. The larger the period of the signal under test and the lower the frequency, the greater the error. Therefore, it is only suitable for high-frequency measurement scenarios.

[0004] The indirect measurement method involves counting a reference clock within one cycle of the signal being measured to calculate the period of the signal and thus determine its frequency. This method determines the signal period by counting the reference clock cycles within one cycle, and then converts this to the signal frequency. The measurement error arises from ±1 reference clock cycle. However, to ensure the accuracy of this method, the period of the signal being measured must be sufficiently large relative to the reference clock, thus limiting its applicability to low-frequency measurement scenarios.

[0005] The equal-precision measurement method generates a gate signal by counting the cycles of the signal under test. During the gate signal time, a reference clock is counted, and the frequency of the signal under test is calculated according to the proportional relationship between the reference clock frequency, the number of reference clock cycles, and the number of cycles of the signal under test. However, while the equal-precision method uses the signal under test for timing, counts the reference clock, and calculates the frequency according to a proportional relationship, the measurement error in each frequency band originates from ±1 reference clock cycle, ensuring equal precision across the entire frequency band. However, a reasonable count value for the number of cycles of the signal under test is required; otherwise, inaccurate measurement results or excessively long measurement times may still occur.

[0006] In digital frequency measurement technology, there are three main factors affecting digital frequency measurement: measurement range, measurement accuracy, and measurement time. The above three methods have limitations in measurement range or low measurement accuracy. Therefore, it is necessary to provide an FPGA-based adaptive frequency measurement device and testing method that is more adaptable, compatible with multiple measurement ranges, improves measurement accuracy, and allows for controllable measurement time. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide an FPGA-based adaptive frequency measurement device and test method that is more adaptable, compatible with multiple measurement ranges, can improve measurement accuracy, and can control measurement time.

[0008] The technical solution adopted in this invention is as follows: This invention includes a high-speed voltage comparator, an FPGA frequency measurement module, and a computing unit connected in sequence. The high-speed voltage comparator receives the signal under test and converts the signal under test into digital pulses. The FPGA frequency measurement module performs measurement and counting to obtain the counting result of the signal under test and the counting result of the reference clock. The computing unit calculates the frequency of the signal under test.

[0009] As can be seen from the above scheme, the FPGA-based adaptive frequency measurement device is applied to frequency measurement of wide-band signals, taking into account measurement range, measurement accuracy, and measurement time. It utilizes FPGA to achieve precise counting, analyzes the approximate frequency range of the measured signal, and sets appropriate measurement methods and times, thereby solving problems in traditional frequency measurement techniques. It is more adaptable, compatible with both low-frequency and high-frequency measurement scenarios, improves measurement accuracy, effectively controls measurement time, and adaptively selects and sets the measurement method and time.

[0010] In a preferred embodiment, the FPGA frequency measurement module includes a frequency prediction module, a frequency counting module, and a frequency output module connected in sequence. The frequency prediction module includes an edge detector, a prediction counter, a counting comparator, a low-frequency flag register, and a time setting register connected in sequence. The frequency counting module includes a timer counter, a first gate generator, a second gate generator, and a third gate generator connected in sequence. The second gate generator is connected to a measured signal counter, and the third gate generator is connected to a reference clock counter. The frequency output module includes a measured signal counting result register, a data selector, and a reference clock counting result register. The measured signal counter is connected to the measured signal counting result register, and the reference clock counter is connected to the reference clock counting result register via the data selector. Both the edge detector and the measured signal counter are connected to the measured signal.

[0011] A test method for an FPGA-based adaptive frequency measurement device, the test method comprising the following steps:

[0012] Step A: The high-speed voltage comparator converts the measured signal into a digital pulse of the same frequency and transmits it to the edge detector;

[0013] Step B: The edge detector detects a complete cycle of the measured signal. During this signal cycle, the prediction counter is enabled to count the reference clock. When a complete signal cycle ends, the count value of the prediction counter is sent to the count comparator. The count comparator outputs a comparison result by comparing the range of the count value, which is used to roughly determine the size of the measured signal cycle, that is, the frequency range.

[0014] Step C: The low-frequency flag register generates a low-frequency flag based on the size of the frequency range, thereby controlling whether the time setting register, the measured signal counter, and the reference clock counter are disabled.

[0015] Step D: The measured signal count result register outputs the measured signal count result S1; the reference clock count result register outputs the reference clock count result S2, and the reference clock frequency S3 is a known value. The arithmetic unit calculates the frequency f of the measured signal according to the measured signal count result S1, the reference clock count result S2, and the reference clock frequency S3. The frequency f of the measured signal = reference clock frequency S3 * measured signal count result S1 / reference clock count result S2.

[0016] The Step C includes the following sub-steps:

[0017] Step C1: When f < S3, which means the signal frequency is low enough, the low-frequency flag register generates a low-frequency flag. The time setting register, the count values of the measured signal counter, and the reference clock counter are all disabled, and the measured signal count result register is set to 1, and the count value of the prediction counter is transmitted to the reference clock count result register.

[0018] Step C2: When f > S3, which means the signal frequency is high enough, the value of the measured signal count result register is the count value of the measured signal counter, and the value of the reference clock count result register is the output value of the data selector. The output value of the data selector is determined by the comparison result of the count comparator.

[0019] Step C2.1: When the comparison result shows that the measured signal frequency is lower than the reference clock, the output value of the data selector is the count value of the reference clock counter, the value of the measured signal count result register is the count result of the second gate generator, and the value of the reference clock count result register is the count result of the third gate generator.

[0020] Step C2.2: When the frequency of the measured signal is higher than the reference clock, the output of the data selector is the measurement time count value of the timer counter, the value of the measured signal count result register is the count result of the second gate generator, and the value of the reference clock count result register is the count result of the first gate generator. Attached Figure Description

[0021] Figure 1 This is a system block diagram of the present invention;

[0022] Figure 2 This is a system block diagram of the FPGA frequency measurement module;

[0023] Figure 3 This is a signal graph of the present invention applied in a low-frequency measurement scenario;

[0024] Figure 4 This is a signal graph of the present invention applied in a high-frequency measurement scenario;

[0025] Figure 5 It is a signal graph obtained using the direct measurement method;

[0026] Figure 6 It is a signal graph obtained by using an indirect measurement method;

[0027] Figure 7 It is a signal graph obtained by using the equal precision measurement method. Detailed Implementation

[0028] like Figure 1 As shown, in this embodiment, the present invention includes a high-speed voltage comparator 1, an FPGA frequency measurement module 2, and an arithmetic unit 3 connected in sequence. The high-speed voltage comparator 1 receives the signal under test 4 and converts the signal under test 4 into digital pulses. The FPGA frequency measurement module 2 performs measurement counting to obtain the counting result of the signal under test 4 and the reference clock counting result. The arithmetic unit 3 calculates the frequency of the signal under test 4.

[0029] like Figure 2As shown, in this embodiment, the FPGA frequency measurement module 2 includes a frequency prediction module 21, a frequency counting module 22, and a frequency output module 23, which are connected in sequence. The frequency prediction module 21 includes an edge detector 211, a prediction counter 212, a counting comparator 213, a low-frequency flag register 214, and a time setting register 215, which are connected in sequence. The frequency counting module 22 includes a timer / counter 221, a first gate generator 222, a second gate generator 223, and a third gate generator 224, which are connected in sequence. The second gate generator 223 is connected to... There is a measured signal counter 225, the third gate generator 224 is connected to a reference clock counter 226, the frequency output module 23 includes a measured signal counting result register 231, a data selector 232, and a reference clock counting result register 233. The measured signal counter 225 is connected to the measured signal counting result register 231, and the reference clock counter 226 is connected to the reference clock counting result register 233 via the data selector 232. The edge detector 211 and the measured signal counter 225 are both connected to the measured signal 4.

[0030] In this embodiment, a test method for an FPGA-based adaptive frequency measurement device includes the following steps:

[0031] Step A: The high-speed voltage comparator 1 converts the measured signal 4 into a digital pulse of the same frequency and transmits it to the edge detector 211;

[0032] Step B: The edge detector 211 detects a complete cycle of the measured signal 4. During this signal cycle, the prediction counter 212 is enabled to start counting the reference clock. When a complete signal cycle ends, the count value of the prediction counter 212 is sent to the counting comparator 213. The counting comparator 213 outputs a comparison result by comparing the size range of the count value, which is used to roughly determine the size of the cycle of the measured signal 4, i.e., the frequency range.

[0033] Step C: The low-frequency flag register 214 generates a low-frequency flag based on the size of the frequency range, thereby controlling whether the time setting register 215, the measured signal counter 225, and the reference clock counter 226 are disabled.

[0034] Step D: The measured signal counting result register 231 outputs the measured signal counting result S1; the reference clock counting result register 233 outputs the reference clock counting result S2, and the reference clock frequency S3 is a known value;

[0035] The arithmetic unit 3 calculates the frequency f of the measured signal 4 based on the measured signal count result S1, the reference clock count result S2, and the reference clock frequency S3. The frequency f of the measured signal 4 is: reference clock frequency S3 * measured signal count result S1 / reference clock count result S2.

[0036] In this embodiment, step C includes the following sub-steps:

[0037] Step C1: When the comparison result shows that the count value is large enough, which means that the signal frequency is low enough, the low frequency flag register 214 will generate a low frequency flag, the time setting register 215, the count value of the measured signal counter 225 and the count value of the reference clock counter 226 will be disabled, the measured signal count result register 231 will be set to 1, and the count value of the prediction counter 212 will be transmitted to the reference clock count result register 233.

[0038] Step C2: When the comparison result shows that the count value is small enough, which means that the signal frequency is high enough, the value of the measured signal count result register 231 is the count value of the measured signal counter 225, and the value of the reference clock count result register 233 is the output value of the data selector 232. The output value of the data selector 232 is determined by the comparison result of the count comparator 213.

[0039] Step C2.1: When the comparison result shows that the frequency of the measured signal 4 is lower than the reference clock, the output value of the data selector 232 is the count value of the reference clock counter 226, the value of the measured signal count result register 231 is the count result of the second gate generator 223, and the value of the reference clock count result register 233 is the count result of the third gate generator 224.

[0040] Step C2.2: When the frequency of the measured signal 4 is higher than the reference clock, the output of the data selector 232 is the measurement time count value of the timer counter 221, the value of the measured signal count result register 231 is the count result of the second gate generator 223, and the value of the reference clock count result register 233 is the count result of the first gate generator 222.

[0041] like Figure 3As shown, in this embodiment, the time setting register 215 sets a reasonable measurement time based on the comparison result of the counter 213. The higher the frequency, the shorter the measurement time should be; the lower the frequency, the longer the measurement time should be. This drives the timer / counter 221 to time and perform further measurements. This process uses the indirect measurement method for low-frequency signals to complete the measurement in advance, while for high-frequency signals, an adaptive measurement time setting is used to control the measurement time.

[0042] In this embodiment, the timer / counter 221 uses a counting reference clock to time the measurement time. During the timing process, the first gate generator 222 is enabled to generate a gate signal A in the reference clock domain. Gate signal A is aligned with the reference clock. Gate signal A is synchronized to the second gate generator 223 to generate a gate signal B in the measured clock domain. Gate signal B is aligned with the measured signal. Gate signal B is synchronized to the third gate generator 224 to generate a gate signal C in the reference clock domain. Gate signal C is aligned with the reference clock.

[0043] like Figure 4 As shown, in this embodiment, gate signal A is a software gate for timing measurement, gate signal B is a software gate that generates ±1 deviation of the measured clock relative to gate signal A, and gate signal C is a software gate that generates ±1 deviation of the reference clock relative to gate signal B. During the activation of gate signals B and C, the measured signal counter 225 and the reference clock counter 226 are enabled to count the measured signal and the reference clock, respectively. After gate signals B and C are deactivated, the count values ​​of the measured signal counter 225 and the reference clock counter 226 are sent to the measured signal counting result register 231 and the data selector 232, respectively.

[0044] The value of the measured signal counting result register 231 is always the counting result under gate signal B. When the frequency of the measured signal is lower than the reference clock, the value of the measured signal counting result register 231 is the counting result of gate signal C. When the frequency of the measured signal is higher than the reference clock, the value of the reference clock counting result register 233 is the counting result of gate signal A, i.e., measurement time counting. When the frequency of the measured signal is lower, the measurement error is controlled from ±1 reference clock cycle, which is equivalent to the principle of equal precision measurement. When the frequency of the measured signal is higher, the measurement error is controlled from ±1 measured signal cycle, which is equivalent to the principle of direct measurement. In this process, the source of measurement error is adaptively controlled, further improving the measurement accuracy.

[0045] In this embodiment, the measured signal 4 includes analog signals such as sine waves and triangular waves.

[0046] In this embodiment, the test method of the FPGA-based adaptive frequency measurement device has a wider measurement range compared to the direct measurement method and the indirect measurement method; compared to the direct measurement method and the equal precision measurement method, it can fix the measurement error source of the entire frequency band to ±1 test signal or reference clock cycle, resulting in higher measurement accuracy; compared to the direct measurement method and the equal precision measurement method, which are prone to increased measurement error and problems such as excessively short or long measurement time caused by setting a gate signal of a certain length, its adaptive setting of the measurement time results in better performance and greater stability.

[0047] In this embodiment, the output of the computing unit 3 is transmitted to the host computer or the display screen through the communication interface, or it can be transmitted to the MCU for calculation and output through the AXI bus.

[0048] In this embodiment, the reference clock frequency is S3 (unit: MHz), and the predicted count value is pre_cnt.

[0049] pre_cnt == 0 (f > S3), measurement time set to 1ms;

[0050] pre_cnt <= S3(f >= 1MHz), measurement time set to 10ms;

[0051] pre_cnt <= S3*1000 (f >= 1KHz), measurement time set to 100ms;

[0052] pre_cnt <= S3*10000 (f >= 100Hz), measurement time set to 200ms;

[0053] Otherwise: if pre_cnt > S3*10000 (f< 100Hz), the count result of the measured signal is set to 1, and the count result of the reference clock is set to the value of pre_cnt.

Claims

1. An FPGA-based adaptive frequency measurement device, characterized in that: It includes a high-speed voltage comparator (1), an FPGA frequency measurement module (2), and an arithmetic unit (3) connected in sequence. The high-speed voltage comparator (1) is connected to the signal under test (4). The high-speed voltage comparator (1) converts the signal under test (4) into digital pulses. The FPGA frequency measurement module (2) performs measurement and counting to obtain the counting result of the signal under test (4) and the reference clock counting result. The arithmetic unit (3) calculates the frequency of the signal under test (4). The FPGA frequency measurement module (2) includes a frequency prediction module (21), a frequency counting module (22), and a frequency output module (23) connected in sequence. The frequency prediction module (21) includes an edge detector (211), a prediction counter (212), a counting comparator (213), a low-frequency flag register (214), and a time setting register (215) connected in sequence. The frequency counting module (22) includes a timer counter (221), a first gate generator (222), a second gate generator (223), and a third gate generator (224) connected in sequence. The second gate generator (223) is connected to a counter of the signal under test (225). The third gate generator (224) is connected to a reference clock counter (226). The frequency output module (23) includes a test signal counting result register (231), a data selector (232), and a reference clock counting result register (233). The test signal counter (225) is connected to the test signal counting result register (231) via a low-active enable power code buffer. The reference clock counter (226) is connected to the reference clock counting result register (233) via the data selector (232) and the low-active enable power code buffer in sequence. The edge detector (211) and the test signal counter (225) are both connected to the test signal (4). The prediction counter (212) is connected to the reference clock counting result register (233) via a high-active enable code buffer. The counting comparator (213) is connected to the time setting register (215) and the data selector (232). The set signal is connected to the measured signal counting result register (231) via a high-active enable code buffer. The time setting register (215) is connected to the timer counter (221). The timer counter (221) is connected to the data selector (232). The low-frequency flag register (214) is connected to the enable terminals of two low-active enable code buffers and two high-active enable code buffers, respectively.

2. A test method for the FPGA-based adaptive frequency measurement device as described in claim 1, characterized in that, The testing method includes the following steps: Step A: The high-speed voltage comparator (1) converts the measured signal (4) into a digital pulse of the same frequency and transmits it to the edge detector (211). Step B: The edge detector (211) detects a complete period of the measured signal (4). During this signal period, the prediction counter (212) is enabled to start counting the reference clock. When a complete signal period ends, the count value of the prediction counter (212) is sent to the counting comparator (213). The counting comparator (213) outputs a comparison result by comparing the size range of the count value, which is used to roughly determine the size of the period of the measured signal (4), i.e., the frequency range. Step C: The low-frequency flag register (214) generates a low-frequency flag based on the size of the frequency range, thereby controlling whether the time setting register (215), the measured signal counter (225), and the reference clock counter (226) are disabled. Step C includes the following sub-steps: Step C1: When the comparison result shows that the count value is large enough, which means that the signal frequency is low enough, the low frequency flag register (214) will generate a low frequency flag, the count value of the time setting register (215), the count value of the signal under test (225) and the count value of the reference clock counter (226) will be disabled, and the count result register (231) of the signal under test will be set to 1. The count value of the prediction counter (212) will be transmitted to the reference clock count result register (233). Step C2: When the comparison result shows that the count value is small enough, which means that the signal frequency is high enough, the value of the test signal count result register (231) is the count value of the test signal counter (225), the value of the reference clock count result register (233) is the output value of the data selector (232), and the output value of the data selector (232) is determined by the comparison result of the count comparator (213). Step C2.1: When the comparison result shows that the frequency of the measured signal (4) is lower than the reference clock, the output value of the data selector (232) is the count value of the reference clock counter (226), the value of the measured signal count result register (231) is the count result of the second gate generator (223), and the value of the reference clock count result register (233) is the count result of the third gate generator (224). Step C2.2: When the frequency of the measured signal (4) is higher than the reference clock, the output of the data selector (232) is the measurement time count value of the timer counter (221), the value of the measured signal count result register (231) is the count result of the second gate generator (223), and the value of the reference clock count result register (233) is the count result of the first gate generator (222). Step D: The measured signal counting result register (231) outputs the measured signal counting result S1; the reference clock counting result register (233) outputs the reference clock counting result S2, and the reference clock frequency S3 is a known value; the arithmetic unit (3) calculates the frequency f of the measured signal (4) based on the measured signal counting result S1, the reference clock counting result S2 and the reference clock frequency S3, and the frequency f of the measured signal (4) = reference clock frequency S3 * measured signal counting result S1 / reference clock counting result S2.

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