Current accuracy simulation test method, device, equipment and storage medium

Abstract

The present application discloses a current accuracy simulation test method, apparatus, device, and storage medium, relating to the field of computer technology. The method comprises: in response to detecting that a server mainboard is powered on, establishing interconnection with a chip to be tested; performing a current accuracy test on the chip to be tested to generate current accuracy test data; in response to detecting that the slope of the curve in the current accuracy test data is within a target standard range, simulating a current accuracy curve under the maximum value of the positive and negative accuracy deviation of the chip to be tested, and adjusting the current compensation value of the chip to be tested until the simulated current accuracy curve can meet the target standard. The present application can quickly debug the optimal firmware version to meet the Imon test of multiple return board stages as much as possible.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a current accuracy simulation test method, device, equipment and storage medium. Background Art

[0002] With the rapid growth and development of internet companies, server performance requirements are increasing, and so are the operational stability requirements for server systems. The hardware power supply design on the motherboard is crucial for ensuring stable motherboard operation. The solutions selected for these power supply designs are becoming increasingly integrated. The requirements for current accuracy are also increasing. Manufacturers have Imon (Iout monitor, current accuracy detection) testing requirements for the CPU (Central Processing Unit) and Memory (Memory) power supply VR (Voltage Regulation), and corresponding specifications (Specifications) for current accuracy detection. Imon verification compares the actual current at the VR load end with the current value detected by the VR chip to determine whether the difference meets the corresponding specifications. An Imon curve that is too high or too low can affect CPU performance.

[0003] Currently, when performing IMON testing on each VR group on a server motherboard, the test results are checked to see if they meet the corresponding specifications. A project involves multiple retests. For a single board within a project, if the chip itself has poor precision, the optimal firmware version cannot be guaranteed. Consequently, when testing multiple boards with the same VR and firmware version, some boards may pass IMON testing while others fail. For example, due to inherent chip current tolerances, a VR firmware version that passed IMON testing on one version may fail on the next version. This necessitates re-debugging and re-testing until a VR firmware version that passes both versions is found. This results in the need to re-debug and re-verify firmware versions in multiple retests, which is time-consuming, labor-intensive, and leads to costly repeated verification. Therefore, how to quickly debug the optimal firmware version to meet IMON testing requirements across multiple retests is a pressing technical challenge. Summary of the Invention

[0004] In order to solve at least one of the problems mentioned in the above background technology, the present application provides a current accuracy simulation test method, device, equipment and storage medium, which can quickly debug the optimal firmware version to meet the Imon test of multiple return board stages as much as possible.

[0005] The specific technical solutions provided in the embodiments of this application are as follows:

[0006] In a first aspect, a current accuracy simulation test method is provided, which is applied to a test terminal and includes:

[0007] In response to detecting that the server mainboard is powered on, establishing interconnection with the chip under test;

[0008] Performing a current accuracy test on the chip to be tested to generate current accuracy test data;

[0009] In response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, a current accuracy curve is simulated under the maximum positive and negative accuracy deviation of the chip to be tested, and the current compensation value of the chip to be tested is adjusted until the simulated current accuracy curve can meet the target standard.

[0010] Furthermore, the method further comprises:

[0011] In response to detecting that the slope of the curve in the current accuracy test data is not within a target standard range, the current gain of the chip to be tested is adjusted until the adjusted slope of the curve meets the target standard range.

[0012] Furthermore, in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, simulating the current accuracy curve of the chip under test under the maximum positive and negative accuracy deviation, and adjusting the current compensation value of the chip under test until the simulated current accuracy curve can meet the target standard, including:

[0013] In response to detecting that the slope of the curve in the current accuracy test data is within a target standard range, simulating a first current accuracy curve of the chip under test under a return-to-zero current accuracy detection curve model;

[0014] In response to detecting that the first current accuracy curve meets the target standard, simulating a second current accuracy curve under the condition of maximum positive and negative accuracy deviation of the chip under test based on the zero-return current accuracy detection curve model, and adjusting the current compensation value of the chip under test until the simulated second current accuracy curve can meet the target standard;

[0015] The zero current accuracy detection curve model is used to simulate a current accuracy curve of the chip under test that adjusts the current deviation to zero when the current load is zero ampere.

[0016] Furthermore, in response to detecting that the slope of the curve in the current accuracy test data is within a target standard range, simulating a first current accuracy curve of the chip under test under a return-to-zero current accuracy detection curve model includes:

[0017] In response to detecting that the slope of the curve in the current accuracy test data is within a target standard range, adjusting the current compensation value of the chip under test and running a current accuracy detection test until the tested current accuracy curve as a whole meets the target standard;

[0018] Input the accuracy specification of the chip to be tested, and record the current deviation of the chip to be tested under a current load of zero ampere;

[0019] A current accuracy curve of the chip under test adjusting the current deviation to zero under a zero ampere current load condition is simulated as a first current accuracy curve of the chip under test under the zero current accuracy detection curve model.

[0020] Furthermore, the method further comprises:

[0021] In response to detecting that the first current accuracy curve does not meet the target standard, the code of the chip under test is adjusted according to the current accuracy simulation deviation until the first current accuracy curve meets the target standard.

[0022] Furthermore, the adjusting the current compensation value of the chip to be tested until the simulated second current accuracy curve can meet the target standard also includes:

[0023] The current compensation value of the chip under test is adjusted and the current accuracy detection test is re-run until the tested current accuracy curve as a whole meets the target standard and the simulated second current accuracy curves all meet the target standard.

[0024] Furthermore, in response to detecting that the server mainboard is powered on, establishing interconnection with the chip to be tested includes:

[0025] In response to detecting that the server mainboard is powered on, matching the chip to be tested through chip addressing;

[0026] Establish interconnection with the chip to be tested through Python.

[0027] In a second aspect, a current accuracy simulation test device is provided, the device comprising:

[0028] A communication module, configured to establish an interconnection with the chip under test in response to detecting that the server mainboard is powered on;

[0029] A testing module, configured to perform a current accuracy test on the chip to be tested and generate current accuracy test data;

[0030] A simulation module is used to simulate the current accuracy curve of the chip under test under the maximum positive and negative accuracy deviation in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, and adjust the current compensation value of the chip under test until the simulated current accuracy curve can meet the target standard.

[0031] According to a third aspect, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the current accuracy simulation test method when executing the computer program.

[0032] In a fourth aspect, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer-executable instructions are used to execute the current accuracy simulation test method.

[0033] The embodiments of the present application have the following beneficial effects:

[0034] The embodiments of the present application provide a current accuracy simulation test method, apparatus, equipment, and storage medium, which can simulate the maximum positive and negative accuracy deviation of the chip under test, that is, the worst-case scenario Imon, and can debug the optimal VRFW of the chip under test in the first test. At the same time, it is ensured that subsequent return boards can pass the Imon test, avoiding a large amount of repeated verification, saving manpower and material resources, and saving time costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0036] Figure 1 The following is a general flow chart of the current accuracy simulation test method provided by an embodiment of the present application;

[0037] Figure 2 A specific flow chart of a current accuracy simulation test method according to an embodiment of the present application is shown;

[0038] Figure 3 A schematic structural diagram of a current accuracy simulation test device provided in an embodiment of the present application is shown;

[0039] Figure 4 An exemplary system is shown that can be used to implement the various embodiments described in this application. DETAILED DESCRIPTION

[0040] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] It should be understood that in the description of this application, unless the context clearly requires otherwise, words such as "include", "comprises", and the like throughout the specification and claims should be interpreted as inclusive rather than exclusive or exhaustive; that is, as "including but not limited to".

[0042] It should also be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0043] Example 1

[0044] This application provides a current accuracy simulation test method, which is applied to the test end. Figure 1 , methods include:

[0045] S1, in response to detecting that the server mainboard is powered on, establishing interconnection with the chip under test;

[0046] S2. Perform current accuracy test on the chip to be tested and generate current accuracy test data;

[0047] S3. In response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, a current accuracy curve is simulated under the maximum positive and negative accuracy deviation of the chip under test, and the current compensation value of the chip under test is adjusted until the simulated current accuracy curve can meet the target standard.

[0048] Specifically, the Imon test analysis found that for the same project, the main reason for the inconsistent Imon test results of multiple boards with the same solution is related to the reference current of the chip under test, and the reference current is determined by the accuracy of the chip. The inconsistent accuracy of each chip will lead to differences in the test results. In order to avoid repeated debugging due to inconsistent chip accuracy, the optimal VRFW can be debugged in the first test, and at the same time, to ensure that the subsequent return boards can pass the Imon test, it is necessary to simulate the worst-case scenario Imon, that is, the maximum positive and negative accuracy deviation of the above-mentioned chip under test. If the current accuracy curve (Imon curve) under the maximum positive and negative accuracy deviation of the chip under test can meet the target standard (such as IntelSpec), then the optimal VRFW can be debugged, thereby avoiding repeated debugging, thereby improving work efficiency and reducing manpower and material resources. The above-mentioned test end can be a PC or a client. First, it is necessary to establish an interconnection with the chip under test on the motherboard so that the test can be performed on the test end. For example, you can first build the Imon test environment, install Gen5, connect the Imon simulation control board, and power on the server motherboard. After the server motherboard is powered on, it is necessary to establish an interconnection with the chip to be tested. The chip to be tested can be found and interconnected through the Imon simulation module and the Gen5 control interface. Then, the current accuracy test (Imon test) can be performed on the chip to be tested through Gen5, current accuracy test data can be generated, the test report can be automatically captured, and compared with the target standard. It can be compared with the middle curve of the target standard (such as IntelSpec) to detect whether it is within the target standard range. If it is detected that the slope of the curve in the current accuracy test data is within the target standard range, it is necessary to simulate the current accuracy curve under the maximum positive and negative accuracy deviation of the chip to be tested, and adjust the current compensation value of the chip to be tested until all simulated current accuracy curves can meet the target standard (such as IntelSpec). By adopting such technical means, it can be guaranteed that the optimal VRFW (firmware version) can be debugged in the first test, and at the same time, it can be guaranteed that the subsequent return board cards can pass the Imon test, avoiding a lot of repeated verification, saving manpower and material resources, and saving time and cost.

[0049] The following will be combined with the Figure 2 For further explanation:

[0050] In some embodiments, S1 comprises:

[0051] S11, in response to detecting that the server mainboard is powered on, matching the chip to be tested through chip addressing;

[0052] S12. Establish interconnection with the chip under test through Python.

[0053] Exemplarily, the test system on which the method embodiment is based may include a PC terminal, a load meter, a Gen5tool, an Imon simulation control board, and an online Imon simulation module. The PC terminal is the test terminal, and the test can be performed at the test terminal. The online Imon simulation module integrates the functions of automatically capturing Imon test data, returning to zero model, chip addressing, and generating simulation Imon curves, etc. The chip to be tested can be found / matched through the online Imon simulation module and the Gen5 control interface, and the chip addressing function integrated in the online Imon simulation module can be used, and the interconnection can be established through Python. It should be noted that the above examples are only examples for matching the target standard (IntelSpec) of Intel manufacturers, and are implemented through the Gen5 control interface configured by Intel. The method flow can also be used as an implementation method for other target manufacturers and / or target standards, which will not be described in detail here.

[0054] In some embodiments, the method further comprises:

[0055] 101. In response to detecting that a slope of a curve in current accuracy test data is not within a target standard range, adjust the current gain of the chip under test until the adjusted slope of the curve meets the target standard range.

[0056] Specifically, if the slope of the curve in the current accuracy test data is not within the target standard range, it is first necessary to adjust the current gain (Igain) of the chip under test until the adjusted slope of the curve meets the target standard range, ensuring the consistency of the test curve slope and increasing test efficiency.

[0057] In some embodiments, S3 includes:

[0058] S31, in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, simulating a first current accuracy curve of the chip under test under a return-to-zero current accuracy detection curve model;

[0059] S32. In response to detecting that the first current accuracy curve meets the target standard, a second current accuracy curve is simulated under the condition of maximum positive and negative accuracy deviation of the chip under test based on the zero current accuracy detection curve model, and the current compensation value of the chip under test is adjusted until the simulated second current accuracy curve can meet the target standard.

[0060] The zero current accuracy detection curve model is used to simulate a current accuracy curve of the chip under test to adjust the current deviation to zero when the current load is zero ampere.

[0061] Specifically, if the slope of the curve in the current accuracy test data is within the target standard range, it means that the slope of the test curve is consistent, that is, the slope of the test curve is OK. Then, the current compensation (Ioffset) of the chip under test needs to be debugged. First, the first current accuracy curve of the chip under test needs to be simulated under the zero current accuracy detection curve model. Among them, the zero current accuracy detection curve model is used to simulate the current accuracy curve of the chip under test when the current deviation under the zero ampere (0A) current load condition is adjusted to zero. Then, it is necessary to ensure that the first current accuracy curve meets the target standard (IntelSpec). Finally, based on the zero current accuracy detection curve model, the second current accuracy curve under the maximum positive and negative accuracy deviation of the chip under test is simulated, and the current compensation value of the chip under test is adjusted until the simulated second current accuracy curve can meet the target standard. By adopting such technical means, the current compensation (Ioffset) of the chip under test that meets the worst case can be obtained, that is, the current gain (Igain) and current compensation (Ioffset) are both met, and the code of the current chip under test is debugged.

[0062] In some embodiments, S31 includes:

[0063] S311, in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, adjusting the current compensation value of the chip under test and running the current accuracy detection test until the tested current accuracy curve as a whole meets the target standard;

[0064] S312, input the accuracy specification of the chip to be tested, and record the current deviation of the chip to be tested under zero ampere current load;

[0065] S313 , simulating a current accuracy curve of the chip under test to adjust the current deviation to zero under a zero ampere current load condition, as a first current accuracy curve of the chip under test under the zero current accuracy detection curve model.

[0066] For example, after detecting that the slope of the curve in the current accuracy test data is within the target standard range, the current compensation value (Ioffset) of the chip to be tested can be adjusted first, and the Gen5Python test Imon can be run. The Imon test results are automatically imported into the test report and the Imon simulation module, first making the adjusted current compensation value (Ioffset) meet the test current accuracy curve as a whole to meet the target standard. Then input the chip accuracy Spec in the simulation module, and record the current deviation of the current chip to be tested under 0A load conditions, and simulate the current accuracy curve of the chip to be tested to adjust the current deviation to zero when the zero ampere current load condition is met. At this time, the chip reference current is zeroed, which serves as the first current accuracy curve of the chip to be tested under the zero current accuracy detection curve model. Then it is necessary to ensure that the first current accuracy curve meets the target standard.

[0067] In some embodiments, the method further comprises:

[0068] 201. In response to detecting that a first current accuracy curve does not meet a target standard, adjust a code of a chip under test according to a current accuracy simulation deviation until the first current accuracy curve meets the target standard.

[0069] Specifically, if the first current accuracy curve does not meet the target standard, it is first necessary to adjust the chip code under test according to the Imon simulation situation so that the first current accuracy curve under the zero current accuracy detection curve model meets the target standard.

[0070] In some embodiments, S32 further includes:

[0071] S321 , adjusting the current compensation value of the chip under test and re-running the current accuracy detection test until the tested current accuracy curve as a whole meets the target standard and the simulated second current accuracy curves also meet the target standard.

[0072] Specifically, if any of the second current accuracy curves within the maximum positive and negative accuracy deviation range of the chip to be tested simulated on the basis of the zero current accuracy detection curve model does not meet the target standard (IntelSpec), it is necessary to adjust the current compensation value of the chip to be tested according to the simulated current compensation value and re-run the current accuracy detection test, and re-make the current accuracy curve of the test meet the target standard as a whole and all the simulated curves meet the target standard at the same time. By adopting such technical means, it is possible to make the debugged chip code meet the target standard that the current accuracy curve of the test meets the target standard as a whole, the first current accuracy curve under the zero current accuracy detection curve model meets the target standard, and the second current accuracy curve under the maximum positive and negative accuracy deviation of the chip to be tested simulated on the basis of the zero current accuracy detection curve model can meet the target standard, so that the optimal VRFW of the chip to be tested can be debugged in one test, while ensuring that the subsequent return boards can pass the Imon test, avoiding a large amount of repeated verification, saving manpower and material resources, and saving time costs.

[0073] In this embodiment, the maximum positive and negative precision deviation of the chip under test, that is, the Imon of the worst scenario, can be simulated. The optimal VRFW of the chip under test can be debugged in the first test, and at the same time, it is ensured that the subsequent return boards can pass the Imon test, avoiding a large number of repeated verifications, saving manpower and material resources, and saving time costs.

[0074] It should be noted that the terms "S1", "S2", etc. are used only for the purpose of describing the steps and do not specifically refer to the order or sequence, nor are they used to limit this application. They are merely for the convenience of describing the method of this application and should not be understood as indicating the order of the steps. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0075] Example 2

[0076] Corresponding to the above embodiment, the present application also provides a current accuracy simulation test device, referring to Figure 3 , the device includes: a communication module, a test module and a simulation module.

[0077] Among them, the communication module is used to establish an interconnection with the chip to be tested in response to detecting that the server mainboard is powered on; the test module is used to perform a current accuracy test on the chip to be tested and generate current accuracy test data; the simulation module is used to simulate the current accuracy curve of the chip to be tested under the maximum value of the positive and negative accuracy deviation in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, and adjust the current compensation value of the chip to be tested until the simulated current accuracy curve can meet the target standard.

[0078] Furthermore, the simulation module is also used to adjust the current gain of the chip to be tested until the adjusted curve slope meets the target standard range in response to detecting that the curve slope in the current accuracy test data is not within the target standard range.

[0079] Furthermore, the simulation module is also used to simulate a first current accuracy curve of the chip under test under the zero current accuracy detection curve model in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range; and is used to simulate a second current accuracy curve of the chip under test under the maximum value of the positive and negative accuracy deviation of the chip under test based on the zero current accuracy detection curve model in response to detecting that the first current accuracy curve meets the target standard, and adjust the current compensation value of the chip under test until the simulated second current accuracy curve can meet the target standard. The zero current accuracy detection curve model is used to simulate the current accuracy curve of the chip under test to adjust the current deviation under the zero ampere current load condition to zero.

[0080] Furthermore, the simulation module is also used to adjust the current compensation value of the chip to be tested and run the current accuracy detection test until the tested current accuracy curve as a whole meets the target standard in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range; and is used to input the accuracy specifications of the chip to be tested and record the current deviation of the chip to be tested under the current load of zero ampere; and is also used to simulate the current accuracy curve of the chip to be tested to adjust the current deviation under the current load of zero ampere to zero, as the first current accuracy curve of the chip to be tested under the zero current accuracy detection curve model.

[0081] Furthermore, the simulation module is further configured to, in response to detecting that the first current accuracy curve does not meet the target standard, adjust the code of the chip under test according to the current accuracy simulation deviation until the first current accuracy curve meets the target standard.

[0082] Furthermore, the simulation module is also used to adjust the current compensation value of the chip under test and re-run the current accuracy detection test until the tested current accuracy curve as a whole meets the target standard and the simulated second current accuracy curve can meet the target standard.

[0083] Furthermore, the communication module is also used to match the chip to be tested through chip addressing in response to detecting that the server mainboard is powered on; and to establish interconnection with the chip to be tested through Python.

[0084] The specific limitations of the current accuracy simulation test device can refer to the relevant limitations in the method embodiment, so they are not described here. The various modules in the above-mentioned current accuracy simulation test device can be implemented in whole or in part by software, hardware, and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0085] Example 3

[0086] Corresponding to the above embodiment, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the above current accuracy simulation test method can be implemented.

[0087] like Figure 4 As shown, in some embodiments, the system can be used as any of the above-mentioned electronic devices for the current accuracy simulation test method in each of the above-mentioned embodiments. In some embodiments, the system may include one or more computer-readable media (e.g., system memory or NVM / storage device) having instructions and one or more processors (e.g., (one or more) processors) coupled to the one or more computer-readable media and configured to execute the instructions to implement the module to perform the actions described in this application.

[0088] For one embodiment, the system control module may include any suitable interface controller to provide any suitable interface to at least one of the processor(s) and / or any suitable device or component in communication with the system control module.

[0089] The system control module may include a memory controller module to provide an interface to the system memory. The memory controller module may be a hardware module, a software module, and / or a firmware module.

[0090] The system memory can be used, for example, to load and store data and / or instructions for the system. For one embodiment, the system memory can include any suitable volatile memory, such as a suitable DRAM. In some embodiments, the system memory can include double data rate type four synchronous dynamic random access memory (DDR4 SDRAM).

[0091] For one embodiment, the system control module may include one or more input / output (I / O) controllers to provide interfaces to the NVM / storage devices and communication interface(s).

[0092] For example, NVM / storage devices may be used to store data and / or instructions. The NVM / storage devices may include any suitable non-volatile memory (e.g., flash memory) and / or may include any suitable non-volatile storage device(s) (e.g., one or more hard disk drives (HDDs), one or more compact disk (CD) drives, and / or one or more digital versatile disk (DVD) drives).

[0093] The NVM / storage device may include storage resources that are physically part of the device on which the system is installed, or it may be accessible to the device without being part of the device. For example, the NVM / storage device may be accessible over a network via (one or more) communication interfaces.

[0094] The communication interface(s) may provide an interface for the system to communicate over one or more networks and / or with any other suitable devices. The system may wirelessly communicate with one or more components of a wireless network according to any of one or more wireless network standards and / or protocols.

[0095] For one embodiment, at least one of the processor(s) may be packaged together with the logic of one or more controllers of a system control module (e.g., a memory controller module). For one embodiment, at least one of the processor(s) may be packaged together with the logic of one or more controllers of a system control module to form a system-in-package (SiP). For one embodiment, at least one of the processor(s) may be integrated on the same die with the logic of one or more controllers of a system control module. For one embodiment, at least one of the processor(s) may be integrated on the same die with the logic of one or more controllers of a system control module to form a system-on-chip (SoC).

[0096] In various embodiments, the system may be, but is not limited to, a server, a workstation, a desktop computing device, or a mobile computing device (e.g., a laptop computing device, a handheld computing device, a tablet computer, a netbook, etc.). In various embodiments, the system may have more or fewer components and / or a different architecture. For example, in some embodiments, the system includes one or more cameras, a keyboard, a liquid crystal display (LCD) screen (including a touch screen display), a non-volatile memory port, multiple antennas, a graphics chip, an application-specific integrated circuit (ASIC), and a speaker.

[0097] It should be noted that the application can be implemented in software and / or a combination of software and hardware, for example, can be implemented using an application specific integrated circuit (ASIC), a general purpose computer or any other similar hardware device. In one embodiment, the software program of the application can be executed by a processor to realize the steps or functions described above. Similarly, the software program of the application (including relevant data structures) can be stored in a computer-readable recording medium, for example, a RAM memory, a magnetic or optical drive or a floppy disk and similar devices. In addition, some steps or functions of the application can be implemented using hardware, for example, as a circuit that cooperates with a processor to perform each step or function.

[0098] In addition, a part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes but is not limited to a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0099] Communication media include media by which communication signals containing, for example, computer-readable instructions, data structures, program modules, or other data are transmitted from one system to another. Communication media may include guided transmission media such as cables and wires (e.g., fiber optic, coaxial, etc.) and wireless (unguided transmission) media capable of propagating energy waves, such as acoustic, electromagnetic, RF, microwave, and infrared. Computer-readable instructions, data structures, program modules, or other data may be embodied as, for example, a modulated data signal in a wireless medium such as a carrier wave or similar mechanism such as that embodied as part of spread spectrum technology. The term "modulated data signal" refers to a signal that has one or more of its characteristics changed or set in such a manner as to encode information in the signal. Modulation may be analog, digital, or a hybrid modulation technique.

[0100] Here, according to one embodiment of the present application, a device is included, which includes a memory for storing computer program instructions and a processor for executing the program instructions, wherein, when the computer program instructions are executed by the processor, the device is triggered to run the methods and / or technical solutions based on the aforementioned multiple embodiments of the present application.

[0101] Example 4

[0102] Corresponding to the above embodiment, the present application further provides a computer-readable storage medium storing computer-executable instructions, and the computer-executable instructions are used to execute the current accuracy simulation test method.

[0103] In this embodiment, computer-readable storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. For example, computer-readable storage media include, but are not limited to, volatile memory, such as random access memory (RAM, DRAM, SRAM); and non-volatile memory, such as flash memory, various read-only memories (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic / ferroelectric memories (MRAM, FeRAM); and magnetic and optical storage devices (hard disks, magnetic tapes, CDs, DVDs); or other media now known or later developed that can store computer-readable information / data for use by a computer system.

[0104] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0105] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A current accuracy simulation test method, applied to a test terminal, characterized in that: include: In response to detecting that the server mainboard is powered on, establishing interconnection with the chip under test; Performing a current accuracy test on the chip to be tested to generate current accuracy test data; In response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, the current accuracy curve of the chip under test is simulated under the maximum value of the positive and negative accuracy deviation, and the current compensation value of the chip under test is adjusted until the simulated current accuracy curve can meet the target standard, including: in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, the first current accuracy curve of the chip under test is simulated under the zero current accuracy detection curve model; in response to detecting that the first current accuracy curve meets the target standard, the second current accuracy curve of the chip under test is simulated under the maximum value of the positive and negative accuracy deviation based on the zero current accuracy detection curve model, and the current compensation value of the chip under test is adjusted until the simulated second current accuracy curve can meet the target standard, wherein the zero current accuracy detection curve model is used to simulate the current accuracy curve of the chip under test to adjust the current deviation to zero under the zero ampere current load condition.

2. The current accuracy simulation test method according to claim 1, characterized in that: The method further comprises: In response to detecting that the slope of the curve in the current accuracy test data is not within a target standard range, the current gain of the chip to be tested is adjusted until the adjusted slope of the curve meets the target standard range.

3. The current accuracy simulation test method according to claim 1, characterized in that: In response to detecting that the slope of the curve in the current accuracy test data is within a target standard range, simulating a first current accuracy curve of the chip under test under a return-to-zero current accuracy detection curve model includes: In response to detecting that the slope of the curve in the current accuracy test data is within a target standard range, adjusting the current compensation value of the chip under test and running a current accuracy detection test until the tested current accuracy curve as a whole meets the target standard; Input the accuracy specification of the chip to be tested, and record the current deviation of the chip to be tested under a current load of zero ampere; A current accuracy curve of the chip under test adjusting the current deviation to zero under a zero ampere current load condition is simulated as a first current accuracy curve of the chip under test under the zero current accuracy detection curve model.

4. The current accuracy simulation test method according to claim 1, characterized in that: The method further comprises: In response to detecting that the first current accuracy curve does not meet the target standard, the code of the chip under test is adjusted according to the current accuracy simulation deviation until the first current accuracy curve meets the target standard.

5. The current accuracy simulation test method according to claim 3, characterized in that: The step of adjusting the current compensation value of the chip under test until the simulated second current accuracy curve meets the target standard further includes: The current compensation value of the chip under test is adjusted and the current accuracy detection test is re-run until the tested current accuracy curve as a whole meets the target standard and the simulated second current accuracy curves all meet the target standard.

6. The current accuracy simulation test method according to claim 1, characterized in that: The step of establishing interconnection with the chip to be tested in response to detecting that the server mainboard is powered on includes: In response to detecting that the server mainboard is powered on, matching the chip to be tested through chip addressing; Establish interconnection with the chip to be tested through Python.

7. A current accuracy simulation test device, characterized in that: The device comprises: A communication module, configured to establish an interconnection with the chip under test in response to detecting that the server mainboard is powered on; A testing module, configured to perform a current accuracy test on the chip to be tested and generate current accuracy test data; A simulation module is used to simulate the current accuracy curve of the chip under test under the condition of maximum positive and negative accuracy deviation in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, and adjust the current compensation value of the chip under test until the simulated current accuracy curve can meet the target standard, including: in response to detecting that the slope of the curve in the current accuracy test data is within the target standard range, simulating the first current accuracy curve of the chip under test under the zero current accuracy detection curve model; in response to detecting that the first current accuracy curve meets the target standard, simulating the second current accuracy curve of the chip under test under the condition of maximum positive and negative accuracy deviation based on the zero current accuracy detection curve model, adjusting the current compensation value of the chip under test until the simulated second current accuracy curve can meet the target standard, wherein the zero current accuracy detection curve model is used to simulate the current accuracy curve of the chip under test to adjust the current deviation to zero under the zero ampere current load condition.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the current accuracy simulation test method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium storing computer-executable instructions, characterized in that: The computer-executable instructions are used to execute the current accuracy simulation test method according to any one of claims 1 to 6.

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