A three-dimensional processor array reconstruction method for removing bottlenecks and compensation

Abstract

The application discloses a three-dimensional processor array reconstruction method for removing a bottleneck and compensation, which removes a bottleneck surface limiting the size of a logic array to break the limitation of the size of array reconstruction, and uses a mechanism of compensating for a faulty unit of a neighbor by using a faultless processor unit on the bottleneck surface, so as to effectively improve the utilization rate of the faultless processor unit in the reconstruction process, break the limitation of the size of processor array reconstruction, increase the reconstruction size of the three-dimensional processor array, and further set a maximum size replacement time to realize time limitation, so that invalid iteration can be terminated in time, and the timeliness of the algorithm is ensured.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional processor array technology, and more specifically to a method for reconstructing a three-dimensional processor array that eliminates bottlenecks and provides compensation. Background Technology

[0002] With the rapid advancements in VLSI and WSI integration technologies and processes, advanced integration techniques have led to a continuous increase in the integration density of chips and various electronic components. Compared to two-dimensional (2D) processor arrays, three-dimensional (3D) processor arrays offer advantages such as reduced interconnect latency, lower power consumption, and increased bandwidth. However, as the density of 3D processor arrays increases, the complex and variable system architecture during large-scale parallel computing leads to a continuous increase in the failure rate of processor units within the 3D processor array. For some complex electronic systems with high real-time requirements (such as spacecraft or infantry fighting vehicles), disassembling such complex electronic systems requires significant time and manpower, making it difficult to replace faulty 3D processor arrays within a limited timeframe. Therefore, it is necessary to use reconstruction algorithms to reconstruct fault-free subarrays within the 3D processor array to ensure its reliability and sustainable use. Summary of the Invention

[0003] The present invention addresses the problem that processor unit failures in a three-dimensional processor array can affect the reliability of the entire system, and provides a method for reconstructing a three-dimensional processor array to eliminate bottlenecks and provide compensation.

[0004] To solve the above problems, the present invention is achieved through the following technical solution:

[0005] A method for reconstructing a three-dimensional processor array that eliminates bottlenecks and provides compensation includes the following steps:

[0006] Step 1: Initialize all tags in the physical array, set the current record size Scale = 0, set the current size replacement count k = 1, and set the maximum size replacement count;

[0007] Step 2: Select the cell cluster containing the most faulty processor units from the unmarked cell clusters in the current physical array, mark the cell cluster on the current physical array, and mark the physical plane in the column direction of the cell cluster as the bottleneck surface;

[0008] Step 3: Construct the logic plane in the xy direction;

[0009] When constructing each logic plane, start from the first logic row of the current logic plane and continue along the positive x-axis until the last logic row of the current logic plane.

[0010] When constructing each logical row, start traversing from the cell cluster of the first physical column of the physical row corresponding to the current logical row, and continue traversing along the positive y-axis until the cell cluster of the first physical column of the physical row corresponding to the current logical row is reached.

[0011] When traversing cell clusters, determine whether the current cell cluster is on the bottleneck surface within the current physical array:

[0012] 1) If the current cell cluster is on the bottleneck surface, then the current cell cluster is ignored.

[0013] 2) If the current cell cluster is not on the bottleneck surface, select the processor cell with the smallest unmarked physical layer coordinates in the current cell cluster as a candidate cell, and determine whether the current candidate processor cell is adjacent to the bottleneck surface:

[0014] 2.1) If the current candidate processor unit is not adjacent to the bottleneck surface, then further determine whether the current candidate processor unit is a faulty processor unit:

[0015] 2.1.1) If the current candidate processor unit is a fault-free processor unit, then the current candidate processor unit is used as the processor unit of the current logical row, and the current candidate processor unit is marked on the current physical array.

[0016] 2.1.2) If the current candidate processor unit is a faulty processor unit, mark the current candidate processor unit on the current physical array and return to step 2);

[0017] 2.2) If the current candidate processor unit is adjacent to the bottleneck plane, then further determine whether the current candidate processor unit is a faulty processor unit:

[0018] 2.2.1) If the current candidate processor unit is a fault-free processor unit, then the current candidate processor unit is used as the processor unit of the current logical row, and the current candidate processor unit is marked on the current physical array;

[0019] 2.2.2) If the current candidate processor unit is a faulty processor unit, compensation is triggered. That is, according to the compensation priority, the fault-free processor unit of the column predecessor or column successor on the bottleneck surface adjacent to the current candidate processor unit is taken as the processor unit of the current logical row; if the compensation is unsuccessful, the current candidate processor unit is marked on the current physical array and 2) is returned.

[0020] Step 4: When constructing the logic plane, if no suitable processor unit can be found in a certain cell cluster of the current physical array, then all the logic planes that have been constructed are linked together to generate a logic array.

[0021] Step 5: Calculate the scale Scale′ of the currently generated logical array and compare it with the scale Scale of the current record:

[0022] If Scale′ > Scale, then first set the current record size Scale = Scale′, then initialize the markers in the current physical array except for the bottleneck surface, and return to step 2;

[0023] Otherwise, first increment the current size replacement count k by 1, and then determine whether the current size replacement count k has reached the set maximum size replacement count: if it has not reached, initialize the markers in the current physical array except for the bottleneck surface, and return to step 2; if it has reached, output the currently generated logical array and complete the reconstruction.

[0024] In step 3.2.2 above, the compensation priority is:

[0025] ① If the xz plane in the positive y-axis direction of the current candidate processor unit is the bottleneck plane, and the column-following processor unit of the current candidate processor unit is a fault-free processor unit, then the column-following processor unit of the current candidate processor unit is used as the processor unit of the current logical row, and the column-following processor unit of the current candidate processor unit is marked on the current physical array.

[0026] ② If the xz plane in the negative y-axis direction of the current candidate processor unit is a bottleneck plane, and the bottleneck plane is the first column xz plane or the xz plane in the negative y-axis direction of the bottleneck plane is also a bottleneck plane, and the column predecessor processor unit of the current candidate processor unit is a fault-free processor unit, then the column predecessor processor unit of the current candidate processor unit is used as the processor unit of the current logical row, and the column predecessor processor unit of the current candidate processor unit is marked on the current physical array.

[0027] In step 3 above, after the construction of the current logical plane is completed, it is necessary to mark the unavailable processor units on the current physical array based on the current logical plane;

[0028] For each processor unit e′ on the current logical plane x，y，z If processor unit e′ x，y，z Within the cell cluster, the physical layer coordinates are greater than the processor unit e′. x，y，z A processor unit u in physical layer coordinates is defined as an unavailable processor unit if it meets one of the following four conditions;

[0029] Z(u)<Z(e′ x-1，y，z )

[0030] Z(u)<Z(e′ x+1，y，z )

[0031] Z(u)<Z(e′ x，y-1，z )

[0032] Z(u)<Z(e′ x，y+1，z )

[0033] Where Z(u) is the physical layer coordinate of processor unit u, Z(e′) x-1，y，z ) is the processor unit e′ x，y，z The line pre-processor unit e′ x-1，y，z The physical layer coordinates, Z(e′) x+1，y，z ) is the processor unit e′ x，y，z The row of the back drive processor unit e′ x-1，y，z The physical layer coordinates, Z(e′) x，y-1，z ) is the processor unit e′ x，y，z The column pre-processor unit e′ x-1，y，z The physical layer coordinates, Z(e′) x，y+1，z ) is the processor unit e′ x，y，z The column rear-drive processor unit e′ x-1，y，z The physical layer coordinates.

[0034] Compared with the prior art, this invention proposes for the first time a method for finding constraints that limit the size of the reconstructed three-dimensional processor array. Without limiting the compensation distance of the route, it uses a method of excluding the bottleneck surface and using the fault-free processor units on the bottleneck surface to compensate for faulty components on other planes. This not only breaks the constraints that limit the size of the reconstructed processor array, but also makes full use of the fault-free processor units that should have been removed to reconstruct the processor array, thereby improving the reconstructed size of the processor array. Attached Figure Description

[0035] Figure 1 This is a planar schematic diagram of a three-dimensional processor array. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific examples.

[0037] A physical array (main array) refers to a three-dimensional processor array manufactured using integrated circuit technology, which may contain some faulty processor units that may have failed during manufacturing or use. The three-dimensional processor array with fault-free processor units generated after the physical array is reconstructed using a reconstruction algorithm is called a logical array (target array).

[0038] In a physical array, rows, columns, and layers are called physical rows, physical columns, and physical layers. In a logical array, rows, columns, and layers are called logical rows, logical columns, and logical layers. For a given processor unit e... x，y，zIts position in the three-dimensional processor array can be represented by three-dimensional coordinates, namely the row coordinates X(e). x，y，z ) = x, column coordinate Y(e) x，y，z ) = y, layer coordinates Z(e x，y，z ) = z. Except for the boundary processor unit, each processor unit e x，y，z Each has a corresponding pre-processor unit and a successor processor unit. Processor unit e x-1，y，z and e x+1，y，z They are respectively called e x，y，z The pre-processor and post-processor; processor unit e x，y-1，z and e x，y+1，z They are respectively called e x，y，z The column pre-processor and column successor processor; processor unit e x，y，z-1 and e x，y，z+1 They are respectively called e x，y，z Layer pre-processors and layer successor processors. In a physical array, if a series of processor units contain the same row coordinate x and column coordinate y, then the set of these processor units is called a cell cluster H. x，y H x，y ={e|X(e)=x,Y(e)=y}.

[0039] In a physical array, the processor plane is called the physical plane; in a logical array, the processor plane is called the logical plane. In a three-dimensional processor array, the plane along the column-layer direction is the yz plane. Figure 1 The yz-plane in the middle), the plane in the row direction, i.e., the xz plane ( Figure 1 The xz-plane in the middle), the plane in the row and column directions, i.e., the xy-plane ( Figure 1 In this context, xy-plane represents the planes in the three directions of a three-dimensional processor array, where yz-plane represents the plane formed by processor units with the same x-axis coordinate, xz-plane represents the plane formed by processor units with the same y-axis coordinate, and xy-plane represents the plane formed by processor units with the same z-axis coordinate.

[0040] Based on the above knowledge, the present invention proposes a method for reconstructing a three-dimensional processor array that eliminates bottlenecks and provides compensation, comprising the following steps:

[0041] Step 1: Initialize all markers in the physical array (i.e., the markers of processor units, cell clusters, and bottleneck surfaces in the physical array), set the current record size Scale = 0, set the current size replacement count k = 1, and set the maximum size replacement count;

[0042] Step 2: Select the cell cluster containing the most faulty processor units from the unmarked cell clusters in the current physical array, mark the cell cluster on the current physical array, and mark the physical plane (xz-plane) in the row direction of the cell cluster as the bottleneck surface;

[0043] Step 3: Construct the logic plane in the xy direction;

[0044] When constructing each logic plane, start from the first logic row of the current logic plane and continue along the positive x-axis until the last logic row of the current logic plane.

[0045] When constructing each logical row, start traversing from the cell cluster of the first physical column of the physical row corresponding to the current logical row, and continue traversing along the positive y-axis until the cell cluster of the first physical column of the physical row corresponding to the current logical row is reached.

[0046] When traversing cell clusters, determine whether the current cell cluster is on the bottleneck surface within the current physical array:

[0047] 1) If the current cell cluster is on the bottleneck surface, then directly ignore (pass through) the current cell cluster;

[0048] 2) If the current cell cluster is not on the bottleneck surface, select the processor cell with the smallest unmarked physical layer coordinates in the current cell cluster as a candidate cell, and determine whether the current candidate processor cell is adjacent to the bottleneck surface:

[0049] 2.1) If the current candidate processor unit is not adjacent to the bottleneck surface, then further determine whether the current candidate processor unit is a faulty processor unit:

[0050] 2.1.1) If the current candidate processor unit is a fault-free processor unit, then the current candidate processor unit is used as the processor unit of the current logical row, and the current candidate processor unit is marked on the current physical array.

[0051] 2.1.2) If the current candidate processor unit is a faulty processor unit, mark the current candidate processor unit on the current physical array and return to step 2);

[0052] 2.2) If the current candidate processor unit is adjacent to the bottleneck plane, then further determine whether the current candidate processor unit is a faulty processor unit:

[0053] 2.2.1) If the current candidate processor unit is a fault-free processor unit, then the current candidate processor unit is used as the processor unit of the current logical row, and the current candidate processor unit is marked on the current physical array;

[0054] 2.2.2) If the current candidate processor unit is a faulty processor unit, compensation is triggered. That is, based on the compensation priority, the fault-free processor unit preceding or following the current candidate processor unit on the bottleneck surface adjacent to the current logical row is selected as the processor unit for the current logical row; where the compensation priority is:

[0055] ① If the xz plane in the positive y-axis direction of the current candidate processor unit is the bottleneck plane, and the column-following processor unit of the current candidate processor unit is a fault-free processor unit, then the column-following processor unit of the current candidate processor unit is used as the processor unit of the current logical row, and the column-following processor unit of the current candidate processor unit is marked on the current physical array.

[0056] ② If the xz plane in the negative y-axis direction of the current candidate processor unit is a bottleneck surface, and the bottleneck surface is the xz plane of the first column, or the xz plane in the negative y-axis direction of the bottleneck surface is also a bottleneck surface, and the column predecessor processor unit of the current candidate processor unit is a fault-free processor unit, then the column predecessor processor unit of the current candidate processor unit is used as the processor unit of the current logical row, and the column predecessor processor unit of the current candidate processor unit is marked on the current physical array.

[0057] If compensation fails, mark the current candidate processor unit on the current physical array and return 2);

[0058] After the current logical plane is constructed, the unavailable processor units on the current physical array need to be marked based on the current logical plane;

[0059] For each processor unit e′ on the current logical plane x，y，z If processor unit e′ x，y，z Within the cell cluster, the physical layer coordinates are greater than the processor unit e′. x，y，z A processor unit u in physical layer coordinates is defined as an unavailable processor unit if it meets one of the following four conditions;

[0060] Z(u)<Z(e′ x-1，y，z )

[0061] Z(u)<Z(e′ x+1，y，z )

[0062] Z(u)<Z(e′ x，y-1，z )

[0063] Z(u)<Z(e′ x，y+1，z )

[0064] Where Z(u) is the physical layer coordinate of processor unit u, Z(u) > Z(e′) x，y，z ), Z(e′x-1，y，z ) is the processor unit e′ x，y，z The line pre-processor unit e′ x-1，y，z The physical layer coordinates, Z(e′) x+1，y，z ) is the processor unit e′ x，y，z The row of the back drive processor unit e′ x-1，y，z The physical layer coordinates, Z(e′) x，y-1，z ) is the processor unit e′ x，y，z The column pre-processor unit e′ x-1，y，z The physical layer coordinates, Z(e′) x，y+1，z ) is the processor unit e′ x，y，z The column rear-drive processor unit e′ x-1，y，z The physical layer coordinates.

[0065] Step 4: When constructing the logic plane, if no suitable processor unit can be found in a certain cell cluster of the current physical array, then the currently constructed logic planes are linked together to generate a logic array.

[0066] Step 5: Calculate the scale Scale′ of the currently generated logical array and compare it with the scale Scale of the current record:

[0067] If Scale′ > Scale, then first set the current record size Scale = Scale′, then initialize the markers in the current physical array except for the bottleneck surface (i.e. initialize the processor units and unit clusters in the current physical array), and return to step 2;

[0068] Otherwise, first increment the current size replacement count k by 1, and then determine whether the current size replacement count k has reached the set maximum size replacement count: if it has not reached the maximum size replacement count, initialize the markers in the current physical array except for the bottleneck surface (i.e. initialize the processor units and unit clusters in the current physical array) and return to step 2; if it has reached the maximum size replacement count, output the currently generated logical array and complete the reconstruction.

[0069] This invention breaks the limitation on the scale of array reconstruction by finding and eliminating bottleneck surfaces that restrict the size of the logic array, and by using fault-free processor units on the bottleneck surface to compensate for faulty neighboring units. This effectively improves the utilization rate of fault-free processor units during reconstruction, breaks the limitation on the scale of processor array reconstruction, and increases the reconstruction scale of three-dimensional processor arrays. In addition, by setting a maximum number of replacements to implement time limits, invalid iterations can be terminated in a timely manner, ensuring the timeliness of the algorithm.

[0070] It should be noted that although the embodiments described above are illustrative, they are not intended to limit the invention. Therefore, the invention is not limited to the specific embodiments described above. Any other embodiments obtained by those skilled in the art under the guidance of this invention without departing from its principles are considered to be within the protection scope of this invention.

Claims

1. A three-dimensional processor array reconstruction method that eliminates bottlenecks and compensates, characterized by, The steps include the following: Step 1, initialize all marks in the physical array, let the current record scale Scale = 0, let the current scale replacement times k = 1, and set the maximum scale replacement times; Step 2, select the cell cluster containing the most number of fault processor units from the unmarked cell cluster in the current physical array, mark the cell cluster on the current physical array, and mark the physical plane in the column direction of the cell cluster as the bottleneck plane; Step 3, construct the xy direction logical plane; When constructing each logical plane, first construct from the first logical row of the current logical plane, along the positive direction of the x axis, to the last logical row of the current logical plane; When constructing each logical row, first traverse from the cell cluster of the first physical column of the physical row corresponding to the current logical row, along the positive direction of the y axis, to the cell cluster of the first physical column of the physical row corresponding to the current logical row; When traversing the cell cluster, judge whether the current cell cluster is on the bottleneck plane in the current physical array: 1) if the current cell cluster is on the bottleneck plane, directly ignore the current cell cluster; 2) if the current cell cluster is not on the bottleneck plane, select an unmarked processor unit with the smallest physical layer coordinate in the current cell cluster as the candidate unit, and judge whether the current candidate processor unit is adjacent to the bottleneck plane: 2.1) if the current candidate processor unit is not adjacent to the bottleneck plane, further judge whether the current candidate processor unit is a fault processor unit: 2.1.1) if the current candidate processor unit is a non-fault processor unit, take the current candidate processor unit as the processor unit of the current logical row, and mark the current candidate processor unit on the current physical array; 2.1.2) if the current candidate processor unit is a fault processor unit, mark the current candidate processor unit on the current physical array, and return to 2); 2.2) if the current candidate processor unit is adjacent to the bottleneck plane, further judge whether the current candidate processor unit is a fault processor unit: 2.2.1) if the current candidate processor unit is a non-fault processor unit, take the current candidate processor unit as the processor unit of the current logical row, and mark the current candidate processor unit on the current physical array; 2.2.2) if the current candidate processor unit is a fault processor unit, trigger compensation, that is, take the non-fault processor unit adjacent to the column predecessor or column successor of the current candidate processor unit on the bottleneck plane as the processor unit of the current logical row according to the compensation priority; If the compensation is unsuccessful, mark the current candidate processor unit on the current physical array, and return to 2); Step 4, when constructing the logical plane, if no processor unit meeting the requirements can be found in a cell cluster of the current physical array, link all the logical planes constructed to generate a logical array; Step 5, calculate the scale Scale' of the current generated logical array, and compare it with the current record scale Scale: If Scale' > Scale, first set the current record scale Scale = Scale', then initialize the markers in the current physical array except the bottleneck face, and return to step 2; Otherwise, first set the current scale replacement times k = k + 1, then judge whether the current scale replacement times k reaches the set maximum scale replacement times: if not, initialize the markers in the current physical array except the bottleneck face, and return to step 2; if yes, output the current generated logical array, and complete the reconstruction.

2. The three-dimensional processor array reconstruction method of claim 1, wherein, In 2.2.2) of step 3, the compensation priority is: ①If the xz plane in the positive direction of the y axis of the current candidate processor unit is the bottleneck face, and the column successor processor unit of the current candidate processor unit is a faultless processor unit, then the column successor processor unit of the current candidate processor unit is the processor unit of the current logical row, and the column successor processor unit of the current candidate processor unit is marked on the current physical array; ②If the xz plane in the negative direction of the y axis of the current candidate processor unit is the bottleneck face, and the bottleneck face is the first column xz plane or the xz plane in the negative direction of the y axis of the bottleneck face is also the bottleneck face, and the column predecessor processor unit of the current candidate processor unit is a faultless processor unit, then the column predecessor processor unit of the current candidate processor unit is the processor unit of the current logical row, and the column predecessor processor unit of the current candidate processor unit is marked on the current physical array.

3. The three-dimensional processor array reconstruction method of excluding bottleneck and compensation according to claim 1, in step 3, after completing the construction of the current logical plane, the unavailable processor units on the current physical array need to be marked based on the current logical plane; For each processor element e' on the current logical plane x，y，z , if the processor element e' is in a cell cluster where the physical layer coordinates of the processor elements u, which have physical layer coordinates greater than the physical layer coordinates of the processor element e', satisfy one of the following four conditions, then the processor element u is defined as an unusable processor element: x，y，z x，y，z 1. The physical layer coordinates of the processor elements u are greater than the physical layer coordinates of the processor element e' by at least one in each dimension.

2. The physical layer coordinates of the processor elements u are greater than the physical layer coordinates of the processor element e' by at least two in each dimension.

3. The physical layer coordinates of the processor elements u are greater than the physical layer coordinates of the processor element e' by at least three in each dimension.

4. The physical layer coordinates of Z(u) < Z(e' ) < Z(e) x-1，y，z ) Z(u) < Z(e' ) < Z(e) x+1，y，z ) Z(u) < Z(e' ) < Z(e) x，y-1，z ) Z(u) < Z(e' ) < Z(e) x，y+1，z ) wherein Z(u) represents the physical layer coordinates of processor unit u, Z(e′) x-1，y，z ) is the processor unit e′ x，y，z The line pre-processor unit e′ x-1，y，z The physical layer coordinates, Z(e′) x+1，y，z ) is the processor unit e′ x，y，z The row of the back drive processor unit e′ x-1，y，z The physical layer coordinates, Z(e′) x，y-1，z ) is the processor unit e′ x，y，z The column pre-processor unit e′ x-1，y，z The physical layer coordinates, Z(e′) x，y+1，z ) is the processor unit e′ x，y，z The column rear-drive processor unit e′ x-1，y，z The physical layer coordinates.

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