A processor chip branch prediction target buffer security enhancement method and electronic device

Abstract

The application provides a processor chip branch prediction buffer security strong method and an electronic device. The method comprises: a security domain private key generation and application method, dividing a program security domain and generating two private security keys for each security domain, and ensuring that randomization seeds adopted by different security domains are irrelevant; a structure design of a branch prediction buffer with a label domain and a data domain separated, which is combined with a branch prediction buffer skew lookup and update mechanism to realize a security branch prediction buffer skew randomization lookup and update mechanism within a system life cycle, and the structure design of the branch prediction buffer with the label domain and the data domain separated is combined to realize security within the system life cycle.

Description

Technical Field

[0001] This invention belongs to the field of processor architecture, and specifically relates to a method and electronic device for enhancing the security of the branch prediction target buffer of a processor chip. Background Technology

[0002] In modern processors, the application of branch prediction units has brought significant performance improvements, but it has also introduced numerous security challenges. One such challenge is the branch prediction analysis attack, which falls under the category of microarchitecture analysis attacks and has been previously identified. Recently, researchers demonstrated the immense power of microarchitecture side-channel attacks through the newly discovered Spectre attack, a type of transient execution attack. This vulnerability bypasses memory protection, enabling arbitrary memory access and even computation. This attack exploits the branch prediction buffer, revealing serious security flaws in the current design of the branch prediction buffer.

[0003] There are two fundamental factors contributing to Spectrum attacks and branch prediction attacks: first, the reuse of branch prediction resources by high-performance processors; and second, the use of only compressed information when indexing the branch prediction buffer using virtual addresses. Specifically, the storage method of the prediction target address in the branch target buffer is similar to a cache, with a fixed mapping relationship between its index and branch instruction address. Attackers can exploit methods similar to cache attacks based on reuse and conflict to attack the branch prediction unit. If the victim's and attacker's addresses are mapped to the same set, they can either reuse each other's information or evict each other's information from the branch prediction buffer. On the other hand, unlike a cache, the branch prediction buffer's index and tags only use compressed virtual addresses and historical information for lookup and comparison. This significantly increases the probability of different branches reusing the same entry. If the conflict is controlled by the attacker, the branch target buffer can be maliciously injected with specified branch prediction information. The victim's branch, due to speculative execution mechanisms, jumps to the malicious target, and this information is leaked through other side channels.

[0004] To defend against attacks targeting the branch prediction buffer, various defensive methods have been proposed by academia and industry, involving modifications to the internal structure of the branch prediction buffer. However, these methods suffer from significant performance overhead; for example, traditional branch prediction buffer structures require periodic changes to the randomization key to maintain security using randomized indexes. Furthermore, existing methods cannot provide comprehensive protection against all types of attacks. Summary of the Invention

[0005] In view of the security problems caused by the fixed mapping relationship between the index and the branch instruction address in existing branch prediction methods, this invention provides a method and electronic device for enhancing the security of the branch prediction buffer in a processor chip. This invention isolates the mapping relationship between the index and the branch instruction address in different security domains, restructures the branch prediction buffer, and proposes a search and update mechanism based on skewed randomization, enabling it to defend against all currently proposed attacks targeting the branch prediction buffer.

[0006] A method for enhancing the security of a processor chip branch prediction buffer includes the following steps:

[0007] Step 1: When the system starts, different processes are assigned to different security domains, and the original index number of the branch prediction target buffer of the security domain is obtained;

[0008] Step 2: When the system starts, it generates an index encryption key that is twice the number of security domains and assigns it to different security domains. The key is then applied to the original index of the security domain to obtain a new index number.

[0009] Step 3: Reuse the index encryption key for content encryption;

[0010] Step 4: When querying the branch prediction target content, use the index number to index the two label groups in the label field of the skewed randomization branch prediction target buffer, and select the label group with more invalid labels and the data storage unit pointed to by the label group to store the branch prediction target information.

[0011] Step 5: When updating the branch prediction target content, randomly select two data storage units, choose the data storage unit with fewer invalid tags in the tag group to which the pointed-to tag storage unit belongs, evict it, and store the new branch prediction target content.

[0012] Furthermore, the security domains are divided according to protection levels, which are thread-level granularity and different processor operating states.

[0013] Furthermore, the encryption key is generated by PRINCE cryptographic hardware circuitry or other random number generation methods.

[0014] Furthermore, the branch prediction target buffer consists of a label field and a data field. The label field comprises several label groups, each with a fixed number of label storage units. The label storage units in each label group are divided into two parts: intrinsic labels and additional labels. The product of the number of intrinsic labels and the number of label groups is equal to the number of data storage units in the data array. The number of additional labels is determined by the designer. The content field consists of a data array containing several data storage units.

[0015] Furthermore, each tag storage unit has a forward pointer that can point to any data storage unit, and each data storage unit has a forward pointer that can point to any tag storage unit, enabling it to perceive the number of invalid tags in its tag group. An invalid tag refers to a tag storage unit that does not point to a data storage unit, or points to an invalid data storage unit.

[0016] Furthermore, the method of applying the key to the branch prediction buffer index is to XOR the key and the original index of the branch prediction buffer respectively to obtain two new indices. Encrypting the content with the index encryption key means XORing the content with either of the two keys to obtain ciphertext content. When updating the branch prediction target content, the ciphertext is stored, and when the content is indexed, it is decrypted using the key.

[0017] Furthermore, the method for using the branch prediction buffer in the process is as follows: When searching the branch prediction buffer, first index the two label groups in the label field, compare the labels, and if a match is found, the data unit at the data array position pointed to by the label group's pointer is the indexed data unit. If a match is not found, update the branch prediction buffer, select an invalid label from the label group with more invalid labels, and randomly select two data storage units in the data array of the data field. Determine which of the two data storage units points to the label group with fewer invalid labels, and establish a mutual pointing relationship between this data storage unit and the previous invalid label.

[0018] Furthermore, the "content" and "branch prediction target content" refer to the address of the branch target instruction. The "skewness" refers to the tendency to select the one with more invalid tags from two indexed tag groups when searching the branch prediction buffer, and to select the one with fewer invalid tags from two indexed tag groups when updating the branch prediction buffer. The "randomization" means that the index for searching the encrypted branch prediction buffer is randomized, and the two tag groups detected during updates are randomly selected. The security of this mechanism is manifested in that: during the system's lifetime, different processes will not index the same data storage unit in the branch prediction buffer, avoiding reuse attacks. Simultaneously, processes will not index tag groups without invalid tags during their lifetime, avoiding eviction attacks.

[0019] Furthermore, a storage medium storing a computer program, wherein the computer program executes the above-described method.

[0020] Furthermore, an electronic device includes a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the above-described method.

[0021] Compared with existing safe branch prediction buffer mechanisms, the advantages of this invention are:

[0022] This invention eliminates the need to change the key during system operation, reducing the additional overhead of generating and storing keys.

[0023] This invention ensures that different processes will not index the same data storage unit in the branch prediction buffer, thus comprehensively defending against reuse attacks by the same or different threads.

[0024] In this invention, the process will not index a tag group without an invalid tag, thus providing comprehensive defense against eviction attacks from the same or different threads.

[0025] This invention defends against all proposed attacks not only against the branch prediction buffer, but also takes into account the aggressiveness of future more advanced attack algorithms.

[0026] This invention provides security throughout the system's lifecycle. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the branch prediction target buffer structure proposed in this invention;

[0028] Figure 2 This is a schematic diagram of the branch prediction target content search and update mechanism proposed in this invention when the target is not hit. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below through specific embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0030] Example 1: See Figure 1 , Figure 2 A method for enhancing the security of a processor chip branch prediction buffer includes the following steps:

[0031] Step 1: When the system starts, different processes are assigned to different security domains, and the original index number of the branch prediction target buffer of the security domain is obtained;

[0032] Step 2: When the system starts, it generates an index encryption key that is twice the number of security domains and assigns it to different security domains. The key is then applied to the original index of the security domain to obtain a new index number.

[0033] Step 3: Reuse the index encryption key for content encryption;

[0034] Step 4: When querying the branch prediction target content, use the index number to index the two label groups in the label field of the skewed randomization branch prediction target buffer, and select the label group with more invalid labels and the data storage unit pointed to by the label group to store the branch prediction target information.

[0035] Step 5: When updating the branch prediction target content, randomly select two data storage units, choose the data storage unit with fewer invalid tags in the tag group to which the pointed-to tag storage unit belongs, evict it, and store the new branch prediction target content.

[0036] The security domains are divided according to the protection level, which is at the thread level and different processor operating states.

[0037] The encryption key is generated by PRINCE cryptographic hardware circuitry or other random number generation methods.

[0038] The branch prediction target buffer consists of a label field and a data field. The label field comprises several label groups, each with a fixed number of label storage units. Each label group's label storage units are divided into two parts: intrinsic labels and additional labels. The number of intrinsic labels is equal to the product of the number of label groups and the number of data storage units in the data array. The number of additional labels is determined by the designer. The content field consists of a data array containing several data storage units.

[0039] Each tag storage unit has a forward pointer that can point to any data storage unit, and each data storage unit has a forward pointer that can point to any tag storage unit, enabling it to perceive the number of invalid tags in its tag group. An invalid tag refers to a tag storage unit that does not point to a data storage unit, or points to an invalid data storage unit.

[0040] The method of applying the key to the branch prediction buffer index is to XOR the key and the original index of the branch prediction buffer to obtain two new indices. Encrypting the content with the index encryption key means XORing the content with either of the two keys to obtain ciphertext content. When updating the branch prediction target content, the ciphertext is stored, and when the content is indexed, it is decrypted using the key.

[0041] The process uses the branch prediction buffer as follows: When searching the branch prediction buffer, first index the two label groups in the label field and compare the labels. If a match is found, the data unit at the data array position pointed to by the label group's pointer is the indexed data unit. If a match is not found, update the branch prediction buffer, select an invalid label from the label group with more invalid labels, and randomly select two data storage units from the data array in the data field. Determine which of the two data storage units points to the label group with fewer invalid labels, and establish a mutual pointing relationship between this data storage unit and the previous invalid label.

[0042] The "content" and "branch prediction target content" refer to the address of the branch target instruction. "Bias" refers to the tendency to selectively choose the one with more invalid tags from two indexed tag groups when searching the branch prediction buffer, and to selectively choose the one with fewer invalid tags from two indexed tag groups when updating the branch prediction buffer. "Randomization" means that the index for searching the encrypted branch prediction buffer is randomized, and the two tag groups detected during updates are randomly selected. The security of this mechanism is demonstrated by the following: during the system's lifetime, different processes will not index the same data storage unit in the branch prediction buffer, avoiding reuse attacks. Simultaneously, processes will not index tag groups without invalid tags during their lifetime, avoiding eviction attacks.

[0043] Example 2: A storage medium storing a computer program, wherein the computer program executes the above-described method.

[0044] Example 3: An electronic device includes a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the above-described method.

[0045] Example 4: This invention mainly includes four aspects: 1) A method for generating and using private keys for security domains, dividing the program security domains and generating two private security keys for each security domain, ensuring that the randomization seeds used in different security domains are independent of each other; 2) A structural design of a branch prediction buffer that separates the label domain and the data domain, which, combined with the skewed lookup and update mechanism of the branch prediction buffer, achieves security throughout the system's lifecycle; 3) A skewed randomization lookup and update mechanism of the branch prediction buffer, which, combined with the structural design of the branch prediction buffer that separates the label domain and the data domain, achieves security throughout the system's lifecycle.

[0046] The solution adopted by this invention to solve its technical problem mainly includes the following:

[0047] 1) Methods for generating and using private keys in the security domain

[0048] To prevent malicious training or branch prediction targeting information between processes, safety domains are divided using thread-level granularity, with each thread forming a separate safety domain. Similarly, to prevent malicious training or branch prediction targeting information by programs running on different processors, safety domains can be divided according to different running states.

[0049] This invention does not depend on the method of security domain partitioning and can provide security for any form of security domain partitioning.

[0050] Because the keys for different security domains are random, it is impossible to restore the branch target buffer information between different security domains.

[0051] The two keys can be generated using various existing software or hardware random number generation methods, such as pseudo-random number generators and the PRINCE encryption function, including but not limited to the specific techniques mentioned above.

[0052] The key is automatically generated when the system boots up and awaits allocation. When a new security domain appears, the system will dynamically allocate two keys to that security domain.

[0053] The method of applying the key to the branch prediction buffer index is to XOR the key and the original index of the branch prediction buffer respectively to obtain two new indices. Encrypting the content with the index encryption key means XORing the content with either of the two keys to obtain the ciphertext content. When updating the branch prediction target content, the ciphertext is stored, and when the content is indexed, it is decrypted using the key.

[0054] (ii) Branch prediction buffer structure design with separate label and data fields

[0055] This invention decouples and separates the label storage unit and data storage unit of the conventional branch prediction target buffer. Specifically, the branch prediction target buffer is divided into two parts: a label field and a data field.

[0056] A tag field consists of several tag groups, each with a fixed number of tag storage units. The number of tag storage units in each tag group is divided into two parts: an inherent number and an additional number. The inherent number is equal to the product of the tag group's size and the number of data storage units in the data array. The additional number is determined by the designer. Each tag storage unit has a forward pointer that can point to any data storage unit, and each data storage unit has a forward pointer that can point to any tag storage unit, allowing it to perceive the number of invalid tags in its tag group. An invalid tag is one that does not point to a data storage unit or points to an invalid data storage unit.

[0057] The content field consists of a data array, which contains several data storage units.

[0058] Each tag storage unit has a forward pointer that can point to any data storage unit, and each data storage unit has a forward pointer that can point to any tag storage unit, and can perceive the number of invalid tags in its tag group.

[0059] (iii) Branch prediction buffer skewed randomization lookup and update mechanism

[0060] The process uses the branch prediction buffer as follows: When searching the branch prediction buffer, first index the two tag groups in the tag field and compare the tags. If a match is found, the data unit at the data array position pointed to by the tag group's pointer is the indexed data unit. If a match is not found, update the branch prediction buffer, select an invalid tag from the tag group with more invalid tags, and randomly select two data storage units from the data array in the data field. Determine which tag group the two data storage units point to has fewer invalid tags, establish a mutual pointing relationship between this data storage unit and the previous invalid tag, and store the encrypted data.

[0061] The specific steps are illustrated below with examples.

[0062] The branch prediction target buffer is the core module of the current branch predictor. The security enhancement method for the branch prediction target buffer of processor chips based on skewed randomization can be applied to the case of branch prediction target buffer based on branch instruction address index. The following will take a specific branch prediction buffer as an example to introduce the application of this method.

[0063] 1) The original index of the branch prediction target buffer is usually generated by all or part of the bits of the branch instruction address. The length of the selected bit depends on the size of the branch prediction target buffer. For example, if the size is 1KB, the [11:2] bits of the branch instruction address can be used for indexing, and so on.

[0064] 2) XOR the two private keys with the original index to obtain a new index value. Using the two index values, first index the two tag groups in the tag field and compare the tags. If a match is found, the data unit at the data array position pointed to by the pointer of the tag group is the indexed data unit. Select the data in it as the branch prediction jump target and send it into the processor pipeline.

[0065] 3) When the branch target buffer index is not hit, update the branch prediction buffer, select an invalid tag from the tag group with more invalid tags, and randomly select two data storage units in the data array of the data field. Determine which tag group the two data storage units point to has fewer invalid tags, establish a mutual pointing relationship between the data storage unit and the previous invalid tag, and store the data after XORing with the key.

[0066] 4) The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Those skilled in the art can modify or make equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be determined by the claims.

Claims

1. A method for enhancing the security of a processor chip branch prediction target buffer, characterized in that, The method includes the following steps: Step 1: When the system starts, different processes are assigned to different security domains, and the original index number of the branch prediction target buffer of the security domain is obtained; Step 2: When the system starts, it generates an index encryption key that is twice the number of security domains and assigns it to different security domains. The key is then applied to the original index of the security domain to obtain a new index number. Step 3: Reuse the index encryption key for content encryption; Step 4: When querying the branch prediction target content, use the new index number to index the two label groups in the label field of the skewed randomization branch prediction target buffer, and select the label group with more invalid labels and the data storage unit pointed to by the label group to store the branch prediction information. Step 5: When updating the branch prediction target content, randomly select two data storage units, select the data storage unit with fewer invalid tags in the tag group to which the pointed-to tag storage unit belongs, evict it, and store the new branch prediction target content. The method of using the branch prediction buffer in the process is as follows: when searching the branch prediction buffer, first index the two label groups in the label field, compare the labels, if a match is found, the data unit at the data array position pointed to by the pointer of the label group is the indexed data unit; if a match is not found, update the branch prediction buffer, select an invalid label from the label group with more invalid labels, and randomly select two data storage units in the data array of the data field, determine which label group the two data storage units point to has fewer invalid labels, and establish a mutual pointing relationship between the data storage unit and the previous invalid label; The content and branch prediction target content refer to the branch target instruction address. Bias refers to the tendency to select the one with more invalid tags from two indexed tag groups when searching the branch prediction buffer and to select the one with fewer invalid tags from two indexed tag groups when updating the branch prediction buffer. Randomization refers to the randomization of the encrypted index for searching the branch prediction buffer and the randomization of the two indexed tag groups during the update. The security of the mechanism is reflected in the fact that different processes will not index the same data storage unit in the branch prediction buffer during the system's lifecycle, thus avoiding reuse attacks. At the same time, processes will not index tag groups without invalid tags, thus avoiding eviction attacks.

2. The processor chip branch prediction target buffer security enhancement method according to claim 1, characterized in that, In step 1, the security domain is divided according to the protection level, which is the thread granularity and the different running states of the processor.

3. The processor chip branch prediction target buffer security enhancement method according to claim 1, characterized in that, In step 2, the encryption key is generated by the PRINCE cryptographic hardware circuit or other random number generation methods.

4. The processor chip branch prediction target buffer security enhancement method according to claim 1, characterized in that, In step 4, the branch prediction target buffer consists of a label field and a data field. The label field consists of several label groups, each label group has a fixed number of label storage units. The label storage units of each label group are divided into two parts: one part is the inherent labels and the other part is the additional labels. The product of the number of inherent labels and the number of label groups is equal to the number of data storage units in the data array. The number of additional labels is determined by the designer. The content field consists of a data array, which contains several data storage units.

5. The processor chip branch prediction target buffer security enhancement method according to claim 4, characterized in that, Each tag storage unit has a forward pointer that can point to any data storage unit, and each data storage unit has a forward pointer that can point to any tag storage unit. It can sense the number of invalid tags in its tag group. An invalid tag means that the tag storage unit does not point to a data storage unit, or points to an invalid data storage unit.

6. The processor chip branch prediction target buffer security enhancement method according to claim 1, characterized in that, The method of applying the key to the branch prediction buffer index is to XOR the key and the original index of the branch prediction buffer to obtain two new indices. Encrypting the content with the index encryption key means XORing the content with either of the two keys to obtain ciphertext content. When updating the branch prediction target content, the ciphertext is stored, and when the content is indexed, it is decrypted using the key.

7. A storage medium storing a computer program, wherein the computer program executes any one of the processor chip branch prediction target buffer security enhancement methods according to claims 1-6.

8. An electronic device comprising a memory and a processor, the memory storing a computer program, the processor being configured to run the computer program to perform any of the processor chip branch prediction target buffer security enhancement methods of claims 1-6.

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