A method and system for detecting security vulnerabilities in register-transfer level information flow modeling

Abstract

This invention discloses a method and system for detecting security vulnerabilities in register-transfer level information flow modeling. It constructs an information flow security model of the register-transfer level hardware design, extracts security attributes based on the model, and performs security verification based on the extracted attributes. If the security verification passes completely, it indicates that the design meets the given security attributes and there are no security vulnerabilities violating these attributes. Conversely, if the security verification fails, it indicates that the design has security vulnerabilities violating these attributes. This invention enables a formal description of the security behavior and security attributes of register-transfer level hardware design. The constructed register-transfer level information flow security model is entirely described using HDL language, allowing for effective integration with existing EDA testing and verification tools. Thirdly, this invention is deployed in the design and verification phases of the EDA process, thus effectively detecting potential security vulnerabilities within the HDL design early in the design process, providing a design basis for high-reliability hardware design.

Description

Technical Field

[0001] This invention belongs to the field of hardware security, specifically relating to a method and system for detecting security vulnerabilities in register-transfer level information flow modeling. Background Technology

[0002] Hardware, as the root of trust in computer systems, has long been considered secure and reliable. However, the frequent hardware security issues in recent years indicate the existence of numerous security vulnerabilities in hardware. Once exploited by attackers, these vulnerabilities can lead to the leakage of sensitive information, tampering with critical information, loss of system functionality, or even system destruction. However, the functional models and functional correctness verification involved in existing EDA processes are insufficient for qualitative detection of security vulnerabilities. Therefore, it is essential to research modeling methods for hardware design security behavior and qualitative detection methods for hardware security vulnerabilities that can be integrated with EDA processes.

[0003] Information flow analysis techniques have proven capable of modeling and designing security behaviors and attributes from an information flow security perspective. Mainstream hardware information flow analysis methods fall into two main categories: language-level hardware information flow analysis methods and gate-level hardware information flow analysis methods. Language-level hardware information flow analysis methods use type system languages ​​to describe design specifications and security attributes, and then combine static / dynamic checks and theorem proofs to verify whether design behavior conforms to security policies. For example, the Proof Carrying Hardware (PCH) framework provides a formal hardware description language based on high-order logic, Formal-HDL, for translating the security levels of designed and defined signals, and then combines a theorem prover to prove, in a human-computer interactive manner, that the design security behavior conforms to security attribute theorems. Another example is SecVerilog, which extends the syntax and semantics of the Verilog language with a type system, using annotations to explicitly add security types to each variable in the code, and then combining this with the compiler to statically check for violations of information flow security policies during the compilation phase. However, design rewriting requires designers to have a deep understanding of formal languages, and is often accompanied by a huge workload and the possibility of human translation errors. Gate-level hardware information flow analysis differs from language-level hardware information flow analysis. It directly targets the underlying logic of the hardware design, constructing HDL-based information flow tracing logic on top of the gate-level netlist. This logic uses information flow security tag propagation to intuitively reflect the direction of data flow, and then leverages existing EDA testing and verification tools to capture harmful information flow and detect design security flaws. However, low-level gate-level information flow tracing logic cannot capture the intermediate variable relationships caused by return-to-convergence fan-out, potentially leading to false positives; therefore, it cannot accurately identify hardware security vulnerabilities. Summary of the Invention

[0004] The purpose of this invention is to provide a method and system for detecting security vulnerabilities in register-transfer level information flow modeling, so as to overcome the problem of low accuracy in hardware security vulnerability detection in existing technologies.

[0005] A method for detecting security vulnerabilities in register-transfer level information flow modeling includes the following steps:

[0006] S1, Construct an information flow security model for register-transfer level hardware design;

[0007] S2, security attribute extraction based on information flow security model;

[0008] S3. Perform security verification based on the extracted security attributes. If the security verification passes completely, it means that the design meets the given security attributes and there are no security vulnerabilities that violate the security attributes. Otherwise, if the security verification fails, it means that the design has security vulnerabilities that violate the security attributes.

[0009] Preferably, the register-transfer level hardware design includes data flow operations and control flow operations. Data flow operations and control flow operations are defined as functions f:OP(Exp_LHS,Exp_RHS) and m:OP(Exp_LHS,Ctrl,Exp1,Exp2), respectively. Here, Exp_LHS represents the output expression, OP represents the operation type, Ctrl represents the control condition expression, Exp_RHS represents the input expression for the data flow operation, and Exp1 and Exp2 represent the input expressions for the control flow operation. Data flow operations include logical operations, unconditional continuous assignment statements, and unconditional procedural assignment statements. Control flow operations include conditional procedural assignment statements and continuous assignment statements.

[0010] Preferably, the form of continuous assignment statements and procedural assignment statements with unconditional judgments in data flow operations is as follows: the security attribute label of the expression Exp_RHS on the right side of the assignment symbol is assigned to the security attribute label of the expression Exp_LHS on the left side of the assignment symbol. Specifically, the security attribute label propagation logic of the expression Exp_RHS on the right side of the symbol is modeled according to the precise label propagation strategy adopted by the register transfer level information flow security model.

[0011] Preferably, the information flow tracing logic function for conditional assignment statements is represented as m_IFT:

[0012] And Ctrl t ={width,{Single t}}, where width is Exp1 t and Exp2 t The bit width, while Single tThe information flow tracking logic is the phase OR of all bits of Ctrl.

[0013] Preferably, security attributes are extracted based on the information flow security model: high-level security specifications or security requirements are mapped to the register transfer level information flow security model constructed in step S1 through security domain division or security attribute label assignment, and security attributes are formally described in the form of assertions using security parameters.

[0014] Preferably, a two-level security grid is used to divide the design security domain: from the perspective of confidentiality, the design is divided into confidential and non-confidential areas; from the perspective of integrity, the design can be divided into trusted and untrusted areas, and corresponding security labels are assigned to the signals in different areas to characterize their security attributes.

[0015] Preferably, the information flow security model and security attributes of the register transfer level hardware are integrated and sent together to the EDA testing and verification tool for security attribute verification.

[0016] A register-transfer level information flow modeling security vulnerability detection system includes an information flow modeling module, an attribute extraction module, and a verification module;

[0017] The information flow modeling module is used to construct an information flow security model for register-transfer level hardware design.

[0018] The attribute extraction module is used to extract security attributes based on the information flow security model.

[0019] The verification module is used to perform security verification based on the extracted security attributes. If the security verification passes completely, it means that the design meets the given security attributes and there are no security vulnerabilities that violate the security attributes; otherwise, if the security verification fails, it means that the design has security vulnerabilities that violate the security attributes.

[0020] Preferably, the register-transfer level hardware design includes data flow operations and control flow operations. Data flow operations and control flow operations are defined as functions f:OP(Exp_LHS,Exp_RHS) and m:OP(Exp_LHS,Ctrl,Exp1,Exp2), respectively. Here, Exp_LHS represents the output expression, OP represents the operation type, Ctrl represents the control condition expression, Exp_RHS represents the input expression for the data flow operation, and Exp1 and Exp2 represent the input expressions for the control flow operation. Data flow operations include logical operations, unconditional continuous assignment statements, and unconditional procedural assignment statements. Control flow operations include conditional procedural assignment statements and continuous assignment statements.

[0021] Preferably, the form of continuous assignment statements and procedural assignment statements with unconditional judgments in data flow operations is as follows: the security attribute label of the expression Exp_RHS on the right side of the assignment symbol is assigned to the security attribute label of the expression Exp_LHS on the left side of the assignment symbol. Specifically, the security attribute label propagation logic of the expression Exp_RHS on the right side of the symbol is modeled according to the precise label propagation strategy adopted by the register transfer level information flow security model.

[0022] Compared with the prior art, the present invention has the following beneficial technical effects:

[0023] This invention provides a method for detecting security vulnerabilities in register-transfer level (RTL) information flow modeling. It constructs an information flow security model of the RTL hardware design, extracts security attributes based on this model, and performs security verification based on the extracted attributes. If the security verification passes completely, it indicates that the design meets the given security attributes and there are no security vulnerabilities violating these attributes. Conversely, if the security verification fails, it indicates that the design has security vulnerabilities violating these attributes. This invention enables a formal description of the security behavior and attributes of RTL hardware design. The constructed RTL information flow security model is entirely described using HDL language, allowing for effective integration with existing EDA testing and verification tools. Thirdly, this invention is deployed in the design and verification phases of the EDA process, thus effectively detecting potential security vulnerabilities within the HDL design early in the design process, providing a design basis for high-reliability hardware design. Attached Figure Description

[0024] Figure 1 This is a flowchart of the security vulnerability detection method for register transfer level information flow modeling in an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the propagation logic of full attribute tags in an embodiment of the present invention.

[0026] Figure 3 This is a flowchart of the AES encryption algorithm in an embodiment of the present invention.

[0027] Figure 4 This is a schematic diagram of the verification results in an embodiment of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] like Figure 1 As shown, this invention provides a method for detecting security vulnerabilities in register-transfer level (RTL) information flow modeling. It describes the security behavior of RTL designs from an information flow security perspective, verifies design security attributes, and detects hardware security vulnerabilities. Specifically, it includes the following steps:

[0031] S1, Construct an information flow security model for register-transfer level hardware design;

[0032] The register-transfer level information flow security model employs a precise tag propagation strategy, which marks each bit of the signal with fine-grained tags (i.e., single-bit tags), takes into account the impact of the flipping of contaminated inputs on the output, and passes the tags of contaminated inputs to the output.

[0033] Register-transfer level hardware design includes data flow operations and control flow operations. Data flow operations and control flow operations are defined as functions f:OP(Exp_LHS, Exp_RHS) and m:OP(Exp_LHS, Ctrl, Exp1, Exp2), respectively. Here, Exp_LHS represents the output expression, OP represents the operation type, Ctrl represents the control condition expression, Exp_RHS represents the input expression for the data flow operation, and Exp1 and Exp2 represent the input expressions for the control flow operation. Data flow operations include logical operations, unconditional sequential assignment statements, and unconditional procedural assignment statements. Control flow operations include conditional procedural assignment statements and sequential assignment statements.

[0034] Construction of the security attribute label propagation logic for data stream operations:

[0035] The unconditional continuous assignment statements and unconditional procedural assignment statements in data stream operations are relatively simple, requiring only the assignment of the security attribute label of the expression Exp_RHS on the right side of the assignment symbol to the security attribute label of the expression Exp_LHS on the left side of the assignment symbol. Furthermore, considering that the calculation of the security attribute label of the expression Exp_RHS on the right side of the assignment symbol involves combinational logic operations and concatenation operations, this invention models the security attribute label propagation logic of the expression Exp_RHS on the right side of the symbol according to the precise label propagation strategy adopted by the register transfer level information flow security model. The resulting security attribute label propagation logic for data stream operations is shown in Table 1, subdivided into 12 basic data stream operation security attribute label propagation logics: those with concatenation operations, those with AND operations, those with OR operations, and those with bit selection operations. Any combination of these 12 basic data stream operation security attribute label propagation logics can be used to construct security attribute label propagation logics for arbitrarily complex data stream operations.

[0036] Construction of the security attribute label propagation logic for control flow operations:

[0037] Control flow operations mainly involve conditional statements. Consider the control flow operation function m: OP(Exp_LHS, Ctrl, Exp1, Exp2). When the control expression Ctrl is polluted, the inversion of Ctrl will inevitably change the execution path of the operation function m, causing pollution of the output Exp_LHS. If the results of Exp1 and Exp2 are the same, the inversion of Ctrl will not affect the value of Exp_LHS. Therefore, the pollution of Exp_LHS is only related to the pollution of Exp1 and Exp2. Similarly, if the results of Exp1 and Exp2 are different, the inversion of Ctrl will inevitably change the value of Exp_LHS, affecting its value. Therefore, the pollution of Exp_LHS is related to the pollution of Exp1, Exp2, and Ctrl. Furthermore, considering that the control expression Ctrl is multi-bit in actual design, and the inversion of individual bits will not affect the logical truth value of the control expression Ctrl, it is necessary to use the pollution label of each bit in the control expression Ctrl to calculate the pollution label of the entire control expression Ctrl. According to the above rules, the information flow tracing logic function for conditional assignment statements is represented as follows:

[0038] And Ctrl t ={width,{Single t}}, where width is Exp1 t and Exp2 t The bit width, while Single t The information flow tracing logic is a bitwise OR operation for all bits of Ctrl. Figure 2 Taking the "if-else" statement in (a) as an example, its security attribute label propagation logic can be expressed as follows: Figure 2 The logical structure shown in (b) is as follows. Here, x, y, and out are the input and output of the "if-else" statement, respectively, and sel is a three-bit selection line; x t y t out t ,sel t These are their respective security attribute labels. If the selection line sel is true, the logical value of the input x is assigned to the output out, and the security attribute label of the output out is calculated simultaneously; conversely, if the selection line sel is false, the logical value of the input y is assigned to the output out, and the security attribute label of the output out is calculated simultaneously.

[0039] Table 1: Information Flow Tracking Logic for Data Flow Operations

[0040]

[0041] By utilizing the aforementioned security attribute label propagation logic for data flow operations and control flow operations, modeling of arbitrary register transfer level hardware designs can be achieved.

[0042] S2, security attribute extraction based on information flow security model;

[0043] Security specifications or requirements in hardware design are often described using highly abstract natural language. This invention maps these highly abstract security specifications or requirements to the register-transfer level information flow security model constructed in step S1 by dividing the design into security domains or assigning security attribute labels. Security attributes are then formally described using specific security parameters in assertion form. This invention employs a two-level security lattice to divide the design security domains. Specifically, from a confidentiality perspective, the design is divided into confidential and non-confidential areas; from an integrity perspective, it can be divided into trusted and untrusted areas. Corresponding security labels are assigned to signals in different areas to characterize their security attributes.

[0044] S3, perform security verification based on the extracted security attributes;

[0045] The information flow security model and security attributes of the register transfer level hardware generated in steps S1 and S2 above are integrated and sent to an EDA testing and verification tool (such as Mentor Graphics Questa Form) to verify the security attributes.

[0046] If the security verification passes completely, it means that the design meets the given security attributes and there are no security vulnerabilities that violate the security attributes; otherwise, if the security verification fails, it means that the design has security vulnerabilities that violate the security attributes.

[0047] This invention provides a method for detecting security vulnerabilities in register-transfer level information flow modeling, and provides a register-transfer level information flow security model, which formally describes the security behavior and security attributes of register-transfer level hardware design. The register-transfer level information flow security model constructed by this invention is entirely described using HDL language and can be effectively integrated with existing EDA testing and verification tools. Thirdly, this invention is deployed in the design and verification phase of the EDA process, and therefore can effectively detect potential security vulnerabilities in HDL design in the early stages of design, providing a design basis for high-reliability hardware design.

[0048] Example:

[0049] The present invention will now be further described in conjunction with the embodiments and accompanying drawings:

[0050] This invention proposes a register-transfer-level (HDL) information flow modeling security vulnerability detection method to address the threats posed by potential security vulnerabilities in hardware design. First, a register-transfer-level (HDL) information flow security model of the hardware design is constructed using security attribute tag propagation logic. Second, the design is divided according to security specifications or security requirements and mapped to the HDL information flow security model, with security attributes formally described using SystemVerilog assertions. Finally, the assertions are integrated with the constructed HDL information flow security model and fed into a verification tool for validation. If the validation is successful, the original HDL design is considered secure and free of vulnerabilities; otherwise, the verification tool will provide a counterexample. Designers can then modify the HDL design based on the counterexample.

[0051] The hardware environment implemented is as follows: Intel i7-6700 CPU, @3.4G (2 processors) computer, 32.0GB memory; the software environment is: Windows 10 32-bit operating system, modeling tools, verification tool Mentor Graphics QuestaFormal, and logic simulation tool Mentor Graphics Modelsim.

[0052] This invention uses Trust-HUB's AES hardware encryption algorithm core test benchmark as the test object. The AES encryption process includes an encryption core (including various transformations) and a key expansion process. The encryption core's transformation calculations include S-box transformations, row transformations, column transformations, and key XOR transformations. In a 128-bit AES encryption process, a total of 10 rounds of iteration are required, with each subsequent round iterating based on the previous round. The output of the previous round is repeatedly subjected to byte substitution (using an S-box), row shift transformations, column mixing transformations, and key XOR transformations to produce the output of the current round. The key expansion process provides the 128-bit round key required for each round's transformations. A complete calculation of the 128-bit AES encryption algorithm requires 10 rounds of transformations to finally produce the desired ciphertext. The AES encryption algorithm flow is as follows: Figure 3 As shown, this core contains a hardware Trojan that leaks the key. When the input plaintext is all 128 bits, i.e., state = Times new Roman, the hardware Trojan is activated and outputs the key to an external port, Antena.

[0053] Register-transfer-level information flow security model generation:

[0054] Based on the construction method of register-transfer-level information flow security model, a corresponding register-transfer-level information flow security model is constructed for each module in the AES design, and then integrated to form the register-transfer-level information flow security model of the AES design.

[0055] Security attribute generation:

[0056] In this design, the key is security-critical and should not flow to the non-confidential pin, Antena. Therefore, the key and the output Antena are labeled as confidential and non-confidential respectively, and it is observed whether a corrupted key flows to the Antena pin.

[0057] Security verification:

[0058] The verification process requires integrating the register-transfer level information flow security model and security attributes constraining the AES design and inputting them into the verification tool Mentor Graphics QuestaFormal. Passing the verification indicates that the hardware design does not contain any hardware trojans that violate security attributes; otherwise, the hardware design contains hardware trojans. Verification results show that, for example… Figure 4 As shown, the security label Antena_t on the Antena pin changed from "0" to "1", indicating that the information output by the Antena pin contains key information, and the key flows to the Antena pin. Therefore, it can be proven that there is a hardware Trojan in the design that leaks the key to the Antena pin.

[0059] This invention provides a method for detecting security vulnerabilities in register-transfer level information flow modeling, enabling a formal description of the security behavior and attributes of register-transfer level hardware design. The register-transfer level information flow security model constructed by this invention is entirely described using HDL language and can be effectively integrated with existing EDA testing and verification tools. This invention is deployed in the design and verification phases of the EDA process, thus effectively detecting potential security vulnerabilities in HDL design in the early stages of design, and providing a design basis for high-reliability hardware design.

Claims

1. A method for detecting security vulnerabilities in register-transfer level information flow modeling, characterized in that, Includes the following steps: S1, Construct an information flow security model for register-transfer level hardware design; S2, security attribute extraction based on information flow security model; S3. Perform security verification based on the extracted security attributes. If the security verification passes completely, it indicates that the design meets the given security attributes and there are no security vulnerabilities that violate the security attributes. Conversely, if security verification fails, it indicates that the design contains security vulnerabilities that violate security attributes. Register-transfer-level hardware design includes data flow operations and control flow operations, which are defined as functions. and in, This indicates the output expression. Indicates the operation type. This represents a control condition expression. The input expression represents the data stream operation. and The input expression represents the control flow operation; data flow operations include logical operations, consecutive assignment statements with unconditional judgments, and procedural assignment statements with unconditional judgments; control flow operations include procedural assignment statements with conditional judgments and consecutive assignment statements; the form of consecutive assignment statements with unconditional judgments and procedural assignment statements with unconditional judgments in data flow operations is: the expression on the right side of the assignment symbol... The security attribute tag is assigned to the expression on the left side of the assignment operator. The security attribute labels are specifically applied to the right-hand side expressions of the symbols, following the precise label propagation strategy employed in the register-transfer-level information flow security model. The security attribute label propagation logic is modeled; the information flow tracing logic function of conditional assignment statements is represented as follows: and ,in for and The bit width, and for The information flow tracking logic for all bit phases, where Exp_LHS t Ctrl t Exp1 t Exp2 t These are the security attribute tags Exp_LHS, Ctrl, Exp1, and Exp2, respectively.

2. The method for detecting security vulnerabilities in register-transfer level information flow modeling according to claim 1, characterized in that, Security attribute extraction based on information flow security model: High-level abstract security specifications or security requirements are mapped to the register transfer level information flow security model constructed in step S1 through security domain division or security attribute label assignment, and security attributes are formally described in the form of assertions using security parameters.

3. The method for detecting security vulnerabilities in register-transfer level information flow modeling according to claim 2, characterized in that, A two-level security lattice is used to divide the design security domain: from a confidentiality perspective, the design is divided into confidential and non-confidential areas; From an integrity perspective, the design can be divided into trusted and untrusted areas, and corresponding security labels can be assigned to signals in different areas to characterize their security attributes.

4. The method for detecting security vulnerabilities in register-transfer level information flow modeling according to claim 1, characterized in that, The information flow security model and security attributes of the register transfer level hardware are integrated and fed into the EDA testing and verification tool for security attribute verification.

5. A security vulnerability detection system for register-transfer level information flow modeling, characterized in that, It includes an information flow modeling module, an attribute extraction module, and a validation module; The information flow modeling module is used to construct an information flow security model for register-transfer level hardware design. The attribute extraction module is used to extract security attributes based on the information flow security model. The verification module is used to perform security verification based on the extracted security attributes. If the security verification passes completely, it indicates that the design meets the given security attributes and there are no security vulnerabilities that violate the security attributes. Conversely, if security verification fails, it indicates that the design contains security vulnerabilities that violate security attributes. Register-transfer-level hardware design includes data flow operations and control flow operations, which are defined as functions. and in, This indicates the output expression. Indicates the operation type. This represents a control condition expression. The input expression represents the data stream operation. and The input expression represents the control flow operation; data flow operations include logical operations, consecutive assignment statements with unconditional judgments, and procedural assignment statements with unconditional judgments; control flow operations include procedural assignment statements with conditional judgments and consecutive assignment statements; the form of consecutive assignment statements with unconditional judgments and procedural assignment statements with unconditional judgments in data flow operations is: the expression on the right side of the assignment symbol... The security attribute tag is assigned to the expression on the left side of the assignment operator. The security attribute labels are specifically applied to the right-hand side expressions of the symbols, following the precise label propagation strategy employed in the register-transfer-level information flow security model. The security attribute label propagation logic is modeled; the information flow tracing logic function of conditional assignment statements is represented as follows: and ,in for and The bit width, and for The information flow tracking logic for all bit phases, where Exp_LHS t Ctrl t Exp1 t Exp2 t These are the security attribute tags Exp_LHS, Ctrl, Exp1, and Exp2, respectively.

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