A high-energy-efficiency and low-latency BNN hardware accelerator

Abstract

The present invention discloses a high-energy-efficiency, low-latency BNN hardware accelerator, comprising: a global control unit, an input cache unit, an output cache unit, an image processing module, a weight cache unit, and a computing unit module; wherein the global control unit generates a control signal for controlling the image processing module's processing of input images, the reading and writing of data in the input and output cache units and the weight cache unit, and the computing unit module's computing process; the input and output module is used to store input and output images; the image processing module is used to crop the input image to obtain non-all-zero regions; the weight cache unit is used to store weight and bias data; and the computing unit module is used to perform convolution, pooling, and activation operations on non-all-zero regions. The present invention utilizes an all-zero value skipping method to effectively reduce the network's computational load, computational cycle, and computational power consumption, thereby improving the speed and efficiency of handwritten digit image reasoning.

Description

Technical Field

[0001] The present invention belongs to the field of hardware design for integrated circuit artificial intelligence, and specifically relates to a BNN hardware accelerator with high energy efficiency and low latency. Background Art

[0002] In recent years, with the continuous advancement of science and technology, people's production and lifestyles have undergone tremendous changes. The development of artificial intelligence, in particular, has not only made our lives more convenient but also enriched them, allowing us to enjoy the joys of technology. Currently, artificial intelligence has achieved breakthroughs in many fields and has been integrated into every aspect of our lives, such as smart healthcare, autonomous driving, natural language processing, and image recognition.

[0003] Convolutional neural networks (CNNs) are a key technology driving the development of artificial intelligence, favored by researchers due to their flexibility, short development cycles, and strong scalability. However, as network accuracy increases, the depth and scale of neural networks also increase, consuming significant resources and posing significant challenges to the design of CNN accelerators.

[0004] Because the high computational and parameter count of CNNs is detrimental to hardware design, a lightweight neural network, Binary Neural Networks (BNNs), has been proposed. Using the most brute-force quantization method, BNNs reduce the full-precision data in CNNs to just two values: "-1" and "+1." This theoretically reduces storage requirements by a factor of 32. Furthermore, BNNs employ XNOR and bit-counting schemes instead of traditional multiplication-accumulation operations, reducing the complexity of convolution calculations. This approach not only reduces computational effort and parameter count, lowers power consumption, and accelerates network inference, but also eases hardware design, making the application of neural networks feasible on mobile embedded devices.

[0005] Although binary convolutional neural networks have been optimized in many ways compared to traditional convolutional neural networks, the forward derivation implementation of most binary convolutional neural networks is still very computationally intensive, just like traditional convolutional neural networks. This includes the following two issues:

[0006] (1) The problem of increasing the amount of computation due to the value 0 in BNN: During the BNN hardware design process, in order to avoid the resource loss caused by the sign bit representation, the original binary data ("-1" and "+1") will be re-encoded. After encoding, the value 0 is used to represent the original "-1" value, and the value 1 is used to represent the original "+1" value. The result of the calculation of this value 0 with any value is no longer 0, so it cannot be ignored in the calculation process, resulting in an increase in the amount of computation. However, the value 0 in CNN has no meaning, and the result of its multiplication with any number is still 0, so its calculation process can be skipped. This difference in the value of 0 makes many existing 0-value skipping schemes in CNN unable to be directly used in BNN. This will undoubtedly increase the network's computing cycle and power consumption, so it is worthwhile to study how to skip the calculation of the value 0.

[0007] (2) There is a problem of repeated calculation in the convolution layer: In the designed BNN accelerator, since each convolution kernel data is 1 bit, there are only 2 ways to combine the data for a 3×3 convolution kernel. 9 This is much smaller than the 32-bit full-precision data combination in CNN (there are 2 288 If the above 3×3 convolution kernel is split into three 1×3 row convolution kernels, the number of data combinations will be further reduced to only 2. 3 = 8 different values: 000, 001, 010, 011, 100, 101, 110, and 111. During the convolution calculation process, due to weight sharing and multiple output channels, the same input data may be calculated multiple times with the same row of convolution kernel data. These multiple calculations are repetitive and unnecessary, which not only prolongs the calculation cycle but also increases computing power. Summary of the Invention

[0008] In response to the problems existing in the above-mentioned BNN hardware accelerator, the present invention proposes a high-energy-efficiency and low-latency BNN hardware accelerator, in order to effectively reduce the network's computing workload, computing cycle and computing power consumption, thereby improving the inference speed and efficiency of handwritten digital images.

[0009] The technical solution adopted by the present invention to achieve the above-mentioned object is:

[0010] The present invention provides a high-energy-efficiency and low-latency BNN hardware accelerator, which comprises: a global control unit, an input cache unit, an output cache unit, an image processing module, a weight cache unit, and a calculation unit module;

[0011] The weight cache unit is used to store the weight bias parameters of the trained network model;

[0012] The input cache unit is used to store input images loaded from an off-chip cache;

[0013] After the input image is completely loaded into the input buffer unit, the image processing module, under the control of the global control unit, performs an all-zero value detection on the input image to determine the area with non-all-zero values ​​and the area with all-zero values, thereby cropping the input image to retain the non-all-zero value area and obtain a cropped feature map;

[0014] Under the control of the global control unit, the computing unit module obtains the weight bias parameters from the weight cache unit, and performs a convolution operation with the cropped feature map to obtain the convolution result of the current layer. The convolution result of the current layer is accumulated and then normalized, activated and pooled to obtain the pooling result of the current layer. The pooling result of the current layer is then input into the next layer for convolution, accumulation, activation and pooling operations. After the activation operation is completed in the last layer, the predicted category of the image data is obtained and stored in the output cache unit.

[0015] The high energy efficiency and low latency BNN hardware accelerator described in the present invention is also characterized in that: the image processing module includes: a detection circuit and a cropping circuit;

[0016] The detection circuit includes: a primary register module, a secondary register module, and a tertiary register module;

[0017] The first-level register module includes: a register module a1, a buffer module, and an accumulator module;

[0018] The register module a1 receives the external pixel value valid signal data_vld and the global clock signal clk. If data_vld is high and clk reaches a rising edge, the current pixel value of the input image is bitwise ORed with the previous pixel value stored in the register module a1 and saved. Otherwise, the pixel value stored in the register module a1 remains unchanged.

[0019] The buffer module receives an external pixel value valid signal data_vld, a column signal col of a current pixel value, and a global clock signal clk. If data_vld is high and clk reaches a rising edge, a bitwise OR operation is performed on the current pixel value of the input image and the pixel value having the same column signal col in the buffer module and the pixel value is saved; otherwise, the pixel value stored in the buffer module remains unchanged.

[0020] The accumulator module receives an external row read end signal row_end and a global clock signal clk. When row_end is high and clk reaches a rising edge, the accumulator module adds 1 to the accumulated value A stored in itself. Otherwise, the accumulated value A in the accumulator module remains unchanged.

[0021] The secondary register module includes: a first register module r1 and a second register module r2;

[0022] The first register module r1 receives the external column read end signal col_end and the global clock signal clk. If col_end is high and clk reaches a rising edge, the register module a1 saves the stored pixel value to the first register module r1. Otherwise, the pixel value stored in the first register module r1 remains unchanged.

[0023] The second register module r2 receives an external row read end signal row_end and a global clock signal clk. If row_end is high and clk reaches a rising edge, the pixel value stored in the buffer module is saved in the second register module r2. Otherwise, the pixel value stored in the second register module r2 remains unchanged.

[0024] The three-level register module includes: t1 register, t2 register, t3 register, t4 register, and is used to store four coordinate values ​​Ymin, Ymax, Xmin, Xmax of the non-all-zero value area respectively;

[0025] The t1 register receives the external column read end signal col_end, the global clock signal clk and the row signal row of the current pixel value. When col_end is high and clk has not reached the rising edge, the pixel value stored in the first register module r1 is inverted and an AND operation is performed with the pixel value stored in the register module a1. If the result of the AND operation is 1, 1 is subtracted from the row signal row and saved in the t1 register, thereby obtaining the row minimum coordinate value Ymin of the non-all-zero value area. Otherwise, it indicates that the minimum row value has not been detected in the current row. If the minimum row value is still not detected after all rows are detected, 0 is saved in the t1 register, t2 register, t3 register, and t4 register respectively.

[0026] The t2 register receives the external column read end signal col_end, the global clock signal clk and the row signal row of the current pixel value. When col_end is high and clk has not reached the rising edge, the register module a1 inverts the stored pixel value and performs an AND operation with the pixel value stored in the first register module r1. If the result of the AND operation is 1, the row signal row is subtracted by 1 and saved in the t2 register, thereby obtaining the row maximum coordinate value Ymax of the non-all-zero value area; otherwise, it indicates that the maximum row value has not been detected for the current row; if the maximum row value has not been detected after all rows have been detected, the size of the input image is saved in the t2 register;

[0027] The t3 register receives the external row read end signal row_end, the global clock signal clk and the accumulated value A output by the accumulator module. When row_end is at a high level and clk has not reached a rising edge, the second register module r2 inverts the stored pixel value and performs an AND operation with the pixel value stored in the buffer module. If the result of the AND operation is 1, the accumulated value A stored in the accumulator module is subtracted by 1 and saved in the t3 register, thereby obtaining the column minimum coordinate value Xmin of the non-all-zero value area. Otherwise, it indicates that the minimum column value has not been detected in the current column. If the maximum column value has not been detected after all columns have been detected, 0 is saved in the t3 register.

[0028] The t4 register receives the external row read end signal row_end, the global clock signal clk, and the accumulated value A output by the accumulator module. When row_end is at a high level and clk has not reached a rising edge, the pixel value stored in the buffer module is inverted and an AND operation is performed with the pixel value of the register module r2. If the result of the AND operation is 1, the accumulated value A stored in the accumulator module is subtracted by 1 and saved in the t4 register, thereby obtaining the column maximum coordinate value Xmax of the non-all-zero value area. Otherwise, it indicates that the maximum column value has not been detected for the current column. If the maximum column value is still not detected after all columns are detected, the size of the current input image is saved in the t4 register.

[0029] The clipping circuit includes: a multiplier, an adder, and a shift register;

[0030] The multiplier reads the row minimum coordinate value Ymin in the t1 register and multiplies it by the size of the input image to obtain a multiplication result B;

[0031] The adder reads the column minimum coordinate value Xmin in the t3 register and adds it to the multiplication result B to obtain the shift result C of the input image;

[0032] The shift register shifts the input image in the input buffer unit according to the shift result C to obtain a cropped feature map.

[0033] Compared with the prior art, the beneficial technical effects of the present invention are embodied in:

[0034] 1. The present invention adopts an all-0 value skipping method. By analyzing the distribution law of the input feature map data, it is found that when the data in a convolution window are all 0 values, the calculation result will be a fixed constant. The constant can be calculated and saved in advance, and then directly output to the output feature map to skip the calculation process of the 0 value, thereby reducing the amount of calculation; and by designing an all-0 value detection circuit, it is used to detect the area of ​​non-all-0 values ​​in the input feature map, and then derive the area of ​​all-0 values ​​to skip the calculation of these all-0 value areas, thereby reducing the amount of calculation of the network and solving the problem of increased calculation caused by 0 values.

[0035] 2. This paper designs a BNN hardware accelerator based on a field programmable gate array (FPGA). Experimental results show that at a frequency of 100 MHz, the accelerator achieves an average power consumption ratio of 1.81 TOPS / W, at least a 100% improvement in energy efficiency compared to existing BNN accelerator solutions. It can infer a handwritten digit image in just 0.63 μs, with a peak throughput of 3225.6 GOPS. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a network architecture diagram of the network model L_BNN of the present invention;

[0037] Figure 2 This is the overall structure diagram of the accelerator of the present invention;

[0038] Figure 3 Detection circuit diagram of the present invention;

[0039] Figure 4 A cutting circuit diagram for the present invention;

[0040] Figure 5 It is a design diagram of the pre-calculation scheme of the present invention;

[0041] Figure 6 Schematic diagram of the pre-calculation result cache and convolution calculation unit of the present invention. DETAILED DESCRIPTION

[0042] In this embodiment, Figure 1 As shown in the figure, a high-efficiency and low-latency BNN hardware accelerator is designed to address the problem of increased computational complexity and computational cycles caused by a large number of zero values ​​in the hardware design process of a binary neural network (BNN), as well as the problem of increased computational cycles and computational power consumption caused by repeated operations on the same weight data and the same feature map data in the BNN. Figure 2As shown, it includes: a global control unit, an input cache unit, an output cache unit, an image processing module, a weight cache unit, and a calculation unit module;

[0043] The weight cache unit is used to store the weight bias parameters of the trained network model;

[0044] The input cache unit is used to store image data loaded from the off-chip cache;

[0045] After all the image data is loaded into the input buffer unit, the image processing module, under the control of the global control unit, performs an all-zero value detection on the image data to determine the area with non-all-zero values ​​and the area with all-zero values, and then crops the image data to retain the non-all-zero value area to obtain a cropped feature map;

[0046] Under the control of the global control unit, the computing unit module obtains the weight bias parameters from the weight cache unit and performs convolution operation with the cropped feature map to obtain the convolution result of the current layer. The convolution result of the current layer is accumulated and then normalized, activated and pooled to obtain the pooling result of the current layer. The pooling result of the current layer is then input into the next layer for convolution, accumulation, activation and pooling operations until the activation operation is completed in the last layer, and the predicted category of the image data is output.

[0047] The image processing module includes: detection circuit, cropping circuit, such as Figure 3 As shown;

[0048] The detection circuit includes: a first-level register module, a second-level register module, and a third-level register module;

[0049] The first-level register module includes a register module a1, a buffer module, and an accumulator module;

[0050] Register module a1 receives the external pixel value valid signal data_vld and the global clock signal clk. If data_vld is high and clk reaches the rising edge, the pixel value data of the input image is bitwise ORed with the value stored in register module a1 and saved. Otherwise, the value stored in register module a1 remains unchanged.

[0051] The buffer module receives the external pixel value valid signal data_vld, the column signal col of the pixel value data and the global clock signal clk. If data_vld is high and clk reaches the rising edge, the current pixel value of the input image and the pixel value with the same column signal col in the buffer module are bitwise ORed and saved. Otherwise, the value stored in the buffer module remains unchanged.

[0052] The accumulator module receives the external row read end signal row_end and the global clock signal clk. When row_end is high and clk reaches the rising edge, the accumulator module adds 1 to the output value A. Otherwise, the value A of the accumulator module remains unchanged. Through continuous accumulation, the final output value A is the column value of the current pixel value.

[0053] The secondary register module includes: two register modules r1 and r2;

[0054] Register module r1 receives the external column read end signal col_end and the global clock signal clk. If col_end is high and clk reaches a rising edge, the value stored in register module a1 is saved to register module r1. Otherwise, the value stored in register module r1 remains unchanged.

[0055] Register module r2 receives the external row read end signal row_end and the global clock signal clk. If row_end is high and clk reaches the rising edge, the value stored in the buffer module is saved to register module r2. Otherwise, the value stored in register module r2 remains unchanged.

[0056] The three-level register module includes four registers t1, t2, t3, and t4, which store the four coordinate values ​​Ymin, Ymax, Xmin, and Xmax of the non-all-zero value area respectively;

[0057] The t1 register receives the external column read end signal col_end, the global clock signal clk, and the row signal row of the pixel value data. When col_end is high and clk has not reached the rising edge, the value of the register module r1 is inverted and ANDed with the value of the register module a1. If the result of the AND operation is 1, the row signal row is subtracted by 1 and saved in the t1 register to obtain the row minimum coordinate value Ymin of the non-all-zero value area. If the minimum row value is still not detected after all rows are detected, 0 is saved in the t1, t2, t3, and t4 registers respectively.

[0058] The t2 register receives the external column read end signal col_end, the global clock signal clk, and the row signal row of the pixel value data. When col_end is high and clk has not reached the rising edge, the value of register module a1 is inverted and then ANDed with the value of register module r1. If the result of the AND operation is 1, the row signal row is subtracted by 1 and saved in the t2 register to obtain the row maximum coordinate value Ymax of the non-all-zero value area; if all rows are detected and the maximum row value is still not detected, the current input image size is saved in the t2 register;

[0059] The t3 register receives the external row read end signal row_end, the global clock signal clk, and the value A output by the accumulator module. When row_end is high and clk has not reached the rising edge, the value of the register module r2 is inverted and then ANDed with the value of the buffer module. If the result of the AND operation is 1, the value A output by the accumulator module is subtracted by 1 and saved in the t3 register to obtain the column minimum coordinate value Xmin of the non-all-zero value area. Otherwise, 0 is saved in the t3 register.

[0060] The t4 register receives the external row read end signal row_end, the global clock signal clk, and the value A output by the accumulator module. When row_end is high and clk has not reached the rising edge, the value of the buffer module is inverted and then ANDed with the value of the register module r2. If the result of the AND operation is 1, the value A output by the accumulator module is subtracted by 1 and saved in the t4 register to obtain the column maximum coordinate value Xmax of the non-all-zero value area. If all columns are detected and the maximum column value is still not detected, the current input image size is saved in the t4 register.

[0061] The clipping circuit includes a multiplier, an adder, a shift register and an input buffer unit, such as Figure 4 As shown;

[0062] The input buffer unit stores input image data;

[0063] The multiplier reads the minimum row coordinate value Ymin in the t1 register and multiplies it by the input image size to obtain the result B;

[0064] The adder reads the column minimum coordinate value Xmin in the t3 register and adds it to the above result B to obtain the image shift result C;

[0065] The shift register shifts the input image data in the input buffer unit according to the shift result C to obtain the final cropping feature map.

[0066] In specific implementation, the pre-result cache unit solution and hardware design of the computing unit are as follows:

[0067] In the fully binary input feature map, there are only two data values, 0 or 1. Therefore, in the calculation process with the convolution kernel, the input feature map data (size 1×3) corresponding to the convolution kernel of size 1×3 has only 8 combinations (000-111). In order to avoid a large number of repeated calculations in the convolution calculation module, the 8 combinations of input feature map data and the 8 combinations of weight data are pre-calculated, with a total of 64 combinations. After the improvement, the calculation unit can skip the original XNOR and Popcount calculation process and directly look up the table to get the calculation result, and can reduce the number of calculations by 78.3% (before the improvement, calculating the result of a 33 convolution required 9 XNOR operations, 11 addition operations, and 3 shift operations, a total of 23 operations; after the improvement, only 3 table lookups and 2 addition operations are required, a total of 5 operations), reducing computing power consumption;

[0068] like Figure 5 As shown, in the 64 pre-calculated results, it can be found that there are some special calculations in the pre-calculation process. The reason why they are special is that the calculation results of some combinations can be obtained by inverting the results of other combinations, or are equal to the results of other combinations. For example, combination 2 and combination 9 are essentially the same operation, and the data involved in the operation are the same, so the calculation results are the same; for example, combination 19 and combination 43, after bitwise inverting (a1, a2, a3) of combination 19, combination 43 can be obtained, so the result of combination 19 can be inverted to obtain the result of combination 43; for example, combination 27 and combination 38, after bitwise inverting (a1, a2, a3) and (w1, w2, w3) of combination 27, combination 38 can be obtained. Since both inputs are inverted, the final result remains unchanged, so the results of combination 27 and combination 38 are the same. There are many combinations with the above three characteristics, and these characteristics are actually the operation properties of the XNOR gate;

[0069] According to these properties, Figure 5 The pre-calculated results shown in (b) are compressed, and the compressed pre-calculated results are as follows Figure 5 As shown in (c), it can be seen that after compression, there are only 10 combinations, with a compression rate of 84.4%, which can further reduce the hardware resource overhead caused by pre-calculation cache;

[0070] Figure 6 The figure shows the hardware design of the pre-calculation result cache unit and the convolution calculation unit. The pre-calculation result cache unit is composed of a 10×3 register stack, which stores the compressed calculation results of 10 weights and input feature map data combinations. The index address of the pre-calculation result cache unit is 4 bits because the highest bit of the input feature map data and weight data is 0, so the highest bit can be omitted.

[0071] The convolution calculation unit consists of three PE arrays and an adder tree to implement a 3×3 convolution kernel calculation. Each PE array consists of 8×14 PE units, which can implement an 8×14 row convolution kernel calculation at a time. 8 represents 8 input channels, and 14 represents 14 rows of convolution data for each input channel. Each PE unit implements a 1×3 row convolution kernel operation.

[0072] The convolution calculation unit obtains the calculation results by accessing the pre-calculation result cache unit. The specific operation process is as follows:

[0073] Step 1: When the input feature map data and weight data enter the convolution calculation unit, the data will first be distributed to 3 groups of PE_ arrays, and then each PE array will be distributed again, and the data will be distributed to each PE unit to participate in the calculation.

[0074] Step 2: Sort the input feature map data and weight data by size in the PE unit, and use the sorted result as the index address of the pre-calculated result cache to find the corresponding result.

[0075] Step 3: Determine whether the result read from the pre-calculated result cache needs to be inverted based on the XOR result of the highest bit of the input feature map data and the weight data. If the XOR result is 1, it means that the read result does not need to be inverted; otherwise, it needs to be inverted.

[0076] Step 4: The results of the three PE arrays are accumulated through an addition tree to obtain a complete convolution kernel operation result, which is output to the pooling unit for pooling operation.

Claims

1. A high-energy-efficiency, low-latency BNN hardware accelerator, characterized by: include: Global control unit, input cache unit, output cache unit, image processing module, weight cache unit, calculation unit module; The weight cache unit is used to store the weight bias parameters of the trained network model; The input cache unit is used to store input images loaded from an off-chip cache; After the input image is completely loaded into the input buffer unit, the image processing module, under the control of the global control unit, performs an all-zero value detection on the input image to determine the area with non-all-zero values ​​and the area with all-zero values, thereby cropping the input image to retain the non-all-zero value area and obtain a cropped feature map; Under the control of the global control unit, the computing unit module obtains the weight bias parameters from the weight cache unit, and performs a convolution operation with the cropped feature map to obtain the convolution result of the current layer. The convolution result of the current layer is accumulated and then normalized, activated and pooled to obtain the pooling result of the current layer. The pooling result of the current layer is then input into the next layer for convolution, accumulation, activation and pooling operations. After the activation operation is completed in the last layer, the predicted category of the image data is obtained and stored in the output cache unit.

2. The high-energy-efficiency, low-latency BNN hardware accelerator according to claim 1, characterized in that: The image processing module includes: a detection circuit and a cropping circuit; The detection circuit includes: a primary register module, a secondary register module, and a tertiary register module; The first-level register module includes: a register module a1, a buffer module, and an accumulator module; The register module a1 receives the external pixel value valid signal data_vld and the global clock signal clk. If data_vld is high and clk reaches a rising edge, the current pixel value of the input image is bitwise ORed with the previous pixel value stored in the register module a1 and saved. Otherwise, the pixel value stored in the register module a1 remains unchanged. The buffer module receives an external pixel value valid signal data_vld, a column signal col of a current pixel value, and a global clock signal clk. If data_vld is high and clk reaches a rising edge, a bitwise OR operation is performed on the current pixel value of the input image and the pixel value having the same column signal col in the buffer module and the pixel value is saved; otherwise, the pixel value stored in the buffer module remains unchanged. The accumulator module receives an external row read end signal row_end and a global clock signal clk. When row_end is high and clk reaches a rising edge, the accumulator module adds 1 to the accumulated value A stored in itself. Otherwise, the accumulated value A in the accumulator module remains unchanged. The secondary register module includes: a first register module r1 and a second register module r2; The first register module r1 receives the external column read end signal col_end and the global clock signal clk. If col_end is high and clk reaches a rising edge, the register module a1 saves the stored pixel value to the first register module r1. Otherwise, the pixel value stored in the first register module r1 remains unchanged. The second register module r2 receives an external row read end signal row_end and a global clock signal clk. If row_end is high and clk reaches a rising edge, the pixel value stored in the buffer module is saved in the second register module r2. Otherwise, the pixel value stored in the second register module r2 remains unchanged. The three-level register module includes: t1 register, t2 register, t3 register, t4 register, and is used to store four coordinate values ​​Ymin, Ymax, Xmin, Xmax of the non-all-zero value area respectively; The t1 register receives the external column read end signal col_end, the global clock signal clk and the row signal row of the current pixel value. When col_end is high and clk has not reached the rising edge, the pixel value stored in the first register module r1 is inverted and an AND operation is performed with the pixel value stored in the register module a1. If the result of the AND operation is 1, 1 is subtracted from the row signal row and saved in the t1 register, thereby obtaining the row minimum coordinate value Ymin of the non-all-zero value area. Otherwise, it indicates that the minimum row value has not been detected in the current row. If the minimum row value is still not detected after all rows are detected, 0 is saved in the t1 register, t2 register, t3 register, and t4 register respectively. The t2 register receives the external column read end signal col_end, the global clock signal clk and the row signal row of the current pixel value. When col_end is high and clk has not reached the rising edge, the register module a1 inverts the stored pixel value and performs an AND operation with the pixel value stored in the first register module r1. If the result of the AND operation is 1, the row signal row is subtracted by 1 and saved in the t2 register, thereby obtaining the row maximum coordinate value Ymax of the non-all-zero value area; otherwise, it indicates that the maximum row value has not been detected for the current row; if the maximum row value has not been detected after all rows have been detected, the size of the input image is saved in the t2 register; The t3 register receives the external row read end signal row_end, the global clock signal clk and the accumulated value A output by the accumulator module. When row_end is at a high level and clk has not reached a rising edge, the second register module r2 inverts the stored pixel value and performs an AND operation with the pixel value stored in the buffer module. If the result of the AND operation is 1, the accumulated value A stored in the accumulator module is subtracted by 1 and saved in the t3 register, thereby obtaining the column minimum coordinate value Xmin of the non-all-zero value area. Otherwise, it indicates that the minimum column value has not been detected in the current column. If the maximum column value has not been detected after all columns have been detected, 0 is saved in the t3 register. The t4 register receives the external row read end signal row_end, the global clock signal clk, and the accumulated value A output by the accumulator module. When row_end is at a high level and clk has not reached a rising edge, the pixel value stored in the buffer module is inverted and an AND operation is performed with the pixel value of the register module r2. If the result of the AND operation is 1, the accumulated value A stored in the accumulator module is subtracted by 1 and saved in the t4 register, thereby obtaining the column maximum coordinate value Xmax of the non-all-zero value area. Otherwise, it indicates that the maximum column value has not been detected for the current column. If the maximum column value is still not detected after all columns are detected, the size of the current input image is saved in the t4 register. The clipping circuit includes: a multiplier, an adder, and a shift register; The multiplier reads the row minimum coordinate value Ymin in the t1 register and multiplies it by the size of the input image to obtain a multiplication result B; The adder reads the column minimum coordinate value Xmin in the t3 register and adds it to the multiplication result B to obtain the shift result C of the input image; The shift register shifts the input image in the input buffer unit according to the shift result C to obtain a cropped feature map.

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