Integrated circuit chip package without lead frame

Abstract

Embodiments of the present disclosure relate to an integrated circuit chip package that does not utilize a leadframe. An integrated circuit die includes a semiconductor substrate, an interconnect layer including bond pads, and a passivation layer covering the interconnect layer and including openings at the bond pads. The passivation layer supports a conductive redistribution layer including conductive wires and conductive vias. An insulating layer covers the conductive redistribution layer and the passivation layer. Trenches formed in an upper surface of the insulating layer define pedestal regions in the insulating layer. Vias extend from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and contact a portion of the conductive redistribution layer. Metal pads are formed at the upper surface of each pedestal region in contact with the vias associated therewith. The metal pads are used for leads of a quad flat no-lead (QFN) type package.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 304,087, filed January 28, 2022, the disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present invention relates generally to packaging of integrated circuit chips, and in particular to integrated circuit chip packaging that does not utilize a leadframe. BACKGROUND

[0004] Reference is made to Figure 1 which shows a cross-section of a conventional integrated circuit package 10 (e.g., quad flat no-lead (QFN) type). A leadframe 12, e.g., made of copper, includes die pads 12a and a plurality of leads 12b extending outwardly from the die pads 12a. An integrated circuit die 16 is mounted to the upper surfaces of the die pads 12a using an adhesive material. The integrated circuit die 16 includes a semiconductor (e.g., silicon) substrate 16a and an interconnect layer 16b extending over the substrate 16a. The substrate 16a supports a plurality of integrated circuit devices, such as transistors. The interconnect layer 16b includes a plurality of metallization layers supporting interconnect lines and interconnect vias, and a plurality of bond pads 16c. Bond wires 18 electrically connect the bond pads 16c to the leads 12b. An encapsulant 20 encapsulates the leadframe 12, the integrated circuit die 16, and the bond wires 18. SUMMARY

[0005] In one embodiment, a leadframe-free integrated circuit package includes: an integrated circuit die including: a semiconductor substrate having a front side; an interconnect layer extending over the front side of the semiconductor substrate, wherein the interconnect layer includes a plurality of bond pads; and a passivation layer covering an upper surface of the interconnect layer and including openings at the bond pads; a conductive redistribution layer supported by the upper surface of the passivation layer, the conductive redistribution layer including conductive lines extending over the passivation layer and conductive vias extending through the openings in the passivation layer to contact the bond pads; an insulating layer covering the conductive redistribution layer and the passivation layer, wherein the insulating layer includes a plurality of channels formed in an upper surface thereof to define a plurality of pedestal regions in the insulating layer; a via extending from an upper surface of the pedestal region through the pedestal region and the insulating layer to reach and contact a portion of the conductive redistribution layer; and a metal pad formed at the upper surface of the pedestal region and in contact with the via.

[0006] In one embodiment, a method for forming a leadless frame integrated circuit package includes: providing an integrated circuit including: a semiconductor substrate having a front side; an interconnect layer extending over the front side of the semiconductor substrate, wherein the interconnect layer includes a plurality of bond pads; and a passivation layer covering an upper surface of the interconnect layer and including openings at the bond pads; forming a conductive redistribution layer supported by the upper surface of the passivation layer, the conductive redistribution layer including conductive wires extending over the passivation layer and conductive vias extending through the openings in the passivation layer to contact the bond pads; laminating a stack including an insulating layer and a metal layer over the conductive redistribution layer; forming a plurality of openings in the metal layer; extending the plurality of openings through the insulating layer to the conductive redistribution layer; electroplating to fill the plurality of openings with metal to form vias; patterning the metal layer to form a plurality of metal pads in contact with the vias; and forming a plurality of trenches in the insulating layer to define a footprint region of the insulating layer at each metal pad.

[0007] In one embodiment, a leadless frame integrated circuit package includes: an integrated circuit die having a front surface including a plurality of bond pads and a passivation layer; a conductive redistribution layer over the passivation layer and electrically connected to the plurality of bond pads; an insulating layer over the conductive redistribution layer, wherein the insulating layer includes a plurality of trenches defining a plurality of footprint regions; a via extending through each footprint region to reach and contact the conductive redistribution layer; and a metal pad at an upper surface of each footprint region and in contact with its via.

[0008] In one embodiment, a leadless frame integrated circuit package includes: an integrated circuit die having a front surface including a plurality of bond pads and a passivation layer; an encapsulation surrounding sides and a back of the integrated circuit die; a conductive redistribution layer over the passivation layer and electrically connected to the plurality of bond pads; an insulating layer over the conductive redistribution layer and the encapsulation, wherein the insulating layer includes a plurality of trenches defining a plurality of footprint regions; a via extending through each footprint region to reach and contact the conductive redistribution layer; and a metal pad at an upper surface of each footprint region and in contact with its via. BRIEF DESCRIPTION OF DRAWINGS

[0009] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings in which:

[0010] Figure 1 A cross-sectional view of a conventional integrated circuit package is shown.

[0011] Figure 2 A cross-sectional view of a chip size integrated circuit package without a lead frame is shown.

[0012] Figure 3 is Figure 2 A plan view of the chip size integrated circuit package shown in FIG. 1.

[0013] Figure 4 A chip size integrated circuit package as shown in Figure 2 is mounted on a support substrate.

[0014] Figure 5 A cross-sectional view of a chip scale integrated circuit package without a leadframe is shown.

[0015] Figure 6 is Figure 5 A plan view of a chip scale integrated circuit package as shown in

[0016] Figure 7 A chip size integrated circuit package as shown in Figure 5 is mounted on a support substrate.

[0017] Figures 8A-8J Steps of a manufacturing process for manufacturing a chip size integrated circuit package as shown in Figure 2 are shown.

[0018] Figures 9A-9N Steps of a manufacturing process for manufacturing a chip scale integrated circuit package as shown in Figure 5 are shown. DETAILED DESCRIPTION

[0019] Reference is made to Figure 2 , Figure 2A cross-sectional view of a chip-size integrated circuit package 100 that does not utilize a leadframe is shown. An integrated circuit die 102 includes a semiconductor (e.g., silicon) substrate 102a having a front side and a back side. The substrate 102a supports a plurality of integrated circuit devices, such as transistors, at the front side. An insulating coating 102b is mounted to the back side. An interconnect layer 102c extends over the front side of the substrate 102a. The interconnect layer 102c includes a plurality of metallization layers that support interconnect lines and interconnect vias, and a plurality of bond pads 102d. A passivation layer 102e covers an upper surface of the interconnect layer 102c, and includes openings that expose the bond pads 102d. A conductive redistribution layer (RDL) 104 is supported by the upper surface of the passivation layer 102e. The RDL 104 includes conductive lines 104a that extend over the passivation layer 102e and conductive vias 104b that extend through openings in the passivation layer 102e to contact the bond pads 102d. A resin layer 106 covers the RDL 104 and the passivation layer 102e. The resin layer 106 includes a plurality of channels 106a formed in an upper (i.e., front) surface. In a preferred implementation, the channels 106a have a depth from the upper surface that is less than a thickness of the resin layer 106 (however, it should be noted that in alternative embodiments, the channels 106a can extend completely through the resin layer 106 to reach the upper surface of the passivation layer 102e). The channels 106a define a plurality of pedestal (or standoff) regions 106b in the resin layer 106. Each pedestal region 106b includes a via 106c that extends from an upper surface of the pedestal region 106b to reach and contact a portion of the RDL 104 (e.g., along one of the conductive lines 104a). Metal pads 110 are formed at the upper surface of each pedestal region 106b in contact with the associated via 106c.

[0020] Figure 3 A plan view of the upper surface of the chip-size integrated circuit package 100 is shown. It should be noted that the channels 106a separate the metal pads 110. An arrangement of the metal pads 110 in a regular array is preferred, but not required. Providing metal pads 110 that all have the same shape and area is one example implementation, and it should be understood that the arrangement of the metal pads in size and location is a matter of design choice.

[0021] Figure 4 Installation of the chip-size integrated circuit package 100 onto a support substrate 140 (e.g., a printed circuit board) is shown. Solder 142 connections are formed between the metal pads 110 of the package 100 and metal pads 144 of the support substrate 140. It should be noted here that the pedestal regions 106b act as standoffs that space the integrated circuit die 102 from an upper surface of the support substrate 140. The metal pads 110 form leads of a quad flat no-lead (QFN) type package.

[0022] It should be noted that the size and shape of the peripheral side edges of package 100 are identical to the size and shape of the peripheral side edges of integrated circuit die 102. Package 100 is accordingly "chip size," having the same width and length dimensions as integrated circuit die 102. In this configuration, the die / package area ratio of package 100 is equal to 1.

[0023] Referring to Figure 5 , Figure 5 A cross-sectional view of a chip-level integrated circuit package 200 is shown that does not utilize a leadframe. Integrated circuit die 202 includes a semiconductor (e.g., silicon) substrate 202a having a front side and a back side. Substrate 202a supports a plurality of integrated circuit devices, such as transistors, at the front side. An interconnect layer 202c extends over the front side of substrate 202a. Interconnect layer 202c includes a plurality of metallization layers that support interconnect lines and interconnect vias, as well as a plurality of bond pads 202d. A passivation layer 202e covers the upper surface of interconnect layer 202c, and includes openings that expose bond pads 202d. Integrated circuit die 202 is encapsulated in an encapsulant 203 that surrounds the peripheral side edges of substrate 202a, interconnect layer 202c, and passivation layer 202e, and covers the back side of substrate 202a. The upper surface of passivation layer 202e is not covered by encapsulant 203. A conductive redistribution layer (RDL) 204 is supported by the upper (coplanar) surfaces of passivation layer 202e and encapsulant 203. RDL 204 includes conductive lines 204a that extend over passivation layer 202e, and conductive vias 204b that extend through openings in passivation layer 202e to contact bond pads 202d. A resin layer 206 covers RDL 204, passivation layer 202e, and encapsulant 203. Resin layer 206 includes a plurality of channels 206a formed in the upper (i.e., front) surface. In a preferred implementation, the depth of channels 206a from the upper surface is less than the thickness of resin layer 206 (however, it should be noted that in alternative embodiments, the depth of channels 206a can completely through resin layer 206 to reach the upper surface of passivation layer 202e). Channels 206a define a plurality of pedestal (or standoff) regions 206b in resin layer 206. Each pedestal region 206b includes a via 206c that extends from the upper surface of pedestal region 206b to reach and contact a portion of RDL 204 (e.g., along one of conductive lines 204a). Metal pads 210 are formed at the upper surface of each pedestal region 206b, in contact with the associated via 206c.

[0024] Figure 6 A plan view of the upper side of chip size integrated circuit package 200 is shown. A regular array of metal pads 210 is preferred, but not required. Providing metal pads 210 that are all the same shape and area is one exemplary implementation, and it should be understood that the arrangement of metal pads in size and location is a matter of design choice.

[0025] Figure 7 A chip-sized integrated circuit package 200 is shown mounted to a support substrate 140 (e.g., a printed circuit board). A solder 142 connection is formed between a metal pad 210 of the package 200 and a metal pad 144 of the support substrate 140. It is noted here that the base region 206b serves as a standoff to space the integrated circuit die 202 from the upper surface of the support substrate 140. The metal pad 210 forms a lead of a quad flat no-lead (QFN) type package.

[0026] It is noted that the size and shape of the peripheral side edges of the package 200 are larger than the size and shape of the peripheral side edges of the integrated circuit die 202. The package 200 is accordingly "chip-scale", having larger width and length dimensions than the integrated circuit die 202. In this configuration, the die / package area ratio of the package 200 is very close to 1.

[0027] Reference is now made to Figures 8A-8J which shows steps of a manufacturing process for fabricating the package 100.

[0028] Figure 8A — A semiconductor wafer includes a semiconductor substrate layer 102a having a front side and a back side. The wafer includes a plurality of integrated circuit regions 800, each supporting a plurality of integrated circuit devices, such as transistors, at the front side of the semiconductor layer 102a. An insulating coating 102b is mounted at the back side of the wafer. An interconnect layer 102c extends over the front side of the substrate 102a. The interconnect layer 102c includes a plurality of metallization layers supporting interconnect lines and interconnect vias, and a plurality of bond pads 102d.

[0029] Figure 8B — A passivation layer 102e is formed over the semiconductor wafer to cover the interconnect layer 102c. An opening 802 in the passivation layer 102e exposes the bond pads 102d.

[0030] Figure 8C — An electrically conductive redistribution layer (RDL) 104 is then formed on the passivation layer 102e. The RDL 104 includes conductive lines and conductive vias (which fill the opening 802). The RDL 104 can be formed, for example, using deposition of a blanket metal layer, followed by patterning by photolithography.

[0031] Figure 8D — A stack including a resin layer 806 and an electrically conductive layer 808 is then laminated to the RDL 104 and the passivation layer 102e. The electrically conductive layer 808 can be made, for example, of copper or an alloy including copper.

[0032] Figure 8E— Openings 810 are then formed to extend through the conductive layer 808. For example, the openings 810 can be formed using a laser drilling process.

[0033] Figure 8F — The openings 810' are then extended through the resin layer 806 and to the RDL 104. The extension of the openings 810' in the resin layer 806 can be formed, for example, using a plasma etching process.

[0034] Figure 8G — A plating process is then used to fill the openings 810' with a conductive material that forms the vias 106c.

[0035] Figure 8H — The conductive layer 808 is then photopatterned to form the metal pads 110. The conductive layer 808 can be patterned using conventional masking and etching processes by forming openings 812 that extend through the conductive layer 808.

[0036] Figure 8I — Trenches 106a (aligned with the openings 812) are then formed in the resin layer 806 to define the pedestal regions 106b. Any suitable plasma etching process can be used to form the trenches 106a, while using the photopatterned metal pads 110 and openings 812 as etching masks.

[0037] Figure 8J — A conventional wafer dicing process is then performed to cut the wafer into a plurality of packages 100. The dicing can be done using a sawing process along the scribe lines 816.

[0038] Reference is now made to Figures 9A-9N which shows steps of a manufacturing process for manufacturing the package 200.

[0039] Figure 9A — The semiconductor wafer includes a semiconductor substrate layer 202a having a front side and a back side. The wafer includes a plurality of integrated circuit regions 900, each supporting a plurality of integrated circuit devices, such as transistors, at the front side of the semiconductor layer 202a. An interconnect layer 202c extends over the front side of the substrate 202a. The interconnect layer 202c includes a plurality of metallization layers that support interconnect lines and interconnect vias, as well as a plurality of bond pads 202d.

[0040] Figure 9B — A passivation layer 202e is formed over the semiconductor wafer to cover the interconnect layer 202c. Openings 902 in the passivation layer 202e expose the bond pads 202d.

[0041] Figure 9C— A conductive redistribution layer (RDL) 204 is then formed on the passivation layer 202e. The RDL 204 includes conductive lines and conductive vias (which fill the openings 902). The RDL 204 can be formed, for example, using deposition of a blanket metal layer, followed by patterning by photolithography.

[0042] Figure 9D — A conventional wafer singulation process is then performed to cut the wafer into a plurality of integrated circuit chips 906. Singulation can be accomplished using a sawing process along the scribe lines 904.

[0043] Figure 9E — The individual integrated circuit chips 906 are then flipped upside down and mounted to a chip carrier board 908. The board 908 is formed of a rigid support layer 908a and a compressible layer 908b that conforms to and surrounds the RDL 204.

[0044] Figure 9F — A molding process is then performed to mold an encapsulation material 910 around each integrated circuit chip 906.

[0045] Figure 9G — The chip carrier board 908 is then removed, and a structure 912 formed of the integrated circuit chips 906 encapsulated by the encapsulation material 910 is flipped upside down.

[0046] Figure 9H — A stack including a resin layer 914 and a conductive layer 916 is then laminated to the RDL 204 and the passivation layer 202e. The conductive layer 916 can be made of, for example, copper or an alloy including copper.

[0047] Figure 9I — An opening 920 is then formed to extend through the conductive layer 916. The opening 920 can be formed, for example, using a laser drilling process.

[0048] Figure 9J — The opening 920' is then extended to pass through the resin layer 914 and to the RDL 204. The extension of the opening 920' in the resin layer 914 can be formed, for example, using a plasma etching process.

[0049] Figure 9K — A plating process is then used to fill the opening 920' with a conductive material that forms the via 206c.

[0050] Figure 9L — The conductive layer 916 is then photolithographically patterned to form the metal pads 210. The conductive layer 916 can be patterned using conventional masking and etching processes by forming openings 924 that extend through the conductive layer 916.

[0051] Figure 9M— The trench 206a (aligned with the opening 924) is then formed in the resin layer 914 to define the pedestal region 206b. Any suitable plasma etching process can be used to form the trench 206a in the structure 926, while using the lithographically patterned metal pad 210 and the opening 924 as an etch mask.

[0052] Figure 9N — A conventional wafer singulation process is then performed to cut the structure 926 into multiple packages 200. Singulation can be accomplished using a sawing process along the scribe lines 928.

[0053] The packages 100 and 200 have many advantages over conventional package designs that utilize a leadframe (see, e.g., U.S. Patent No. 6,372,135). Figure 1 There is a high die / package area ratio, which can equal 1 for the package 100 and is very close to 1 for the package 200. Due to the thick copper pads 110, 210 and the use of the pedestals 106b, 206b as standoffs, the packages 100, 200 have high thermal coefficient on board (TCOB) characteristics and higher package reliability. The packages 100 and 200 also advantageously present a low profile when mounted. The packages 100 and 200 further support improved thermal and electrical performance.

[0054] While the application has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered illustrative or exemplary and not restrictive; the application is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A leadless frame integrated circuit package, comprising: an integrated circuit die including a semiconductor substrate having a front side, an interconnect layer extending over the front side of the semiconductor substrate, wherein the interconnect layer includes a plurality of bond pads, and a passivation layer covering an upper surface of the interconnect layer and including openings at the plurality of bond pads; a conductive redistribution layer supported by an upper surface of the passivation layer, the conductive redistribution layer including conductive lines extending over the passivation layer and conductive vias extending through the openings in the passivation layer to contact the plurality of bond pads; an insulating layer covering the conductive redistribution layer and the passivation layer, wherein the insulating layer includes a plurality of channels formed in an upper surface thereof to define a plurality of pedestal regions in the insulating layer; a via extending from an upper surface of the pedestal regions through the pedestal regions and the insulating layer to reach and contact a portion of the conductive redistribution layer; and a metal pad formed at the upper surface of the pedestal regions and in contact with the via.

2. The integrated circuit package of claim 1, wherein the insulating layer is made of a resin material.

3. The integrated circuit package of claim 1, wherein a die / package area ratio is equal to 1.

4. The integrated circuit package of claim 1, wherein a depth of each channel of the plurality of channels is less than a thickness of the insulating layer.

5. The integrated circuit package of claim 1, further comprising a protective layer on a back surface of the semiconductor substrate.

6. The integrated circuit package of claim 1, further comprising an encapsulant surrounding side edges and a back surface of the semiconductor substrate.

7. The integrated circuit package of claim 6, wherein a die / package area ratio of the encapsulant is close to 1.

8. The integrated circuit package of claim 1, wherein the metal pad forms a lead of a quad flat no-lead (QFN) type package.

9. A method for forming a leadless frame integrated circuit package, comprising: providing an integrated circuit including a semiconductor substrate having a front side, an interconnect layer extending over the front side of the semiconductor substrate, wherein the interconnect layer includes a plurality of bond pads, and a passivation layer covering an upper surface of the interconnect layer and including openings at the plurality of bond pads; forming a conductive redistribution layer supported by an upper surface of the passivation layer, the conductive redistribution layer including conductive lines extending over the passivation layer and conductive vias extending through the openings in the passivation layer to contact the plurality of bond pads; laminating a stack including an insulating layer and a metal layer over the conductive redistribution layer; forming a plurality of openings in the metal layer; extending the plurality of openings through the insulating layer to reach the conductive redistribution layer; electroplating to fill the plurality of openings with metal to form vias; patternizing the metal layer to form a plurality of metal pads in contact with the vias; and a plurality of channels are formed in the insulating layer to define a pedestal region of the insulating layer at each metal pad.

10. The method of claim 9, wherein a depth of each channel of the plurality of channels is less than a thickness of the insulating layer.

11. The method of claim 9, further comprising forming a protective layer on a back surface of the semiconductor substrate.

12. The method of claim 9, further comprising encapsulating the integrated circuit in an encapsulant.

13. The method of claim 9, wherein the insulating layer is made of a resin material.

14. A leadless frame integrated circuit package, comprising: an integrated circuit die having a front surface including a plurality of bond pads and a passivation layer; a conductive redistribution layer over the passivation layer and electrically connected with the plurality of bond pads; an insulating layer over the conductive redistribution layer, wherein the insulating layer includes a plurality of channels defining a plurality of pedestal regions; a via extending through each pedestal region to reach and contact the conductive redistribution layer; and a metal pad at an upper surface of each pedestal region and in contact with its via.

15. The integrated circuit package of claim 14, wherein a depth of each channel of the plurality of channels is less than a thickness of the insulating layer.

16. The integrated circuit package of claim 14, wherein the metal pads form leads of a quad flat no-lead (QFN) type package.

17. A leadless frame integrated circuit package, comprising: an integrated circuit die having a front surface including a plurality of bond pads and a passivation layer; an encapsulant surrounding side and back surfaces of the integrated circuit die; a conductive redistribution layer over the passivation layer and electrically connected with the plurality of bond pads; an insulating layer over the conductive redistribution layer and the encapsulant, wherein the insulating layer includes a plurality of channels defining a plurality of pedestal regions; a via extending through each pedestal region to reach and contact the conductive redistribution layer; and a metal pad at an upper surface of each pedestal region and in contact with its via.

18. The integrated circuit package of claim 17, wherein a depth of each channel of the plurality of channels is less than a thickness of the insulating layer.

19. The integrated circuit package of claim 17, wherein the metal pads form leads of a quad flat no-lead (QFN) type package. ​ ​

Images