A grid line preparation method for improving efficiency and reducing cost of silicon heterojunction solar cells

Abstract

A kind of grid line preparation method for silicon heterojunction solar cell efficiency improvement and cost reduction belongs to solar cell field. Grid line pattern is formed on the substrate deposited with silicon nitride by laser, after removing loss layer after alkali washing process, then depositing passivation layer and back field layer can effectively avoid the passivation layer damage problem caused by laser, and avoid the parasitic absorption of front amorphous silicon layer and TCO.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, specifically to a method for preparing a solar cell and its electrodes. Background Technology

[0002] Silicon heterojunction (SHJ) solar cells are expected to become the next generation of mass-produced solar cells due to their high open-circuit voltage, low-temperature fabrication process, and simple manufacturing steps. However, because the front side of SHJ cells requires full-area coverage with a transparent conductive oxide (TCO) film and an amorphous silicon (a-Si) film to transport charge carriers, the absorption of free charge carriers by the TCO and a-Si films leads to the loss of short-circuit current, affecting the cell's conversion efficiency. Furthermore, the low-temperature fabrication process of SHJ cells limits the use of low-temperature silver paste with higher silver consumption to screen-print grid lines as electrodes for transmitting photocurrent, preventing the use of high-temperature silver paste with lower silver consumption. This increases the production cost of SHJ cells, hindering their mass production. Moreover, the width of the low-temperature silver paste grid lines is limited by the precision of screen printing, increasing the shading area on the front side and preventing further reduction of the shading area, thus limiting the improvement of cell conversion efficiency.

[0003] How to improve battery efficiency while reducing the manufacturing cost of grid lines has been a key focus of SHJ battery research in recent years. Electroplated copper grid line technology is currently the most promising alternative to screen printing. Replacing traditional low-temperature silver paste grid lines with electroplated copper grid lines can reduce the manufacturing cost of SHJ batteries. Furthermore, using specialized patterning techniques such as photolithography and lasers can significantly reduce the grid line width, increase the light-receiving area on the front of the battery, and improve conversion efficiency. The current mainstream SHJ copper grid line process includes: 1. Depositing an electroplating seed layer using magnetron sputtering (PVD) to conduct the electroplating current. 2. Photolithography of the grid line pattern to achieve selective electroplating of the grid line area. 3. Electroplating process to achieve rapid grid line deposition. 4. Etching of the photoresist film and seed layer to complete the final SHJ battery fabrication. While photolithography can further reduce the grid line width, the cost of the photoresist film used in photolithography makes the cost advantage of electroplated copper grid lines not significant compared to traditional screen-printed low-temperature silver paste grid lines. While laser technology can also reduce grid line width, it can damage the passivation layer of SHJ batteries, leading to a decrease in battery conversion efficiency.

[0004] Furthermore, due to the presence of a transparent conductive oxide (TCO) film on the front and back surfaces of SHJ solar cells, the adhesion between the TCO film and the narrower electroplated copper grid lines is poor, and the stress on the copper grid lines can further lead to grid line detachment. This invention patent proposes a method for fabricating SHJ solar cells that solves the parasitic absorption problem and the adhesion problem of the electroplated copper grid lines. It can also reduce the amount of low-temperature silver paste used and replace the photolithography and PVD processes in the mainstream electroplated copper grid process, thereby reducing production costs. Summary of the Invention

[0005] To address the shortcomings of current electroplated copper grid line technology, the technical solution of this invention is implemented as follows:

[0006] This invention provides a method for manufacturing a silicon-based heterojunction solar cell with a partially contacted structure and an electroplated copper grid.

[0007] The battery structure is as follows Figure 1 As shown, the front partial contact structure means that only the area where the front grid line contacts the substrate has an emitter. The area outside the area where the front grid line contacts the substrate is referred to as the non-contact area between the front grid line and the substrate. From top to bottom, it includes: anti-reflection layer, passivation layer, and substrate. The area where the front grid line contacts the substrate from top to bottom includes: electrode protection layer, electrode, electrode blocking layer, emitter, passivation layer, and substrate. The corresponding substrate contact area is a groove structure, i.e., grid line groove. The electrode and electrode blocking layer above the emitter and passivation layer are covered at the bottom and sides until they are flush with the anti-reflection layer of the non-contact area. The back structure of the battery from bottom to top includes: electrode, TCO layer, back field, passivation layer, and substrate.

[0008] The preparation method includes the following steps:

[0009] (1) First, the initial substrate silicon wafer is cleaned and texturized to form a pyramid textured structure on both sides of the silicon wafer;

[0010] (2) A passivation layer is deposited on the front side of the silicon wafer after step (1) to passivate the dangling bonds on the silicon wafer surface and to serve as a buffer layer for subsequent laser processes, thereby reducing substrate damage to the gate groove area caused by laser.

[0011] (3) Deposit an anti-reflection layer on the front side of the sample treated in step (2) and use it as an insulating mask layer for subsequent electroplating;

[0012] (4) The antireflection layer of the sample processed in step (3) is patterned using a laser to form a grid pattern. The line width is determined by the size of the laser spot. The laser used is an ultraviolet nano laser, an ultraviolet picosecond laser, a green nanosecond laser, a green picosecond laser, etc., and the laser spot size is 5-20μm.

[0013] (5) The sample processed in step (4) is subjected to an alkaline washing process to remove the passivation layer of the laser pattern area and the laser damage area of ​​the substrate, forming a gate groove area.

[0014] (6) Deposit a passivation layer and an emitter / back field layer sequentially on the front and back sides of the sample processed in step (5);

[0015] (7) Deposit a TCO layer on the back side of the sample treated in step (6);

[0016] (8) The sample processed in step (7) is deposited sequentially with an electrode blocking layer, an electrode, and an electrode protective layer in the front grid groove area by photo-induced electroplating.

[0017] (9) The sample treated in step (8) is washed with alkali to remove the passivation layer and back field layer outside the grid groove area, and then dried;

[0018] (10) The sample processed in step (9) is screen-printed with electrodes on the back and then cured to complete the entire battery preparation.

[0019] In the above scheme, the front electrode is a single layer of metal material or multiple layers of different metal materials stacked together. The metal material is at least one of copper, aluminum, tin, iron, or an alloy thereof. The electrode width is between 10-30 μm, and the electrode height is between 5-30 μm.

[0020] In the above scheme, the antireflection layer is at least one of silicon nitride, silicon oxide, etc. The thickness of the antireflection layer is between 40-80 nm.

[0021] In the above scheme, both the emitter and the back field layer are heavily doped hydrogenated amorphous silicon or microcrystalline silicon, with a thickness of 5-10 nm.

[0022] In the above scheme, the passivation layer is one of undoped intrinsic hydrogenated amorphous silicon or microcrystalline silicon, with a thickness of 1-5 nm.

[0023] In the above scheme, the substrate is a doped silicon substrate, such as at least one of n-type single crystal silicon, p-type single crystal silicon, n-type polycrystalline silicon, and p-type polycrystalline silicon, with a thickness of 120-200 μm.

[0024] In the above scheme, the front electrode protective layer, the electrode, and the electrode blocking layer are deposited by photo-induced electroplating. The electrode protective layer and the electrode blocking layer are both made of pure Ni metal material, and the electrode is made of pure Cu metal material.

[0025] In the above scheme, the TCO layer is one of the following materials: ITO, IWO, ICO, AZO, etc., and is deposited by one of the following methods: PVD, RPD, etc.

[0026] In the above scheme, the back electrode is prepared by printing silver paste grid lines using screen printing technology.

[0027] This invention provides a method for fabricating a locally contact silicon heterojunction solar cell combined with an electroplated copper grid. Compared with traditional silicon heterojunction solar cells, it eliminates the cost of low-temperature silver paste material on the front side and avoids parasitic absorption by the front amorphous silicon layer and TCO. Compared with traditional electroplated copper grid technology, it eliminates the need for electroplating seed layer deposition and photolithography processes, reducing the cost of seed layer deposition equipment and photolithography equipment, and saving the cost of expensive photolithography materials. This invention forms the grid pattern on a silicon nitride-deposited substrate using a laser. After removing the loss layer through an alkaline washing process, the passivation layer and back field layer are deposited, which effectively avoids passivation layer damage caused by the laser. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the battery structure described in this invention.

[0029] Figure 2 This is a basic implementation flowchart of the present invention. Detailed Implementation

[0030] The present invention will be further described below with reference to the embodiments, but the present invention is not limited to the following embodiments.

[0031] For ease of understanding, the technical implementation route of the solar cell of this invention is described below with reference to schematic diagrams. The cell structure is as follows: Figure 1 As shown. The preparation method includes the following steps:

[0032] (1) As Figure 2 As shown in (II), firstly... Figure 1 (I) The initial submerged silicon wafer is cleaned and texturized to form a pyramid textured structure on both sides of the silicon wafer.

[0033] (2) Figure 2 As shown in (III), a 5-10 nm hydrogenated intrinsic amorphous silicon passivation layer is deposited on the front side of the silicon wafer after step one to passivate the dangling bonds on the silicon wafer surface and to serve as a buffer layer for subsequent laser processes, thereby reducing substrate loss in the gate area caused by laser.

[0034] (3) Figure 2 As shown in (Ⅳ), a 50-80 nm silicon nitride layer is deposited on the front side of the sample after step two as an anti-reflection layer and a subsequent electroplating insulating mask layer.

[0035] (4) Figure 2 As shown in (V), the sample processed in step three is patterned with silicon nitride using a laser to form a grid pattern. The line width is determined by the size of the laser spot. The laser can be ultraviolet nano-laser, ultraviolet picosecond laser, green nanosecond laser, green picosecond laser, etc., and the laser spot size is 5-20 μm.

[0036] (5) Figure 2As shown in (VI), the sample processed in step four is subjected to an alkaline washing process to remove the hydrogenated intrinsic amorphous silicon layer in the gate line region and the laser-damaged region of the substrate, forming a gate line groove. The groove depth is 1-10 μm.

[0037] (6) Figure 2 As shown in (Ⅶ), a 5-10 nm passivation layer and an emitter are sequentially deposited on the front side of the sample after step five, and a 5-10 nm hydrogenated intrinsic amorphous silicon passivation layer and a heavily doped hydrogenated amorphous silicon back field layer are sequentially deposited on the back side.

[0038] (7) Figure 2 As shown in (VIII), a 30-80 nm ITO layer is deposited on the back side of the sample processed in step six.

[0039] (8) Figure 2 As shown in (IX), the sample processed in step seven is subjected to photo-induced electroplating to sequentially deposit a Ni barrier layer, a copper gate line, and a Ni protective layer in the front gate line area.

[0040] (9) such as Figure 2 As shown in (X), the sample processed in step eight is subjected to alkaline washing to remove the hydrogenated intrinsic amorphous silicon layer and the heavily doped hydrogenated amorphous silicon layer outside the gate trench region, and then dried. (10) Figure 2 As shown in (XI), the sample processed in step nine is screen-printed with low-temperature silver paste grid lines on the back and then cured to complete the entire battery fabrication.

Claims

1. A method for fabricating grid lines for improving efficiency and reducing costs in silicon heterojunction solar cells, characterized in that, The structure of the silicon heterojunction solar cell is as follows: The front partial contact structure means that only the area where the front grid line contacts the substrate has an emitter. The area outside the area where the front grid line contacts the substrate is referred to as the non-contact area between the front grid line and the substrate. From top to bottom, it includes: anti-reflection layer, passivation layer, and substrate. The area where the front grid line contacts the substrate includes, from top to bottom,: electrode protection layer, electrode, electrode blocking layer, emitter, passivation layer, and substrate. The corresponding substrate contact area is a groove structure, i.e., grid line groove. The bottom and side of the electrode and electrode blocking layer above the emitter and passivation layer are covered until they are flush with the anti-reflection layer of the non-contact area. The back structure of the cell from bottom to top includes: electrode, TCO layer, back field, passivation layer, and substrate. The preparation method includes the following steps: (1) First, the initial substrate silicon wafer is cleaned and texturized to form a pyramid textured structure on both sides of the silicon wafer; (2) A passivation layer is deposited on the front side of the silicon wafer after step (1) to passivate the dangling bonds on the silicon wafer surface and to serve as a buffer layer for subsequent laser processes, thereby reducing substrate damage to the gate groove area caused by laser. (3) Deposit an antireflection layer on the front side of the sample treated in step (2) and use it as an insulating mask layer for subsequent electroplating; (4) The antireflection layer of the sample processed in step (3) is patterned using a laser to form a grid pattern. The line width is determined by the size of the laser spot. The laser used is an ultraviolet nano laser, an ultraviolet picosecond laser, a green nanosecond laser, or a green picosecond laser. The laser spot size is 5-20 µm. (5) The sample treated in step (4) is subjected to an alkaline washing process to remove the passivation layer of the laser pattern area and the laser damage area of ​​the substrate, forming a gate groove area. (6) Deposit a passivation layer and an emitter / back field layer sequentially on the front and back sides of the sample processed in step (5); (7) Deposit a TCO layer on the back side of the sample treated in step (6); (8) The sample processed in step (7) is deposited sequentially with an electrode blocking layer, an electrode, and an electrode protective layer in the front grid groove area by photo-induced electroplating. (9) The sample treated in step (8) is washed with alkali to remove the passivation layer and back field layer outside the grid groove area, and then dried; (10) The sample processed in step (9) is screen-printed with electrodes on the back and cured to complete the entire battery preparation.

2. The method according to claim 1, characterized in that, The front electrode is a single layer of metal material or multiple layers of different metal materials stacked together. The metal material is at least one of copper, aluminum, tin, and iron or an alloy thereof. The electrode width is between 10-30 µm and the electrode height is between 5-30 µm.

3. The method according to claim 1, characterized in that, The antireflection layer is made of at least one of silicon nitride and silicon oxide, and the thickness of the antireflection layer is between 40 and 80 nm.

4. The method according to claim 1, characterized in that, Both the emitter and the back field layer are heavily doped hydrogenated amorphous silicon or microcrystalline silicon, with a thickness of 5-10 nm.

5. The method according to claim 1, characterized in that, The passivation layer is one of undoped intrinsic hydrogenated amorphous silicon or microcrystalline silicon, with a thickness of 1-5 nm.

6. The method according to claim 1, characterized in that, The substrate is a doped silicon substrate with a thickness of 120–200 µm.

7. The method according to claim 6, characterized in that, The substrate is at least one of n-type monocrystalline silicon, p-type monocrystalline silicon, n-type polycrystalline silicon, and p-type polycrystalline silicon.

8. The method according to claim 1, characterized in that, The front electrode protective layer, electrode, and electrode blocking layer are deposited by photo-induced electroplating. The electrode protective layer and electrode blocking layer are made of pure Ni metal, and the electrode is made of pure Cu metal.

9. The method according to claim 1, characterized in that, The TCO layer is one of the following materials: ITO, IWO, ICO, or AZO, deposited using either PVD or RPD.

10. The method according to claim 1, characterized in that, The back electrode is prepared by printing silver paste grid lines using screen printing technology.

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