Display substrate, display panel and display device

Abstract

The present disclosure provides a display substrate having a display area and a border area; the display substrate includes a plurality of display pixels and a plurality of dummy pixels; the display pixels are distributed in the display area; the dummy pixels are distributed in the border area; the plurality of display pixels and the plurality of dummy pixels are arranged in an array; the display pixels include a first pixel electrode and a first common electrode; a first voltage difference is formed between the first pixel electrode and the first common electrode; the dummy pixels include a second pixel electrode and a second common electrode; a second voltage difference is formed between the second pixel electrode and the second common electrode; and the difference between the first voltage difference and the second voltage difference is less than a set value. The present disclosure also provides a display panel and a display device.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of display technology, and particularly relate to a display substrate, a display panel, and a display device. Background Art

[0002] Consumers are increasingly demanding higher standards for display device image quality and transmittance, placing higher demands on display technology. The higher the resolution of a display device, the finer the image and the better the image quality. Currently, high-resolution products on the market have smaller pixel pitches, and the excessive number of TFT (thin-film transistor) devices with hundreds of millions of sub-pixels matches the active display area, resulting in more black matrix within the active display area and lowering the transmittance of the display panel. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display substrate, a display panel, and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate having a display area and a frame area;

[0005] The display substrate includes a plurality of display pixels and a plurality of dummy pixels; the display pixels are distributed in the display area; the dummy pixels are distributed in the border area; the plurality of display pixels and the plurality of dummy pixels are arranged in an array;

[0006] The display pixel includes a first pixel electrode and a first common electrode; a first voltage difference is formed between the first pixel electrode and the first common electrode;

[0007] The dummy pixel includes a second pixel electrode and a second common electrode; a second voltage difference is formed between the second pixel electrode and the second common electrode;

[0008] A difference between the first voltage difference and the second voltage difference is smaller than a set value.

[0009] In some embodiments, the array further includes at least two first data lines and a plurality of second data lines; the first data lines and the second data lines extend along a column direction of the array respectively;

[0010] The dummy pixels include pixels of the first type;

[0011] The first type of pixels and the display pixels are in different columns;

[0012] The second pixel electrodes of the first type of pixels in the same column are connected to one first data line;

[0013] The first pixel electrodes of the display pixels in the same column are connected to one second data line;

[0014] The data signal inputted to any one of the first data lines is the same as the data signal inputted to the adjacent one of the second data lines.

[0015] In some embodiments, the dummy pixels further include a second type of pixels, and the second type of pixels are located in the column where the display pixels are located;

[0016] The second-type pixels and the display pixels in the same column, the second pixel electrodes of the second-type pixels and the first pixel electrodes of the display pixels are connected to one second data line.

[0017] In some embodiments, the array further includes a plurality of common voltage lines, each of which extends along a row direction of the array;

[0018] The display pixels and the dummy pixels in the same row, the first common electrodes of the display pixels and the second common electrodes of the dummy pixels are connected to one common voltage line;

[0019] The second common electrodes of the dummy pixels in the same row are connected to one common voltage line;

[0020] The common voltage signals inputted into the plurality of common voltage lines are the same.

[0021] In some embodiments, the array further includes a plurality of common voltage lines, each of which extends along a row direction of the array;

[0022] The first common electrodes of the display pixels in the same row are connected to one common voltage line;

[0023] The second common electrode is suspended;

[0024] The common voltage signals inputted into the plurality of common voltage lines are the same.

[0025] In some embodiments, the array includes at least two first data lines, a plurality of second data lines, and a plurality of common voltage lines; the first data lines and the second data lines extend along the column direction of the array; the plurality of common voltage lines extend along the row direction of the array;

[0026] The dummy pixels include first-type pixels and second-type pixels;

[0027] The first type of pixels are located in a different column from the display pixels; the second type of pixels are located in the same column as the display pixels;

[0028] The second pixel electrodes of the first type of pixels in the same column are connected to one first data line; the first data line is connected to the common voltage line;

[0029] The first pixel electrodes of the display pixels in the same column are connected to one second data line;

[0030] The second pixel electrodes of the second type of pixels in the same row are connected to one common voltage line;

[0031] The first common electrodes of the display pixels in the same row are connected to one common voltage line;

[0032] The common voltage signals inputted on the plurality of common voltage lines are the same;

[0033] The second common electrodes of the first type of pixels and the second type of pixels are suspended.

[0034] In some embodiments, a common voltage bus is further included, located in the border area and surrounding the display area;

[0035] A plurality of first access lines extend from a portion of the common voltage bus corresponding to the first side of the display substrate, the plurality of first access lines are located in the frame area, and the plurality of first access lines are respectively connected to one of the common voltage lines adjacent thereto;

[0036] The first side of the display substrate is the side where the extending ends of the first data line and the second data line are located;

[0037] The plurality of first access lines and the second data lines are alternately distributed.

[0038] In some embodiments, a plurality of second access lines are further extended from a portion of the common voltage bus corresponding to the second side of the display substrate, the plurality of second access lines are located in the frame area, and the plurality of second access lines are respectively connected to an adjacent one of the common voltage lines;

[0039] The second side is opposite to the first side, and the second side of the display substrate is a side where the starting ends of the first data line and the second data line are located;

[0040] The plurality of second access lines and the second data lines are alternately distributed.

[0041] In some embodiments, a plurality of flexible circuit boards are further included;

[0042] A data driving circuit is provided on the flexible circuit board, and the data driving circuit is connected to the starting ends of the first data line and the second data line;

[0043] The plurality of second access lines are respectively located in the spacing area between two adjacent flexible circuit boards.

[0044] In some embodiments, the line width of the first access line is less than or equal to the line width of the second data line;

[0045] The line width of the second access line is smaller than or equal to the line width of the second data line.

[0046] In some embodiments, the shape of the first access line includes a straight line or a broken line;

[0047] The second access line may be in a straight line or a broken line shape.

[0048] In some embodiments, the opening area of ​​the dummy pixel is 1 / 2, 2 / 3 or 4 / 5 times the opening area of ​​the display pixel.

[0049] In some embodiments, the display substrate further includes a third side and a fourth side, the third side is opposite to the fourth side and extends along the column direction of the array respectively;

[0050] The first side and the second side extend along the row direction of the array respectively;

[0051] The third side and the fourth side are connected to the first side and the second side respectively to form an edge of the display substrate;

[0052] The dummy pixels are sequentially arranged along the edge of the display substrate for at least one circle.

[0053] In some embodiments, further comprising a substrate,

[0054] The first common electrode and the first pixel electrode are located on different layers above the substrate and overlap with each other;

[0055] The second common electrode and the second pixel electrode are located on different layers above the substrate and overlap with each other;

[0056] The first common electrode and the second common electrode are located in the same layer; the first pixel electrode and the second pixel electrode are located in the same layer;

[0057] The first pixel electrode and the second pixel electrode are farther away from the substrate than the first common electrode and the second common electrode;

[0058] The first pixel electrode and the second pixel electrode are both slit-shaped electrodes; the first common electrode and the second common electrode are both plate-shaped electrodes.

[0059] In some embodiments, the plurality of common voltage lines, the common voltage bus, the plurality of first access lines, and the plurality of second access lines are located on the same layer;

[0060] The plurality of common voltage lines are respectively extended to two ends thereof and connected to the common voltage bus respectively;

[0061] The first data line and the second data line are located in the same layer;

[0062] The common voltage line and the second data line are located in different layers, and an insulating layer is provided between them;

[0063] The display substrate further includes a plurality of common voltage transfer lines evenly distributed in the display area; the plurality of common voltage transfer lines are located in the same layer as the second data lines and are parallel to the second data lines;

[0064] The plurality of common voltage transfer lines are connected to any two common voltage lines through via holes provided in the insulating layer.

[0065] In a second aspect, an embodiment of the present disclosure further provides a display panel, which includes the above-mentioned display substrate.

[0066] In some embodiments, a cell-aligning substrate is further included, wherein the cell-aligning substrate and the display substrate are aligned to form a cell-aligning gap, and the cell-aligning gap is filled with negative liquid crystal.

[0067] In a third aspect, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed exemplary embodiments with reference to the accompanying drawings, in which:

[0069] Figure 1 This is a schematic diagram of connecting drive signals between display pixels and dummy pixels in a liquid crystal display panel in the disclosed technology.

[0070] Figure 2 Schematic diagram of black stains appearing around the LCD panel.

[0071] Figure 3 Schematic diagram of the locations of local black spots and stains around the LCD panel.

[0072] Figure 4 This is a top view of a pixel of a display substrate and its circuit connections in an embodiment of the present disclosure.

[0073] Figure 5 for Figure 4 The structural cross-sectional view of the substrate along the AA cutting line is shown in FIG.

[0074] Figure 6 This is a top view of a pixel and its circuit connection of another display substrate in an embodiment of the present disclosure.

[0075] Figure 7 This is a top view of a pixel and circuit connection of another display substrate in an embodiment of the present disclosure.

[0076] Figure 8 A top view of a circuit trace of a display substrate in an embodiment of the present disclosure is shown.

[0077] Figure 9 FIG. 1 is another top view showing circuit traces of a substrate in an embodiment of the present disclosure.

[0078] Figure 10 FIG. 4 is a top view of another circuit trace of a display substrate in an embodiment of the present disclosure.

[0079] Figure 11 For the embodiment of the present disclosure Figure 4 The structural cross-sectional view of the substrate along the BB cutting line is shown in FIG.

[0080] Figure 12 Schematic diagram of pixel arrangement of a display substrate in an embodiment of the present disclosure.

[0081] Figure 13 Schematic diagram of the verification situation of Experiment 1.

[0082] Figure 14 Schematic diagram of the verification situation of experimental verification 2.

[0083] Figure 15 Schematic diagram of the verification situation of experimental verification three.

[0084] Figure 16 Schematic diagram of the verification situation of experimental verification four.

[0085] The accompanying drawings are marked as follows:

[0086] 1. Display pixel; 11. First pixel electrode; 12. First common electrode; 2. Dummy pixel; 21. Second pixel electrode; 22. Second common electrode; 110. Branch electrode; 111. Branch electrode group; 112. First electrode; 113. Second electrode; 201. First type of pixel; 202. Second type of pixel; 101. Display area; 102. Frame area; 103. Non-active display area; 3. Substrate; 4. First insulating layer; 5. First data line; 6. Second data line; 7. Common voltage line; 8. Common voltage line Voltage bus; 9. First access line; 10. Second access line; 13. Flexible circuit board; 14. Data drive circuit; 15. Common voltage adapter line; 16. Common voltage introduction point; 17. Black matrix; 18. Gate; 19. Gate insulation layer; 20. Active layer; 23. Second insulation layer; 24. Source; 25. Drain; 26. Third insulation layer; 27. Scan line; 28. Fourth insulation layer; 29. ​​Pixel electrode; 30. Common electrode; 31. Data line; 32. Black line stains; 33. Black dot stains. DETAILED DESCRIPTION

[0087] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a display substrate, a display panel and a display device provided by the embodiments of the present disclosure are further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0088] The embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully enable those skilled in the art to understand the scope of this disclosure.

[0089] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings are schematic in nature, and the shapes of the regions shown in the drawings illustrate specific shapes of the regions, but are not intended to be limiting.

[0090] In the disclosed technology, there is a structural difference in film thickness uniformity between the peripheral non-active display area and the central active display area of ​​the liquid crystal display panel. That is, the film thickness in the active display area is relatively uniform, while in the peripheral non-active display area, some film layers are missing after preparation, resulting in serious film discontinuity and uneven film thickness. This will cause the display pattern at the border edge between the active display area and the non-active display area to be uneven, resulting in poor display around the active display area (i.e., display mura, such as dark lines on the periphery).

[0091] In order to avoid poor display around the effective display area, LCD panels usually set up dummy pixels (i.e., Dummy Pixels) around the effective display area. The film layer structure of the dummy pixels is the same as the structure of the display pixels in the effective display area. The dummy pixels can improve the film layer discontinuity phenomenon around the effective display area, thereby making the display pattern at the border edge of the effective display area and the non-effective display area tend to be uniform, thereby improving the display effect.

[0092] Reference Figure 1 , is a schematic diagram of the drive signal connections between display pixel 1 (AA Pixel) and dummy pixel 2 (Dummy Pixel) in a liquid crystal display panel in the disclosed technology. To ensure that the dummy pixel 2 in the peripheral non-active display area 103 of the panel does not leak light during display, the liquid crystal display panel usually sets the data signal voltage input to the pixel electrode 29 of the dummy pixel 2 (i.e., Dummy Pixel) in the peripheral non-active display area 103 to be the common voltage (i.e., Vcom). The common voltage (i.e., Vcom) is also input to the common electrode 30 of the dummy pixel 2 to ensure that the liquid crystal in the non-active display area 103 does not deflect and remains in a black state. However, the data signal voltage input to the pixel electrode 29 (2ITO) of the display pixel 1 in the active display area 101 is different from the common voltage input to its common electrode 30 (1ITO). The liquid crystal can be deflected by the electric field formed between the pixel electrode 29 and the common electrode 30 of the display pixel 1, thereby achieving effective display of the display pixel 1.

[0093] Reference Figure 1 , a normal data signal voltage Vdata is input to the pixel electrode 29 of the display pixel 1 in the effective display area 101; a common voltage signal Vcom is input to the pixel electrode 29 of the dummy pixel 2 in the inactive display area 103 (for example, the dummy pixel 2 is connected to the common voltage bus 8 located in the inactive display area 103 by connecting the data line 31 connected to its pixel electrode 29 to the common voltage bus 8 located in the inactive display area 103, and inputs the common voltage Vcom); a common voltage Vcom is input to the common electrode 30 of both the display pixel 1 and the dummy pixel 2. Usually, the common voltage Vcom is a constant value, and the voltage signals on the pixel electrode 29 and the common electrode 30 of the dummy pixel 2 are the same. The electric field formed between the two will not cause the liquid crystal to deflect. For high-resolution products, negative liquid crystal is used to improve the transmittance of the display panel. When the liquid crystal display panel uses negative liquid crystal, the dummy pixel 2 appears black. In addition, the inactive display area 103 is blocked by the black matrix, so the dummy pixel 2 will not affect the display. The data signal voltage Vdata on the pixel electrode 29 of the display pixel 1 in the effective display area 101 changes with the display screen. Due to the voltage difference, an electric field is formed between the pixel electrode 29 of the display pixel 1 and the common electrode 30, which can deflect the liquid crystal, thereby realizing normal display of the display pixel 1.

[0094] The difference in the drive signal design between the display pixel 1 and the dummy pixel 2 results in a voltage difference between the two (the voltage difference is the voltage difference that causes the liquid crystal to deflect). This causes the liquid crystal display panel to generate a strong electric field locally at high temperature. The local strong electric field is more likely to attract ionic impurities in the display panel, causing the ionic impurities to aggregate, causing abnormal liquid crystal deflection and the appearance of high-temperature black line stains 32 (see Figure 2 , which is a schematic diagram of black stains appearing around the LCD panel). Especially for display panels using negative liquid crystals for high-resolution products, since negative liquid crystals contain more high-polarity monomers and have a larger polarity, they are prone to generate more impurity ions and free radicals under long-term high-temperature and high-brightness backlight irradiation. Moreover, the ions move quickly at high temperatures and are easily aggregated in a short time under the action of an electric field (especially when the electric field is uneven), causing abnormal liquid crystal deflection, resulting in afterimages or high-temperature black stains and other defects. Figure 2 In the image, two rows of display pixels around the LCD panel are black, and serious black line stains appear 32.

[0095] In addition, refer to Figure 3 A schematic diagram illustrating the locations of localized black spots and stains on the periphery of a liquid crystal display panel. The flexible circuit boards in the liquid crystal display panel are arranged at equally spaced intervals along the bonding edge DP. Data lines 31 are derived from the data driver chip on each flexible circuit board and extend to the opposite edge DPO of the bonding edge DP, providing data drive signal voltage Vdata to display pixels 1 (horizontal scan lines 27 provide scan signals Vgate to display pixels 1). The common voltage bus 8 (COM Bus Line) located in the non-active display area 103 of the liquid crystal display panel's periphery introduces a common voltage signal Vcom to the common voltage line 7 within the active display area 101 via multiple pairs of common voltage introduction points 16, arranged at the bonding edge DP and its opposite edge DPO. This provides the common voltage signal Vcom to the common electrodes 30 of the display pixels 1 distributed within the active display area 101. At the binding side edge DP of the liquid crystal display panel, multiple common voltage introduction points 16 are respectively located in the gap area between two adjacent flexible circuit boards, and the common voltage introduction points 16 located at the opposite side edge DPO are distributed one-to-one with the common voltage introduction points 16 located at the binding side edge DP. Since the number of common voltage introduction points 16 at the binding side edge DP and the opposite side edge DPO is relatively small, and each common voltage introduction point 16 is introduced as a block electrode with a relatively wide width, the local electric field at each common voltage introduction point 16 of the liquid crystal display panel is relatively strong. During the high-temperature reliability test, the strong electric field attracts ionic impurities in the display panel, causing the ionic impurities to aggregate. The corresponding display pixels of the liquid crystal display panel at these locations with strong electric fields appear black, resulting in black dot-shaped stains 33 on the binding side edge and the opposite side edge (see Figure 2 ).

[0096] In order to solve the problem that black pollution is easy to appear around the liquid crystal display panel, the embodiment of the present disclosure provides a display substrate, referring to Figure 4 , is a top view of a pixel and its circuit connection of a display substrate according to an embodiment of the present disclosure. The display substrate has a display area 101 and a border area 102; the display substrate includes a plurality of display pixels 1 (AA pixels) and a plurality of dummy pixels 2 (Dummy pixels); the display pixels 1 are distributed in the display area 101; the dummy pixels 2 are distributed in the border area 102; the plurality of display pixels 1 and the plurality of dummy pixels 2 are arranged in an array; the display pixel 1 includes a first pixel electrode 11 and a first common electrode 12; a first voltage difference is formed between the first pixel electrode 11 and the first common electrode 12; the dummy pixel 2 includes a second pixel electrode 21 and a second common electrode 22; a second voltage difference is formed between the second pixel electrode 21 and the second common electrode 22; and the difference between the first voltage difference and the second voltage difference is less than a set value.

[0097] In some embodiments, the difference between the first voltage difference and the second voltage difference is 0, that is, the voltages applied to the first pixel electrode 11 and the second pixel electrode 21 are the same, and the voltages applied to the first common electrode 12 and the second common electrode 22 are the same.

[0098] In some embodiments, the voltages applied to the first pixel electrode 11 and the second pixel electrode 21 may also be different, and the voltages applied to the first common electrode 12 and the second common electrode 22 may also be different; but the difference between the first voltage difference and the second voltage difference is 0 or close to 0. For example, optionally, the difference between the first voltage difference and the second voltage difference is 0.2V, 0.6V, 0.8V, 1V, etc., which is not limited here.

[0099] In some embodiments, the display substrate may be an array substrate in a liquid crystal display panel.

[0100] By making the difference between the first voltage difference and the second voltage difference smaller than a set value, a voltage difference can be prevented from occurring between the display pixel 1 and the dummy pixel 2, thereby preventing the display substrate from locally generating a strong electric field at high temperature, thereby preventing the local strong electric field from attracting ionic impurities in the display substrate and causing the ionic impurities to aggregate, thereby avoiding the occurrence of high-temperature line contamination caused by abnormal liquid crystal deflection at the location where the ionic impurities aggregate in the display substrate, thereby improving the display effect of the display substrate.

[0101] In some embodiments, reference Figure 5 ,for Figure 4A cross-sectional view of the structure of the display substrate along the AA section line. The display substrate further includes a substrate 3. The first common electrode 12 and the first pixel electrode 11 are located on different layers above the substrate 3 and overlap with each other. The second common electrode 22 and the second pixel electrode 21 are located on different layers above the substrate 3 and overlap with each other. The first common electrode 12 and the second common electrode 22 are located on the same layer. The first pixel electrode 11 and the second pixel electrode 21 are located on the same layer. The first pixel electrode 11 and the second pixel electrode 21 are farther away from the substrate 3 than the first common electrode 12 and the second common electrode 22. The first pixel electrode 11 and the second pixel electrode 21 are both slit-shaped electrodes. The first common electrode 12 and the second common electrode 22 are both plate-shaped electrodes. In this embodiment, the first pixel electrode 11 and the second pixel electrode 21 are both provided to include a plurality of branch electrodes 110, and include at least two branch electrode groups 111, wherein a portion of the branch electrode groups 111 are connected together by the first electrode 112 extending in the direction of the second data line 6, and the other portion of the branch electrode group 111 is connected together by the second electrode 113 extending in the direction of the second data line 6, and in a pixel electrode region, the first electrode 112 and the second electrode 113 are located on opposite sides of the pixel electrode region, and the branch electrode group 111 on the side opposite to the first electrode 112 is not connected together, and the branch electrode group 111 on the side opposite to the second electrode 113 is not connected together. The pixel electrode designed in this way can improve the color shift problem of the display. In this case, both the dummy pixel 2 and the display pixel 1 adopt this type of pixel electrode structure design. Of course, when the pixel electrode is arranged between the common electrode and the substrate 3, the pixel electrode can adopt a plate-like structure design, and the common electrode adopts the following structure: Figure 4 The shape design of the pixel electrodes shown is not limited here. Optionally, the display substrate in this embodiment is of ADS type (Advanced Super Dimension Switch, advanced super-dimensional field switching technology). A first insulating layer 4 is provided between the first common electrode 12 and the second common electrode 22 in the same layer and the first pixel electrode 11 and the second pixel electrode 21 in the same layer.

[0102] In some embodiments, the display substrate may also have the first common electrode and the second common electrode further away from the base than the first pixel electrode and the second pixel electrode; the first common electrode and the second common electrode are both slit electrodes; the first pixel electrode and the second pixel electrode are both plate electrodes.

[0103] In some embodiments, the display substrate may be provided with only the first pixel electrode and the second pixel electrode, and the first common electrode and the second common electrode are provided on a cell-matching substrate matched with the display substrate.

[0104] In some embodiments, the first common electrodes 12 of multiple display pixels 1 are independently set; the first pixel electrode 11 and the first common electrode 12 of each display pixel 1 are overlapped with each other to form an electric field that deflects the liquid crystal; the second common electrodes 22 of multiple dummy pixels 2 are independently set; the second pixel electrode 21 and the second common electrode 22 of each dummy pixel 2 are overlapped with each other to form an electric field that deflects the liquid crystal.

[0105] In some embodiments, reference Figure 4 The display substrate further includes at least two first data lines 5 and multiple second data lines 6; the first data lines 5 and the second data lines 6 extend respectively along the column direction Y of the array; the dummy pixels 2 include first-type pixels 201; the first-type pixels 201 and the display pixels 1 are in different columns; the second pixel electrodes 21 of the first-type pixels 201 in the same column are connected to one first data line 5; the first pixel electrodes 11 of the display pixels 1 in the same column are connected to one second data line 6; the data signal input to any first data line 5 is the same as the data signal input to a second data line 6 adjacent to it.

[0106] The first data line 5 and the second data line 6 are located in the same layer and are parallel to each other.

[0107] In some embodiments, the display substrate further includes a plurality of common voltage lines 7, and the plurality of common voltage lines 7 extend along the row direction X of the array; the display pixels 1 and the dummy pixels 2 in the same row, the first common electrode 12 of the display pixel 1 and the second common electrode 22 of the dummy pixel 2 are connected to a common voltage line 7; it should be noted that the connection between the common voltage line and the common electrode can be achieved by overlapping the two in the same layer to achieve electrical connection, such as Figure 4 As shown, the two can also be on different layers and electrically connected through additional vias, which is not limited here; the second common electrodes 22 of the dummy pixels 2 in the same row are connected to a common voltage line 7; the common voltage signals input to the multiple common voltage lines 7 are the same. That is, the first common electrode 12 of the display pixel 1 and the second common electrode 22 of the dummy pixel 2 are input with the same common voltage signal.

[0108] Among them, multiple common voltage lines 7 are located in the same layer and are parallel to each other. The first common electrode 12 of each display pixel 1 and the second common electrode 22 of each dummy pixel 2 are independently set and connected to the common voltage line 7 respectively. The common voltage line 7 inputs common voltage signals to each first common electrode 12 and each second common electrode 22 respectively. When the common voltage line 7 inputs common voltage signals to each first common electrode 12 and each second common electrode 22 respectively, the common voltage line is no longer like Figure 4In the embodiment, the common voltage lines of the dummy pixel 2 and the display pixel 1 in the same row are not connected together, but the common voltage line 7 corresponding to the display pixel 1 and the common voltage line 7 corresponding to the dummy pixel 2 are disconnected and insulated, and signals are respectively input to control the common voltage line 7 connected to the display pixel 1 and the common voltage line 7 connected to the dummy pixel 2.

[0109] In this embodiment, the display substrate includes two first data lines 5, which are respectively located on the left and right sides of the display pixel 1 array of the display area 101 along the column direction Y, and the two first data lines 5 are respectively connected to the second pixel electrodes 21 of each column of first-type pixels 201 located on the left and right sides of the display pixel 1 array of the display area 101 along the column direction Y. The data signal input on each first data line 5 is the same as the data signal on the second data line 6 closest to it, that is, when the display screen changes, the data signal input on each first data line 5 and the data signal on the second data line 6 closest to it change at the same time. For example, the data signal voltage includes but is not limited to 0V-16.5V, and the difference between the first voltage difference of the display pixel 1 and the second voltage difference of the first type of pixel 201 is always kept at 0 or close to 0. In this way, a voltage difference can be prevented from occurring between the display pixel 1 and the dummy pixel 2 at the left and right edges of the display pixel 1 array column direction Y in the display area 101, thereby avoiding the generation of a strong electric field at the left and right edges of the display pixel 1 array column direction Y in the display area 101 during high temperature reliability, thereby avoiding the strong electric field at the left and right edges of the display pixel 1 array column direction Y in the display area 101 attracting ionic impurities in the display substrate, causing the ionic impurities to aggregate, thereby fundamentally avoiding the occurrence of high-temperature line contamination defects caused by abnormal liquid crystal deflection at the ionic impurity aggregation location in the display substrate.

[0110] In some embodiments, reference Figure 4The dummy pixel 2 further includes a second-type pixel 202, which is located in the same column as the display pixel 1. The second-type pixel 202 and the display pixel 1 in the same column, as well as the second pixel electrode 21 of the second-type pixel 202 and the first pixel electrode 11 of the display pixel 1, are connected to a second data line 6. That is, the data signal input to the second pixel electrode 21 of the second-type pixel 202 is the same as the data signal input to the first pixel electrode 11 of the display pixel 1 in the same column. That is, the difference between the first voltage difference of the display pixel 1 and the second voltage difference of the second type of pixel 202 is always maintained at 0. This can prevent a voltage difference from occurring between the display pixel 1 and the dummy pixel 2 at the upper and lower edges of the display pixel 1 array in the row direction X in the display area 101, thereby preventing a strong electric field from being generated at the upper and lower edges of the display pixel 1 array in the row direction X in the display area 101 during high temperature reliability. This further prevents the strong electric field at the upper and lower edges of the display pixel 1 array in the row direction X in the display area 101 from attracting ionic impurities in the display substrate, causing the ionic impurities to aggregate, thereby fundamentally avoiding the occurrence of high-temperature line contamination defects caused by abnormal liquid crystal deflection at the locations where the ionic impurities aggregate in the display substrate.

[0111] exist Figure 4 In the embodiment, the opening area of ​​the dummy pixel 2 is 1 / 2 times, 2 / 3 times, or 4 / 5 times the opening area of ​​the display pixel 1. That is, the opening area of ​​the dummy pixel 2 is smaller than the opening area of ​​the display pixel 1. When a data signal voltage is input to the second pixel electrode 21 of the dummy pixel 2 and a common voltage signal is input to the second common electrode 22, the dummy pixel 2 can deflect the liquid crystal under the action of the electric field formed by the second pixel electrode 21 and the second common electrode 22, thereby realizing the light-transmitting display of the dummy pixel 2. However, the dummy pixel 2 is located in the border area 102 and does not need to be light-transmitting. In order to prevent light leakage in the border area 102 when the dummy pixel 2 is displayed, the opening area of ​​the dummy pixel 2 is designed to be smaller than the opening area of ​​the display pixel 1. In addition, the black matrix on the subsequent box substrate can cover the border area 102 of the display substrate, thereby better shielding the light transmitted from the dummy pixel 2 and avoiding light leakage in the border area 102 of the display substrate.

[0112] In some embodiments, reference Figure 6 , which is a top view of a pixel and its circuit connections in another embodiment of the display substrate disclosed herein. The display substrate further includes multiple common voltage lines 7, each extending along the row direction X of the array. The first common electrodes 12 of display pixels 1 in the same row are connected to a common voltage line 7; the second common electrodes 22 are suspended in the air; and the common voltage signals input to the multiple common voltage lines 7 are the same.

[0113] Among them, multiple common voltage lines 7 are located in the same layer and are parallel to each other. No voltage signal is input to the second common electrode 22 of the dummy pixel 2, that is, a 0V voltage signal is input to the second common electrode 22; at this time, the second voltage difference formed between the second pixel electrode 21 and the second common electrode 22 of each dummy pixel 2 is the data signal voltage (that is, the data signal voltage -0); the first voltage difference formed between the first pixel electrode 11 and the first common electrode 12 of the display pixel 1 adjacent to the dummy pixel 2 is the difference between the data signal voltage and the common voltage signal; since the data signal input to the second pixel electrode 21 of the dummy pixel 2 is the same as the data signal on the first pixel electrode 11 of the display pixel 1 closest to it, the first voltage difference is the data signal voltage relative to the disclosed technology. The difference between the first voltage difference and the second voltage difference is 0 in the scheme of the common voltage signal. In this embodiment, the difference between the first voltage difference and the second voltage difference is significantly reduced. Therefore, the technical solution in this embodiment can also reduce the voltage difference between the display pixel 1 and the dummy pixel 2 at the edge of the display pixel 1 array around the display area 101, thereby improving or avoiding the strong electric field generated around the edge of the display pixel 1 array in the display area 101 when the display substrate is under high temperature reliability, thereby improving or avoiding the strong electric field around the edge of the display pixel 1 array in the display area 101 attracting ionic impurities in the display substrate and causing the ionic impurities to aggregate, thereby fundamentally improving or avoiding the occurrence of high-temperature line contamination caused by abnormal liquid crystal deflection at the location where ionic impurities aggregate in the display substrate.

[0114] In some embodiments, reference Figure 7 , is a top view of a pixel and its circuit connection of another display substrate in an embodiment of the present disclosure. The display substrate includes at least two first data lines 5, multiple second data lines 6, and multiple common voltage lines 7; the first data lines 5 and the second data lines 6 extend along the column direction Y of the array; the multiple common voltage lines 7 extend along the row direction X of the array; the dummy pixels 2 include a first type of pixel 201 and a second type of pixel 202; the first type of pixel 201 is in a different column from the display pixel 1; the second type of pixel 202 is located in the same column as the display pixel 1; the second pixel electrode 21 of the first type of pixel 201 in the same column is connected to a first data line 5; the first data line 5 is connected to the common voltage line 7; the first pixel electrode 11 of the display pixel 1 in the same column is connected to a second data line 6; the second pixel electrode 21 of the second type of pixel 202 in the same row is connected to a common voltage line 7; the first common electrode 12 of the display pixel 1 in the same row is connected to a common voltage line 7; the common voltage signal input to the multiple common voltage lines 7 is the same; and the second common electrodes 22 of the first type of pixel 201 and the second type of pixel 202 are suspended.

[0115] Among them, the first data line 5 and the second data line 6 are located in the same layer and are parallel to each other. A plurality of common voltage lines 7 are located in the same layer and are parallel to each other. The second pixel electrodes 21 of the first type of pixel 201 and the second type of pixel 202 are respectively input with common voltage signals, and the input signals of the second common electrodes 22 of the first type of pixel 201 and the second type of pixel 202 are both 0V voltage signals; therefore, the second voltage difference formed between the second pixel electrode 21 and the second common electrode 22 of each dummy pixel 2 is the common voltage signal (i.e., the common voltage signal -0); the first voltage difference formed between the first pixel electrode 11 and the first common electrode 12 of the display pixel 1 adjacent to the dummy pixel 2 is the difference between the data signal voltage and the common voltage signal; compared with the first voltage difference in the public technology being the difference between the data signal voltage and the common voltage signal value, and the second voltage difference is 0. In this embodiment, the difference between the first voltage difference and the second voltage difference is significantly reduced, that is, the technical solution in this embodiment reduces the voltage difference between the display pixel 1 and the dummy pixel 2 at the edge of the display pixel 1 array in the display area 101, which can improve or avoid the strong electric field generated at the edge of the display pixel 1 array in the display area 101 when the display substrate is under high temperature reliability, thereby improving or avoiding the strong electric field at the edge of the display pixel 1 array in the display area 101 attracting ionic impurities in the display substrate and causing the ionic impurities to aggregate, thereby fundamentally improving or avoiding the occurrence of high-temperature line contamination caused by abnormal liquid crystal deflection at the location where the ionic impurities aggregate in the display substrate.

[0116] exist Figure 6 and Figure 7 In the embodiment of FIG, the opening area of ​​the dummy pixel 2 is the same as the opening area of ​​the display pixel 1. Figure 6 and Figure 7 In an embodiment of the display substrate, either a data signal voltage is input to the second pixel electrode 21 of the dummy pixel 2, and the second common electrode 22 is left floating; or a common voltage signal is input to the second pixel electrode 21 of the dummy pixel 2, and the second common electrode 22 is left floating; in these two schemes, the dummy pixel 2 will not generate an electric field that deflects the liquid crystal, so the dummy pixel 2 will not display light through it. Therefore, the border area 102 of the display substrate will not leak light due to the setting of the dummy pixel 2, and the opening area of ​​the dummy pixel 2 can be the same as the opening area of ​​the display pixel 1.

[0117] In some embodiments, reference Figure 8, which is a top view of a circuit routing of a display substrate in an embodiment of the present disclosure. The display substrate further includes a common voltage bus 8, which is located in the frame area 102 and surrounds the display area 101; a plurality of first access lines 9 extend from the portion of the common voltage bus 8 corresponding to the first side a of the display substrate, and the plurality of first access lines 9 are located in the frame area 102, and the plurality of first access lines 9 are respectively connected to a common voltage line 7 adjacent thereto; the first side a of the display substrate is the side where the extended ends of the first data lines 5 and the second data lines 6 are located; the plurality of first access lines 9 and the second data lines 6 are alternately distributed at intervals. It should be noted that the alternately distributed at intervals here can mean that a second data line 6 is provided for every other first access line 9, or that a plurality of second data lines 6 are provided for every multiple first access lines 9, or that a second data line 6 is provided for every multiple first access lines 9, and the present invention is not limited to this.

[0118] The common voltage bus 8 and the plurality of first access lines 9 are located on the same layer; the common voltage bus 8 and the plurality of common voltage lines 7 are located on the same layer and are interconnected. The common voltage bus 8 is used to provide a common voltage signal to the plurality of common voltage lines 7. The plurality of first access lines 9 and the second data lines 6 are parallel to each other and are equally spaced.

[0119] In some embodiments, the line width of the first access line 9 is less than or equal to the line width of the second data line 6 .

[0120] In some embodiments, the number of the first access lines 9 is 1 / N times the number of the second data lines 6 ; wherein N=1, 2, 3 . . . 12; and N is an integer.

[0121] In this embodiment, as described above, by setting the introduction point where the common voltage bus 8 introduces the common voltage signal to the common voltage line 7 as a plurality of first access lines 9 with relatively thin line widths that are evenly arranged along the arrangement direction of the second data lines 6, compared with the introduction point where the common voltage bus 8 introduces the common voltage signal to the common voltage line 7 in the disclosed technology, the number of first access lines 9 in this embodiment is much greater than the number of introduction points in the disclosed technology; the width of the first access line 9 in this embodiment is much smaller than the width of the introduction point in the disclosed technology; the local electric field strength at the connection point between the first access line 9 and the common voltage line 7 is greatly reduced, and in addition, The first access line 9 and the second data line 6 are evenly and alternately distributed at equal intervals, and the difference between the second voltage difference of the dummy pixel 2 and the first voltage difference of the display pixel 1 is 0 or close to 0, which greatly improves or avoids the local electric field at the connection point of the first access line 9 and the common voltage line 7 attracting ionic impurities in the display panel, causing the ionic impurities to accumulate, thereby improving or avoiding the blackening phenomenon of the display pixel 1 at the connection point of the first access line 9 and the common voltage line 7, and further improving or avoiding the black dot-shaped stains at the connection point of the first access line 9 and the common voltage line 7, thereby improving the display effect of the display substrate.

[0122] In some embodiments, the shape of the first access line 9 includes a straight line (see Figure 8 ) or broken line (refer to Figure 9 , which is another top view of the circuit routing of the display substrate in the embodiment of the present disclosure).

[0123] Among them, in order to ensure that the routing resistance of multiple second data lines 6 is consistent (that is, to ensure that the routing length of each second data line 6 is consistent), the extended end of each second data line 6 forms a zigzag routing; accordingly, the first access line 9 with a shorter routing length and correspondingly distributed in the area where the extended end of the second data line 6 is located is designed to be a zigzag shape that matches the shape of the extended end of the second data line 6. On the one hand, the two can be made parallel and not cross each other, thereby improving or avoiding signal crosstalk between the first access line 9 and the second data line 6; on the other hand, the first access line 9 can be correspondingly distributed in the interval between two adjacent second data lines 6, so that the display substrate does not need to increase additional space and area to accommodate the first access line 9.

[0124] It should also be noted that when the shape of the first access line 9 is a straight line, the local line segment of the second data line 6 corresponding to the first access line 9 distribution position area is also set to a straight line to achieve the above-mentioned two technical effects; and in order to ensure that the wiring resistance of the second data line 6 is consistent, the broken line local segment can be laid out in other areas, such as the part of the binding wiring fan-out area on the binding side of the display substrate close to the display area 101.

[0125] In some embodiments, reference Figure 10 , is another top view of the circuit routing of a display substrate in an embodiment of the present disclosure. Multiple second access lines 10 extend from the portion of the common voltage bus 8 corresponding to the second side b of the display substrate. These multiple second access lines 10 are located in the border area 102 and are each connected to an adjacent common voltage line 7. The second side b, which is opposite the first side a, is the side where the first data lines 5 and the second data lines 6 begin. The multiple second access lines 10 are alternately spaced and arranged with the second data lines 6.

[0126] The common voltage bus 8 and the plurality of second access lines 10 are located in the same layer. The plurality of second access lines 10 and the second data lines 6 are parallel to each other and are equally spaced.

[0127] In some embodiments, the line width of the second access line 10 is less than or equal to the line width of the second data line 6 .

[0128] In some embodiments, the number of the second access lines 10 is 1 / N times the number of the second data lines 6 ; wherein N=1, 2, 3 . . . 12; and N is an integer.

[0129] In this embodiment, as described above, by setting the introduction points for the common voltage bus 8 to introduce the common voltage signal to the common voltage line 7 as a plurality of second access lines 10 with relatively thin line widths that are evenly arranged along the arrangement direction of the second data lines 6, the number of the second access lines 10 in this embodiment is much greater than the number of introduction points in the public technology, and the width of the second access line 10 in this embodiment is much smaller than the width of the introduction point in the public technology. This greatly reduces the local electric field strength at the connection point between the second access line 10 and the common voltage line 7. In addition, The second access line 10 and the second data line 6 are evenly and alternately distributed at equal intervals, and the difference between the second voltage difference of the dummy pixel 2 and the first voltage difference of the display pixel 1 is 0 or close to 0, which greatly improves or avoids the local electric field at the connection point of the second access line 10 and the common voltage line 7 attracting ionic impurities in the display panel, causing the ionic impurities to accumulate, thereby improving or avoiding the blackening phenomenon of the display pixel 1 at the connection point of the second access line 10 and the common voltage line 7, and further improving or avoiding the black dot-shaped stains at the connection point of the second access line 10 and the common voltage line 7, thereby improving the display effect of the display substrate.

[0130] In some embodiments, the shape of the second access line 10 includes a straight line (see Figure 10 ) or broken line shape (not shown in the figure).

[0131] In some embodiments, reference Figure 10 The display substrate also includes a plurality of flexible circuit boards 13; a data driving circuit 14 (i.e., a data driving IC) is provided on the flexible circuit board 13, and the data driving circuit 14 is connected to the starting end of the first data line 5 and the second data line 6; and a plurality of second access lines 10 are respectively located in the spacer area between two adjacent flexible circuit boards 13.

[0132] Among them, multiple second access lines 10 are divided into multiple groups, each group includes multiple second access lines 10, and the multiple second access lines 10 in each group are dispersedly arranged in the spacing area between two adjacent flexible circuit boards 13; compared with the solution in the public technology that a block-shaped wider introduction electrode is separately set in the spacing area between two adjacent flexible circuit boards 13, the local electric field strength at the connection point between the second access line 10 and the common voltage line 7 is greatly reduced, thereby greatly improving or avoiding the local electric field at the connection point between the second access line 10 and the common voltage line 7 attracting ionic impurities in the display panel, causing the ionic impurities to aggregate, thereby improving or avoiding the blackening phenomenon of the display pixel 1 at the connection point between the second access line 10 and the common voltage line 7, improving or avoiding the poor black dot-shaped stains at the connection point between the second access line 10 and the common voltage line 7, and improving the display effect of the display substrate.

[0133] It should be noted that the surface of the display substrate in contact with the liquid crystal is provided with an orientation film, and the orientation film forms its orientation direction through a rubbing process. At present, the rubbing direction of the rubbing process is from the second side b of the display substrate to the first side a. In the case where the pixel electrode and the common electrode of the dummy pixel in the public technology are both connected to the common voltage signal, the rubbing process will cause more serious black line stains on the other sides of the display substrate except the second side b, and will cause more serious black dot stains on the first side a of the display substrate, while the black line stains and black dot stains on the second side b of the display substrate are not very obvious. Therefore, in some embodiments, the common voltage bus 8 corresponding to the second side b of the display substrate can still adopt the scheme of separately setting a block-shaped wider introduction electrode in the interval area between the two adjacent flexible circuit boards 13 in the public technology to achieve the purpose of introducing the common voltage signal from the common voltage bus 8 to the common voltage line 7.

[0134] In some embodiments, reference Figures 8-10 , multiple common voltage lines 7, a common voltage bus 8, multiple first access lines 9 and multiple second access lines 10 are located on the same layer; multiple common voltage lines 7 are respectively extended to their two ends to connect the common voltage bus 8 respectively; the first data line 5 and the second data line 6 are located on the same layer; the common voltage line 7 and the second data line 6 are respectively located on different layers, and an insulating layer is provided between them; the display substrate also includes multiple common voltage transfer lines 15, which are evenly distributed in the display area 101; the multiple common voltage transfer lines 15 and the second data line 6 are located on the same layer, and are parallel to the second data line 6; the multiple common voltage transfer lines 15 are respectively connected to any two common voltage lines 7 through vias opened in the insulating layer.

[0135] Among them, multiple common voltage lines 7 extend along the row direction X of the array and are distributed parallel to each other in the display area 101. Each common voltage line 7 corresponds to a side of each row of pixels close to the second side b of the display substrate, and is used to provide a common voltage signal for the common electrode of each row of pixels; multiple common voltage lines 7 also extend to their ends to connect with the common voltage bus 8 surrounding the border area 102, so that the common voltage bus 8 provides a common voltage signal to each common voltage line 7. The provision of the above-mentioned common voltage adapter line 15 can ensure that the common voltage signal on the common voltage bus 8 can be provided to each common voltage line 7 in the display area 101 in a more balanced manner, so that the common voltage signal at any position on each common voltage line 7 is consistent, and signal attenuation will not occur due to the long routing distance of the common voltage signal on the common voltage line 7, thereby further ensuring the display effect of the display substrate.

[0136] In some embodiments, a common voltage driving circuit (i.e., a common voltage driving IC, not shown in the figure) is also provided on the flexible circuit board 13. The common voltage driving circuit is connected to the common voltage bus 8 and is used to output a common voltage signal to the common voltage bus 8.

[0137] In this embodiment, the flexible circuit board 13 is in a COF form, that is, the data driving circuit 14 and the common voltage driving circuit are both integrated on the flexible circuit board 13 .

[0138] In some embodiments, the flexible circuit board 13 can also be in COG form, that is, the data driving circuit (i.e., data driving IC) and the common voltage driving circuit (i.e., common voltage driving IC) are not integrated on the flexible circuit board, but are directly arranged in the border area of ​​the display substrate (such as the binding side border area of ​​the display substrate).

[0139] In some embodiments, reference Figure 11 , for the embodiment of the present disclosure Figure 4 The structure of the display substrate is sectional drawing along the BB section line. The display substrate also includes a pixel circuit for driving the display pixel 1 and the dummy pixel 2 to display. The pixel circuit is a circuit formed by connecting a capacitor and a plurality of transistors. The pixel circuit is not described in detail here. The transistor includes a gate 18, a gate insulating layer 19, an active layer 20, a second insulating layer 23, a source 24 and a drain 25 arranged in sequence on the substrate 3. The source 24, the drain 25 and the first data line 5 and the second data line 6 are located on the same layer. A third insulating layer 26 is also provided on the side of the source 24 and the drain 25 facing away from the substrate 3. The first pixel electrode 11 and the second pixel electrode are arranged on the side of the third insulating layer 26 facing away from the substrate 3.

[0140] In some embodiments, reference Figure 4 and Figure 11 The display substrate further includes a plurality of scan lines 27, each of which corresponds to a side of each row of pixels close to the first side a of the display substrate, and is used to provide a scan signal for the display of each row of pixels. The gate 18, the plurality of scan lines 27, and the plurality of common voltage lines are located in the same layer and are parallel to each other. The first common electrode 12 and the second common electrode are located on the side of the gate 18 close to the substrate 3, and a fourth insulating layer 28 is provided between the gate 18 and the first common electrode 12 and the second common electrode of the same layer. In this embodiment, the fourth insulating layer 28, the gate insulating layer 19, the second insulating layer 23, and the third insulating layer 26 together constitute Figure 5 A first insulating layer 4 is formed between the first common electrode 12 and the second common electrode 22 in the same layer and the first pixel electrode 11 and the second pixel electrode 21 in the same layer.

[0141] It should be noted that the positions of the film layers in the display substrate are not limited to the above-mentioned film layer position setting schemes, which will not be listed here one by one.

[0142] In some embodiments, reference Figure 12 , which is a schematic diagram of a pixel arrangement of a display substrate according to an embodiment of the present disclosure. The display substrate further includes a third side c and a fourth side d, which are opposite to each other and extend along the column direction Y of the array; a first side a and a second side b extend along the row direction X of the array; the third side c and the fourth side d are respectively connected to the first side a and the second side b to form the edge of the display substrate; and the dummy pixels 2 are sequentially arranged along the edge of the display substrate for at least one circle.

[0143] In some embodiments, the dummy pixels 2 are arranged in a circle 1-3 times along the edge of the display substrate. The film structure of the dummy pixels is the same as that of the display pixels 1. The arrangement of the dummy pixels 2 in a circle 1-3 times can effectively reduce the film discontinuity around the display area 101, thereby making the display pattern at the edge of the display area 101 and the border area 102 more uniform, thereby improving the display effect.

[0144] In this embodiment, the dummy pixels 2 are sequentially arranged along the edge of the display substrate.

[0145] In some embodiments, the opening shape of the dummy pixel 2 is the same as or similar to the opening shape of the display pixel 1. This configuration can further improve the film discontinuity around the display area 101, thereby making the display pattern at the edge of the display area 101 and the border area 102 more uniform and improving the display effect.

[0146] The following verification experiment was designed based on the display pixel and dummy pixel connection drive signal scheme in the display panel in the disclosed technology and the display pixel and dummy pixel connection drive signal scheme in the display substrate of the embodiment of the present disclosure.

[0147] Experimental verification 1: reference Figure 13 , for Figure 1Based on the scheme for connecting drive signals between display pixels and dummy pixels in a liquid crystal display panel, a schematic diagram shows the black stains around the display substrate after the common voltage introduction point 16 on the first side a of the display substrate is cut off. In this verification, the connections between the common voltage introduction point 16 set on the first side a of the display substrate and the second pixel electrode and the second common electrode of the dummy pixels distributed on the third side c and the fourth side d of the display substrate and the common voltage line are cut off. At this point, the common voltage on the dummy pixels is evenly distributed, and there is no local strong electric field. The large black dot-like stains concentrated at the common voltage introduction point 16 disappear. However, the difference between the second voltage difference on the dummy pixels and the first voltage difference on the display pixels still exists. The black linear stains around the display substrate still exist, and the local small black dot-like stains 33 around the display substrate are reduced in severity, and the small black dot-like stains 33 are randomly distributed.

[0148] Experimental verification 2: reference Figure 14 , for Figure 1 Display pixel and dummy pixel connection drive signal scheme in liquid crystal display panel and embodiment of the present disclosure Figure 4 Based on the scheme of connecting the display pixels and dummy pixels in the display substrate with driving signals, the black matrix 17 covering the border area 102 of the display substrate is expanded into the display area 101 to cover the row of display pixels 1 at the outermost edge of the display area 101. The experimental results show that no black stains are generated around the display substrate. Figure 1 The solution in the example actually shows that the black stains around the substrate actually exist, but are blocked by the black matrix and cannot be seen. Figure 4 In the solution, since the second voltage difference on the dummy pixel 2 is consistent with the first voltage difference on the row of display pixels 1 closest to the dummy pixel 2, the black stains around the actual display substrate have been eliminated and are also invisible when blocked by the black matrix.

[0149] Experimental verification three: respectively Figure 1 Display pixel and dummy pixel connection drive signal scheme in liquid crystal display panel and embodiment of the present disclosure Figure 4 Based on the display pixel and dummy pixel connection drive signal scheme in the display substrate, Figure 14 The black matrix covering the display substrate frame area 102 is removed, referring to Figure 15 , for Figure 1 Based on the scheme of connecting driving signals of display pixels and dummy pixels in the liquid crystal display panel, Figure 14 FIG. 1 is a schematic diagram of an experiment after the black matrix covering the border area 102 of the display substrate is removed. Figure 1 After the black matrix of the middle solution is removed, the black dot stains 33 and black line stains 32 around the display substrate still exist; Figure 4After the black matrix of the middle solution is removed, the black dot stains and black line stains around the display substrate are no longer visible; therefore, the Figure 14 The invisible black stains around the display substrate are not due to black matrix covering. This proves that the disappearance of black stains around the display substrate is not due to the black matrix covering effect, but rather because the second voltage difference on dummy pixel 2 is consistent with the first voltage difference on the row of display pixels 1 closest to dummy pixel 2, eliminating the local strong electric field in the area around the display substrate that could cause ionic impurities to accumulate.

[0150] Experimental Verification 4: Reference Figure 16 , for Figure 1 On the basis of the driving signal scheme for connecting display pixels and dummy pixels in the liquid crystal display panel, an experimental schematic diagram is shown after a data signal voltage of 0 grayscale (i.e., L0) is input to the pixel electrodes of the two rows of display pixels 1 at the outermost edge of the display area 101, and a normal data signal voltage of 255 grayscale (i.e., L255) is input to the pixel electrodes of the remaining display pixels 1 in the display area 101; at this time, the data signal voltage on the pixel electrodes of the two rows of display pixels 1 at the outermost edge of the display area 101 is consistent with the data signal voltage on the pixel electrodes of the dummy pixels 2, so that the area with a voltage difference between the dummy pixels 2 around the display area 101 and the remaining normal display pixels 1 in the display area 101 is larger. The reliability experiment results show that the black stains around the display substrate are aggravated, specifically: the black line stains 32 are widened, and the black dot stains 33 are enlarged. The experimental results can reversely prove the effectiveness of the technical solution for improving or eliminating black stains around the display substrate in the embodiment of the present disclosure.

[0151] The display substrate provided in the embodiment of the present disclosure can prevent a voltage difference from occurring between display pixels and dummy pixels by making the difference between the first voltage difference and the second voltage difference smaller than a set value, thereby avoiding the local generation of a strong electric field on the display substrate during high-temperature reliability, and further avoiding the local strong electric field from attracting ionic impurities in the display substrate and causing the ionic impurities to aggregate, thereby avoiding the occurrence of high-temperature line contamination caused by abnormal liquid crystal deflection at the location where the ionic impurities aggregate in the display substrate, thereby improving the display effect of the display substrate.

[0152] An embodiment of the present disclosure further provides a display panel, which includes the display substrate in the above embodiment.

[0153] In some embodiments, the display panel further includes an alignment substrate, which is aligned with the display substrate to form an alignment gap. The alignment gap is filled with negative liquid crystal. The negative liquid crystal can improve the transmittance of high-resolution (e.g., 8K resolution, i.e., a resolution of 7680*4320) display panels, thereby improving the display brightness of the display panel.

[0154] In some embodiments, the cell substrate includes a black matrix, and the black matrix covers a border area of ​​the display substrate.

[0155] By adopting the display substrate in the above embodiment, it is possible to avoid the occurrence of black stain defects around the display panel, thereby improving the display effect of the display panel.

[0156] An embodiment of the present disclosure further provides a display device, which includes the display panel in the above embodiment.

[0157] By adopting the display panel in the above embodiment, it is possible to avoid the occurrence of black stains around the display device, thereby improving the display effect of the display device.

[0158] The display device can be any product or component with a display function, such as an LCD panel, an LCD TV, a mobile phone, a tablet computer, a notebook computer, a monitor, a notebook computer, a digital photo frame, a navigator, or the like.

[0159] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate having a display area and a frame area; The display substrate includes a plurality of display pixels and a plurality of dummy pixels; the display pixels are distributed in the display area; the dummy pixels are distributed in the border area; the plurality of display pixels and the plurality of dummy pixels are arranged in an array; The display pixel includes a first pixel electrode and a first common electrode; a first voltage difference is formed between the first pixel electrode and the first common electrode; The dummy pixel includes a second pixel electrode and a second common electrode; a second voltage difference is formed between the second pixel electrode and the second common electrode; The difference between the first voltage difference and the second voltage difference is less than a set value; The display substrate includes at least two first data lines, a plurality of second data lines, and a plurality of common voltage lines; the first data lines and the second data lines extend along the column direction of the array respectively; the plurality of common voltage lines extend along the row direction of the array respectively; The display substrate further includes a common voltage bus located in the frame area and surrounding the display area; A plurality of first access lines extend from a portion of the common voltage bus corresponding to the first side of the display substrate, the plurality of first access lines are located in the frame area, and the plurality of first access lines are respectively connected to one of the common voltage lines adjacent thereto; The first side of the display substrate is the side where the extending ends of the first data line and the second data line are located; The plurality of first access lines and the second data lines are alternately distributed.

2. The display substrate according to claim 1, wherein The dummy pixels include pixels of the first type; The first type of pixels and the display pixels are in different columns; The second pixel electrodes of the first type of pixels in the same column are connected to one first data line; The first pixel electrodes of the display pixels in the same column are connected to one second data line; The data signal inputted to any one of the first data lines is the same as the data signal inputted to the adjacent one of the second data lines.

3. The display substrate according to claim 2, wherein: The dummy pixels further include a second type of pixels, and the second type of pixels are located in the column where the display pixels are located; The second-type pixels and the display pixels in the same column, the second pixel electrodes of the second-type pixels and the first pixel electrodes of the display pixels are connected to one second data line.

4. The display substrate according to claim 3, wherein: The display pixels and the dummy pixels in the same row, the first common electrodes of the display pixels and the second common electrodes of the dummy pixels are connected to one common voltage line; The second common electrodes of the dummy pixels in the same row are connected to one common voltage line; The common voltage signals inputted into the plurality of common voltage lines are the same.

5. The display substrate according to claim 3, wherein: The first common electrodes of the display pixels in the same row are connected to one common voltage line; The second common electrode is suspended; The common voltage signals inputted into the plurality of common voltage lines are the same. The display substrate according to claim 1 , wherein: The dummy pixels include first-type pixels and second-type pixels; The first type of pixels are located in a different column from the display pixels; the second type of pixels are located in the same column as the display pixels; The second pixel electrodes of the first type of pixels in the same column are connected to one first data line; the first data line is connected to the common voltage line; The first pixel electrodes of the display pixels in the same column are connected to one second data line; The second pixel electrodes of the second type of pixels in the same row are connected to one common voltage line; The first common electrodes of the display pixels in the same row are connected to one common voltage line; The common voltage signals inputted on the plurality of common voltage lines are the same; The second common electrodes of the first type of pixels and the second type of pixels are suspended.

7. The display substrate according to any one of claims 4 to 6, wherein: A plurality of second access lines are further extended from a portion of the common voltage bus corresponding to the second side of the display substrate, the plurality of second access lines are located in the frame area, and the plurality of second access lines are respectively connected to an adjacent one of the common voltage lines; The second side is opposite to the first side, and the second side of the display substrate is a side where the starting ends of the first data line and the second data line are located; The plurality of second access lines and the second data lines are alternately distributed.

8. The display substrate according to claim 7, wherein: Also included are a plurality of flexible circuit boards; A data driving circuit is provided on the flexible circuit board, and the data driving circuit is connected to the starting ends of the first data line and the second data line; The plurality of second access lines are respectively located in the spacing area between two adjacent flexible circuit boards.

9. The display substrate according to claim 8, wherein: The line width of the first access line is less than or equal to the line width of the second data line; The line width of the second access line is smaller than or equal to the line width of the second data line.

10. The display substrate according to claim 9, wherein: The shape of the first access line includes a straight line or a broken line; The second access line has a straight line or a broken line shape.

11. The display substrate according to claim 4, wherein The opening area of ​​the dummy pixel is 1 / 2 times, 2 / 3 times or 4 / 5 times the opening area of ​​the display pixel.

12. The display substrate according to claim 7, wherein: The display substrate further includes a third side and a fourth side, wherein the third side is opposite to the fourth side and extends along the column direction of the array respectively; The first side and the second side extend along the row direction of the array respectively; The third side and the fourth side are connected to the first side and the second side respectively to form an edge of the display substrate; The dummy pixels are sequentially arranged along the edge of the display substrate for at least one circle.

13. The display substrate according to claim 1, wherein Also includes a substrate, The first common electrode and the first pixel electrode are located on different layers above the substrate and overlap with each other; The second common electrode and the second pixel electrode are located on different layers above the substrate and overlap with each other; The first common electrode and the second common electrode are located in the same layer; the first pixel electrode and the second pixel electrode are located in the same layer; The first pixel electrode and the second pixel electrode are farther away from the substrate than the first common electrode and the second common electrode; The first pixel electrode and the second pixel electrode are both slit-shaped electrodes; The first common electrode and the second common electrode are both plate-shaped electrodes.

14. The display substrate according to claim 7, wherein: The plurality of common voltage lines, the common voltage bus, the plurality of first access lines, and the plurality of second access lines are located on the same layer; The plurality of common voltage lines are respectively extended to two ends thereof and connected to the common voltage bus respectively; The first data line and the second data line are located in the same layer; The common voltage line and the second data line are located in different layers, and an insulating layer is provided between them; The display substrate further includes a plurality of common voltage transfer lines evenly distributed in the display area; the plurality of common voltage transfer lines are located in the same layer as the second data lines and are parallel to the second data lines; The plurality of common voltage transfer lines are connected to any two common voltage lines through via holes provided in the insulating layer.

15. A display panel, wherein: The display substrate comprises the display substrate according to any one of claims 1 to 14.

16. The display panel according to claim 15, wherein: It also includes a cell-aligning substrate, wherein the cell-aligning substrate and the display substrate are aligned to form a cell-aligning gap, and the cell-aligning gap is filled with negative liquid crystal.

17. A display device, wherein: A display panel comprising any one of claims 15-16.

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