Dft architecture for analog circuits

Abstract

The present application relates to DFT architecture for analog circuits. An integrated circuit (IC) includes a first functional analog pin or pad, a first analog test bus coupled to the first functional analog pin or pad, first and second analog circuits coupled to the first analog test bus, and a test controller configured to connect an input or output of the first analog circuit to the first analog test bus when the IC is in a functional mode of operation such that the input or output of the first analog circuit is accessible by the first functional operating analog pin or pad and to leave an input or output of the second analog circuit disconnected from the first analog test bus, and to selectively connect inputs or outputs of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus when the IC is in a test mode.

Description

Technical Field

[0001] This disclosure generally relates to electronic systems and methods, and in certain embodiments, to a design for testability (DFT) architecture for analog circuits. Background Technology

[0002] Analog circuits in integrated circuits (ICs) are typically tested to ensure that their functionality and electrical parameters meet expectations. Ensuring analog circuits meet expectations can be particularly important in automotive ICs, where compliance with standards such as the Automotive Safety Integrity Level (ASIL) risk classification scheme defined by ISO 26262 may be required. Therefore, ICs such as automotive ICs often include testability features to configure, control, and / or observe one or more aspects of one or more analog circuits within such ICs.

[0003] Examples of analog circuits that can be tested in ICs include analog-to-digital converters (ADCs), digital-to-analog converters (DACs), comparators, and amplifiers.

[0004] An example of using testability features of analog circuits is to provide dedicated test registers (e.g., programmable via JTAG) to configure the analog circuit under test.

[0005] Another example of using analog circuit testability features is providing dedicated analog test pins to control inputs or observe the output of the analog circuit under test. For instance, if an IC's DAC is not designed to provide outputs to external pins of the IC during functional operation, the output of such a DAC can be routed to a dedicated analog test pin so that it can be observed during test mode. As another example, if an IC's ADC is not designed to receive inputs from external pins of the IC during functional operation, inputs for such an ADC can be provided during test mode via a dedicated analog test pin (which is routed to the ADC's input). Dedicated analog test pins are typically grounded during functional operation (e.g., grounded in the PCB of the final product, such as by soldering and connecting to the PCB's ground plane). Summary of the Invention

[0006] According to one embodiment, an integrated circuit includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; a first analog circuit coupled to the first analog test bus; a second analog circuit coupled to the first analog test bus; and a test controller configured to: when the integrated circuit is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus such that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep the input or output of the second analog circuit disconnected from the first analog test bus; and when the integrated circuit is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.

[0007] According to one embodiment, an integrated circuit includes: first and second functional analog pins or pads; first and second analog test buses respectively coupled to the first and second functional analog pins or pads; a first digital-to-analog converter (DAC) having an output coupled to the first analog test bus; a second DAC having an output coupled to the second analog test bus; a differential analog-to-digital converter (ADC) having a first input coupled to the first analog test bus and a second input coupled to the second analog test bus; and a test controller configured to: when the integrated circuit is in a functional operating mode, connect the output of the first DAC to the first analog test bus such that the output of the first DAC is accessible by the first functional analog pin or pad, connect the output of the second DAC to the second analog test bus such that the output of the second DAC is accessible by the second functional analog pin or pad, and keep the first and second inputs of the differential ADC disconnected from the first and second analog test buses respectively; and when the integrated circuit is in a test mode, connect the first and second inputs of the differential ADC to the first and second analog test buses respectively, provide first and second analog signals to the first and second analog test buses using the first and second DACs respectively, and determine whether the first DAC, the second DAC, or the differential ADC is faulty based on the output of the differential ADC.

[0008] According to one embodiment, a method includes: when an integrated circuit is in a non-test mode, connecting an input or output of a first analog circuit to a first analog test bus coupled to a first functional analog pin or pad, such that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keeping the input or output of a second analog circuit disconnected from the first analog test bus; and when the integrated circuit is in a test mode, selectively connecting the inputs or outputs of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus. Attached Figure Description

[0009] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A schematic diagram of a portion of an IC according to an embodiment of the present invention is shown;

[0011] Figure 2 The illustration depicts a parallel testing method according to an embodiment of the present invention. Figure 1 A flowchart of an embodiment method for two DACs of an IC;

[0012] Figure 3 The illustration depicts a parallel testing method according to an embodiment of the present invention. Figure 1 A flowchart of an embodiment method for multiple ADCs of an IC;

[0013] Figure 4 The illustration depicts a parallel testing method according to an embodiment of the present invention. Figure 1 A flowchart of an embodiment of a method using multiple comparators of an IC;

[0014] Figure 5 and Figure 6 The illustration depicts a test according to an embodiment of the present invention. Figure 1 A flowchart illustrating an embodiment of a method using multiple DACs, ADCs, and comparators in an IC;

[0015] Figure 7 The illustration depicts a test according to an embodiment of the present invention. Figure 1 A flowchart of an embodiment method for multiple DACs of an IC; and

[0016] Figure 8 The illustration depicts a test according to an embodiment of the present invention. Figure 1 The flowchart illustrates an embodiment of a method for using multiple DACs, ADCs, and comparators in an IC.

[0017] Unless otherwise stated, corresponding reference numerals and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the preferred embodiments, and the figures are not necessarily drawn to scale. Detailed Implementation

[0018] The following discusses in detail the making and use of the disclosed embodiments. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of making and using the invention and do not limit the scope of the invention.

[0019] The following description illustrates various specific details to provide a thorough understanding of several exemplary embodiments according to the description. These embodiments may be obtained without one or more specific details, or by other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure different aspects of the embodiments. References to "embodiment" in this specification indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment," which may appear at different points in this specification, do not necessarily refer exactly to the same embodiment. Furthermore, particular constructions, structures, or features may be combined in any suitable manner in one or more embodiments.

[0020] Embodiments of the invention will be described in a specific context, such as a DFT architecture for testing analog circuits like DACs, ADCs, and comparators. In some embodiments, the DFT architecture can be used to test other types of analog circuits, such as temperature sensors and bias generators.

[0021] The increasing complexity of ICs, such as automotive ICs, and the high levels of quality expected in such ICs, may lead to an increase in dedicated testability resources within the ICs. For example, complex System-on-Chip (SoC) devices, such as automotive-grade microcontroller ICs, may include multiple dedicated analog test pins (e.g., dedicated pins designed for applying analog signals as inputs to the analog circuit under test or for observing analog signals output from the analog circuit under test) for testing multiple analog circuits within the complex SoC. Reducing the pin count of the IC may be desirable (e.g., to achieve a target die area or form factor). It may also be desirable to reduce the test time associated with testing multiple analog circuits within the SoC.

[0022] In one embodiment of the invention, the functional analog pins of the IC (pins designed to operate as analog lines during normal operation) are also used during test mode to route analog test signals for testing one or more DACs, ADCs, and comparators. The functional analog pins are connected to an analog test bus. The analog test bus is connected to the inputs of one or more ADCs and comparators and to the outputs of one or more DACs. During functional operation mode (outside of test mode), the functional analog pins function as functional analog pins for one or more DACs, ADCs, and comparators. During test mode, the functional analog pins operate as outputs to observe the outputs of the analog test bus, or as inputs to the analog test bus. In some embodiments, analog signals from the analog test bus (e.g., originating from one or more DACs) are observed at the functional analog pins during test mode. In some embodiments, analog signals from the analog test bus (originating from the functional analog pins or from the outputs of one or more DACs) are used as inputs to one or more ADCs and comparators, for example, to test one or more ADCs and comparators in parallel.

[0023] By reusing functional analog pins for testing purposes of one or more ADCs, DACs, and comparators, some embodiments advantageously avoid the need for dedicated analog test pins for testing one or more ADCs, DACs, and comparators, thereby advantageously reusing test pin overhead.

[0024] In some embodiments, because the functional analog pins are designed to carry analog signals during functional mode and already include analog circuitry to allow the use of functional analog pins for carrying analog signals, reusing functional analog pins during test mode to test one or more analog circuits advantageously results in lower overhead (e.g., smaller area) compared to reusing functional digital pins (e.g., GPIO pins) to test analog circuitry. For example, enabling a GPIO cell to carry not only digital signals but also analog signals might require adding dedicated analog lines inside the cell (appropriately sized to minimize resistivity and interference), protecting it with ESD structures, and adding logic to disable both digital input / output buffers and pull-up / pull-down circuitry (if they are not present) for (analog mode functionality).

[0025] By connecting a functional analog test bus to the inputs of multiple ADCs and comparators, some embodiments advantageously achieve test parallelism, thereby advantageously reducing test time. By using an analog test bus connected between the outputs of one or more DACs and the inputs of one or more ADCs and comparators, some embodiments advantageously allow for built-in self-test (BIST) solutions, where the output of one or more DACs is used to test one or more ADCs and comparators, advantageously without intervention from automatic test equipment (ATE).

[0026] Figure 1 A schematic diagram of a portion of an IC 100 according to an embodiment of the present invention is shown. The IC 100 includes pads 152 and 154, analog test buses 162 and 164, N DAC modules 102 (where N is greater than or equal to 1), L DAC modules 106 (where L is greater than or equal to 1), M ADC modules 104 (where M is greater than or equal to 1), P comparator modules 108 (where P is greater than or equal to 1), and a test controller 110.

[0027] In some embodiments, IC 100 is packaged such that pads 152 and 154 are coupled (e.g., via bonding wires) to corresponding pins 152 and 154 of IC 100.

[0028] In some embodiments, pads or pins 152 and 154 are functional pads or pins accessible during the functional operation mode of IC 100. For example, in some embodiments, during the functional operation mode, pad or pin 152 provides the output of one of N DAC modules 102, and pad or pin 154 provides the output of one of L DAC modules 106. In some embodiments, during the functional operation mode, pads or pins 152 and 154 provide differential inputs to one of M ADC modules 104 or to one of P comparator modules 108.

[0029] exist Figure 1 In the illustrated embodiment, in functional operation mode, the output of DAC 124 of DAC module 1021 is connected to pad or pin 152, and in functional operation mode, the output of DAC 124 of DAC module 1061 is connected to pad or pin 154. During functional operation mode, DAC modules 1022 to 102... N The output of DAC 124 is not connected to analog test bus 162 (e.g., the output of such DAC 124 is at high impedance (hi-Z) or routed to the function node by demultiplexer 129), DAC modules 1062 to 102 LThe output of DAC 124 is not connected to analog test bus 164 (e.g., the output of such DAC 124 is at high impedance or routed to a function node by demultiplexer 129), and multiplexers (MUX) 136, 138, 146 and 148 are configured to select inputs coupled to the respective function nodes, rather than selecting inputs from the associated analog test buses (e.g., 162, 164).

[0030] exist Figure 1 In the illustrated embodiment, the outputs of DAC 124 in module 1021 and DAC 124 in module 1061 are connected to analog test buses 162 and 164, respectively, via demultiplexer 129. In some embodiments, since the outputs of demultiplexer 129 in DAC modules 1021 and 1061 are short-circuited, demultiplexer 129 in modules 1021 and 1061 can be omitted, and the DAC outputs of modules 1021 and 1061 can be directly connected to analog test buses 162 and 164, respectively.

[0031] As will be described in more detail below, during the test mode of IC 100, test controller 110 controls modules 102, 104, 106, and 108 to selectively connect the output of DAC 124 and / or the input of ADC 134 and / or the input of comparator 144 to analog test buses 162 and 164 and perform one or more tests to test one or more of modules 102, 104, 106, and 108.

[0032] In some embodiments, each ADC module 104 includes an ADC 134, MUXs 136 and 138, a demultiplexer 139, and DFT logic circuitry 132. The ADC 134 is configured to provide a digital code in a known manner based on the input voltage provided by the outputs of the MUXs 136 and 138. The DFT logic circuitry 132 is configured to cause the MUXs 136 and 138 to selectively connect the inputs of the ADC 134 to a functional node or to analog test buses 162 and 164 based on the outputs from the test controller 110. In some embodiments, the DFT logic circuitry 132 is configured to cause the demultiplexer 139 to selectively connect the outputs of the ADC 134 to a functional node or to the test controller 110 based on the outputs of the test controller 110. In some embodiments, the DFT logic circuitry 132 may be implemented, for example, with digital circuitry, such as using combinational logic. In some embodiments, the MUXs 136 and 138 may be implemented in any manner known in the art. In some embodiments, the demultiplexer 139 may be implemented in any manner known in the art. In some embodiments, the ADC 134 may be implemented in any manner known in the art.

[0033] Examples of functional nodes that can be connected to the inputs of one or more of the MUXs 136 and 138 include nodes within the IC100 that have voltages to be converted into digital codes by the ADC 134 during functional operation mode (i.e., not in test mode). Examples of functional nodes that can be connected to the output of the demultiplexer 139 include digital buses, registers, etc.

[0034] In some embodiments (such as) Figure 1 As shown in the diagram, ADC 134 is a differential ADC. In some embodiments, ADC 134 can be implemented as a single-ended ADC.

[0035] In some embodiments (such as) Figure 1 As shown in the diagram, each ADC 134 of each ADC module 104 is similar to or identical to each other. In some embodiments, one or more ADCs of ADC module 104 may be different (e.g., they may have different resolutions, may be single-ended or differential, may operate at different sampling rates, etc.).

[0036] In some embodiments, each DAC module in DAC modules 102 and 106 includes a DAC 124, a MUX 126, a demultiplexer 129, and a DFT logic circuit 122. DAC 124 is configured to provide an analog signal (e.g., voltage) in a known manner based on an input code provided by the output of MUX 126. DFT logic circuit 122 is configured to cause MUX 126 to selectively connect the input of DAC 124 to a function node or to test controller 110 based on the output from test controller 110. In some embodiments, digital logic circuit 122 is configured to selectively connect the output of DAC 124 to an analog test bus (e.g., 162, 164) or to a function node based on the output of test controller 110. In some embodiments, DFT logic circuit 122 may be implemented, for example, with digital circuitry, such as using combinational logic. In some embodiments, MUX 126 may be implemented in any manner known in the art. In some embodiments, DAC 124 may be implemented in any manner known in the art. For example, in some embodiments, DAC 124 may be a buffered DAC. In some embodiments, DAC124 may be an unbuffered DAC (e.g., a DAC designed to provide only internal circuitry outputs of IC 100). In some embodiments where DAC 124 is an unbuffered DAC, additional injection-proof switches may be added to the DAC's output to allow the DAC to be placed in a high-impedance (hi-Z) state and safely interfaced with the pins or pads (e.g., 152, 154) of IC 100.

[0037] Examples of functional nodes that can be connected to the inputs of one or more MUXs in MUX 126 include nodes within IC 100 that have digital codes (such as digital buses, registers, etc.) to be converted into voltages by DAC 124 during functional operation mode (i.e., not in test mode). Examples of functional nodes that can be connected to the output of demultiplexer 129 include inputs to other analog circuitry of IC 100, such as amplifiers, comparators, regulators, etc.

[0038] In some embodiments (such as) Figure 1 As shown in the diagram, each DAC 124 of each DAC module 102 and 106 is similar to or identical to each other. In some embodiments, one or more DACs of DAC module 102 or 106 may be different (e.g., they may have different resolutions, may operate at different sampling rates, etc.).

[0039] In some embodiments, each comparator module 108 includes a comparator 144, MUXs 146 and 148, a demultiplexer 149, and DFT logic circuitry 142. Comparator 144 is configured to provide an output (e.g., high / low) in a known manner based on an input voltage provided by the outputs of MUXs 146 and 148. DFT logic circuitry 142 is configured to cause MUXs 146 and 148 to selectively connect the input of comparator 144 to a functional node or to analog test buses 162 and 164 based on the output of test controller 110. In some embodiments, DFT logic circuitry 142 is configured to cause demultiplexer 149 to selectively connect the output of comparator 144 to a functional node or to test controller 110 based on the output of test controller 110. In some embodiments, DFT logic circuitry 142 may be implemented, for example, with digital circuitry, such as using combinational logic. In some embodiments, MUXs 146 and 148 may be implemented in any manner known in the art. In some embodiments, comparator 144 may be implemented in any manner known in the art.

[0040] Examples of functional nodes that can be connected to the inputs of one or more of the MUXs 146 and 148 include nodes within the IC100 that have a voltage to be compared with a threshold or with a voltage at another node of the IC100 during functional operation mode (i.e., not in test mode). Examples of functional nodes that can be connected to the output of the demultiplexer 149 include other analog or digital circuitry of the IC100, register bits, etc.

[0041] In some embodiments, such as Figure 1As shown in the diagram, each comparator 144 of each comparator module 108 is similar to or identical to each other. In some embodiments, one or more comparators of comparator module 108 may be different (e.g., they may have different hysteresis, may operate at different speeds, etc.). In some embodiments, comparator 144 may be implemented in any manner known in the art.

[0042] In some embodiments, such as Figure 1 As shown in the diagram, each MUX 136 of module 104 is similar to or identical to each other, each MUX 138 of module 104 is similar to or identical to each other, each MUX 126 of module 102 or 106 is similar to or identical to each other, and each MUX 148 of module 108 is similar to or identical to each other. In some embodiments, one or more MUXs of modules 102, 104, 106 and / or 108 may be different (e.g., they may have different numbers of inputs, etc.).

[0043] In some embodiments (such as) Figure 1 As shown in the diagram, each demultiplexer 139 of module 104 is similar to or identical to each other, each demultiplexer 129 of module 102 or 106 is similar to or identical to each other, and each demultiplexer 149 of module 108 is similar to or identical to each other. In some embodiments, one or more demultiplexers of modules 102, 104, 106 and / or 108 may be different (e.g., may have different numbers of outputs, etc.).

[0044] In some embodiments, the test controller 110 is configured to operate based on the operating mode signal S mode The state is used to control DFT logic circuits 122, 132, and 142. For example, when signal S... mode When the indicated functional operating mode (non-test mode) is engaged, the test controller 110 configures the DFT logic circuits 122, 132, and 142 such that the MUXs 126, 136, 138, 146, and 148, as well as the demultiplexers 129, 139, and 149, couple the associated DAC 124, ADC 134, and comparator 144 to the corresponding functional nodes. As will be described in more detail below, when signal S... mode When a test mode is indicated, the test controller 110 configures the DFT logic circuits 122, 132, and 142 such that the MUXs 126, 136, 138, 146, and 148, as well as the demultiplexers 129, 139, and 149, couple the associated DAC 124, ADC 134, and comparator 144 to the associated analog test bus (e.g., 162, 164) and / or couple the associated DAC 124, ADC 134, and comparator 144 to the test controller 110 to perform one or more tests.

[0045] During test mode, test controller 110 is configured to perform one or more tests to determine if one or more of DAC 124, ADC 134, and / or comparator 144 are faulty. In some embodiments, when a fault is detected, test controller 110 is configured to activate a flag indicating that the circuit has failed the test. In some embodiments, the flag may be received by ATE (not shown) or by the main controller of IC 100 (not shown), and the ATE or main controller may warn the user that a fault has occurred.

[0046] In some embodiments, IC 100 may be, for example, an automotive SoC, such as an automotive microcontroller. In some embodiments, IC 100 may be implemented as other types of ICs, such as a power management IC (PMIC).

[0047] In some embodiments, IC 100 is packaged such that pads 152 and 154 are coupled to corresponding pins of IC 100, for example, via bonding wires.

[0048] Figure 2 A flowchart of an embodiment method 200 for parallel testing of two DACs of IC 100 according to an embodiment of the present invention is illustrated. Method 200 includes steps 202, 204, 206, 208, 210, 212, and 214. Steps 202, 204, 206, 208, 210, 212, and 214 may be performed by or using a test controller 110. In some embodiments, one or more of steps 202, 204, 206, 208, 210, 212, and 214 may be performed by or can be performed by an ATE.

[0049] During step 202, the IC under test (e.g., 100) enters a test mode. For example, in some embodiments, a mode signal (e.g., S) is activated. mode The status changes to indicate that test mode has been entered.

[0050] During step 204, the first DAC (e.g., from DAC modules 1021 to 102) N The output of one of the DACs is connected to the first analog test bus (e.g., 162) via a demultiplexer (e.g., 129), while the outputs of the other DACs (e.g., those from DAC module 102) are not connected to the first analog test bus (e.g., are in a high-impedance state), for example, to avoid contention for the first analog test bus. During step 204, the output of the second DAC (e.g., from DAC modules 1061 to 1062) is connected to the first analog test bus (e.g., 162) via a demultiplexer (e.g., 129), while the outputs of the other DACs (e.g., those from DAC modules 1061 to 1062) are not connected to the first analog test bus (e.g., are in a high-impedance state), for example, to avoid contention for the first analog test bus. LThe output of one of the DACs (e.g., 134) is connected to a second analog test bus (e.g., 164) via a demultiplexer (e.g., 129), while the outputs of other DACs (e.g., DAC module 106) are not connected to the second analog test bus (e.g., are in a high-impedance state), for example, to avoid contention for the second analog test bus. In some embodiments, ADC 134 and comparator 144 are configured to ignore inputs to analog test buses 162 and 164 during steps 204, 206, and 208. As will be described in more detail below, in some embodiments, one or more (or all) ADC 134 and / or comparator 144 are configured to use inputs from analog test buses 162 and 164 to test one or more (or all) ADC 134 and / or comparator 144 (e.g., in parallel) during steps 204, 206, and 208.

[0051] During step 206, corresponding digital inputs are provided to the first and second DACs (e.g., via corresponding MUX 126). In some embodiments, the digital inputs are provided to the first and second DACs by a test controller (e.g., 110). In some embodiments, the digital inputs are provided to the first and second DACs by an ATE. In some embodiments, the digital inputs provided to the first and second DACs are the same. In some embodiments, the digital inputs provided to the first and second DACs are different.

[0052] During step 208, the outputs of the first and second DACs are observed on the first and second analog test buses, respectively. For example, in some embodiments, (e.g., by ATE) the outputs of the first and second DACs are observed at a first pad or pin (e.g., 152) and a second pad or pin (e.g., 154) respectively coupled to the first and second analog test buses. As will be described in more detail below, in some embodiments, the outputs of the first and second DACs are observed by an ADC (e.g., 134) respectively.

[0053] During step 210, it is determined whether the first or second DAC is faulty based on the outputs of the first and second DACs. For example, in some embodiments, the ATE or test controller 110 that observes the output of the first (or second) DAC may determine whether the first (or second) DAC is faulty based on the observed output and the input of the first (or second) DAC. In some embodiments, if a fault is detected during step 210, a flag is activated (e.g., by the test controller).

[0054] As illustrated in steps 212 and 214, in some embodiments, steps 202, 204, 206, and 208 may be performed for each pair of DACs of IC 100. In some embodiments, steps 202, 204, 206, and 208 may be performed for a single DAC at a time.

[0055] like Figure 2 As illustrated, in some embodiments, the two DACs of IC 100 can be advantageously tested in parallel, and pairs of DACs can be tested, for example, sequentially, using only two analog test buses, and advantageously without the need for any dedicated analog test pins.

[0056] Figure 3 A flowchart illustrating an embodiment of a method 300 for parallel testing of multiple ADCs of an IC 100 according to an embodiment of the present invention is shown. Method 300 includes steps 202, 302, 304, 306, and 308. In some embodiments, step 202 may be performed in a manner similar to that described with respect to method 200. In some embodiments, steps 302, 304, 306, and 308 may be performed by or using a test controller 110. In some embodiments, one or more of steps 302, 304, 306, and 308 may be performed by or caused to be performed by an ATE (Automatic Test Equipment).

[0057] During step 302, the ADC modules (1041 to 104) M The first and second inputs of one or more (or all) ADCs are connected to a first analog test bus (e.g., 162) and a second analog test bus (e.g., 164), respectively, via corresponding first MUX (e.g., 136) and second MUX (e.g., 138). As will be described in more detail below, in some embodiments, during step 302, the comparator modules (1081 to 108...) P The first and second inputs of one or more (or all) comparators are respectively connected to the first and second analog test buses.

[0058] During step 304, analog signals (e.g., voltage) are provided to the first and second analog test buses. For example, in some embodiments, the analog signals are provided to the first and second analog test buses via pads or pins 152 and 154, respectively, using ATE. In some embodiments, analog signals are provided to the first and second analog test buses using DAC 124 having an output coupled to the first analog test bus and DAC 124 having an output coupled to the second analog test bus.

[0059] During step 306, the outputs of one or more (or all) ADCs are observed individually. For example, in some embodiments, the outputs of one or more (or all) ADCs are routed to a test controller (e.g., 110) and observed by the test controller. In some embodiments, the outputs of one or more (or all) ADCs are routed to one or more registers of IC 100 and observed by the ATE or the master controller of IC 100 by accessing such registers. In some embodiments, such registers are located within DFT logic circuitry 132. In some embodiments, the outputs of one or more (or all) ADCs are routed to digital pads (not shown) and accessed by the ATE.

[0060] During step 308, a fault in one or more ADCs is determined (e.g., by a test controller, a main controller, or an ATE) based on the output of one or more ADCs. In some embodiments, if a fault is detected during step 308, a flag is activated (e.g., by a test controller).

[0061] In some embodiments where the ADC 134 is implemented as a single-ended ADC, the ADC 134 can be tested using only a single analog test bus.

[0062] like Figure 3 As illustrated, in some embodiments, multiple or all differential ADCs of IC 100 can advantageously be tested in parallel using only two analog test buses and advantageously without the use of any dedicated analog test pins. In some embodiments, multiple or all single-ended ADCs of IC 100 can advantageously be tested in parallel using only one analog test bus and advantageously without the use of any dedicated analog test pins. In some embodiments where the input to the ADC under test is provided by one or more DACs of IC 100, the ADC can advantageously be tested in the field without the use of ATE.

[0063] Figure 4 A flowchart illustrating an embodiment method 400 for parallel testing of multiple comparators of IC 100 according to an embodiment of the present invention is shown. Method 400 includes steps 202, 402, 304, 404, and 406. In some embodiments, steps 202 and 304 may be performed in a manner similar to that described with respect to methods 200 and 300. In some embodiments, steps 402, 404, and 406 may be performed by or using a test controller 110. In some embodiments, one or more of steps 402, 404, and 406 may be performed by an ATE or made to be performed by an ATE.

[0064] During step 402, the comparator modules (1081 to 108)P The first and second inputs of one or more (or all) comparators of the ADC are connected to a first analog test bus (e.g., 162) and a second analog test bus (e.g., 164), respectively, via corresponding first MUX (e.g., 146) and second MUX (e.g., 148). In some embodiments, during step 402, the ADC modules (1041 to 104) M The first and second inputs of one or more (or all) ADCs are respectively connected to the first and second analog test buses.

[0065] During step 404 and after step 304, the outputs of one or more comparators are observed. For example, in some embodiments, the outputs of one or more comparators are routed to a test controller (e.g., 110) and observed by the test controller. In some embodiments, the outputs of one or more comparators are routed to one or more registers of IC 100 and observed by the ATE or the master controller of IC 100 by accessing these registers. In some embodiments, such registers are located within DFT logic circuitry 142. In some embodiments, the outputs of one or more comparators are routed to digital pads (not shown) and accessed by the ATE.

[0066] During step 406, a fault in one or more comparators is determined (e.g., by a test controller, main controller, or ATE) based on the output of one or more (or all) comparators. In some embodiments, if a fault is detected during step 406, a flag is activated (e.g., by a test controller).

[0067] In some embodiments where one of the inputs to comparator 144 is fixed (e.g., a fixed threshold), comparator 144 can be tested using only a single analog test bus.

[0068] like Figure 4 As illustrated, in some embodiments, multiple or all comparators of IC 100 can advantageously be tested in parallel using one or at most two analog test buses and advantageously without the use of any dedicated analog test pins. In some embodiments where the input of the comparator under test is provided by one or more DACs of IC 100, the comparator can advantageously be tested in the field without the use of ATE.

[0069] Figure 5A flowchart illustrating an embodiment of a method 500 for testing a plurality of DACs, ADCs, and comparators of IC 100 according to an embodiment of the present invention is shown. Method 500 includes steps 502 and 504. Step 502 includes steps 202, 204, 206, 208, 210, 212, and 214. Step 504 includes steps 204, 302, 304, 306, 308, 402, 404, and 406. In some embodiments, steps 202, 204, 206, 208, 210, 212, 214, 302, 304, 306, 308, 402, 404, and 406 may be performed in a manner similar to that described with respect to methods 200, 300, and 400.

[0070] In some embodiments, during step 502, the DAC of IC 100 is tested, for example using ATE (e.g., for performing steps 208 and 210). Once the DAC of IC 100 has been tested (and passed the test), during step 504, the ADC and comparator of IC 100 are tested in parallel (e.g., in BIST mode) by providing analog signals to the analog test bus using (e.g., a pair) of already tested (and good) DACs.

[0071] By using an ATE (Automatic Test Equipment) during step 502 to test the DAC, some embodiments advantageously allow determining whether the DAC of IC 100 is good (e.g., ensuring that the functionality and electrical parameters of such a DAC meet expectations). By testing all ADCs and comparators of IC 100 using a tested and good DAC, some embodiments advantageously determine in parallel whether any ADC and comparator is faulty without using an ATE (this may make the test run faster than when using an ATE). In some embodiments, using a tested and good DAC of IC 100 to test the ADC of IC 100 has the additional advantage of cross-checking the BIST with the ATE by comparing the results of step 504 (from step 308) with the results of step 502 (from step 210).

[0072] In some embodiments, such as when ADC 134 is a single-ended ADC and one of the inputs to comparator 144 is fixed, method 500 can be performed using a single analog test bus without the need for dedicated analog test pins.

[0073] like Figure 5 As illustrated, some embodiments advantageously use one or at most two analog test buses without the need for dedicated analog test pins or pads to test all DACs, ADCs, and comparators of IC 100.

[0074] Figure 6A flowchart illustrating an embodiment of a method 600 for testing a plurality of DACs, ADCs, and comparators of IC 100 according to an embodiment of the present invention is shown. Method 600 includes steps 202, 204, 206, 208, 210, 212, 214, 302, 304, 306, 308, 402, 404, and 406. In some embodiments, steps 202, 204, 206, 208, 210, 212, 214, 302, 304, 306, 308, 402, 404, and 406 may be performed in a manner similar to that described with respect to methods 200, 300, and 400.

[0075] like Figure 6 As shown, one or more (or all) ADCs and comparators are repeatedly tested with different DAC pairs. In some embodiments, repeatedly testing the same ADC and / or comparator with different DACs advantageously allows for the detection of faults in one or more DACs, ADCs, and comparators in a BIST manner without the use of ATE. For example, if all ADCs fail the test when testing the first pair of DACs (step 308), but all ADCs pass the test when testing the second pair of DACs (step 308), then it can be determined that the first pair of DACs is faulty during step 210. In some embodiments, if the same ADC fails the test during multiple DAC pair tests (during step 308), then it can be determined that the ADC is faulty during step 308.

[0076] Some embodiments offer advantages including simultaneously satisfying constraints on the number of pins or pads available for testing at a given step in the test flow (during characterization, production, or in the field) and the number of desired signals to be controlled / observed, potentially achieving optimal test parallelism. By testing the analog circuitry of an IC (e.g., ADCs, DACs, and comparators) without the need for dedicated analog test pins or pads, some embodiments advantageously allow testing such analog circuitry in pin- or pad-constrained devices. Some embodiments advantageously implement internal testing of such analog circuitry (using BIST) without the need for ATE. Some embodiments advantageously achieve high test parallelism (e.g., by testing all ADCs and comparators in parallel), which can advantageously reduce test time.

[0077] In some embodiments, by using instances of the same analog circuit design (e.g., 102 / 106, 104, 108) including DFT logic circuitry, some embodiments advantageously achieve scalability and simplify signal routing and congestion. For example, in some embodiments, the use of a common analog bus advantageously simplifies the routing of analog signals. In some embodiments, tight physical coupling of the DFT logic circuitry with its respective modules advantageously simplifies the routing of module configuration signals.

[0078] In some embodiments (e.g., such as) Figure 1 As shown in the diagram, each DAC module in DAC modules 102 and 106 corresponds to an instance of the same DAC module design, each ADC module in ADC module 104 corresponds to an instance of the same ADC module design, and each comparator module in comparator module 108 corresponds to an instance of the same comparator module design. By incorporating DFT logic circuitry (e.g., 122, 132, 142), MUX (126, 136, 138, 146, 148), and demultiplexers (e.g., 129, 139, 149) within the analog circuitry (e.g., 102, 104, 106, 108), some embodiments advantageously achieve portability of the DFT solution from one generation of devices to the next generation of devices or across different devices, thereby advantageously helping to reduce product development time and make device design and test procedure development more efficient.

[0079] In some embodiments, the DFT logic circuitry associated with modules 102, 104, 106, and 108 is implemented as a digital block built around its associated module. For example, analog modules (e.g., 102, 104, 106, and 108) can be designed first, and then the DFT digital circuitry can be attached to the already designed analog modules. In such embodiments, modularity is achieved because it may be sufficient to instantiate the associated DFT logic circuitry multiple times around the corresponding instantiation of the associated analog module to achieve testability.

[0080] like Figure 2 , Figure 5 and Figure 6 As illustrated, in some embodiments, two analog test buses can be used to test two DACs of IC 100 in parallel. In some embodiments, a single analog test bus can be used to test two, three, or more DACs of IC 100 in parallel. For example, Figure 7A flowchart of an embodiment method 700 for testing a plurality of DACs of IC 100 according to an embodiment of the present invention is illustrated. Method 700 includes steps 202, 204, 208, 212, 214, 702, 704, 706, 708, and 710. In some embodiments, steps 202, 204, 208, 212, and 214 may be performed in a manner similar to that described with respect to method 200. In some embodiments, steps 702, 704, 706, 708, and 710 may be performed by or using a test controller 110. In some embodiments, one or more of steps 702, 704, 706, 708, and 710 may be performed by an ATE or made to be performed by an ATE.

[0081] During step 702, the same digital code is provided to the inputs of all DACs (e.g., all DACs 124 of all DAC modules 102 and 106), for example via a MUX (e.g., 126). In some embodiments, the digital code is provided to all DACs by a test controller (e.g., 110). In some embodiments, the digital code is provided to all DACs by an ATE.

[0082] After connecting the first pair of DACs to the first analog test bus (e.g., 162) and the second analog test bus (e.g., 164) during step 204, the output generated by the first pair of DACs is observed during step 208 and stored during step 704. In some embodiments, the output is observed by one or more ADCs 134 (via the analog test bus) and stored in the memory of the test controller. In some embodiments, the output is observed by the ATE (via the analog test bus) and stored in the ATE.

[0083] As illustrated in loop 722 (which includes steps 204, 208, 704, 212, and 214), all DAC pairs are iterated, and their corresponding outputs are stored in memory for use with the same digital code.

[0084] As illustrated in loop 724 (which includes steps 706 and 708), after testing all DACs with a first digital code, all DACs are then tested with new digital codes until all DACs are tested with all selected digital codes. For example, in some embodiments, the digital codes form a digital ramp that begins, for example, with code R and ends with code Q. In some embodiments, R and Q correspond to the minimum and maximum input codes of the DAC, respectively. For example, for an 8-bit DAC, the minimum input code could be 0 and the maximum input code could be 255. In some embodiments, Q is lower than the maximum input code of the DAC and R is higher than the minimum input code of the DAC.

[0085] In some embodiments, during step 708, the numeric code is monotonically updated (e.g., by ramping up or down, for example) starting with code R (or Q) and ending with code Q (or R). In some embodiments, each code between R and Q is tested (each update during step 708 changes the numeric code by 1). In some embodiments, not every code between R and Q is tested (e.g., each update during step 708 changes the numeric code by more than 1).

[0086] If the result of step 706 is "No", then during step 710, for each DAC, it is determined whether the DAC is faulty based on the data stored during the execution of the corresponding step 704.

[0087] In some embodiments, loop 722 is performed by rapidly connecting and disconnecting DAC 124 to select the desired pair of DAC 124 by switching demultiplexer 129 (e.g., at rates of tens of kHz, such as between 10 kHz and 100 kHz), and loop 724 is performed by monotonically and rapidly updating the digital code. In such embodiments, the voltage at the analog test bus can resemble (or be) a voltage ramp, and the settling time before observation (measurement) during step 208 can be minimized because the voltage at the analog test bus is already at or near a stable value. Therefore, in some embodiments, it is advantageous to use analog test bus 162 and method 700 to test multiple DACs in parallel (e.g., all DACs of DAC module 102), and it is advantageous to use analog test bus 164 and method 700 to test multiple DACs in parallel (e.g., all DACs of DAC module 106).

[0088] In some embodiments, method 500 may be adapted to include the parallel testing illustrated in method 700. For example, in some embodiments, step 502 may be performed as method 700.

[0089] In some embodiments, method 600 may be adapted to include the parallel testing illustrated in method 700. For example, Figure 8A flowchart illustrating an embodiment of a method 800 for testing a plurality of DACs, ADCs, and comparators of IC 100 according to an embodiment of the present invention is shown. Method 800 includes steps 202, 204, 212, 214, 302, 304, 306, 402, 404, 406, 702, 704, 706, 708, and 802. In some embodiments, steps 202, 204, 212, 214, 302, 304, 306, 402, 404, 406, 702, 704, 706, and 708 may be performed in a manner similar to that described with respect to methods 200, 300, 400, and 700.

[0090] like Figure 8 As shown, method 800 operates in a similar manner to method 600, but tests multiple DACs simultaneously instead of testing DAC pairs sequentially. During method 800, the output of the DAC is observed by observing the output of one or more (or all) ADCs during step 306, and such output is stored during step 704.

[0091] If the result of step 706 is "No", then during step 802, for each DAC and ADC pair, it is determined whether the DAC or ADC is faulty based on the data stored during the execution of the corresponding step 704.

[0092] Some embodiments offer advantages such as reusing functional pins or pads to provide test capabilities to analog circuitry (e.g., DACs, ADCs, and / or comparators) without the need for dedicated analog test pins, thus advantageously allowing zero overhead in terms of not requiring additional analog test pins to add testability to such analog circuitry. Additional advantages of some embodiments include the ability to test multiple DACs in a quasi-parallel manner using a single shared analog test bus by rapidly and sequentially switching the outputs of multiple DACs while simultaneously ramping the input codes of all DACs.

[0093] Other advantages of some embodiments include the ability to cross-check results between ATE and BIST type tests (e.g., by measuring analog signals from an analog test bus with an ATE and comparing the measurement results with the output of an ADC).

[0094] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and the claims filed herein.

[0095] Example 1. An integrated circuit includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; a first analog circuit coupled to the first analog test bus; a second analog circuit coupled to the first analog test bus; and a test controller configured to: when the integrated circuit is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus such that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep the input or output of the second analog circuit disconnected from the first analog test bus; and when the integrated circuit is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.

[0096] Example 2. The integrated circuit according to Example 1 further includes a plurality of digital-to-analog converters (DACs) having respective outputs coupled to a first analog test bus, wherein the first analog circuit or the second analog circuit includes a DAC among the plurality of DACs, and wherein, when the integrated circuit is in test mode, a test controller is configured to: provide the same first digital code to a respective input of each of the plurality of DACs; sequentially connect the output of each of the plurality of DACs to the first analog test bus such that the respective DAC provides a respective first analog signal to the first analog test bus, and disconnect the respective output of the respective DAC from the first analog test bus after the respective DAC has provided the respective first analog signal to the first analog test bus; and determine whether one or more of the plurality of DACs are faulty based on the first analog signal provided to the first analog test bus.

[0097] Example 3. An integrated circuit according to one of Examples 1 or 2 further includes a first analog-to-digital converter (ADC) having an input coupled to a first analog test bus, wherein when the integrated circuit is in test mode, the test controller is further configured to: for each of the plurality of DACs, use the first ADC to measure a corresponding first analog signal at the first analog test bus, wherein the test controller is configured to determine, based on the output of the first ADC, whether one or more of the plurality of DACs is faulty.

[0098] Example 4. An integrated circuit according to any one of Examples 1 to 3 further includes a plurality of digital-to-analog converters (DACs) having respective outputs coupled to a first analog test bus, wherein when the integrated circuit is in test mode, a test controller is configured to: provide a monotonic digital code sequence to the respective inputs of the plurality of DACs, wherein the test controller is configured to simultaneously provide each digital code in the monotonic digital code sequence to the respective input of each of the plurality of DACs; for each digital code in the monotonic digital code sequence, sequentially for each of the plurality of DACs, connect the respective output of the respective DAC to the first analog test bus such that the respective DAC provides a respective first analog signal to the first analog test bus; after the respective DAC provides the respective analog signal to the first analog test bus, disconnect the respective output of the respective DAC from the first analog test bus; and determine whether one or more of the plurality of DACs are faulty based on the first analog signal provided to the first analog test bus.

[0099] Example 5. An integrated circuit according to one of Examples 1 to 4, wherein a first analog circuit or a second analog circuit includes a DAC among a plurality of DACs.

[0100] Example 6. An integrated circuit according to one of Examples 1 to 5 further includes a plurality of analog-to-digital converters (ADCs) having respective inputs coupled to a first analog test bus, wherein when the integrated circuit is in test mode, the test controller is further configured to: measure a corresponding first analog signal at the first analog test bus using the plurality of ADCs for each of the plurality of DACs and for each digital code in a monotonic digital code sequence, wherein the test controller is configured to determine whether one or more of the plurality of DACs is faulty based on the outputs of the plurality of ADCs.

[0101] Example 7. An integrated circuit according to one of Examples 1 to 6, wherein the test controller is also configured to determine whether one or more of the multiple ADCs are faulty based on the output of the multiple ADCs.

[0102] Example 8. An integrated circuit according to one of Examples 1 to 7, wherein a first analog circuit or a second analog circuit includes one of a plurality of ADCs.

[0103] Example 9. An integrated circuit according to any one of Examples 1 to 8 further includes: a plurality of analog-to-digital converters (ADCs) having a first input coupled to a first analog test bus, a plurality of digital-to-analog converters (DACs) having outputs coupled to the first analog test bus, and a plurality of comparators having a first input coupled to the first analog test bus, wherein the first analog circuit or the second analog circuit includes one of the plurality of DACs and one of the plurality of ADCs, or one of the plurality of comparators, wherein the test controller is configured to: connect the output of the first DAC of the plurality of DACs to the first analog test bus; connect a corresponding first input of each of the plurality of ADCs to the first analog test bus; connect a corresponding first input of each of the plurality of comparators to the first analog test bus; provide an analog signal to the first analog test bus with the output of the first DAC when the first inputs of the plurality of ADCs and the first inputs of the plurality of comparators are connected to the analog test bus; and determine whether one or more of the plurality of ADCs are faulty based on the corresponding outputs of the plurality of ADCs; and determine whether one or more of the plurality of comparators are faulty based on the corresponding outputs of the plurality of comparators.

[0104] Example 10. An integrated circuit according to any one of Examples 1 to 9, further comprising: a plurality of DAC modules, each of the plurality of DAC modules including a corresponding DAC among the plurality of DACs and design-for-test (DFT) logic circuitry; a plurality of ADC modules, each of the plurality of ADC modules including a corresponding ADC among the plurality of ADCs and DFT logic circuitry; a plurality of comparator modules, each of the plurality of comparator modules including a corresponding comparator among the plurality of comparators and DFT logic circuitry, wherein a test controller includes outputs coupled to corresponding inputs of the DFT logic circuitry of the plurality of DAC modules, the plurality of ADC modules, and the plurality of comparator modules, and wherein the test controller is configured to: connect the output of the first DAC to a first analog test bus using the DFT logic circuitry of the DAC module including the first DAC; connect a corresponding first input of each of the plurality of ADCs to the first analog test bus using the corresponding DFT logic circuitry of the plurality of ADC modules; and connect a corresponding first input of each of the plurality of comparators to the first analog test bus using the corresponding DFT logic circuitry of the plurality of comparator modules.

[0105] Example 11. An integrated circuit according to one of Examples 1 to 10, wherein each of the plurality of DAC modules is an instance of the same DAC design, each of the plurality of ADC modules is an instance of the same ADC design, and each of the plurality of comparator modules is an instance of the same comparator module design.

[0106] Example 12. An integrated circuit according to any one of Examples 1 to 11 further includes a plurality of DAC modules, each of the plurality of DAC modules including a corresponding DAC of the plurality of DACs, and a demultiplexer having an input coupled to the output of the corresponding DAC, wherein a first analog circuit includes a first DAC module of the plurality of DAC modules, wherein the demultiplexer of the first DAC module includes a first output coupled to a first analog test bus and a second output shorted to the first output, and wherein the demultiplexer of the second DAC module of the plurality of DAC modules includes a first output coupled to the first analog test bus and a second output coupled to a functional internal node of the integrated circuit.

[0107] Example 13. An integrated circuit according to any one of Examples 1 to 12, further comprising: a second functional analog pin or pad; a second analog test bus coupled to the second functional analog pin or pad; a third analog circuit coupled to the second analog test bus; and a fourth analog circuit coupled to the second analog test bus, wherein the test controller is configured to: when the integrated circuit is in a functional operating mode, connect an input or output of the third analog circuit to the second analog test bus such that the input or output of the third analog circuit is accessible by the second functional analog pin or pad, and keep the input or output of the fourth analog circuit disconnected from the second analog test bus; and when the integrated circuit is in a test mode, test the third analog circuit using the second analog test bus, connect the input or output of the fourth analog circuit to the second analog test bus, and test the fourth analog circuit using the first analog test bus.

[0108] Example 14. An integrated circuit according to any one of Examples 1 to 13 further includes: a first digital-to-analog converter (DAC) having an output coupled to a first analog test bus, a second DAC having an output coupled to a second analog test bus, and a differential analog-to-digital converter (ADC) having a first input coupled to the first analog test bus and a second input coupled to the second analog test bus, wherein when the integrated circuit is in test mode, a test controller is configured to: connect the output of the first DAC to the first analog test bus; connect the output of the second DAC to the second analog test bus; connect the first and second inputs of the differential ADC to the first and second analog test buses, respectively; provide a first analog signal to the first analog test bus using the first DAC; provide a second analog signal to the second analog test bus using the second DAC; and determine whether the differential ADC is faulty based on the output of the differential ADC.

[0109] Example 15. An integrated circuit according to one of Examples 1 to 14, wherein the first analog circuit includes a first buffered digital-to-analog converter (DAC) having an output coupled to a first analog test bus, and wherein during a functional operation mode, the output of the first buffered DAC is connected to a first functional analog pin or pad and configured to provide an analog signal to the first functional analog pin or pad based on the input of the first buffered DAC.

[0110] Example 16. An integrated circuit according to one of Examples 1 to 15, wherein the second analog circuit includes a second unbuffered DAC having an output coupled to a first analog test bus.

[0111] Example 17. An integrated circuit according to one of Examples 1 to 16, wherein the second analog circuit includes an analog-to-digital converter (ADC) or comparator having an input coupled to a first analog test bus.

[0112] Example 18. An integrated circuit according to one of Examples 1 to 17, wherein the first analog circuit includes a first analog-to-digital converter (ADC) having an input coupled to a first analog test bus.

[0113] Example 19. An integrated circuit according to one of Examples 1 to 18, wherein the second analog circuit includes: a digital-to-analog converter (DAC) having an output coupled to a first analog test bus, a second ADC having an input coupled to the first analog test bus, or a comparator having an input coupled to the first analog test bus.

[0114] Example 20. An integrated circuit according to one of Examples 1 to 19, wherein the integrated circuit is disposed in a printed circuit board (PCB) and wherein the first functional analog pin or pad is not connected to the ground plane of the PCB.

[0115] Example 21. An integrated circuit according to one of Examples 1 to 20, wherein the integrated circuit includes a first functional pad coupled to a first functional analog pin via a bonding wire.

[0116] Example 22. An integrated circuit includes: first and second functional analog pins or pads; first and second analog test buses respectively coupled to the first and second functional analog pins or pads; a first digital-to-analog converter (DAC) having an output coupled to the first analog test bus; a second DAC having an output coupled to the second analog test bus; a differential analog-to-digital converter (ADC) having a first input coupled to the first analog test bus and a second input coupled to the second analog test bus; and a test controller configured to: when the integrated circuit is in a functional operating mode, connect the output of the first DAC to the first analog test bus such that the output of the first DAC is accessible by the first functional analog pin or pad, connect the output of the second DAC to the second analog test bus such that the output of the second DAC is accessible by the second functional analog pin or pad, and keep the first and second inputs of the differential ADC disconnected from the first and second analog test buses respectively; and when the integrated circuit is in a test mode, connect the first and second inputs of the differential ADC to the first and second analog test buses respectively, provide first and second analog signals to the first and second analog test buses using the first and second DACs respectively, and determine whether the first DAC, the second DAC, or the differential ADC is faulty based on the output of the differential ADC.

[0117] Example 23. A method comprising: when an integrated circuit is in a non-test mode, connecting an input or output of a first analog circuit to a first analog test bus coupled to a first functional analog pin or pad such that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keeping the input or output of a second analog circuit disconnected from the first analog test bus; and when the integrated circuit is in a test mode, selectively connecting the inputs or outputs of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.

[0118] While the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of exemplary embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art during the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An integrated circuit, comprising: First function analog pin or first function analog pad; A first analog test bus is coupled to the first functional analog pin or the first functional analog pad. The first analog circuit is coupled to the first analog test bus; The second analog circuit is coupled to the first analog test bus; as well as The test controller is configured as follows: When the integrated circuit is in functional operation mode, the input or output of the first analog circuit is connected to the first analog test bus, so that the input or output of the first analog circuit can be accessed by the first functional analog pin or the first functional analog pad, while the input or output of the second analog circuit remains disconnected from the first analog test bus. When the integrated circuit is in test mode, the input or output of the first analog circuit and the input or output of the second analog circuit are selectively connected to the first analog test bus to test the first analog circuit and the second analog circuit using the first analog test bus.

2. The integrated circuit of claim 1, further comprising a plurality of digital-to-analog converters (DACs), the plurality of DACs having corresponding outputs coupled to the first analog test bus, wherein the first analog circuit or the second analog circuit includes one of the plurality of DACs, and wherein, When the integrated circuit is in the test mode, the test controller is configured as follows: The same first digital code is provided to the corresponding input of each of the plurality of DACs; For each of the plurality of DACs, the output of the corresponding DAC is sequentially connected to the first analog test bus, such that the corresponding DAC provides a corresponding first analog signal to the first analog test bus, and after the corresponding DAC provides the corresponding first analog signal to the first analog test bus, the corresponding output of the corresponding DAC is disconnected from the first analog test bus. as well as The first analog signal provided to the first analog test bus is used to determine whether one or more of the plurality of DACs are faulty.

3. The integrated circuit of claim 2, further comprising a first analog-to-digital converter (ADC), the first ADC having an input coupled to the first analog test bus, wherein when the integrated circuit is in the test mode, the test controller is further configured to: For each of the plurality of DACs, the first ADC is used to measure a corresponding first analog signal at a first analog test bus, wherein the test controller is configured to determine whether one or more of the plurality of DACs are faulty based on the output of the first ADC.

4. The integrated circuit of claim 1, further comprising a plurality of digital-to-analog converters (DACs), the plurality of DACs having corresponding outputs coupled to the first analog test bus, wherein when the integrated circuit is in the test mode, the test controller is configured to: A monotonic digital code sequence is provided to the corresponding inputs of a plurality of DACs, wherein the test controller is configured to simultaneously provide each digital code in the monotonic digital code sequence to the corresponding input of each of the plurality of DACs; For each digital code in the monotonic digital code sequence, sequentially for each of the plurality of DACs, the corresponding output of the corresponding DAC is connected to the first analog test bus, such that the corresponding DAC provides a corresponding first analog signal to the first analog test bus, and after the corresponding DAC provides the corresponding analog signal to the first analog test bus, the corresponding output of the corresponding DAC is disconnected from the first analog test bus. as well as The first analog signal provided to the first analog test bus is used to determine whether one or more of the plurality of DACs are faulty.

5. The integrated circuit of claim 4, wherein the first analog circuit or the second analog circuit includes one of the plurality of DACs.

6. The integrated circuit of claim 4, further comprising a plurality of analog-to-digital converters (ADCs) having corresponding inputs coupled to the first analog test bus, wherein when the integrated circuit is in the test mode, the test controller is further configured to: For each of the plurality of DACs and for each digital code in the monotonic digital code sequence, the corresponding first analog signal at the first analog test bus is measured using the plurality of ADCs, wherein the test controller is configured to determine whether one or more of the plurality of DACs are faulty based on the output of the plurality of ADCs.

7. The integrated circuit of claim 6, wherein the test controller is further configured to determine whether one or more of the plurality of ADCs are faulty based on the output of the plurality of ADCs.

8. The integrated circuit of claim 6, wherein the first analog circuit or the second analog circuit comprises one of the plurality of ADCs.

9. The integrated circuit according to claim 1, further comprising: The system comprises a plurality of analog-to-digital converters (ADCs) coupled to a first input of the first analog test bus, a plurality of digital-to-analog converters (DACs) coupled to an output of the first analog test bus, and a plurality of comparators coupled to a first input of the first analog test bus, wherein the first analog circuit or the second analog circuit includes one of the plurality of DACs and one of the plurality of ADCs, or one of the plurality of comparators, wherein the test controller is configured to: Connect the output of the first DAC among the plurality of DACs to the first analog test bus; Connect the corresponding first input of each of the plurality of ADCs to the first analog test bus; as well as Connect the corresponding first input of each of the plurality of comparators to the first analog test bus; When the first inputs of the plurality of ADCs and the first inputs of the plurality of comparators are connected to the analog test bus, the output of the first DAC provides an analog signal to the first analog test bus. as well as Based on the corresponding outputs of the plurality of ADCs, determine whether one or more of the plurality of ADCs are faulty; as well as The fault of one or more of the comparators is determined based on the corresponding outputs of the comparators.

10. The integrated circuit according to claim 9, further comprising: Multiple DAC modules, each of the multiple DAC modules including a corresponding DAC among the multiple DACs, and a Design for Testability (DFT) logic circuit; Multiple ADC modules, each of the multiple ADC modules including a corresponding ADC among the multiple ADCs, and DFT logic circuitry; as well as A plurality of comparator modules, each of the plurality of comparator modules including a corresponding comparator among the plurality of comparators, and DFT logic circuitry, wherein a test controller includes an output, the output of the test controller being coupled to a corresponding input of the DFT logic circuitry of the plurality of DAC modules, a corresponding input of the DFT logic circuitry of the plurality of ADC modules, and a corresponding input of the DFT logic circuitry of the plurality of comparator modules, and wherein the test controller is configured to: Using the DFT logic circuit of the DAC module including the first DAC, the output of the first DAC is connected to the first analog test bus; Using the corresponding DFT logic circuits of the plurality of ADC modules, the corresponding first input of each of the plurality of ADCs is connected to the first analog test bus, and Using the corresponding DFT logic circuits of the plurality of comparator modules, the corresponding first input of each of the plurality of comparators is connected to the first analog test bus.

11. The integrated circuit of claim 10, wherein each of the plurality of DAC modules is an instance of the same DAC design, each of the plurality of ADC modules is an instance of the same ADC design, and each of the plurality of comparator modules is an instance of the same comparator module design.

12. The integrated circuit of claim 1, further comprising a plurality of DAC modules, each of the plurality of DAC modules including a corresponding DAC of the plurality of DACs and a demultiplexer having an input coupled to the output of the corresponding DAC, wherein the first analog circuit includes a first DAC module of the plurality of DAC modules, wherein the demultiplexer of the first DAC module includes a first output coupled to the first analog test bus and a second output shorted to the first output, and wherein the demultiplexer of the second DAC module of the plurality of DAC modules includes a first output coupled to the first analog test bus and a second output coupled to a functional internal node of the integrated circuit.

13. The integrated circuit according to claim 1, further comprising: Second-function analog pin or second-function analog pad; The second analog test bus is coupled to the second functional analog pin or the second functional analog pad; The third analog circuit is coupled to the second analog test bus; as well as A fourth analog circuit is coupled to the second analog test bus, wherein the test controller is configured to: When the integrated circuit is in the functional operation mode, the input or output of the third analog circuit is connected to the second analog test bus, so that the input or output of the third analog circuit can be accessed by the second functional analog pin or the second functional analog pad, while the input or output of the fourth analog circuit remains disconnected from the second analog test bus. When the integrated circuit is in the test mode, the third analog circuit is tested using the second analog test bus, the input or output of the fourth analog circuit is connected to the second analog test bus, and the fourth analog circuit is tested using the first analog test bus.

14. The integrated circuit according to claim 13, further comprising: The integrated circuit comprises a first digital-to-analog converter (DAC) having an output coupled to the first analog test bus, a second DAC having an output coupled to the second analog test bus, and a differential ADC having a first input coupled to the first analog test bus and a second input coupled to the second analog test bus, wherein the test controller is configured to: Connect the output of the first DAC to the first analog test bus; Connect the output of the second DAC to the second analog test bus; The first input and the second input of the differential ADC are respectively connected to the first analog test bus and the second analog test bus; The first analog signal is provided to the first analog test bus using the first DAC; The second analog signal is provided to the second analog test bus using the second DAC; as well as The differential ADC is used to determine whether it is faulty.

15. The integrated circuit of claim 1, wherein the first analog circuit includes a first buffered digital-to-analog converter (DAC) having an output coupled to the first analog test bus, and wherein during the functional operation mode, the output of the first buffered DAC is connected to the first functional analog pin or the first functional analog pad and configured to provide an analog signal to the first functional analog pin or the first functional analog pad based on the input of the first buffered DAC.

16. The integrated circuit of claim 15, wherein the second analog circuit includes a second unbuffered DAC having an output coupled to the first analog test bus.

17. The integrated circuit of claim 15, wherein the second analog circuit includes an analog-to-digital converter (ADC) or a comparator having an input coupled to the first analog test bus.

18. The integrated circuit of claim 1, wherein the first analog circuit includes a first analog-to-digital converter (ADC) having an input coupled to the first analog test bus.

19. The integrated circuit of claim 1, wherein the second analog circuit comprises: A digital-to-analog converter (DAC) having an output coupled to the first analog test bus, a second ADC having an input coupled to the first analog test bus, or a comparator having an input coupled to the first analog test bus.

20. The integrated circuit of claim 1, wherein the integrated circuit is disposed in a printed circuit board (PCB), and wherein the first functional analog pin or the first functional analog pad is not connected to the ground plane of the PCB.

21. The integrated circuit of claim 1, wherein the integrated circuit includes the first functional analog pad, the first functional analog pad being coupled to the first functional analog pin via a bonding wire.

22. An integrated circuit, comprising: First function analog pin or first function analog pad; second function analog pin or second function analog pad; The first analog test bus and the second analog test bus are respectively coupled to the first functional analog pin or the first functional analog pad and the second functional analog pin or the second functional analog pad. A first digital-to-analog converter (DAC) has an output coupled to the first analog test bus; The second DAC has an output coupled to the second analog test bus; A differential ADC has a first input coupled to the first analog test bus and a second input coupled to the second analog test bus; as well as The test controller is configured as follows: When the integrated circuit is in functional operation mode, the output of the first DAC is connected to the first analog test bus so that the output of the first DAC can be accessed by the first functional analog pin or the first functional analog pad; the output of the second DAC is connected to the second analog test bus so that the output of the second DAC can be accessed by the second functional analog pin or the second functional analog pad; and the first and second inputs of the differential ADC are kept disconnected from the first analog test bus and the second analog test bus, respectively. When the integrated circuit is in test mode, the first input and the second input of the differential ADC are connected to the first analog test bus and the second analog test bus, respectively. The first DAC and the second DAC are used to provide the first analog signal and the second analog signal to the first analog test bus and the second analog test bus, respectively. Based on the output of the differential ADC, it is determined whether the first DAC, the second DAC, or the differential ADC is faulty.

23. A method comprising: When the integrated circuit is in non-test mode Connect the input or output of the first analog circuit to a first analog test bus coupled to a first functional analog pin or a first functional analog pad, such that the input or output of the first analog circuit can be accessed by the first functional analog pin or the first functional analog pad. Keep the input or output of the second analog circuit disconnected from the first analog test bus; as well as When the integrated circuit is in test mode, the input or output of the first analog circuit and the input or output of the second analog circuit are selectively connected to the first analog test bus to test the first analog circuit and the second analog circuit using the first analog test bus.

Images