A clock data alignment method and device applied to pseudo-random binary sequence

Abstract

This invention provides a clock data alignment method and apparatus for pseudo-random binary sequences. A crystal oscillator generates a clock signal; a phase interpolator, based on a phase shift control signal output by a phase shift controller, shifts the phase of the received clock signal to obtain an offset clock signal; a PRBS checker receives PRBS data and the offset clock signal and performs phase alignment check on both, generating a flag signal indicating whether the phases of the PRBS data and the offset clock signal are aligned based on the check result; the phase shift controller adjusts or records the current phase offset value based on the received flag signal, and outputs a phase shift control signal to the phase interpolator based on the phase offset value to readjust the phase of the clock signal until the phase of the obtained offset clock signal is aligned with the data phase, thereby improving the alignment accuracy and efficiency of the clock data and avoiding the problem of uncontrollable delay in traditional methods.

Description

Technical Field

[0001] This invention relates to the field of digital communication technology, and more specifically, to a clock data alignment method and apparatus for pseudo-random binary sequences (PRBS). Background Technology

[0002] A pseudo-random binary sequence data stream refers to a pseudo-random sequence containing only 0s and 1s. It possesses not only the statistical properties of random sequences and the good autocorrelation properties of Gaussian noise, but also a certain defined encoding rule, allowing for repeated generation and processing. It is widely used in the field of communication, for example, in the simulation and testing of high-speed digital communication links to simulate real data streams. The PRBS generator generates a PRBS data stream, which is then transmitted through a self-checking path (LB PATH) including transmission paths such as CDR and Driver to a PRBS checker for comparison and verification. If the verification passes, simulation or testing can be performed based on the PRBS data stream. The PRBS checker is the reverse process of generating the PRBS data stream; it registers the received PRBS data stream for one clock cycle (parallel data), encodes the registered PRBS data stream using PRBS, and compares the encoded PRBS data stream with the latest received clock signal. If they match, the PRBS data stream verification is successful.

[0003] Because the LB path for transmitting the PRBS data stream is relatively long, the delay of the PRBS data stream may exceed one clock signal cycle, causing the clock signal and the PRBS data stream to be ineffectively aligned, thus failing to meet the set / hold time of the D flip-flops in the PRBS CHK. Currently, to align the clock signal and the PRBS data stream, a corresponding delay (BUF) is added to the clock signal output by the clock (CLK) generator to delay the clock signal and achieve alignment. However, this method uses a fixed delay value, and the transmission delay time of the clock generator is uncontrollable due to the influence of transmission line length, chip temperature, and manufacturing process, resulting in low alignment accuracy between the clock signal and the PRBS data stream and making clock-data alignment difficult. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a clock data alignment method and apparatus for pseudo-random binary sequences, so as to improve the alignment accuracy of clock signals and PRBS data streams.

[0005] In a first aspect, embodiments of the present invention provide a clock data alignment device for pseudo-random binary sequences, comprising: a crystal oscillator, a phase interpolator, a phase shift controller, and a pseudo-random binary sequence (PRBS) verifier, wherein...

[0006] Crystal oscillator, used to generate 2 with the same preset phase difference m The clock signal is output to the phase interpolator, where m is an integer greater than or equal to 1, and the preset phase difference between adjacent clock signals is 360° / 2. m ;

[0007] The phase interpolator is used to receive the clock signal and perform phase offset according to the phase shift control signal output by the phase shift controller to obtain the offset clock signal, which is then output to the PRBS checker.

[0008] The PRBS checker is used to receive PRBS data and offset clock signal and perform phase alignment check on the two. Based on the check result, it generates a flag bit signal that indicates whether the phases of the PRBS data and the offset clock signal are aligned and outputs it to the phase shift controller.

[0009] The phase shift controller receives the flag signal output by the PRBS verifier, adjusts or records the current phase offset value according to the flag signal, and outputs a phase shift control signal to the phase interpolator according to the phase offset value.

[0010] Adjusting the phase offset value increases or decreases the current phase offset value by a preset phase offset step size.

[0011] In conjunction with the first aspect, embodiments of the present invention provide a first possible implementation of the first aspect, wherein the phase shift controller includes: a receiving unit, a first control unit, a phase shift processing unit, a second control unit, and a recording unit.

[0012] The receiving unit is used to receive the flag bit signal;

[0013] The first control unit is used to output a first control signal to the phase shift processing unit or a second control signal to the recording unit based on the flag bit signal.

[0014] A phase shift processing unit is used to receive a first control signal and, after receiving the first control signal, increase or decrease the current phase offset value by a preset phase offset step size.

[0015] The second control unit is used to output a reset signal to the PRBS verifier and to output a phase shift control signal to the phase interpolator based on the phase offset value.

[0016] The recording unit is used to receive the second control signal and record the current phase offset value when the second control signal is received.

[0017] In conjunction with the first possible implementation of the first aspect, this embodiment of the invention provides a second possible implementation of the first aspect, wherein the phase shift processing unit includes an n-bit register for indicating the current phase offset value and performing calculations on the current phase offset value, where n > m.

[0018] The fixed m-bit register is used to indicate the clock signal information that requires phase interpolation.

[0019] The remaining nm bits of the register are used to indicate specific phase offset values.

[0020] The phase shift step size is 360° / 2 n .

[0021] In conjunction with the second possible implementation of the first aspect, this embodiment of the invention provides a third possible implementation of the first aspect, wherein the number of register bits n ≥ m + 5.

[0022] In conjunction with the first aspect, embodiments of the present invention provide a fourth possible implementation of the first aspect, wherein the apparatus further includes:

[0023] The divider receives the offset clock signal output by the phase interpolator, adjusts the frequency of the offset clock signal according to the sampling clock frequency set by the PRBS checker, and outputs it to the PRBS checker.

[0024] In conjunction with the first aspect, the present invention provides a fifth possible implementation of the first aspect, wherein the clock signal includes: 4 clock signals with a preset phase difference of 90° or 8 clock signals with a preset phase difference of 45°, i.e., m = 2 or 3.

[0025] In conjunction with the first aspect, embodiments of the present invention provide a sixth possible implementation of the first aspect, wherein the phase interpolator includes,

[0026] 2 m Two identical first amplifying tubes and 2 m Two identical first load resistors, 2 m Two identical second amplifying tubes and 2 m Two identical second load resistors: the emitter of each first amplifier tube is connected to a first preset voltage, and the collector is connected to a first load resistor, forming two... m Each stage has a first branch; the emitter of each second amplifier tube is connected to a second preset voltage, and the collector is connected to a second load resistor, forming a 2 m One first-level second branch; each first-level first branch and one first-level second branch are connected in parallel to form 2 mA second-stage branch, wherein the bases of the first amplifier tube and the second amplifier tube are respectively connected to two offset clock signals with a phase difference of 180°;

[0027] 2 m Two identical switching transistors are connected to the second-stage branch to control the on / off state of the second-stage branch; every two second-stage branches are connected in parallel to form a 2 m-1 A third-stage branch contains two first-stage amplifier transistors connected to two clock signals with a 180° phase difference, and two second-stage amplifier transistors connected to two offset clock signals with a 180° phase difference. 2 m-1 The third-level branch connects sequentially with 2 m-1 Two offset clock signals with a phase difference of 180° are connected;

[0028] One current source is used to generate a constant total current I0 to provide adjustable branch current to the third-level branch;

[0029] The phase shift controller outputs a phase shift control signal based on the phase shift value to control the on / off state of the switching transistors and to control the distribution of the constant total current I0 before entering phase 2. m-1 The third-level branch road.

[0030] In conjunction with the sixth possible implementation of the first aspect, the present invention provides a seventh possible implementation of the first aspect, wherein the first amplifying tube is the same as the second amplifying tube, and the first load resistor is the same as the second load resistor.

[0031] Secondly, embodiments of the present invention provide a clock data alignment method for pseudo-random binary sequences (PRBS). Using the aforementioned clock data alignment apparatus, the alignment method includes:

[0032] S1: Crystal oscillators generate crystals with the same preset phase difference of 360° / 2. m 2 m The clock signal is output to the phase interpolator;

[0033] S2: The controller outputs a phase shift control signal to the phase interpolator according to the preset first phase offset value;

[0034] S3: The phase interpolator shifts the phase of the clock signal according to the phase shift control signal to obtain the offset clock signal and outputs it to the PRBS checker.

[0035] S4: The PRBS checker receives PRBS data and offset clock signal and performs phase alignment check on the two. Based on the check result, it generates a flag bit signal and outputs it to the phase shift controller: when the PRBS data and offset clock signal are not phase aligned, it outputs a flag bit signal indicating an error; when the PRBS data and offset clock signal are phase aligned, it outputs a flag bit signal indicating a correct operation.

[0036] S5: When the phase shift controller receives the flag signal indicating an error, it controls the PRBS checker to reset, and at the same time increases the current phase offset value by a preset phase offset step size. Based on the adjusted phase offset value, it outputs a phase control signal to the phase interpolator. The phase interpolator performs phase offset on the clock signal according to the control signal and outputs the obtained offset clock signal to the PRBS checker for alignment verification.

[0037] S6: Repeat the process from S3 to S5 until the phase shift controller receives the flag signal indicating the correctness, then record the current phase offset value, which is the first optimal phase offset value.

[0038] In conjunction with the second aspect, embodiments of the present invention provide a first possible implementation of the second aspect, wherein the method further includes:

[0039] S7: After obtaining the first optimal phase offset value, the controller resets the current phase offset value to the preset second phase offset value, and outputs a phase shift control signal to the phase interpolator according to the preset second phase offset value;

[0040] S8: The controller outputs a phase shift control signal to the phase interpolator according to the preset second phase offset value;

[0041] S9: The phase interpolator shifts the phase of the clock signal according to the phase shift control signal to obtain the offset clock signal and outputs it to the PRBS checker.

[0042] S10: The PRBS checker receives PRBS data and offset clock signal and performs phase alignment check on the two. Based on the check result, it generates a flag bit signal and outputs it to the phase shift controller: when the PRBS data and offset clock signal are not phase aligned, it outputs a flag bit signal indicating an error; when the PRBS data and offset clock signal are phase aligned, it outputs a flag bit signal indicating a correct operation.

[0043] S11: When the phase shift controller receives the flag signal indicating an error, it controls the PRBS checker to reset, reduces the current phase offset value by the preset phase offset step size, and outputs a phase control signal to the phase interpolator according to the adjusted phase offset value. The phase interpolator performs phase offset on the clock signal according to the control signal and outputs the obtained offset clock signal to the PRBS checker for alignment verification.

[0044] S12: Repeat the process from S9 to S11 until the phase shift controller receives the flag signal indicating the correctness, then record the current phase offset value, which is the second optimal phase offset value.

[0045] S13: The controller calculates the average of the first optimal phase offset value and the second optimal phase offset value to obtain the target phase offset value;

[0046] S14: The controller outputs a phase shift control signal to the phase interpolator based on the target phase offset value;

[0047] S15: The phase interpolator shifts the phase of the clock signal according to the phase shift control signal to obtain a target offset clock signal that is aligned with the PRBS data.

[0048] Thirdly, embodiments of the present invention provide a computer device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the above-described clock data alignment method applied to pseudo-random binary sequences are performed.

[0049] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps described above for identifying a clock data alignment method applied to a pseudo-random binary sequence.

[0050] The clock data alignment method and apparatus for pseudo-random binary sequences provided in this invention include: a crystal oscillator, a phase interpolator, a phase shift controller, and a pseudo-random binary sequence (PRBS) checker. The crystal oscillator is used to generate a 2-bit clock data alignment method with a preset phase difference. m The clock signal is output to the phase interpolator, where m is an integer greater than or equal to 1, and the preset phase difference between adjacent clock signals is 360° / 2. mThe phase interpolator receives the clock signal and performs phase offset based on the phase shift control signal output by the phase shift controller to obtain an offset clock signal, which is then output to the PRBS checker. The PRBS checker receives the PRBS data and the offset clock signal and performs phase alignment verification between them. Based on the verification result, it generates a flag signal indicating whether the PRBS data and the offset clock signal are phase aligned and outputs it to the phase shift controller. The phase shift controller receives the flag signal output by the PRBS checker, adjusts or records the current phase offset value based on the flag signal, and outputs a phase shift control signal to the phase interpolator based on the phase offset value. Adjusting the phase offset value involves increasing or decreasing the current phase offset value by a preset phase offset step size. In this way, by adjusting the current phase offset value based on the flag signal output by the PRBS checker until a correctly received flag signal is received, the alignment verification of the PRBS data stream can be performed, effectively improving the alignment accuracy of the clock signal and the PRBS data stream.

[0051] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0052] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This diagram illustrates the structure of a clock data alignment device for pseudo-random binary sequences provided in an embodiment of the present invention.

[0054] Figure 2a A schematic diagram of the phase shift controller structure provided in an embodiment of the present invention is shown;

[0055] Figure 2b A schematic diagram of the phase relationship of the clock signal provided in an embodiment of the present invention is shown;

[0056] Figure 3 A schematic diagram of a specific structure of the phase interpolator provided in an embodiment of the present invention is shown;

[0057] Figure 4 This invention provides a schematic flowchart of a clock data alignment method for pseudo-random binary sequences.

[0058] Figure 5 This is a schematic diagram of the structure of a computer device 500 provided in an embodiment of this application. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0060] This invention provides a clock data alignment method and apparatus for pseudo-random binary sequences, which are described below through embodiments.

[0061] In this embodiment of the invention, the clock signal and the PRBS data stream are aligned by setting up a PRBS verification device with a self-controlled loop.

[0062] Figure 1 A schematic diagram of a clock data alignment device for pseudo-random binary sequences provided in an embodiment of the present invention is shown. Figure 1 As shown, the device includes: a voltage-controlled oscillator (VCO) 101, a phase interpolator (PI) 102, a phase shift controller 103, and a PRBS verifier 104, wherein...

[0063] Crystal oscillator 101 is used to generate 2 crystals with the same preset phase difference. m The clock signal is output to phase interpolator 102, where m is an integer greater than or equal to 1, and the preset phase difference between adjacent clock signals is 360° / 2. m ;

[0064] In one embodiment of the invention, the crystal oscillator generates four clock signals—a first clock signal (CLK1), a second clock signal (CLK2), a third clock signal (CLK3), and a fourth clock signal (CLK4)—with a phase difference of 90°. In another embodiment, to improve subsequent alignment accuracy, the crystal oscillator can also generate eight clock signals with a phase difference of 45°, i.e., the clock signals include: four clock signals with a preset phase difference of 90° or eight clock signals with a preset phase difference of 45°, where m = 2 or 3. In yet another embodiment, the crystal oscillator can also generate other numbers of clock signals, where the phase difference between adjacent clock signals is the quotient of 360 degrees and the number of signals; this embodiment of the invention does not limit this.

[0065] The phase interpolator 102 is used to receive the clock signal and perform phase shift according to the phase shift control signal output by the phase shift controller 103 to obtain the offset clock signal and output it to the PRBS verifier 104.

[0066] PRBS checker 104 is used to receive PRBS data and offset clock signal and perform phase alignment check on the two. Based on the check result, it generates a flag bit signal that characterizes whether the phases of PRBS data and offset clock signal are aligned and outputs it to phase shift controller 103.

[0067] The phase shift controller 103 is used to receive the flag bit signal output by the PRBS verifier 104, adjust or record the current phase offset value according to the flag bit signal, and output a phase shift control signal to the phase interpolator 102 according to the phase offset value.

[0068] Adjusting the phase offset value increases or decreases the current phase offset value by a preset phase offset step size.

[0069] Figure 2a A schematic diagram of the phase shift controller structure provided in an embodiment of the present invention is shown. Figure 2a As shown, in this embodiment of the invention, as an optional embodiment, the phase shift controller 103 includes: a receiving unit 201, a first control unit 202, a phase shift processing unit 203, a second control unit 204, and a recording unit 205, wherein...

[0070] The receiving unit 201 is used to receive the flag bit signal;

[0071] The first control unit 202 is used to output a first control signal to the phase shift processing unit 203 or a second control signal to the recording unit 205 according to the flag bit signal;

[0072] The phase shift processing unit 203 is used to receive a first control signal and, after receiving the first control signal, increase or decrease the current phase shift value by a preset phase shift step size.

[0073] The second control unit 204 is used to output a reset signal to the PRBS verifier and to output a phase shift control signal to the phase interpolator based on the phase offset value.

[0074] The recording unit 205 is used to receive the second control signal and record the current phase offset value when the second control signal is received.

[0075] In this embodiment of the invention, as an optional implementation, the phase shift processing unit includes an n-bit register to indicate the current phase offset value and to perform calculations on the current phase offset value, where n > m.

[0076] The fixed m-bit register is used to indicate the clock signal information that requires phase interpolation.

[0077] The remaining nm bits of the register are used to indicate specific phase offset values.

[0078] The phase shift step size is 360° / 2 n .

[0079] In this embodiment of the invention, as another optional embodiment, the number of register bits n ≥ m + 5.

[0080] When the crystal oscillator outputs four clock signals with a phase difference of 90° (i.e., m=2), a 7-bit shift register can be used. The first two bits of the shift register indicate the clock signal information that requires phase interpolation, and the last five bits indicate the specific phase offset information, that is, further dividing 90° into 2. 5 Phase interpolation is performed, meaning the phase offset step size is 360° / 2. 7 Alternatively, an 8-bit register can be used, in which case the last 6 bits are used to indicate phase offset information, with a phase offset step size of 360° / 2. 8 The larger the number of bits in the shift register, the more bits can be used to indicate phase offset information, resulting in a smaller phase offset step and more accurate phase interpolation. However, the number of bits cannot be increased indefinitely, otherwise it will increase the operational complexity and time of phase interpolation. The optimal value is 5 ≤ ​​n ≤ 10.

[0081] In an optional embodiment of the present invention, the device further includes:

[0082] The divider 105 is used to receive the offset clock signal output by the phase interpolator 102, adjust the frequency of the offset clock signal according to the sampling clock frequency set by the PRBS checker 104, and output it to the PRBS checker 104.

[0083] In this embodiment of the invention, the divider is used for frequency adjustment, that is, to down-clock the clock signal output by the VCO. As an optional embodiment, according to the sampling clock frequency required by the PRBS checker, the clock signal is down-clocked by 1 / 2, 1 / 4, 1 / 8, etc., by the divider.

[0084] In this embodiment of the invention, the divider is a divide-by-two circuit, which includes two cascaded latches. The two cascaded latches constitute a divide-by-two frequency divider. When the clock signal is at its rising edge, the output level is flipped, and when the clock signal is at its falling edge, the output level remains unchanged, thereby achieving a divide-by-two frequency divider.

[0085] In this embodiment of the invention, as an optional embodiment, the phase shift controller uses a 7-bit register to set the maximum number of steps for the phase offset step.

[0086] In one embodiment of the present invention, as an optional embodiment, a phase interpolator (PI), a divider (DIV), a PRBS verifier, and a phase shift controller form a self-control loop to adjust the phase shift of the clock signal output by the VCO in order to verify whether the PRBS data stream generated by the PRBS generator is correct.

[0087] In this embodiment of the invention, as an optional embodiment, the PRBS data stream generated by the PRBS generator is input into the PRBS validator after passing through the self-test path.

[0088] In this embodiment of the invention, the clock signal generated by the VCO is output to the PI, and after phase interpolation is performed in the PI, it is output to the DIV, or to the PRBS checker. The DIV performs a division operation on the received data and outputs it to the PRBS checker. The PRBS checker samples the input PRBS data stream based on the offset clock signal output by the PI or the offset clock signal output by the DIV, and determines whether the PRBS data stream transmitted in the data path is correct based on the sampling result, that is, whether the offset clock signal is aligned with the PRBS data stream.

[0089] In this embodiment of the invention, the phase shift controller interacts with the PI and PRBS checkers to obtain the optimal register value. After obtaining the optimal register value, the phase shift controller no longer interacts with the PI and PRBS checkers. The PI performs phase shifting on the clock signal output by the VCO based on the phase offset value corresponding to the optimal register value and outputs it to the PRBS checker. The PRBS checker verifies the received PRBS data stream based on the offset clock signal used for phase offset calculation. The process for obtaining the optimal register value is as follows:

[0090] The PRBS checker verifies (judges) the received PRBS data stream based on the offset clock signal used for phase offset calculation, and outputs a flag signal corresponding to the judgment result. For example, if the flag signal output by the PRBS checker is "0", it indicates that the sampling is correct and that the clock signal is aligned with the PRBS data stream. If the output flag signal is "1", it indicates that the sampling is incorrect and that the clock signal is not aligned with the PRBS data stream.

[0091] The PRBS checker outputs a flag signal to the phase shift controller (digital unit). The phase shift controller receives the flag signal. In an optional embodiment, the phase shift controller starts scanning from the smallest phase offset step size. If a flag signal indicating a sampling error is received, it indicates that the clock signal is not aligned with the PRBS data stream (FLAG=1). The current phase offset step size is then increased by a preset phase offset step size, i.e., the current phase offset step size is incremented by 1 (code+1). At the same time, a reset signal is output to reset the PRBS checker until a flag signal indicating a correct sampling "0" is received. The value of the first register corresponding to the previous flag signal of this flag signal is recorded.

[0092] Then, the phase shift controller starts scanning from the maximum code number (0x00). If a flag signal indicating a sampling error is received, the current phase offset step size is reduced by the preset phase offset step size, i.e., code-1. At the same time, a reset signal is output to reset the PRBS checker until a flag signal indicating a correct sampling "0" is received. The value of the second register corresponding to the previous flag signal of the flag signal is recorded.

[0093] Calculate the average of the first register value and the second register value to obtain the optimal register value.

[0094] In this embodiment of the invention, as an optional implementation, due to clock jitter, the phase shift controller uses the following formula to calculate the optimal register value as the final output:

[0095] (code1+code2) / 2

[0096] This allows for sufficient margin in the clock signal.

[0097] In subsequent applications, after the phase interpolator obtains the optimal register value, it adjusts the phase of the clock signal based on the phase offset value corresponding to the optimal register value. This ensures correct sampling of the clock signal and achieves alignment between the PRBS data stream and the clock signal. Thus, in this embodiment of the invention, by setting up a self-control loop and considering the impact of transmission line length, chip temperature, and manufacturing process on the transmission delay time of the clock generator, an optimal register value (code) is obtained. This effectively improves the alignment accuracy between the clock signal and the PRBS data stream, thereby enhancing the reliability of the verification results of the PRBS data stream.

[0098] In this embodiment of the invention, as an optional embodiment, if the phase shift controller starts scanning from the smallest phase offset step size to the largest phase offset step size (e.g., 0x7F), and the flag signal output by the PRBS checker is always "1", it indicates that after scanning the entire clock cycle, the phase is still wrong, there is a problem with the data path, and an alarm message is output.

[0099] In this embodiment of the invention, the optimal register value is automatically obtained by using interpolation to achieve phase offset and thus align the clock signal with the PRBS data stream.

[0100] In this embodiment of the invention, as an optional embodiment, the reset signal is a 20ns low-level signal (PRBS checker low-level reset) to clear the flag bit signal of the PRBS checker, so that the PRBS checker can run again.

[0101] In this embodiment of the invention, taking the generation of four clock signals by the VCO: a first clock signal (CLK1), a second clock signal (CLK2), a third clock signal (CLK3), and a fourth clock signal (CLK4) as an example, the alignment of the PRBS data stream with the clock signals is explained.

[0102] Figure 2b A schematic diagram illustrating the phase relationship of the clock signal provided in an embodiment of the present invention is shown. For example... Figure 2b As shown in the embodiment of the present invention, the phase relationship of the four clock signals is as follows:

[0103] CLK1: 0°

[0104] CLK2: 180°

[0105] CLK3: 90°

[0106] CLK4: 270°

[0107] set up:

[0108] CLK 12 =CLK1-CLK2

[0109] CLK 34 =CLK3-CLK4

[0110] Then, CLK 12 With CLK 34 The phase difference is 90°.

[0111] In this embodiment of the invention, the PRBS data stream is aligned with the clock signal by adjusting the phase of the clock signal. At the same time, the frequency of the clock signal can be adjusted according to the clock frequency required by the PRBS Checker.

[0112] In one embodiment of the present invention, as an optional embodiment, the phase interpolator adjusts the phase of the clock signal by using a phase interpolation method based on the received phase offset value.

[0113] In this embodiment of the invention, as an optional embodiment, the phase interpolator includes,

[0114] 2 m Two identical first amplifying tubes and 2 m Two identical first load resistors, 2 m Two identical second amplifying tubes and 2 m Two identical second load resistors: the emitter of each first amplifier tube is connected to a first preset voltage, and the collector is connected to a first load resistor, forming two... m Each stage has a first branch; the emitter of each second amplifier tube is connected to a second preset voltage, and the collector is connected to a second load resistor, forming a 2 m One first-level second branch; each first-level first branch and one first-level second branch are connected in parallel to form 2 m A second-stage branch, wherein the bases of the first amplifier tube and the second amplifier tube are respectively connected to two offset clock signals with a phase difference of 180°;

[0115] 2 m Two identical switching transistors are connected to the second-stage branch to control the on / off state of the second-stage branch; every two second-stage branches are connected in parallel to form a 2 m-1 A third-stage branch contains two first-stage amplifier transistors connected to two clock signals with a 180° phase difference, and two second-stage amplifier transistors connected to two offset clock signals with a 180° phase difference. 2 m-1 The third-level branch connects sequentially with 2 m-1 Two offset clock signals with a phase difference of 180° are connected;

[0116] One current source is used to generate a constant total current I0 to provide adjustable branch current to the third-level branch;

[0117] The phase shift controller outputs a phase shift control signal based on the phase shift value to control the on / off state of the switching transistors and to control the distribution of the constant total current I0 before entering phase 2. m-1 The third-level branch road.

[0118] In conjunction with the sixth possible implementation of the first aspect, the present invention provides a seventh possible implementation of the first aspect, wherein the first amplifying tube is the same as the second amplifying tube, and the first load resistor is the same as the second load resistor.

[0119] Figure 3 A schematic diagram of a specific structure of the phase interpolator provided in an embodiment of the present invention is shown. Figure 3 As shown, the phase interpolator includes: a first resistor 301, a second resistor 302, a first switch 303, a second switch 304, a third switch 305, a fourth switch 306, a fifth switch 307, a sixth switch 308, a seventh switch 309, an eighth switch 310, a ninth switch 311, a tenth switch 312, an eleventh switch 313, a twelfth switch 314, a first bias resistor 315, a second bias resistor 316, a third bias resistor 317, a fourth bias resistor 318, a fifth bias resistor 319, a sixth bias resistor 320, a seventh bias resistor 321, an eighth bias resistor 322, a first current controller 323, a second current controller 324, and a total current controller 325, wherein...

[0120] One end of the first resistor 301 and the second resistor 302 are connected to a preset voltage (VCC), the other end of the first resistor 301 is connected to the positive output node (OutN) of the offset clock signal, and the other end of the second resistor 302 is connected to the negative output node (OutP) of the offset clock signal.

[0121] The collectors of the first switch transistor 303, the fourth switch transistor 306, the fifth switch transistor 307, and the seventh switch transistor 309 are respectively connected to the other end of the first resistor 301;

[0122] The collectors of the second switch 304, the third switch 305, the sixth switch 308, and the eighth switch 310 are respectively connected to the other end of the second resistor 302;

[0123] The bases of the first switch 303 and the third switch 305 are connected to the first clock signal CLK1, the bases of the second switch 304 and the fourth switch 306 are connected to the second clock signal CLK2, the bases of the fifth switch 307 and the eighth switch 310 are connected to the third clock signal CLK3, and the bases of the sixth switch 308 and the seventh switch 309 are connected to the fourth clock signal CLK4.

[0124] The emitter of the first switching transistor 303 is connected to one end of the first bias resistor, the emitter of the second switching transistor 304 is connected to one end of the second bias resistor, the other end of the first bias resistor is connected to the other end of the second bias resistor, and is connected to the collector of the ninth switching transistor 311.

[0125] The emitter of the third switch 305 is connected to one end of the third bias resistor, the emitter of the fourth switch 306 is connected to one end of the fourth bias resistor, the other end of the third bias resistor is connected to the other end of the fourth bias resistor, and is connected to the collector of the tenth switch 312.

[0126] The emitter of the fifth switch transistor 307 is connected to one end of the fifth bias resistor, the emitter of the sixth switch transistor 308 is connected to one end of the sixth bias resistor, the other end of the fifth bias resistor is connected to the other end of the sixth bias resistor, and is connected to the collector of the eleventh switch transistor 313.

[0127] The emitter of the seventh switch 309 is connected to one end of the seventh bias resistor, the emitter of the eighth switch 310 is connected to one end of the eighth bias resistor, the other end of the seventh bias resistor is connected to the other end of the eighth bias resistor, and is connected to the collector of the twelfth switch 314.

[0128] The emitter of the ninth switch 311 is connected to the emitter of the tenth switch 312, and is also connected to one end of the first current controller 323.

[0129] The emitter of the eleventh switch 313 is connected to the emitter of the twelfth switch 314 and is connected to one end of the second current controller 324. The other end of the first current controller 323 and the other end of the second current controller 324 are connected to one end of the total current controller 325, and the other end of the total current controller 325 is grounded.

[0130] The bases of the ninth switch transistor 311, the tenth switch transistor 312, the eleventh switch transistor 313, and the twelfth switch transistor 314 are connected to the output of the phase shift controller.

[0131] In this embodiment of the invention, as an optional embodiment, the first to twelfth switching transistors are all metal-oxide-semiconductor (MOS) transistors. The resistance values ​​of the first to eighth bias resistors are equal. The phase interpolator performs corresponding conversion based on the phase offset value output by the phase shift controller to obtain a control signal. Based on the control signal, the bases of the ninth, tenth, eleventh, and twelfth switching transistors 311, 312, 313, and 314 are controlled, thereby controlling the on / off state of one or more of the ninth, tenth, eleventh, and twelfth switching transistors 311, 312, 313, and 314.

[0132] In an embodiment of the present invention,

[0133] CLK 12 = CLK1 - CLK2 = sin(wt + π / 2)

[0134] CLK 34 = CLK3 - CLK4 = sin(wt)[[ID=十二]]

[0135] In an embodiment of the present invention, CLK 12 and CLK 34 have a phase difference of 90°, so the phase shift range of the clock signal is 90°.

[0136] The output of PI is:

[0137]

[0138] where α = cosθ, β = sinθ, which are weight coefficients related to the first current controller 323 and the second current controller 324, and α 2 + β 2 = 1.

[0139] In actual circuit design, α + β ≈ 1.

[0140] The above formula can be written as:

[0141] CLK out = αCLK 12 + (1 - α)CLK 34

[0142] In an embodiment of the present invention, as an optional embodiment, the period of the clock signal is divided into 2 m quadrants for phase offset interpolation. Suppose the register is n bit (m < n), then the high m bits perform phase interpolation, and the low n - m bits divide one quadrant into 2 n-m parts, each corresponding to a phase offset step. For example, the clock period (the period of the clock signal) is divided into four quadrants (m = 2), each quadrant corresponding to 90 degrees. The 7 - bit register <6:0> controls the current ratio of the first current controller 323 and the second current controller 324, thereby controlling the phase shift (phase offset). Then, in the 7 - bit register, the high two bits <6:5> control the conduction and turn - off of the ninth triode Q9, the thirteenth triode Q 10 、the eleventh triode Q 11 、the twelfth triode Q 12 to determine the quadrant (0° - 90°, 90° - 180°, 180° - 270°, 270° - 0°) where the phase shift of the clock signal is located, and the low five bits <4:0> divide each 90° quadrant into 2 5The intervals are divided into equal parts, meaning the phase shift step size is 2. 5 The phase interpolator controls the phase of the clock signal based on the phase offset value corresponding to the optimal register value output by the phase shift controller, and the phase of the received clock signal. 5 Phase shifting is performed within a certain interval. For example, based on the aforementioned sequential increase of a phase offset step, the phase of the received clock signal is 2.8125°. Then, according to the high two bits <6:5> in the 7-bit register, the quadrant in which the phase shift of the clock signal is controlled is (0°~90°). (0°~90°) is then divided into 2... 5 Each interval is phase-shifted, and the control clock signal is phase-shifted to the next interval for each phase shift.

[0143] In this embodiment of the invention, the input current controller 325 receives a constant total current I0. This total current is divided into a first current I1 and a second current I2. The lower five bits of a 7-bit register are used to control the magnitudes of the first and second currents. Since the first current I1 and the second current I2 divide the current path into six branches, the register value (phase offset value) controls the opening and closing of different branches, thereby controlling the magnitudes of the branch currents I1 and I2. This adjusts the proportion of I1 and I2 in I0, ensuring that the output offset clock signal is close to CLK. 12 or CLK 34 .

[0144] In this embodiment of the invention, as another optional embodiment, the number of clock signals output by the VCO can also be set to 8, with a phase difference of 45° between each CLK signal, corresponding to 8 quadrants, thereby further enhancing its controllability and improving phase shift accuracy.

[0145] In this embodiment of the invention, a self-control loop is set up to control the register value, thereby adjusting the current ratio and achieving the purpose of controlling the phase shift of the clock signal. The size of the register bit width affects the accuracy of the phase shift; a larger bit width results in more segments per quadrant, enabling more precise phase shifting of the clock signal and a wider phase shift range. This solves the problem of uncontrollable delay caused by setting a fixed delay, making the alignment of the clock signal with the PRBS data stream easier, more accurate, and with higher alignment precision. Furthermore, the frequency of the output clock signal can be changed according to the sampling clock requirements of the PRBS Checker, making it widely applicable.

[0146] Figure 4 A schematic flowchart of a clock data alignment method for pseudo-random binary sequences provided by an embodiment of the present invention is shown. Figure 4 As shown, the method includes:

[0147] S1: Crystal oscillators generate crystals with the same preset phase difference of 360° / 2.m 2 m The clock signal is output to the phase interpolator;

[0148] S2: The controller outputs a phase shift control signal to the phase interpolator according to the preset first phase offset value;

[0149] S3: The phase interpolator shifts the phase of the clock signal according to the phase shift control signal to obtain the offset clock signal and outputs it to the PRBS checker.

[0150] S4: The PRBS checker receives PRBS data and offset clock signal and performs phase alignment check on the two. Based on the check result, it generates a flag bit signal and outputs it to the phase shift controller: when the PRBS data and offset clock signal are not phase aligned, it outputs a flag bit signal indicating an error; when the PRBS data and offset clock signal are phase aligned, it outputs a flag bit signal indicating a correct operation.

[0151] S5: When the phase shift controller receives the flag signal indicating an error, it controls the PRBS checker to reset, and at the same time increases the current phase offset value by a preset phase offset step size. Based on the adjusted phase offset value, it outputs a phase control signal to the phase interpolator. The phase interpolator performs phase offset on the clock signal according to the control signal and outputs the obtained offset clock signal to the PRBS checker for alignment verification.

[0152] S6: Repeat the process from S3 to S5 until the phase shift controller receives the flag signal indicating the correctness, then record the current phase offset value, which is the first optimal phase offset value.

[0153] In an optional embodiment of this invention, the method further includes:

[0154] S7: After obtaining the first optimal phase offset value, the controller resets the current phase offset value to the preset second phase offset value, and outputs a phase shift control signal to the phase interpolator according to the preset second phase offset value;

[0155] S8: The controller outputs a phase shift control signal to the phase interpolator according to the preset second phase offset value;

[0156] S9: The phase interpolator shifts the phase of the clock signal according to the phase shift control signal to obtain the offset clock signal and outputs it to the PRBS checker.

[0157] S10: The PRBS checker receives PRBS data and offset clock signal and performs phase alignment check on the two. Based on the check result, it generates a flag bit signal and outputs it to the phase shift controller: when the PRBS data and offset clock signal are not phase aligned, it outputs a flag bit signal indicating an error; when the PRBS data and offset clock signal are phase aligned, it outputs a flag bit signal indicating a correct operation.

[0158] S11: When the phase shift controller receives the flag signal indicating an error, it controls the PRBS checker to reset, reduces the current phase offset value by the preset phase offset step size, and outputs a phase control signal to the phase interpolator according to the adjusted phase offset value. The phase interpolator performs phase offset on the clock signal according to the control signal and outputs the obtained offset clock signal to the PRBS checker for alignment verification.

[0159] S12: Repeat the process from S9 to S11 until the phase shift controller receives the flag signal indicating the correctness, then record the current phase offset value, which is the second optimal phase offset value.

[0160] S13: The controller calculates the average of the first optimal phase offset value and the second optimal phase offset value to obtain the target phase offset value;

[0161] S14: The controller outputs a phase shift control signal to the phase interpolator based on the target phase offset value;

[0162] S15: The phase interpolator shifts the phase of the clock signal according to the phase shift control signal to obtain a target offset clock signal that is aligned with the PRBS data.

[0163] like Figure 5 As shown, one embodiment of this application provides a computer device 500 for performing... Figure 4 The device includes a clock data alignment method for pseudo-random binary sequences, comprising a memory 501, a processor 502 connected to the memory 501 via a bus, and a computer program stored in the memory 501 and executable on the processor 502, wherein the processor 502 executes the computer program to implement the steps of the clock data alignment method for pseudo-random binary sequences.

[0164] Specifically, the memory 501 and processor 502 can be general-purpose memory and processor, without any specific limitations. When the processor 502 runs the computer program stored in the memory 501, it can execute the clock data alignment method applied to pseudo-random binary sequences.

[0165] Corresponding to Figure 4In addition to the clock data alignment method applied to pseudo-random binary sequences, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the aforementioned clock data alignment method applied to pseudo-random binary sequences.

[0166] Specifically, the storage medium can be a general-purpose storage medium, such as a removable disk or hard disk. When the computer program on the storage medium is run, it can execute the clock data alignment method applied to the pseudo-random binary sequence described above.

[0167] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interface; the indirect coupling or communication connection of the system or units may be electrical, mechanical, or other forms.

[0168] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0169] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0170] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0171] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0172] Finally, it should be noted that the above embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A clock data alignment device for pseudo-random binary sequence (PRBS), characterized in that, include: Crystal oscillator, phase interpolator, phase shift controller, and PRBS checker, among which, The crystal oscillator is used to generate 2 with the same preset phase difference. m A clock signal is output to the phase interpolator, where m is an integer greater than or equal to 1, and the preset phase difference between adjacent clock signals is 360° / 2. m ; The phase interpolator is used to receive the clock signal and perform phase shifting according to the phase shift control signal output by the phase shift controller to obtain an offset clock signal, which is then output to the PRBS checker. The PRBS checker is used to receive PRBS data and the offset clock signal and perform phase alignment check on the two. Based on the check result, it generates a flag bit signal that characterizes whether the phases of the PRBS data and the offset clock signal are aligned, and outputs it to the phase shift controller. The phase shift controller is used to receive the flag bit signal output by the PRBS verifier, adjust or record the current phase offset value according to the flag bit signal, and output a phase shift control signal to the phase interpolator according to the phase offset value. The adjustment of the phase offset value is to increase or decrease the current phase offset value by a preset phase offset step size; The phase shift controller includes a receiving unit, a first control unit, a phase shift processing unit, a second control unit, and a recording unit. The receiving unit is used to receive the flag bit signal; The first control unit is configured to output a first control signal to the phase shift processing unit or a second control signal to the recording unit based on the flag bit signal; The phase shift processing unit is used to receive the first control signal and, after receiving the first control signal, increase or decrease the current phase shift value by a preset phase shift step size. The second control unit is used to output a reset signal to the PRBS verifier and to output a phase shift control signal to the phase interpolator based on the phase offset value; The recording unit is configured to receive the second control signal and record the current phase offset value when the second control signal is received. The phase shift processing unit includes an n-bit register to indicate the current phase offset value and to perform calculations on the current phase offset value, where n > m. A fixed m-bit register is used to indicate the clock signal information requiring phase interpolation, and the remaining nm-bit registers are used to indicate the specific phase offset value. The phase offset step size is 360° / 2. n .

2. The clock data alignment device for pseudo-random binary sequence (PRBS) according to claim 1, characterized in that, The number of register bits n ≥ m + 5.

3. A clock data alignment device for pseudo-random binary sequence (PRBS) according to claim 1, characterized in that, The device further includes: The divider receives the offset clock signal output by the phase interpolator, adjusts the frequency of the offset clock signal according to the sampling clock frequency set by the PRBS checker, and outputs it to the PRBS checker.

4. A clock data alignment device for pseudo-random binary sequence (PRBS) according to claim 1, characterized in that, The clock signals include: 4 clock signals with a preset phase difference of 90° or 8 clock signals with a preset phase difference of 45°, i.e., m=2 or 3.

5. A clock data alignment device for a pseudo-random binary sequence (PRBS) according to claim 1, characterized in that, The phase interpolator includes, 2 m Two identical first amplifying tubes and 2 m Two identical first load resistors, 2 m Two identical second amplifying tubes and 2 m Two identical second load resistors: the emitter of each of the first amplifier tubes is connected to a first preset voltage, and the collector is connected to one of the first load resistors, forming two... m Each of the first-stage first branches; the emitter of each of the second amplifier tubes is connected to a second preset voltage, and the collector is connected to a second load resistor, forming 2 m One first-level second branch; each first-level first branch and one first-level second branch are connected in parallel to form 2 m A second-stage branch, wherein the bases of the first amplifier tube and the second amplifier tube are respectively connected to two offset clock signals with a phase difference of 180°; 2 m Two identical switching transistors are connected to the second-stage branch to control the on / off state of the second-stage branch; every two second-stage branches are connected in parallel to form a 2 m-1 A third-level branch, wherein the two first-level amplifier transistors in the third-level branch are respectively connected to the two clock signals with a phase difference of 180°, and the two second-level amplifier transistors in the third-level branch are respectively connected to the two offset clock signals with a phase difference of 180°; the 2 m-1 The third-level branch connects sequentially with 2 m-1 The two offset clock signals with a phase difference of 180° are connected together; A current source is provided to generate a constant total current I0 to provide an adjustable branch current to the third-level branch. The phase shift controller outputs a phase shift control signal based on the phase shift value to control the on / off state of the switching transistor and to control the distribution of the constant total current I0 into the second phase. m-1 The third-level branch road.

6. A clock data alignment device for a pseudo-random binary sequence (PRBS) according to claim 5, characterized in that, The first amplifying transistor is the same as the second amplifying transistor, and the first load resistor is the same as the second load resistor.

7. A clock data alignment method applied to pseudo-random binary sequences (PRBS), characterized in that, The clock data alignment apparatus according to claim 1, wherein the alignment method comprises: S1: The crystal oscillator generates crystals with the same preset phase difference of 360° / 2. m 2 m The clock signal is output to the phase interpolator, where m is an integer greater than or equal to 1; S2: The controller outputs a phase shift control signal to the phase interpolator according to a preset first phase offset value. The phase shift control signal is generated based on the n-bit register of the phase shift processing unit, where n>m. The fixed m-bit register is used to indicate the clock signal information that needs to be phase interpolated, and the remaining nm-bit register is used to indicate the specific phase offset value information. S3: The phase interpolator performs a phase shift on the clock signal according to the phase shift control signal to obtain an offset clock signal and outputs it to the PRBS checker. S4: The PRBS checker receives the PRBS data and the offset clock signal and performs phase alignment check on the two. Based on the check result, it generates a flag bit signal and outputs it to the phase shift controller: when the PRBS data and the offset clock signal are not phase aligned, it outputs a flag bit signal indicating an error; when the PRBS data and the offset clock signal are phase aligned, it outputs a flag bit signal indicating a correct result. S5: The receiving unit of the phase shift controller receives the flag bit signal; the first control unit outputs a first control signal to the phase shift processing unit according to the flag bit signal indicating an error; the second control unit outputs a reset signal to the PRBS checker; the phase shift processing unit increases or decreases the current phase offset value by a preset phase offset step size according to the first control signal; and the second control unit outputs a phase shift control signal to the phase interpolator according to the adjusted phase offset value; the phase interpolator performs phase offset on the clock signal according to the control signal and outputs the obtained offset clock signal to the PRBS checker for alignment verification, wherein the phase offset step size is 360° / 2n; S6: Repeat S3~S5 until the receiving unit of the phase shift controller receives the flag signal indicating correctness. The first control unit outputs a second control signal to the recording unit, and the recording unit records the current phase offset value, which is the first optimal phase offset value.

8. A clock data alignment method for pseudo-random binary sequences (PRBS) according to claim 7, characterized in that, The method further includes: S7: After obtaining the first optimal phase offset value, the controller resets the current phase offset value to a preset second phase offset value, and outputs a phase shift control signal to the phase interpolator according to the preset second phase offset value; S8: The controller outputs a phase shift control signal to the phase interpolator according to a preset second phase offset value; S9: The phase interpolator performs a phase shift on the clock signal according to the phase shift control signal to obtain an offset clock signal and outputs it to the PRBS checker. S10: The PRBS checker receives PRBS data and the offset clock signal and performs phase alignment check on the two. Based on the check result, it generates a flag bit signal and outputs it to the phase shift controller: when the PRBS data and the offset clock signal are not phase aligned, it outputs a flag bit signal indicating an error; when the PRBS data and the offset clock signal are phase aligned, it outputs a flag bit signal indicating a correct result. S11: When the phase shift controller receives the flag signal indicating the error, it controls the PRBS checker to reset, and at the same time reduces the current phase offset value by a preset phase offset step size. It also outputs a phase control signal to the phase interpolator according to the adjusted phase offset value. The phase interpolator performs phase offset on the clock signal according to the control signal and outputs the obtained offset clock signal to the PRBS checker for alignment verification. S12: Repeat S9~S11 until the phase shift controller receives the flag signal indicating correctness, and record the current phase offset value, which is the second optimal phase offset value; S13: The controller calculates the average of the first optimal phase offset value and the second optimal phase offset value to obtain the target phase offset value; S14: The controller outputs a phase shift control signal to the phase interpolator based on the target phase offset value; S15: The phase interpolator performs phase offset on the clock signal according to the phase shift control signal to obtain a target offset clock signal aligned with the PRBS data.

9. A computer device, characterized in that, include: The computer device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the computer device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of a clock data alignment method for a pseudo-random binary sequence (PRBS) as described in claim 7 or 8.

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