A video transmission system based on ARINC818 protocol

Abstract

This invention provides a video transmission system based on the ARINC818 protocol. The system includes a programmable logic controller (PLC), a video compression processor, and a PCIe module. The PLC is connected to the video compression processor at least once, and the PCIe module is also connected to the video compression processor at least once. The PLC receives signals based on the ARINC818 protocol and determines its receiving rate based on the link rate of the signals. The video compression processor receives and processes the digital video signals transmitted by the PLC and outputs them through the PCIe module. This video transmission system improves the efficiency and flexibility of video transmission based on the ARINC818 protocol.

Description

Technical Field

[0001] This invention relates to video transmission systems, and more particularly to a video transmission system based on the ARINC818 protocol. Background Technology

[0002] With the increasing amount of video image information exchanged between airborne electronic systems, traditional buses can no longer meet the current technical requirements for video transmission. For platforms such as aviation and aerospace, the ARINC818 protocol (also known as the "Avionics Digital Video Bus," ADVB) was officially proposed as a video transmission protocol by the Aeronautical Electronics Committee (AEEC) in January 2007. This protocol, based on Fibre Channel, primarily provides definition and support for video image transmission and applications in avionics systems. Besides avionics systems, the ARINC818 protocol can also be applied to systems in various fields such as infrared and optical sensors, radar, map and charting systems, image synthesis, head-up displays, multifunction display devices, and other applications (e.g., automotive systems).

[0003] However, existing video transmission systems based on the ARINC818 protocol have limited link rates and resolutions, and cannot be adjusted in real time according to different link transmission rates, nor can the system program be upgraded in real time. Traditional DSP platforms have low compression efficiency and large data volumes, while FPGA platforms are difficult to develop compression systems. These systems lack online adjustment of compression bitrate and sampling frame rate, and also lack the function of marking regions of interest in the image. Summary of the Invention

[0004] To address the aforementioned problem of low video transmission efficiency based on the ARINC818 protocol, this invention provides a video transmission system based on the ARINC818 protocol. The purpose of this invention is to improve the efficiency and flexibility of video transmission based on the ARINC818 protocol through improvements and integration of the video transmission system.

[0005] To achieve the above objectives, the present invention provides a technical solution as follows: a video transmission system based on the ARINC818 protocol, the system comprising a programmable logic unit (PLU), a video compression processor, and a PCIe module; wherein the PLU is connected to the video compression processor at least once, and the PCIe module is connected to the video compression processor at least once; the PLU receives signals based on the ARINC818 protocol and determines the receiving rate of the PLU based on the link rate of the signals based on the ARINC818 protocol; the video compression processor receives and processes the digital video signals transmitted by the PLU and outputs them through the PCIe module.

[0006] In a preferred embodiment, the programmable logic device includes at least one high-speed transceiver that determines whether the receive rate is appropriate based on the number of IDLE characters or 8B / 10B decoding errors in the ARINC818-based signal.

[0007] In a preferred embodiment, the PCIe module includes a PCIe switching module, which controls the programmable logic device to be updated according to an external program.

[0008] In a preferred embodiment, the programmable logic device includes a PCIe logic module connected to the PCIe switching module; wherein the PCIe logic module receives the external program, and the programmable logic device reads and writes the external program.

[0009] In a preferred embodiment, the video compression processor includes a PCIe interface connected to the PCIe switching module; wherein the programmable logic device outputs additional data to the PCIe switching module through the PCIe logic module, and the video compression processor outputs the processed digital video signal to the PCIe switching module through the PCIe interface.

[0010] In a preferred embodiment, the system includes a first storage module connected to the programmable logic device for storing the external program; wherein the first storage module is a Flash memory chip.

[0011] In a preferred embodiment, the system includes a photoelectric conversion module connected to the programmable logic device; the signal based on the ARINC818 protocol is an electrical signal converted by the photoelectric conversion module.

[0012] In a preferred embodiment, the video compression processor receives external instructions through the PCIe module and processes the digital video signal according to the external instructions; wherein, the external instructions include at least instructions to adjust the compression method and / or compression bitrate, instructions to acquire the video frame rate, and instructions to mark the region of interest.

[0013] In a preferred embodiment, the video compression processor includes at least a video input port and an encoding unit; wherein the video input port receives the digital video signal, and the encoding unit performs compression encoding on the digital video signal.

[0014] In a preferred embodiment, the system includes a second storage module connected to the video compression processor for storing the digital video signal and the video image compressed and encoded by the encoding unit.

[0015] Compared with the prior art, the advantages of the present invention are: (1) The system provided by the present invention can be adaptively adjusted according to the link transmission rate; (2) Data decoding based on the ARINC818 protocol is realized through a programmable logic device, and the program of the programmable logic device can be updated or upgraded in real time, so the system is highly flexible; (3) The collected video data is parsed and transmitted through a unified interface, the interface is simple, and the system is easy to cascade; (4) The compression method, compression bit rate, sampling frame rate and other parameters of the video data can be changed or adjusted in real time according to external instructions, and the region of interest can be marked, so the system is highly flexible. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of a video transmission system based on the ARINC818 protocol provided in one embodiment of the present invention;

[0018] Figure 2 Another embodiment of the present invention provides a schematic diagram of a video transmission system based on the ARINC818 protocol. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In this document, "at least one" or similar expressions mean one or more.

[0021] In this document, the terms “including,” “contains,” “comprising,” “has,” and “have” or similar expressions are open-ended and do not exclude additional unlisted elements, steps, or ingredients.

[0022] In this document, the terms “first,” “second,” or similar expressions are used to distinguish the terms used for the names of components, and the invention is not limited to the order of description herein.

[0023] This invention provides a video transmission system based on the ARINC818 protocol, the purpose of which is to improve the efficiency and flexibility of video transmission based on the ARINC818 protocol through improvements and integration of the video transmission system.

[0024] For better illustration, but not as a limitation of the present invention, the following detailed description is provided in conjunction with the accompanying drawings.

[0025] Figure 1 This is a schematic diagram of a video transmission system based on the ARINC818 protocol provided in one embodiment of the present invention.

[0026] Specifically, such as Figure 1 As shown, the video transmission system includes a programmable logic controller (PLC), a video compression processor, and a PCIe module. The PLC receives signals based on the ARINC818 protocol and determines its receiving rate according to the link rate of the ARINC818 protocol-based signals. The video compression processor receives and processes the digital video signals transmitted by the PLC and outputs them through the PCIe module.

[0027] Figure 2 This is a schematic diagram of a video transmission system based on the ARINC818 protocol provided in another embodiment of the present invention.

[0028] Specifically, such as Figure 2 As shown, the video transmission system includes a programmable logic controller (PLC), a video compression processor, and a PCIe module. The PLC receives signals based on the ARINC818 protocol and determines its receiving rate according to the link rate of the ARINC818 protocol-based signals. The video compression processor receives and processes the digital video signals transmitted by the PLC and outputs them through the PCIe module.

[0029] In an optional embodiment, the video transmission system includes a photoelectric conversion module connected to the programmable logic device (PLD). Specifically, the photoelectric conversion module receives an externally input fiber optic signal based on the ARINC818 protocol, converts the fiber optic signal into an electrical signal, and transmits it to the PLD. In one specific embodiment, the photoelectric conversion module can be a Zhonghang photoelectric conversion module of model HTA8536-MD-Q001YY.

[0030] More specifically, the programmable logic unit (PLU) is used to receive and parse signals based on the ARINC818 protocol, generate digital video signals, and transmit them to a video compression processor for compression encoding. In optional embodiments, such as... Figure 2 As shown, the programmable logic device includes a high-speed transceiver (which can be a GTX interface module, as described below) for receiving ARINC818 protocol data, a data decoding module for parsing the ARINC818 protocol, a FIFO module 1 for buffering video data, a FIFO module 2 for buffering additional data, a video timing generation module for generating video timing data, a video output module for combining video timing data and video data, a video format conversion module for converting video formats, a FIFO module 3 for buffering update / upgrade programs, and a logic upgrade module for writing update / upgrade programs. To avoid ambiguity, other unmentioned components and more detailed descriptions will be provided below.

[0031] Furthermore, such as Figure 2 As shown, in the programmable logic device (PLD), the photoelectric conversion module is connected to the high-speed transceiver; the data decoding module is connected to the high-speed transceiver, FIFO module 1, FIFO module 2, and the video timing generation module; the video timing generation module is connected to FIFO module 1, the data decoding module, and the video output module; the video output module is connected to the video timing generation module, FIFO module 1, and the video format conversion module; and the video format conversion module is connected to the video output module. To avoid ambiguity, the additional data or digital video signals mentioned herein refer to the two types of data generated by parsing the ARINC818 protocol. Video data, broadly speaking, refers to data related to video; in this document, depending on the context, it may include data before parsing the ARINC818 protocol and data after parsing the ARINC818 protocol.

[0032] In one specific embodiment, without limiting the invention, the parsing process of the programmable logic device includes: the data decoding module waits for the high-speed transceiver (which can be a GTX interface module) to complete data alignment, then reads the parallel data sent by the high-speed transceiver (this embodiment takes 32-bit parallel data as an example), and parses the ADVB container in the ARINC818 protocol. The data decoding module can decode video data and additional data; the video data is stored in FIFO module 1, and the additional data is stored in FIFO module 2 (the storage modules for video data and additional data can be determined as needed); the video timing generation module receives the resolution information from the data decoding module (for example, in this embodiment, the resolution information can be selected as 640×512, 768×576, 800×600, 1024×768, 1280×1024, and grayscale images at 8-bit pixel depth), and combines it with the video data buffer (such as...). Figure 2The FIFO module 1 (shown in the diagram) generates field synchronization (VS), line synchronization (HS), and video valid (DE) signals. The video output module reads the video data from FIFO module 1 and combines it with the timing output video generated by the video timing generation module, transmitting it to the video format conversion module to complete the video format conversion and output (in this embodiment, the video format is 16-bit BT1120). The data decoding module's parsing includes receiving SOFi, parsing the resolution information and additional data in object 0, and outputting it; continuously detecting SOFn, parsing the video data in object 2 line by line, and outputting it. When EOFt is received and one frame is parsed, the above process is repeated. In a specific embodiment, the programmable logic device can be a Xilinx XC7K160T-2FBG484I chip.

[0033] In an optional embodiment, the programmable logic device (PLD) includes at least one high-speed transceiver. This high-speed transceiver determines whether the receiving rate is appropriate based on the number of IDLE characters or 8B / 10B decoding errors in the ARINC818-based signal. Specifically, the high-speed transceiver can be a GTX interface module within the PLD. Since the ARINC818-based signal periodically transmits IDLE characters, and according to the ARINC818 protocol, a valid IDLE character will be received within a maximum timeframe of 20217 ns, the PLD can use the periodic reception of IDLE characters as one of the conditions for determining whether the current receiving rate is appropriate. Simultaneously, the GTX interface module also reports 8B / 10B decoding errors through a specific interface (e.g., a notintable interface). If the number of 8B / 10B decoding errors on the link accumulates to a certain amount, it indicates that the current receiving link rate selection is incorrect. Therefore, the PLD can also use the number of 8B / 10B decoding errors as one of the conditions for determining whether the current receiving rate is appropriate. In an optional embodiment, if the PLD determines that the current receiving rate is inappropriate, it switches to the next rate for further evaluation. For example, in this embodiment, the receiving rate of the video transmission system can be selected as 1.0625Gbps, 2.125Gbps, or 4.25Gbps.

[0034] The aforementioned GTX interface module can also be replaced by other data transmission interface modules. In one specific embodiment, taking the GTX interface module as an example, after the GTX interface module is initialized, it begins to receive serial data from the photoelectric conversion module and converts the serial data into parallel data. This parallel data can be 32-bit data or data of other bit lengths. The GTX interface module initialization includes internal CPLL initialization and receiver data path initialization (PMA and PCS). CPLL initialization must be performed before receiver initialization; receiver initialization occurs after the CPLL's lock signal is pulled high.

[0035] In an optional embodiment, the PCIe module includes a PCIe switching module, which controls the programmable logic device (PLD) to update according to an external program. Specifically, the PLD includes a PCIe logic module connected to the PCIe switching module; wherein the PCIe logic module receives the external program, and the PLD reads and writes the external program. In one specific embodiment, the PCIe switching module may be an IDT 89HPES3T3 chip. The external program described herein includes update / upgrade programs for updating, upgrading, and correcting video transmission systems.

[0036] In an optional embodiment, the video transmission system includes a first storage module connected to the programmable logic controller (PLC) for storing the external program; wherein the first storage module is a Flash memory chip. Specifically, if the video transmission system receives an upgrade logic program instruction, the PCIe logic module begins receiving the logic program and caches it in the storage / cache module (e.g., a Flash memory chip) within the PLC. Figure 2 As shown in FIFO module 3, the logic upgrade module in the programmable logic device reads the logic program and writes it to the Flash memory chip to complete the logic program upgrade. In a specific embodiment, the Flash memory chip can be a Cypress S29GL01GT11FHIV10 BPI Flash memory chip.

[0037] In an optional embodiment, the video compression processor includes a PCIe interface connected to the PCIe switching module; wherein the programmable logic unit outputs additional data within the ARINC818 protocol to the PCIe switching module through the PCIe logic module, and the video compression processor outputs processed digital video signal data within the ARINC818 protocol to the PCIe switching module through the PCIe interface. In one specific embodiment, the PCIe logic module reads the cache (e.g., ...) in the programmable logic unit. Figure 2 Additional data in the FIFO module 2 (shown) is transmitted to the PCIe interface via the PCIe switching module. The PCIe interface can be a PCIe 2.0 interface. The processed digital video signal data includes compressed and encoded video data, video data processed according to external instructions, etc.

[0038] In an optional embodiment, the video compression processor receives external instructions through the PCIe module and processes the digital video signal according to the external instructions; wherein, the external instructions include at least instructions to adjust the compression method and / or compression bitrate, instructions to adopt the video frame rate, and instructions to mark the region of interest. In one specific embodiment, the PCIe interface receives the compression bitrate, the adopted frame rate, and the coordinate information of the region of interest, and the video compression processor makes real-time adjustments.

[0039] Specifically, the video compression processor includes at least a video input port and an encoding unit; wherein the video input port receives the digital video signal, and the encoding unit compresses and encodes the digital video signal. Specifically, the video compression processor receives the digital video signal transmitted by the video format conversion module, performs video compression encoding (e.g., H.265 standard compression encoding), stores the data, and sends it to the PCIe switching module via the PCIe interface to achieve video data output. The encoding unit can compress and process the video data based on information such as the compression bitrate, sampling frame rate, and region of interest coordinates received from the PCIe interface.

[0040] In an optional embodiment, the video transmission system includes a second storage module connected to the video compression processor for storing the digital video signal and the video image compressed and encoded by the encoding unit. Specifically, the video input port module receives the digital video signal (a 16-bit BT1120 video signal in this embodiment) processed by the programmable logic device and writes it into the second storage module as a buffer for raw image data. The second storage module can be a DDR3 SDRAM memory. In one specific embodiment, the DDR3 SDRAM memory can be a Shenzhen Guowei Company model SM41J256M16M memory.

[0041] In an optional embodiment, the encoder unit reads the raw image data written by the video input port module from the second storage module and performs compression encoding (e.g., H.265 standard compression encoding); during the encoding process, the reconstructed image is written as a buffer to the second storage module as a reference image for subsequent encoding; the encoded data stream is written to the second storage module, and the video compression processor reads the encoded data and outputs it through the PCIe interface. In one specific embodiment, the video compression processor may be a HiSilicon HI3519V101 SOC chip.

[0042] The present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The above description of the implementation is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Modifications and improvements to the present invention are possible without exceeding the concept and scope defined by the appended claims. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A video transmission system based on the ARINC818 protocol, characterized in that, The system includes a programmable logic controller, a video compression processor, and a PCIe module; wherein... The programmable logic device is connected to the video compression processor at least once, and the PCIe module is connected to the video compression processor at least once. The programmable logic device receives signals based on the ARINC818 protocol, determines the receiving rate of the programmable logic device according to the link rate of the signals based on the ARINC818 protocol, and uses the number of IDLE characters and / or 8B / 10B decoding errors received periodically as a condition to determine whether the current receiving rate is appropriate. The video compression processor receives and processes the digital video signals transmitted by the programmable logic device and outputs them through the PCIe module.

2. The system according to claim 1, characterized in that, The programmable logic unit includes at least one high-speed transceiver, which determines whether the receiving rate is appropriate by the number of IDLE characters or 8B / 10B decoding errors in the signal based on the ARINC818 protocol.

3. The system according to claim 1, characterized in that, The PCIe module includes a PCIe switching module, which controls the programmable logic device to update according to an external program.

4. The system according to claim 3, characterized in that, The programmable logic device includes a PCIe logic module, which is connected to the PCIe switching module; wherein the PCIe logic module receives the external program, and the programmable logic device reads and writes the external program.

5. The system according to claim 4, characterized in that, The video compression processor includes a PCIe interface, which is connected to the PCIe switching module; wherein, the programmable logic device outputs additional data to the PCIe switching module through the PCIe logic module, and the video compression processor outputs the processed digital video signal to the PCIe switching module through the PCIe interface.

6. The system according to claim 4, characterized in that, The system includes a first storage module connected to the programmable logic device for storing the external program; wherein the first storage module is a Flash memory chip.

7. The system according to any one of claims 1-6, characterized in that, The system includes a photoelectric conversion module connected to the programmable logic device; the signal based on the ARINC818 protocol is an electrical signal converted by the photoelectric conversion module.

8. The system according to any one of claims 1-6, characterized in that, The video compression processor receives external instructions through the PCIe module and processes the digital video signal according to the external instructions; wherein, the external instructions include at least instructions to adjust the compression method and / or compression bitrate, instructions to acquire the video frame rate, and instructions to mark the region of interest.

9. The system according to claim 8, characterized in that, The video compression processor includes at least a video input port and an encoding unit; wherein the video input port receives the digital video signal, and the encoding unit performs compression encoding on the digital video signal.

10. The system according to claim 9, characterized in that, The system includes a second storage module connected to the video compression processor for storing the digital video signal and the video image compressed and encoded by the encoding unit.

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