Fault-tolerant quantum hardware using hybrid acoustic electrical qubits

Abstract

A fault-tolerant quantum computer is implemented using hybrid acoustic electrical qubits. A control circuit includes a superconducting quantum interference device (ATS) with an asymmetric screw thread that excites phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit, where the open transmission line is configured to absorb photons from a dump mode of the control circuit.

Description

Background Technology

[0001] Quantum computing uses the laws of quantum physics to process information. Quantum physics is a theory that describes the behavior of reality at a fundamental level. It is currently the only physical theory that can consistently predict the behavior of microscopic quantum objects such as photons, molecules, atoms, and electrons.

[0002] A quantum computer is a device that uses quantum mechanics to allow writing, storing, processing, and reading information encoded in quantum states (such as the state of a quantum object). A quantum object is a physical object that behaves according to the laws of quantum physics. The state of a physical object is a description of that object at a given time.

[0003] In quantum mechanics, the state of a two-level quantum system, or simply a qubit, is a list of two complex numbers, where the sum of the absolute values ​​of these numbers must be one. Each of these two numbers is called an amplitude or quasi-probability. The square of the amplitude gives the probability that it could be negative. Thus, each of these two numbers corresponds to the square root of the event zero and the event one that will occur, respectively. The fundamental and counterintuitive difference between a probabilistic bit (such as a conventional zero bit or one bit) and a qubit is that a probabilistic bit represents a lack of information about a two-level classical system, while a qubit contains the most information about a two-level quantum system.

[0004] Quantum computers are based on qubits, which can exhibit phenomena such as "superposition" and "entanglement." Superposition allows a quantum system to exist in multiple states simultaneously. For example, classical computers are based on bits that are either zero or one, while a qubit can be both zero and one at the same time, but with different probabilities assigned to each. Entanglement is a strong correlation between quantum particles, meaning that even when they are far apart, they are inextricably linked together.

[0005] A quantum algorithm is a reversible transformation of a qubit in a desired and controlled manner, followed by a measurement of one or more qubits. For example, if the system has two qubits, the transformation might modify four numbers; for three qubits, this becomes eight numbers, and so on. Therefore, a quantum algorithm operates on a list of numbers that grows exponentially, determined by the number of qubits. To implement the transformation, for example, the transformation can be broken down into small operations acting on a single qubit or a group of qubits. Such small operations can be called quantum gates, and the arrangement of the gates used to implement the transformation can form a quantum circuit.

[0006] Quantum computers can use different types of qubits, each with its own advantages and disadvantages. For example, some quantum computers may include qubits constructed from superconductors, trapped ions, semiconductors, photonics, etc. Each qubit may experience varying degrees of interference, errors, and decoherence. Furthermore, some qubits may be more useful for generating specific types of quantum circuits or quantum algorithms, while others may be more useful for generating other types. Additionally, cost, runtime, error rate, availability, etc., can vary depending on the quantum computing technology.

[0007] For certain types of quantum computing, such as fault-tolerant computation of large-scale quantum algorithms, the overhead of performing such quantum computations can be very high. For example, for quantum gate types that are not naturally fault-tolerant, the quantum gates can be encoded with error-correcting codes. However, this can increase the overhead of the qubits required to implement large-scale quantum algorithms. Furthermore, performing continuous quantum gates, measuring quantum circuits, etc., can introduce error probabilities in the quantum circuits and / or measurement results of the quantum circuits. Attached Figure Description

[0008] Figure 1A A system comprising a nanomechanical linear harmonic oscillator and a superconducting quantum interference device (ATS) with asymmetric threads, according to some embodiments, is shown, the system being configured to realize hybrid acoustic-electric quantum bits.

[0009] Figure 1B The modeling of a storage mode (a) and a dump mode (b) of a hybrid acoustic-electric quantum bit according to some embodiments is shown, wherein for a large energy decay rate (Kb) that is significantly greater than the two-phonon coupling rate (g2), the dump mode can be adiabatically eliminated, such that the hybrid acoustic-electric quantum bit can be modeled as having a single-phonon decay rate (K1) and being driven by a two-phonon drive having a two-phonon decay rate (K2).

[0010] Figure 2 The Foster network representing a one-dimensional phonon crystal defect resonator (PCDR) is shown according to some embodiments.

[0011] Figure 3 A system comprising a plurality of nanomechanical linear harmonic oscillators and a superconducting quantum interference device (ATS) with asymmetric threads is shown according to some embodiments, the system being configured to provide multimode stability for hybrid acoustic-electric quantum bits realized via the plurality of nanomechanical linear harmonic oscillators.

[0012] Figure 4A system comprising a plurality of nanomechanical linear harmonic oscillators and a superconducting quantum interference device (ATS) with asymmetric threads is shown according to some embodiments. The system is configured to provide multimode stabilization of hybrid acoustic-electric quantum bits realized via the plurality of nanomechanical linear harmonic oscillators, wherein a microwave filter suppresses correlated attenuation processes.

[0013] Figure 5 The process of stabilizing a nanomechanical harmonic oscillator using a superconducting quantum interference device (ATS) with asymmetric threads is illustrated according to some embodiments.

[0014] Figure 6 The process of using a multiplexed ATS to stabilize multiple nanomechanical harmonic oscillators is illustrated according to some implementation schemes.

[0015] Figure 7 The diagram illustrates a data error that occurs when an input error is measured on a set of qubits, according to some embodiments, where the data error results in multiple different compensators.

[0016] Figure 8 This illustrates the logic of the repeating code according to some implementation schemes. The measurement and logic used to measure repetition codes The corresponding circuit.

[0017] Figure 9 The diagram illustrates a circuit for preparing Q=SHS according to some embodiments, where the CNOT gate is a single physical CNOT and is applied if the measurement result is -1.

[0018] Figure 10 The diagram illustrates a circuit for fabricating S according to some embodiments, where the CNOT gate is a single physical CNOT and is applied if the measurement result is -1.

[0019] Figure 11A The diagram illustrates a circuit for implementing a logic Toveley gate using Toveley magic state injection, according to some embodiments, wherein the X and Z bases are measured.

[0020] Figure 11B The following are examples based on some implementation schemes. Figure 11A The Z and X measurements of the circuit shown are based on the Clifford error correction table.

[0021] Figure 12 The diagram illustrates a circuit for implementing a logic CZ gate using a transverse CNOT gate and an S gate, according to some implementation schemes.

[0022] Figure 13 The circuit for preparing the ground state |ψ1> according to some embodiments is shown.

[0023] Figure 14 This illustrates, according to some implementation schemes, the use of controlled g A The circuit implements the first step of Toveley's magical state preparation, in which the STOP algorithm is used to perform one or more rounds of error correction (EC).

[0024] Figure 15 This diagram illustrates a circuit for the second step of preparing the Toveli magical state, according to some embodiments, where g A The number of measurements repeated corresponds to the yard distance (d) minus one and divided by two, where g is measured in each round. A A round of repeating code stabilization measurement is performed between them, and if the error detection measurement or g A If any of the measurements is nontrivial, the protocol is suspended and restarted.

[0025] Figure 16 The diagram illustrates how, according to some implementation schemes, the calculated ground state |ψ1> grows from a first code distance (d1) to a second code distance (d2).

[0026] Figure 17 This illustrates, according to some embodiments, the calculation of the ground state |ψ1> for measuring a code distance of three. A The circuit.

[0027] Figure 18 This illustrates, according to some embodiments, the method for calculating the ground state |ψ1> using a flag qubit measurement. A Alternative circuits.

[0028] Figure 19A This illustrates the g-codon of a distance-5 repeating code prepared using a GHZ state according to some embodiments. A The method of measurement.

[0029] Figure 19B This illustrates implementation methods based on some embodiments. Figure 19A The g shown A The equivalent circuit for measurement.

[0030] Figure 20A The high-level steps of a protocol for implementing the STOP algorithm, according to some implementation schemes, are shown.

[0031] Figure 20B The advanced steps for determining the parameters (ndiff) used in the STOP algorithm are shown according to some implementation schemes.

[0032] Figure 21 The high-level steps of a protocol for using the STOP algorithm to increase the repeating code distance from the first code distance to the second code distance, according to some implementation schemes, are shown.

[0033] Figure 22 The high-level steps of a protocol for implementing logical Toveley gates using a bottom-up approach with Toveley magic state injection, according to some implementation schemes, are shown.

[0034] Figure 23 The following are examples of uses based on some implementation schemes. Figure 22 The high-level steps of extracting low-error-rate logic Toveli gates are described in the bottom-up method described in the paper, which prepares multiple Toveli magic states.

[0035] Figure 24 The layout of multiple bottom-up Toveley magic states for extracting low-error-rate logic Toveley gates is shown according to some implementation schemes.

[0036] Figure 25 The diagram illustrates gadgets for injecting CCZ gates using the |CCZ> magic state according to some implementations, and gadgets for generalized CCZ injection of unitary matrices.

[0037] Figure 26 The diagram illustrates a circuit, according to some implementations, for extracting two low-error-rate logic Toveley gates (CCZ gates) from eight magic-state inputs.

[0038] Figure 27 The Litinski diagram is shown for a lattice operation implementation, according to some embodiments, for performing the extraction of eight Toveley magic states to obtain two low-error-rate logic Toveley gates.

[0039] Figure 28 The process for extracting low-error-rate logic Toveley gates from multiple noisy Toveley magic states is shown according to some implementation schemes.

[0040] Figure 29A This illustrates the process of extracting two low-error-rate logic Toveli gates from eight noisy Toveli magic states, according to some implementation schemes.

[0041] Figure 29B This illustrates the process of extracting a low-error-rate logical Toveley gate from two noisy Toveley magic states, according to some implementation schemes.

[0042] Figure 30 An exemplary method is shown, according to some implementations, for performing lattice operations to extract low-error-rate logic Toveley gates from multiple noisy Toveley magic states.

[0043] Figure 31 The circuit shown is a measurement of the readout qubits of a set of error correction gates while executing the next round of error correction gates, according to some implementation schemes.

[0044] Figure 32A more detailed circuit is shown, according to some embodiments, for performing measurements of the readout qubits of a set of error-correcting gates while executing the next round of error-correcting gates.

[0045] Figure 33 A more detailed circuit is shown, according to some embodiments, for performing measurements of a set of readout qubits of error correction gates while performing the next round of error correction gates, wherein the circuit includes compressing auxiliary qubits before being swapped to the readout qubits, and wherein the measurements include parity measurements of the readout qubits.

[0046] Figure 34 This is a flowchart illustrating a process of using a switching operator to excite the readout qubit according to some implementation schemes, so that a subsequent round of error correction gates can be applied while performing the measurement of the readout qubit.

[0047] Figure 35 This is a flowchart illustrating a process for performing a measurement of a qubit using compression, according to some implementation schemes.

[0048] Figure 36A This is a flowchart illustrating a process for compressing a cat qubit and measuring the “b” mode of the compressed cat qubit according to some embodiments to determine information about a first mode of the compressed cat qubit.

[0049] Figure 36B This is a flowchart illustrating another process for compressing a cat qubit and measuring the “b” mode of the compressed cat qubit according to some embodiments to determine information about the first mode of the compressed cat qubit.

[0050] Figure 37 This is a flowchart illustrating a process, according to some embodiments, for evolving a cat qubit via a three-wave or higher mixed Hamiltonian and performing null, heterodyne, or optical detection on the evolved cat qubit to measure the measurement properties of another boson mode of the cat qubit.

[0051] Figure 38 This illustrates the use of shifted Focke's algorithm to simulate cat qubits (where |α|) according to some implementation schemes. 2 >>1) Process flowchart.

[0052] Figure 39 This is a block diagram illustrating an exemplary computing device that can be used in at least some of the embodiments.

[0053] While embodiments are described herein by way of example and illustrative figures, those skilled in the art will recognize that embodiments are not limited to the described embodiments or figures. It should be understood that the figures and their detailed description are not intended to limit embodiments to the specific forms disclosed, but rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope defined by the appended claims. The headings used herein are for organizational purposes only and are not intended to limit the scope of the specification or claims. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning possible) rather than a mandatory sense (i.e., meaning must). Similarly, the word “include / including / includes” means including but not limited to. When used in the claims, the term “or” is used as inclusive rather than exclusive. For example, the phrase “at least one of x, y, or z” means any one of x, y, and z, and any combination thereof. Detailed Implementation

[0054] This disclosure relates to methods and apparatus for implementing universal gate sets for fault-tolerant and resource-efficient quantum algorithms.

[0055] In many cases, the overhead of performing universal fault-tolerant quantum computation for quantum algorithms can be very high. To perform such fault-tolerant quantum computation, magic state extraction is often used. For example, magic state extraction can be used to simulate non-Clifford gates in a fault-tolerant manner. However, since magic state extraction circuits are not fault-tolerant, Clifford operations must be encoded with large-distance codes to have a failure rate comparable to that of the extracted magic states.

[0056] To perform quantum computing, it might be necessary to build a universal fault-tolerant quantum computer capable of implementing all gates in a universal gate set with a low logical error rate. Furthermore, the overhead of achieving such a low error rate should likely be very low. Lateral gates are a natural way to implement such fault-tolerant gates. However, according to the Eastin-Knill theorem, given any stable subcode, there will always be at least one gate in the universal gate set that cannot be implemented at the logical level using lateral operations.

[0057] To address this issue, several fault-tolerant methods have been explored for implementing gates in a universal gate set. However, magic state extraction remains a leading candidate for realizing a universally fault-tolerant quantum computer. However, the cost of performing magic state extraction remains high. One reason for this high cost is that the Clifford circuits used to extract magic states are typically not fault-tolerant. Therefore, Clifford gates are encoded with error-correcting codes (usually surface codes) to ensure that these gates have a negligible error rate compared to the injected magic states.

[0058] In some implementations, efficiently realizing a universal gate set may involve multiple layers of a quantum computer / quantum algorithm. For example, at the lowest layer, building blocks of a quantum computer may include nanomechanical resonators controlled using a superconducting quantum interference device (SQUID or ATS with asymmetric threads). The nanomechanical resonator can be configured to resonate at one or more frequencies and can be coupled to the ATS, where the ATS controls phonon modes. Furthermore, the ATS can be coupled to a bandpass filter and then to an open-circuit transmission line, allowing photons from the ATS to be absorbed by the environment. At the next level, error correction can be implemented for the quantum computer comprising the nanomechanical resonator and the ATS. For example, error-correcting codes can be constructed that utilize the phonon modes of the ATS and the nanomechanical resonator for error detection and / or correction. At yet another level, error-correcting codes can be used as inputs or outputs of gates to implement gates for the quantum computer. Furthermore, error correction can be applied to the qubits of the gates. At higher levels, logic gates utilizing one or more physical gates can be constructed. Please note that while several protocols described herein, such as the STOP algorithm, bottom-up methods for preparing Toveley gates, top-down extraction of Toveley gates, measurement techniques and / or shifted Focke-Kiehl simulations, are described in accordance with systems utilizing nanomechanical resonators to realize hybrid acoustic-electric quantum bits, in some implementations other hardware types, such as those realizing electromagnetic quantum bits, may be used.

[0059] Superconducting quantum interference device (ATS) with asymmetric threads - phonon hybrid system

[0060] In some implementations, the circuitry for a quantum computer may include a nanomechanical linear resonator and a superconducting quantum interference device (SQUID, ATS) with asymmetric threads. The nanomechanical resonator and ATS can realize qubits that are hybrid acoustic-electric quantum bits, unlike electromagnetic qubits. In some implementations, the nanomechanical resonator and ATS may reside on the same component and can be used to easily scale the system to include additional components with additional nanomechanical resonators that realize additional hybrid acoustic-electric quantum bits. This can also be achieved by scaling the number of qubits required for the quantum computer by including more or fewer components. This approach allows for simpler scaling compared to systems where the components realizing qubits are integrated into a single chip and require newly designed chips to scale the system to have more or fewer qubits. As used herein, the terms “mechanical,” “acoustic,” “phonon,” etc., can be used to describe mechanical circuitry that differs from electromagnetic circuitry.

[0061] In some implementations, more phonon resonators (e.g., nanomechanical resonators) can be connected to the same control circuit, such as an ATS, compared to electromagnetic resonators. This is at least partly due to the smaller size of phonon resonators compared to electromagnetic resonators. However, in such systems, crosstalk between phonon resonators coupled to the same control circuit must be addressed to avoid errors. Multiplexing control of phonon resonators using a common control circuit (e.g., an ATS) will be discussed in further detail below.

[0062] In some implementations, the chip structure including the phonon resonator can take the form of a planar circuit with metal components forming a superconducting circuit (e.g., an ATS). The ATS can be physically connected via leads to very small (e.g., micrometer- or nanometer-scale) suspended mechanical devices, such as linear nanomechanical resonators. The suspended mechanical devices can be located on the same chip as the ATS circuit or can be located on a separate chip that has been heterogeneously integrated with a bottom chip including the ATS and / or additional suspended mechanical devices (e.g., other mechanical resonators) by flip-chip or similar components.

[0063] In some implementations, the electrical connection to the ATS can be placed on top of the piezoelectric material that has been etched into a pattern to form a nanomechanical resonator. In some implementations, different variables, such as piezoelectric coefficient and density, may affect the coupling strength between the ATS and the mechanical resonator. This coupling can be represented by the phonon coupling rate in the Hamiltonian of the system.

[0064] When coupling nanostructures (such as nanomechanical resonators) to a circuit, very small capacitors are required because the nanostructure components (such as nanomechanical resonators) are also very small. Typically, other capacitors are also present in the circuit, such as in an ATS circuit. Because the capacitors used for the nanostructures are so small, these other capacitors in the circuit can reduce the signal voltage and thus dilute the signal directed to one of the nanostructure components (such as the nanomechanical resonator). However, to address this issue, a high-impedance inductor can be coupled into the control circuit between the ATS and the nanomechanical resonator. A high-impedance inductor can have very low parasitic capacitance, so the electric field directed towards the nanomechanical resonator can act on it with minimal dilution caused only by the inductor's capacitance (such as parasitic capacitance). Furthermore, a high-impedance inductor can suppress loss mechanisms.

[0065] In some implementations, the nonlinear coupling of the nanomechanical resonator can be achieved by... +hc is given, where g2 is the coupling ratio between the storage mode (a) and the dump mode (b). In some implementations, nonlinearity can be achieved using a SQUID (superconducting quantum interference device) with asymmetric threads (also referred to herein as "ATS"). An ATS can comprise a superconducting quantum interference device (SQUID) roughly separated in the middle by a linear inductor. In its most general form, the ATS potential is given by the following equation:

[0066]

[0067] In the equation above, It is the phase difference across the ATS, φ ∑ :=(φ ext，1 +φ ext，2 ) / 2, φ Δ :=(φ ext，1 -φ ext，2 ) / 2, and φ ext，1 (φ ext，2 ) is the magnetic flux passing through the left (right) loop, in order to reduce the magnetic flux quantum. Units. Here. E j =(E j，1 +E j，2 ) / 2; and It is a junction asymmetry. This is achieved by adjusting φ using two separate flux lines. ∑ and φ Δ This ATS potential can be further simplified. For example, Figure 1A The diagram shows the ATS 102 included in the control circuit 100, wherein the ATS 102 includes separate flux lines 108 and 110. Note that... Figure 1A The diagram includes an ATS 102 within the control circuit 100, and also includes an enlarged view of the ATS 102 adjacent to the control circuit 102, thus showing the ATS 102 in more detail. The flux line can be configured such that:

[0068] and

[0069]

[0070] In the above equation, ∈ p (t)=∈ p，0 cos(ω p t) is a small alternating current (AC) component added to the direct current (DC) base. At this bias point, and assuming |∈ p (t)|<<1, then regarding The above equation can be simplified to:

[0071]

[0072] use Figure 1A The control circuit 100 shown allows quantum information to be stored in the state of a linear mechanical harmonic oscillator. For example, the quantum information can be stored in storage mode 106. Automatic error correction of the stored quantum information can also be achieved through artificially induced two-phonon drive and two-phonon decay controlled by an ATS. These two-phonon processes are performed via storage mode a and auxiliary mode b (called dump, e.g.) Figure 1A Nonlinear interaction between the dump modes 104 shown To induce. The dump mode is designed to have a large energy decay rate K. d Therefore, it can quickly and irreversibly "dump" the photons it contains into the environment. If K d If the coupling coefficient g2 is much larger (e.g., ~10 times or more), the dump mode can be adiabatically eliminated from the Hamiltonian, for example, as Figure 1B As shown. For example, as Figure 1B As shown on the right, via The emitted phonon pairs can be accurately modeled as consisting of dissipative phonons ~D[a 2 The dissipation process described. Additionally, if the dump mode is linearly driven as This provides a stimulus for the reverse process. The required energy, such as Figure 1B As shown, this can be modeled as an effective two-phonon drive in adiabatic elimination. In summary, the dynamics can be accurately modeled by the following equations:

[0073] Where α = ∈ / g2 and

[0074] Figure 1B The steady state of the dynamics of the system shown is a coherent state |α>, |-α>, or any arbitrary superposition of the two. This protected subspace can be used to encode qubits by the following logical foundation definition: |0 L >=|α>,|1 L >=|-α>. Quantum bits encoded in this way effectively avoid X errors (e.g., bit flips) because the bit flip rate increases with the code distance |α|. 2 It decays exponentially, as long as K2|α| 2 >> K1, where K1 is the typical (e.g., single-photon) decay rate of the storage mode. Due to |α| 2 ~1, this condition is roughly equivalent to K2 / K1 >> 1. However, Z errors (such as phase flips) may not be protected by this code.

[0075] As described above, the ATS is formed by splitting the SQUID using a linear inductor. The magnetic flux of each of the two resulting loops of the ATS passes through two adjacent on-chip flux lines (e.g., Figure 1A The flux lines 108 and 110 shown are controlled. These flux lines can be tuned to appropriate values ​​and can transmit radio frequency (RF) signals at appropriate frequencies to resonate and activate the desired nonlinear interaction in the nanomechanical resonator. Dump mode 104 can be further strongly coupled to the dump line of characteristic impedance Z0, which causes a large energy decay rate as needed.

[0076] In some implementations, the nanomechanical storage resonator (e.g., memory 106) can be a piezoelectric nanomechanical resonator supporting resonance in the GHz range. These resonances can be coupled to the superconducting circuitry of control circuitry 100 via small superconducting electrodes (e.g., terminals) in direct contact with or very close to the vibrating piezoelectric region of the nanomechanical resonator. The values ​​of the nonlinear coupling rate g2, the two-phonon dissipation rate k2, and the ratio K2 / K1 can be calculated as follows:

[0077] First, the admittance Y observed at the terminals of the nanomechanical harmonic oscillator is calculated using a finite element model solver. m (ω). Next, the equivalent circuit is found using the Foster synthesis algorithm (discussed further below). Then, the combinational circuit is diagonalized and the zero-point phase ripple φ is calculated. a，zp and φ b，zp Furthermore, the dissipation rate k of the intrinsic mode is calculated. b And k1. Next, calculate In addition, calculation

[0078] In some implementations, nanomechanical elements, such as nanomechanical resonators that realize storage mode 106 and dump mode 104, can be represented as equivalent circuits that accurately capture their linear response. If the admittance Y seen from the terminals of the mechanical resonator... m If (ω) is known, this operation can be accomplished using Foster synthesis. For example, finite element modeling can be used to calculate the admittance. In some implementations, the Foster network can be used to accurately represent a one-dimensional (e.g., linear) phonon crystal defect resonator (PCDR), which can be a type of nanomechanical resonator used in some implementations. In some implementations, the dump resonator can be modeled with a fixed impedance, such as 1 kiloohm.

[0079] For example, Figure 2A version of the control circuit 100 represented using a Foster network is shown (e.g., equivalent circuit 200). In its simplest form, equivalent circuit 200 can be represented as a 'DC capacitor' in series with an LC block (e.g., L represents the inductor of the LC block, and C represents the capacitor), with additional resistors inserted to account for loss effects in the resonator. For example, Foster network 210 is modeled as including capacitor 204, inductor 206, and resistor 208. The linear portion of the dump resonator (including the inductor that splits the ATS) can also be represented as an LC block, such as LC block 212. In this representation, the dump resonator (e.g., 212) and the storage resonator (e.g., 210) are represented as two linear circuits with linear coupling and can therefore be diagnosed by simple coordinate transformations. For example, Figure 2 The diagnosed circuit representation 214 is shown. The resulting "class storage" is also shown. and "quasi-dump" All eigenmodes contribute to the overall phase drop of the ATS. For example, Therefore, these modes can be redefined through ATS potential energy mixing. Because the inductor has been absorbed into the linear network, the zero-point phase ripple of each mode is given by the following equation:

[0080]

[0081] In the above equation, C is the Maxwell capacitance matrix of the circuit. U is the diagnostic value of C. -1 / 2 L -1 C -1 / 2 an orthogonal matrix, where L -1 It is the inverse inductance matrix. The index k∈{a, b} marks the pattern, and j marks the node in question. Note that in some cases, as described in this article, the sign of j may be omitted because it is self-evident from the context; for example, the node of interest is the node directly above the ATS.

[0082] The approach to ATS hybrid mode is clear because The third-order terms in the Taylor series expansion contain The terms are of the form that require coupling. This is why an ATS is used instead of a regular junction, which has potential...

[0083] For analysis purposes, the pump frequency and drive frequency can be set to ω. p =2ω a -ω b

[0084] And ω d =ω b This makes the item Entering resonance allows for the discarding of other terms in the Rotating Wave Approximation (RWA). Coupling is achieved by... Given. Additionally, a frequency of ω was added. d =ω b linear drive To provide the energy needed for two-photon drive.

[0085] Multimode stability / ATS multiplexing

[0086] In some implementations, the scheme described above can be extended for multi-mode scenarios, where N > 1 memory resonators are simultaneously coupled to a single dump + ATS. This allows for the individual stabilization of the cat subspace for each memory mode. For example, in the form of... The dissipative phonons. However, to avoid simultaneous or coherent loss of phonons from different modes (resulting in the inability to stabilize the desired subspace), incoherent dissipative phonons are required. This can be achieved if the stabilizing pumps and drives used for different modes are intentionally detuned in the following manner:

[0087] in and

[0088] In the above equation, and These are the pump frequency and drive frequency of mode m. By detuning the pump, pump operators of different modes can rotate relative to each other. If the rotation rate is greater than k2, then the form in Lindbladian... The coherence disappears in a time-averaged sense. Drive detuning allows the pump and drive to remain synchronized, even if the pump has been detuned relative to each other.

[0089] In some implementations, a multiplexed ATS can be used to simultaneously stabilize modes a1 and a2, where the pump has been detuned. Simulations can be performed to determine the detuning parameters using the master equations of the simulation, for example:

[0090]

[0091] Bandwidth limitations

[0092] When deharmonic Δ and k b The above adjustments are most effective when the screen size is relatively small. This is because, unlike the single-mode case, where... The two-phonon attenuation of a multimode system is given by the following equation:

[0093]

[0094] The Lorentz inhibition factor can be understood as the photons / phonons emitted by the dump mode due to the stable mode n at a frequency ω. b+Δ n The emission is thus "filtered" by the Lorentz line shape in the dump mode, which has a linewidth k. b This sets an upper limit on the size of the frequency region that detuning is allowed to occupy. Furthermore, in some implementations, to make dissipation incoherent, the detuning Δ... n All can differ from each other by a factor greater than k2. In the frequency domain plot, all spectral lines associated with photon / phonon emission from the dump must be resolved. This also sets a lower limit on the proximity of different tunings. Thus, by setting upper and lower limits, the bandwidth limitation of detuning can be determined. Furthermore, taking these limitations into account, an upper limit can also be determined on the number of modes that a single dump can be simultaneously stabilized. For example, if detuning is chosen as Δ... n = nΔ, where Δ ~ k2, then the maximum number of simultaneously stable modes can be limited to N. max ~k b / Δ~k b / k2. As another example, for typical parameters, such as k b / 2π~10MHz and k2 / 2π~1MHz, which allows for bandwidth limitations that enable the simultaneous stabilization of approximately 10 modes.

[0095] For example, Figure 3 A control circuit 300 is shown, which includes a single dump resonator 302 that stabilizes a plurality of storage resonators 304.

[0096] High-impedance inductors are used to enhance the coupling between the dump resonator and one or more storage resonators.

[0097] In some implementations, the coupling ratio g2 can be increased by using a high-impedance inductor. This is because g2 is strongly dependent on the effective impedance Z of the dump resonator. d For example, g2~Z d 5 / 2 Therefore, in some implementations, the use of a large inductor in the ATS may result in a large effective impedance Z. d In some implementations, the inductors selected to be included in the ATS circuit can be sufficiently linear to ensure the stability of the dump circuit when it is strongly driven during the settling period. For example, the high-impedance inductors used may include planar zigzag or double-helix inductors, helical inductors with air bridges, arrays with a large number (e.g., more than 50) of highly transparent Josephson junctions, or other suitable high-impedance inductors.

[0098] Filtering in Multi-Mode Stabilized / Multiplexed ATS

[0099] In some implementations, microwave filters (e.g., metamaterial waveguides) can be used to mitigate the limitations regarding bandwidth constraints discussed above. Such filters can also be used to eliminate relevant errors in multiplexing stabilization implementations. For example, Figure 4 The control circuit 400 is shown, which includes a single dump resonator 404, a plurality of storage resonators 406, and a filter 402.

[0100] More specifically, when using the same dump resonator and ATS device to stabilize multiple storage modes, many cross terms appear in the Hamiltonian that would not normally appear in the single-mode case. For example, these terms employ g2a j a k b + e -ivt In the form of b-mode adiabatic elimination (e.g., regarding...). Figure 1B (As discussed), these terms actually become form k 2， eff a j a k e -ivt The jump operator. And the desired jump process that causes individual stability of the cat subspace for each harmonic oscillator. Unlike other conditions, the correlated decay terms cause simultaneous phase flipping of the harmonic oscillator j and k. For example, these correlated errors can disrupt error correction in the next layer, such as in repeating or striped surface codes.

[0101] In some implementations, to filter out unwanted terms in the physical Hamiltonian that generate effective dissipatives that cause correlated phase reversals, the detuning of these unwanted terms can be greater than half the filter bandwidth. This can result in exponential suppression of the unwanted terms. In other words, a detuning filter can be selected such that the detuning of the effective Hamiltonian is greater than half the filter bandwidth. Furthermore, the filtering mode (along with the dump mode) can be configured with... Figure 1B A similar approach to the adiabatic elimination discussion of the dump mode is used to adiabatically eliminate it from the model. This can be used to determine the effective dissipators of circuits including the dump resonator 404 and filter 402 (e.g., control circuit 400).

[0102] As described above, if the corresponding emitted photon has a frequency outside the filter bandwidth, the correlated phase error can be suppressed by the filter. In some implementations, all correlated phase errors can be suppressed simultaneously by carefully selecting the frequency of the storage mode. For example, the optimal storage frequency can be determined using a cost function, taking into account the filter bandwidth. For example, in some implementations, a single ATS / dump can be used to suppress decoherence associated with all effective Hamiltonians of the five storage modes. In such implementations, all major sources of random correlated phase errors in cat qubits can be suppressed.

[0103] Multi-terminal mechanical resonator

[0104] In some implementations, nanomechanical resonators (e.g., those shown in Figures 1 to 1) Figure 4 The nanomechanical resonators shown can be designed with multiple terminals, allowing a given nanomechanical resonator to be coupled to more than one ATS / control circuit. For example, a single-connection ATS may include a ground terminal and a signal terminal, wherein the signal terminal is coupled to the control circuit including the ATS. In some embodiments, a multi-terminal nanomechanical resonator may include more than one signal terminal, thus allowing the nanomechanical resonator to be coupled to more than one control circuit / more than one ATS. For example, in some embodiments, a nanomechanical resonator may include three or more terminals, enabling the nanomechanical resonator to be coupled to three or more ATSs. If not needed, additional terminals may be coupled to ground, making the multi-terminal nanomechanical resonator function similarly to a single (or fewer) connected nanomechanical resonator. In some embodiments, different signal terminals of the same nanomechanical resonator may be coupled to different ATSs, wherein the ATS may be used to implement gates between mechanical resonators, such as CNOT gates. For example, this may allow for the implementation of gates for the stabilizer function.

[0105] Example physics gate implementation

[0106] Recall the shift from coupled to shared ATS patterns Multiple photon modes Hamiltonian of the system:

[0107]

[0108] in and also, and Quantitative model and The zero-point fluctuation. To simplify the discussion, we will temporarily ignore the zero-point fluctuation due to the pump ∈ p The small frequency shift caused by (t) is assumed, and the mode frequency is given by its raw frequency (however, in practice, the frequency shift needs to be considered; see below for information on pump-induced frequency shifts). Then, in a rotating coordinate system rotating at each mode's own frequency, the following is obtained:

[0109]

[0110] in and Quantitative model and The zero-point fluctuations. Note that a rotating coordinate system has been used, where each pattern rotates at its own frequency.

[0111] First, this can be achieved by using a pump ∈ p (t)=∈ p cos(ω p t) and select the pump frequency ω p To drive the frequency of the mode (i.e., ω) p =ω k To easily achieve photon mode (i.e.) Linear drive. Then, by using only the leading-order linear term in the sinusoidal potential (e.g., We obtain the desired linear drive:

[0112]

[0113] H′ includes fast oscillation terms, for example Where l≠k, and And other terms that rotate faster. Since the frequency difference between the different modes is approximately 100MHz, but |∈ z | / (2π) is usually much smaller than 100MHz, so the rotating wave approximation (RWA) can be used to ignore the faster oscillation terms.

[0114] To avoid driving unnecessary higher-order terms, one could choose to directly drive phonon modes, but this would increase hardware complexity. Alternatively, a pump could be used at the ATS node. p (t).

[0115] Now let's continue implementing the compensated Hamiltonian for the CNOT gate. For example, the compensated Hamiltonian for the CNOT gate might have the following form:

[0116]

[0117] Without loss of generality, consider the pattern (control) and CNOT gates between (targets). Please note. Including optomechanical coupling between two phonon modes Control mode Linear drive and target mode Selective frequency shift. To achieve optomechanical coupling, one might want to pump ∈ p (t)=∈ p cos(ω p t) Directly driving the cubic term in the sinusoidal potential energy However, the direct-drive approach is unsuitable for the following reasons: due to the item Rotating at frequency ω1, the required pump frequency is determined by ω p =ω1 is given, which is consistent with the design for the pair The linear drive of the mode retains the same pump frequency. Furthermore, the term... It rotates at the same frequency as the unwanted cubic term. Therefore, even by directly driving the phonon mode... To achieve linear drive, but due to frequency conflicts with other cubic terms, it is not possible to use the pump frequency ω. p =ω1 to selectively drive the desired optomechanical coupling.

[0118] In some implementations, to overcome these frequency oscillation problems, the driving term is driven non-resonantly. To achieve optomechanical coupling. For example, using time-dependent Hamiltonians. The effective Hamiltonian is obtained after averaging over time. The fact, the assumption The overall pattern is very small (e.g., And the deharmonicization Δ is sufficiently large. Therefore, given a Hamiltonian... This gives

[0119]

[0120] To be specific, by choosing λ = -2α, optomechanical coupling and... Selective frequency shift of the mode, for example Up to the undesired cross Kerr term In this scheme, the desired selectivity is achieved because the item Other unwanted items (e.g.) Where k≥3) the de-harmonic frequency difference ω2-ω k Therefore, unwanted optomechanical coupling can be suppressed by appropriately selecting the detuning Δ. It is worth noting the unnecessary cross-Kerr terms. In principle, another cubic term can be driven by different deharmonicizations Δ′ ≠ Δ non-resonance. To compensate.

[0121] Finally, a similar method used in the compensated Hamiltonian of the CNOT gate can also be applied to the compensated Hamiltonian of the Toveley gate.

[0122] Example process for implementing an ATS-phonon hybrid system

[0123] Figure 5 The process of stabilizing a nanomechanical harmonic oscillator using a superconducting quantum interference device (ATS) with asymmetric threads is illustrated according to some embodiments.

[0124] In block 502, the control circuitry of the system comprising one or more nanomechanical resonators supplies phonon pairs to the nanomechanical resonators via an ATS to drive the stabilization of the stored modes of the nanomechanical resonators, such that the stored modes are maintained in a coherent state. Furthermore, in block 504, the control circuitry dissipates the phonon / photon pairs from the nanomechanical resonators via an open transmission line of the control circuitry coupled to the nanomechanical resonators and the ATS.

[0125] Figure 6 The process of using a multiplexed ATS to stabilize multiple nanomechanical harmonic oscillators is illustrated according to some implementation schemes.

[0126] In block 602, a storage mode of a plurality of nanomechanical resonators driven by a multiplexed ATS is selected such that the storage mode is detuned. For example, block 602 may include detuning the storage modes supported by the plurality of nanomechanical resonators with a dump resonator comprising a superconducting quantum interference device with asymmetric threads. In block 604, phonon pairs are supplied to a first nanomechanical resonator in the nanomechanical resonator at a first frequency, and in block 606, phonon pairs are supplied to other nanomechanical resonators in the nanomechanical resonator at other frequencies such that the frequencies of the corresponding storage modes of the nanomechanical resonators are detuned. For example, blocks 604 and 606 may include pumping and driving the ATS to activate the two-phonon drive dissipative stabilization of the first nanomechanical resonator in the nanomechanical resonator and suppressing the associated decay processes from the plurality of nanomechanical resonators via a microwave bandpass filter.

[0127] Alternatively, the storage mode frequency and bandwidth of the filter in the control circuit can be selected such that the detuning of unwanted terms is greater than half the filter bandwidth. Then, in block 608, a microwave filter with defined filter bandwidth properties can be used to filter out relevant attenuation terms from multiple nanomechanical resonators.

[0128] The STOP algorithm and the preparation of fault-tolerant universal gate sets, including the bottom-up preparation of Toveley gates.

[0129] In some implementations, the system described above for implementing hybrid acoustic-electric quantum bits can be used to implement a universal gate set. In some implementations, error correction can be used to correct errors and / or noise in such systems. In some implementations, as described herein, the STOP algorithm can provide an efficient protocol for providing error detection and / or correction. In some implementations, the system described above for implementing hybrid acoustic-electric quantum bits may introduce noise biased towards phase-flip errors. With this understanding of error bias, error correction protocols (such as the STOP algorithm) can be used to effectively correct errors. Additionally, as discussed further below, error correction can be used to correct errors when preparing Toveley gates using a bottom-up approach (and / or when using a top-down approach discussed further in the next section).

[0130] In some implementations, the STOP algorithm can be used to determine when it is acceptable to stop (STOP) a stabilizer measurement as part of an error detection / correction operation, while ensuring that the probability of a logical error is low. For example, the STOP algorithm can be used to measure a stabilizer measurement before executing a Tovelimen, where measurement errors are corrected before the Tovelimen is applied.

[0131] An alternative to using a STOP decoder could be graph-based error correction techniques. However, these techniques are typically based on the use of Clifford gates and are less useful when applying Toveley gates. For example, these techniques involve measuring the data qubits at the end of an operation used to determine the error. However, with non-Clifford gates, a single qubit error in the initial input qubits can lead to logical faults that might be undetectable using standard graph-based error correction techniques.

[0132] Conversely, the STOP algorithm measures the stabilizers of the input data qubits, allowing error detection and / or correction to be performed before operations (e.g., non-Clifford gates) are executed. Instead of measuring the stabilizers of the data qubits a fixed number of times, which might be insufficient to detect / correct logic errors in some cases, or unnecessary in others, the STOP algorithm can be used to determine when to stop the stabilizer measurements while still guaranteeing a low probability of logic errors. For example, in some implementations, the STOP algorithm can guarantee that the total number of faults is less than the code distance of the repeatedly encoded data qubits (e.g., repeated codes) divided by two. Therefore, it is known that most repeated data qubits are error-free, and no logic errors occur because most encoded data qubits are correct. For example, errors are tolerable as long as the total number of errors is less than the code distance divided by two. In such cases, errors do not lead to logic errors because most encoded qubits are error-free. Note that physical errors are different from logic errors. Physical errors act on individual qubits, while logic errors are based on the erroneous logical output determined by the physical qubits. Logic errors cannot be directly detected, and if not detected, cannot be corrected. For example, an uncorrected physical error may lead to a logical error, but if the physical error is not detected, the logical error caused by the physical error cannot be measured without knowing the physical error.

[0133] In some implementations, the STOP algorithm can also be applied to qubits used to perform non-Clifford gates (e.g., Toveley gates). Furthermore, in some implementations, the STOP algorithm can be used when increasing the repeating code from a first code distance to a second code distance, where stabilizers at boundaries between multiple code blocks are measured, said code blocks being joined to increase the repeating code. The STOP algorithm can be used to determine when repeated measurements of stabilizers at boundaries can be stopped without introducing logical errors into the extended repeating code.

[0134] In some implementations, when preparing a Toveley gate, the STOP algorithm can be used to detect and / or correct errors in the initial computational ground state used to prepare the Toveley gate. The STOP algorithm can also be used to prepare Clifford gates applied sequentially to implement the Toveley gate, where the STOP algorithm is used to detect / correct errors in the Clifford gate. Additionally, the STOP algorithm can be used in g A Error detection / correction is performed between measurements, which is part of the repeatable measurements prepared using a bottom-up approach to Toveliman, as discussed further below. In some implementations, g can be measured in each round. A One round of error checking is performed between each step.

[0135] In some implementations, the STOP algorithm may follow an algorithm similar to the one shown below:

[0136] Set: t = (d-1) / 2; n diff =0; countSyn=1; SynRep=1

[0137] n diff Increase = 0; test = 0

[0138] while test = 0{

[0139] if n diff =t{

[0140] test = 1;

[0141] }

[0142] Measure the error corrector. Store the error corrector from the previous round in...

[0143] synPreviousRound and store the current corrector in synCurrentRound.

[0144] if (countSyn > 1) {

[0145] if(synPreviousRound=synCurrentRound){

[0146] SynRep = SynRep + 1;

[0147] n diff Increase = 0;

[0148] }else{

[0149] SynRep = 0;

[0150] if(n diff Increase = 0){

[0151] n diiff =n! "##+1;

[0152] n diff Increase = 1;

[0153] else

[0154] n diff Increase = 0

[0155] }

[0156] }

[0157] if(SynRep=tn diff +1){

[0158] test = 1;

[0159] }

[0160] countSyn = countSyn + 1;

[0161] }

[0162] In other words, let S j For the j-th th The error in the round-robin collimator measurement. The goal of the STOP algorithm is to compute the minimum number of faults that could cause a change between two consecutive collimators. The worst case is that a single two-qubit gate fault leads to three different collimator outcomes. To understand this, let S... k-1 Let be the corrector for the (k-1)th round. Now assume we use... Figure 7 The circuit 700 shown is a measurement operator. Input error E in , so that s(E in ) = s k-1 Furthermore, assume that a gate failure in the last two-qubit leads to an error. Error X could result in a possible corrector s k-1 Data error XE in(For example, data error 702), while the Z error flips the corrector result (for example, measurement result 704), resulting in a result that may differ from s. k-1 and s k+1 The corrector s k Therefore, in the absence of any other faults, this example demonstrates that a single fault can lead to three different compensators. k-1 s k and s k+1 .

[0163] The STOP decoder tracks the continuous compensator measurement results s1, s2, ..., s r ′, where r is the number of measurement rounds k and k+1 (with corresponding correctors s) of the two correctors. k and s k+1 The total number of calibrator measurements between (r is not fixed), where the variation in calibrator results is caused by the variable n. diff The minimum number of faults (represented by n) is only possible when n is n. diff It only increases when it does not increase in the k-th round.

[0164] Now assume that for a distance d error-correcting code there are no more than t = (d-1) / 2 faults, if the same corrector s j Repeatedly tn diff If the result is +1, then the calibrator is definitely correct (i.e., there is no measurement error). Therefore, in this case, the calibrator s can be used. j To correct the error and terminate the agreement.

[0165] Similarly, if n diff =t, then there must be at least t errors. Therefore, by repeating the calibrator measurement once more (causing calibrator s...), r And use the corrector for decoding, for s r Therefore, more than t faults are required to generate error correction. Thus, the STOP decoder will terminate if one of the following two conditions is met:

[0166] 1) Continuously obtain tn diff +1 syndrome s j In this case, s j The corrector is used for decoding. Or

[0167] 2) Variable n diff Increase to n diff =t. In this case, the calibrator measurement is repeated once, and the repeated calibrator measurement is used for decoding.

[0168] Stabilizing suboperations using repeating codes

[0169] In some implementations, repeating codes can be used to prepare the logic computation ground state. In some implementations, as described above, the stabilization submeasure of repeating codes can be performed using the STOP algorithm. Furthermore, in some implementations, the methods described herein can be applied to any family of Calderbank-Shor-Steane (CSS) codes.

[0170] In some implementations, the following fact is used for n-qubit repeating codes. First prepare Then proceed with logic Measurement (see) Figure 8 Project the state onto |0> L (Given a +1 result) and |1> L (Given a result of -1). The logic X applied to the data is due to a measurement error on the auxiliary qubit. L =X1 is incorrect, therefore X can be repeated using the STOP algorithm. L The measurement (where the compensator corresponds to the auxiliary qubit measurement result) and the application of appropriate X based on the final measurement result. L Fault tolerance is achieved through correction. For example, if |0> L If the desired state is reached, and the final measurement at the termination of the STOP algorithm is -1, then X1 will be applied to the data. Finally, note that only errors in X can be corrected.

[0171] Data propagates from the auxiliary qubit, but is exponentially suppressed by the cat qubit.

[0172] In some implementations, the ground state can be prepared using methods that involve only stabilizer measurements. For example, from the state... It started as Z L The a+1 eigenstates, when all stable elements of the repeating code are measured (each with a random ±1 result), result in the state:

[0173]

[0174] If X k X k+1 If the measurement result is -1, then correction can be applied to the data. This flips the sign back to +1. However, considering the possibility of measurement error, all stabilizers must be repeated. <X1X2,X2X3,…,X n-1 X nThe measurement of the collimator can be performed. If a physically non-Clifford gate is applied before measuring the data, the STOP algorithm can be used to determine when to stop measuring the collimator results. Subsequently, a minimum weighted perfect match (MWPM) can be applied to the complete collimator history to correct errors and the code space can be repaired by applying appropriate Z-correction based on the initial stabilizer measurement. This second approach for preparing the computational ground state can be used in conjunction with the STOP algorithm when a Clifford gate is applied to the data qubits to prepare the |TOF> magic state.

[0175] Additionally, it should be noted that, although the error E is uncorrectable (z) Z L The logical components (where E) (z) It is correctable) and can always be |0> L Absorption, resulting in the output state |ψ> out =E (z) |0> L However, it has the ability to target |0> L The fault-tolerant preparation scheme (thus repeating all the measurements of the stabilizers a sufficient number of times) remains important. For example, if a single fault leads to a correctable Z-error in weight two (assuming n≥5), a second fault in a subsequent computational part could combine with the weight two error, resulting in an uncorrectable error in the data qubit. Therefore, such a preparation protocol is not fault-tolerant up to the full code distance.

[0176] Implementation of the logical Clifford gate

[0177] Since the CNOT gate is lateral for repetitive codes, the focus can be placed on implementing a set of single-qubit Clifford operations. Recall that the Clifford group is generated by the following equation:

[0178] in

[0179] Please note that H and S given above are the Hadamard and phase gate operators. In some implementations, S and Q = SHS can form a generator set for Clifford operations on a single qubit. When implementing such a state, a state can be executed. The injection is the a+1 eigenstate of the Pauli operator.

[0180] exist Figure 10 In the middle, the method for implementing S is given. L Circuit 1000, wherein the circuit adopts |i> L The input state includes a transverse CNOT gate and a logic Z-basis measurement. If a -1 measurement result is obtained, Z is applied to the data. L Calibration. However, note that measurement errors may cause logical Z-axis errors. LIt was incorrectly applied to the data. Therefore, to ensure fault tolerance, it can be repeated. Figure 10 The circuit uses a STOP algorithm to determine when to terminate. The final measurement results can then be used to determine whether Z-axis termination is necessary. L Correction. Therefore, the implementation of S can be summarized as follows:

[0181] 1.) Implementation Figure 10 The circuit is shown, and the measurement result is denoted as S1;

[0182] 2.) Repeat Figure 10 The circuit uses the STOP algorithm to determine when to terminate; and

[0183] 3.) If the final measurement result S r = +1, then do nothing; otherwise apply Z to the data. L =Z1Z2…Z n .

[0184] Figure 9 The diagram shows a circuit 900 for implementing the logic Q=SHS gate. This circuit is constructed by injecting |i> L The system consists of a state, a transverse CNOT gate, and a logic X-basis measurement applied to the input data qubit. If the measurement result is -1, then Y is applied to the data. L Like the S-gate, Figure 9 The circuit in Q is applied by repeating the STOP algorithm to prevent measurement errors. L The complete implementation is given below:

[0185] 1.) Implementation Figure 9 The circuit is shown in the figure, and the measurement result is set as S1;

[0186] 2.) Repeat Figure 9 The circuit in the code uses the STOP algorithm to determine when to terminate; and

[0187] 3.) If the final measurement result S r = +1, then do nothing; otherwise, apply Y to the data. L =Y1Z2…Z n .

[0188] Please note that identities can be used. From S L and Q L The protocol obtains a logical Hadamard gate. Therefore, it is ignored. Figure 9 and Figure 10 The repetition of the circuit, H L The implementation requires three logic CNOT gates and two |-i> gates. L And a |i> LThe state, two logical Z-basis measurements, and one logical X-basis measurement. Instead of using two logical Hadamard gates and a CNOT gate to obtain the CZ gate, it is... Figure 12 A more efficient circuit is shown. Finally, due to Figure 9 and Figure 10 The circuit in the diagram contains only stabilizer operations and injection. L Therefore, repeating measurements using the STOP algorithm is not absolutely necessary. For example, a fixed number of measurements could be repeated and a majority vote taken instead of using the STOP algorithm. However, the STOP algorithm may be more efficient in low noise conditions because the average number of repetitions of the measurement can be close to t+1, where t = (d-1) / 2.

[0189] Using repeating codes to grow encoded data qubits to a larger code distance.

[0190] In some implementations, the state is encoded with a distance from the d1 repeating code. Growth is a state encoded by distance d2 repeating code. Such a protocol can be used to grow |TOF> magic states, as described further below.

[0191] set up For having a base The stable subgroup of the d1 repeating code is located at a distance from the d1 repeating code. Similarly, Defined as in Furthermore, the stable subgroup of the distance from the d2 repeating code is composed of Provided.

[0192] In addition, g i (d1) Defined as s d1 The i-th stable component in the matrix, and g i (d′1) Defined as The i′-th stable component in the matrix, therefore and Used to Growth to The protocol is given as follows:

[0193] 1.) Preparation state

[0194] 2.) Measurement All stable elements in the state lead to the state

[0195]

[0196] 3.) Repeat using the STOP algorithm The stabilizers in the code space are measured, and MWPM is applied to the collimator history to correct errors and projected into the code space. If If the value measured in the first round is -1, then a correction is applied to the data.

[0197] 4.) Preparation status and measurement

[0198] 5. Repeat step s using the STOP algorithm. d2 All stabilizers are measured, and MWPM is used to correct errors in the comparator history. If stabilizers are stable in the first round... If the measured value is -1, then a correction should be applied.

[0199] The growth plan involves two parts, the first being the status. It grew to The second block involves the state Prepared and by A stable set of qubits (steps 1 to 3). The key is to measure the boundary operator between the two blocks. This effectively merges the two blocks into the encoding state. This is a simplified implementation of lattice manipulation. To understand this, consider the state before step 4:

[0200]

[0201] In the above equation, |1> d1 =X1|0> d1 Furthermore, in measurement And perform correction When the measurement result is -1, then |ψ>3 is projected onto:

[0202]

[0203] Due to the random results and measurement errors that may occur when performing appropriate projections, multiple rounds of repeated stabilization submeasures may be required in steps 3 and 5 (above). A graphical representation of the growth scheme is shown in... Figure 16 As shown in the image.

[0204] |TOF> Bottom-up Fault-Tolerant Preparation of Magical State

[0205] In some implementations, a |TOF> magic state can be prepared using repeating codes, where the |TOF> magic state is used to simulate Toveley's mantle.

[0206] The magical state is given by the following formula: |TOF>

[0207]

[0208] It is stable by the Abel group.

[0209] S TOF = <g A g B g C >

[0210] in,

[0211] g A =X1CNOT 2，3

[0212] g B =X2CNOT 1，3

[0213] g C =Z3CZ 1，2

[0214] Given a copy of the |TOF> magical state, you can use Figure 11A Circuit 1102 in the circuit simulates the Toveley gate, and in Figure 11B The required Clifford correction is given in the table. Note that if the correction involves the stabilizer g... C Then you can use Figure 12 Circuit 1200 in the diagram implements the CZ gate. Furthermore, note that for Clifford correction, 0 represents a +1 measurement result, while 1 represents a -1 measurement result (in the X or Z basis). The stabilizer g is given in the above equation. A g B and g C .

[0215] Next, we will discuss how to fault-tolerantly prepare |TOF> magic states. First, please note the state... By g A and g C Stable. Can be used directly. Figure 13 Circuit 1300 in the circuit is used to prepare this state. Next, before measuring the data, a physical Toveley gate will need to be applied between the auxiliary qubit and |ψ1>. Therefore, it is important to use the STOP algorithm in Figure 13 The fabrication state in circuit 1300 | 0> L and |1> L Otherwise, measurement errors in the final round of auxiliary qubit measurements could lead to logic failures. Once prepared... L 、|1> L and |0> L This allows for horizontal application. Figure 13 CNOT gate 1302.

[0216] Now, given a copy of |ψ1>, it can be achieved by using Figure 14 Circuit 1400 measures g A To prepare a |TOF> magic state, resulting in a state |ψ> out If the measurement result is +1, then |ψ> out =|TOF>. Otherwise, if the measurement is -1, then |ψ> out =Z2|TOF>. Therefore, given a measurement result of -1, apply logic Z to the second code block. L Correction. Figure 17 The controlled g is shown in the middle. A A more detailed implementation of gate 1400 is 1700. For example, circuit 1700 is shown for measuring the code distance d = 3. Typically, d Toveley gates are required. Note that for repeating codes, a single CNOT gate is needed because X... L =X1. Furthermore, due to the transverse CNOT gates, as shown, physical Toveley gates are applied sequentially. Note that this type of circuit can be used with any Calderbank-Shor-Steane (CSS) code. The order of the Toveley gates will remain unchanged. According to X L The minimum weight representation typically requires more two-qubit gates.

[0217] Please note that due to CNOT 1，3 The gate can be performed laterally for repeating codes, and the X on the second code block L The physical X gate on the first qubit of this block is given, therefore the controlled g A The circuit can be highly parallelized, thus greatly simplifying its implementation. For example, Figure 18 Showing the measurement of g A A more parallelized circuit, requiring a flag qubit 1802, is possible. Such a circuit reduces the depth of the Toveley gate by half, but at the cost of an increased time step due to the additional CNOT gate. The flag qubit can also be used to detect X errors occurring on the control qubits of the CNOT and Toveley gates. If an X error occurs, the flag qubit measurement will be -1 instead of +1. Figure 14 , Figure 15 and Figure 17 As shown, if the X or Z base measurement result is -1 instead of +1, the entire |TOF> magic state preparation protocol is aborted and restarted.

[0218] Similar to the discussion above regarding repeating codes, measurement errors on the auxiliary qubits lead to logic Z2 faults, thus requiring repetition of g. A The measurement can be performed deterministically using the STOP algorithm. However, since the circuit depth increases with the repeating code distance, and the controlled g... AThe high cost of gates means this scheme lacks a threshold, resulting in a considerably high logic failure rate. An alternative approach is to repeat g for the distance d repeating code. A The measurement is exactly (d-1) / 2 times to use the error detection scheme. In g A Between each measurement, an error detection round is performed on the data qubits by measuring the stabilizer of the repeating code. This is in Figure 15 As shown in the diagram. If any measurement result is nontrivial, the protocol used to prepare the |TOF> magic state will be aborted and reinitialized. Figure 19A The paper presents a two-dimensional layout of qubits and a method for measuring g. A Example 1900 of the operation sequence is compatible with the ATS architecture described above for distances of 5-repetition codes. This layout uses a minimal number of auxiliary qubits and can be directly generalized to arbitrary repetition code distances. The auxiliary qubits are first used to prepare the GHZ state. Subsequently, the required Toveley and CNOT gates are applied, after which the GHZ state is cleared and the |+> state auxiliary qubits are measured. Figure 19B The figure shows g that implements the d=5 repeating code. A The equivalent circuit for measurement in 1950.

[0219] Please note that, to accommodate the connectivity constraints of the ATS, the lighter gray vertex 1902 needs to be swapped with the darker gray vertex 1904 on the second block (e.g., ...). Figure 19A (As shown in the top left corner of the grid). Due to the reasons discussed above regarding filtered multiplexing ATS, this role reversal between auxiliary qubits and data qubits does not cause additional crosstalk errors and is therefore tolerable. Therefore, Figure 15 All controlled g A Measurement can be used Figure 19B The circuit in 1950 Figure 19A It is implemented under the given qubit layout.

[0220] Finally, please note, Figure 19B The part used to measure g A The circuit 1950 is not fault-tolerant for either X or Y errors. However, since it is assumed that X and Y errors are suppressed exponentially, a flag qubit for detecting the propagation of X-type errors is unnecessary, as long as the X or Y error rate multiplied by the total number of fault locations is below the target level of the algorithm of interest.

[0221] Figure 20A The high-level steps of a protocol for implementing the STOP algorithm according to some implementation schemes are shown.

[0222] In box 2002, a collimator result measurement is performed on any Calderbank-Shor-Steane code. In box 2004, consecutive collimator results are tracked to generate a collimator history. In box 2006, the collimator measurement is stopped if either condition 1 (shown in box 2006A) or condition 2 (shown in box 2006B) is met. Condition 1 is the threshold number of consecutive repetitions of the same collimator result, where the threshold is equal to ((d-1) / 2)-n. diff -1. Condition 2 is n. diff It equals (d-1) / 2, and reaches n diff = (d-1) / 2 An additional correction result has been measured. Measurement of the correction result can be stopped if any of these conditions are met. In box 2008, if condition 1 is met, the repeated correction result is used to perform error correction. Furthermore, in box 2008, if condition 2 is met, the subsequently measured correction result is used to perform error correction.

[0223] Figure 20B This illustrates the parameters (n) used to determine the STOP algorithm according to some implementation schemes. diff Advanced steps.

[0224] In box 2052, initialize n with an initial value equal to zero. diff In box 2054, the first round of calibration result measurement is performed. Furthermore, in box 2056, the second round of calibration result measurement is performed. In box 2058, it is determined whether the calibration result measured in the round performed in box 2056 (e.g., the calibration result of the current round) differs from the calibration result measured in the previous round. If so, then in box 2060, n is determined. diff If n increased in the previous round, then in box 2062... diff Increment by one, and repeat the process for the next round of calibration result measurements. However, note that calibration measurements stop when either condition 1 or condition 2 (as shown in boxes 2006A and 2006B) is met. Calibration measurements stop if the calibration result measured in the round performed at box 2056 (e.g., the calibration result of the current round) is the same as the calibration result measured in the previous round, or if n is determined at box 2060. diff For the previous increment, the process returns to box 2056, and without making n... diff The result of the corrector is measured in another round under the incremental case.

[0225] Figure 21 The high-level steps of a protocol for using the STOP algorithm to increase the repeating code distance from the first code distance to the second code distance, according to some implementation schemes, are shown.

[0226] In box 2102, the |ψ1> state is prepared as described above, for example using... Figure 13 The circuit shown. In block 2104, all stabilizers S are measured. d’1 This leads to the state |ψ2>. This can be accomplished as described above regarding the stabilizing suboperation of the repeating code. In box 2106, the STOP algorithm is used to repeatedly measure S. d’1 The stabilizer in the code is used, and MWPM is applied to the collimator history to correct errors and project the code into an enlarged code space. In box 2108, the |ψ3> state is prepared, and X is measured. d1 X d1+1 In box 2110, the STOP algorithm is used to repeatedly measure S. d2 All stable elements are analyzed, and MWPM is applied to the history of the correctors to correct errors.

[0227] Figure 22 The high-level steps of a protocol for implementing logical Toveley gates using a bottom-up approach with Toveley magic state injection, according to some implementation schemes, are shown.

[0228] In box 2202, the STOP algorithm is used to prepare the fault-tolerant computational ground state, which will be used as the input for the Toveley gate preparation. In box 2204, the CNOT gate is applied laterally to the fault-tolerant computational ground state to prepare the |ψ1> state. In box 2206, g is measured for the |ψ1> state. A , obtain the state |ψ out >. If g A If the measurement has a result of -1, then Z-correction is applied. This projects the |ψ1> state into the |TOFF> state. In box 2208, g is repeated. A The measurement of g makes the measurement of g A (d-1) / 2 times. In g A Error detection is performed between each round of measurements. If for g... A If the error detection measures a non-trivial value, the protocol is aborted and restarted. In box 2210, if g A If all measurements and the error detection performed at 2208 are trivial, then based on g A Measurement and state | ψ out >To prepare the Toveley magic state (e.g., the |TOFF> state). For example, if g A If all measurements and the error detection performed at 2208 are trivial, then |ψ out >=|TOFF>. In box 2212, apply... Figure 11A The Clifford gate sequence is shown in circuit 1102. Furthermore, the application... Figure 11BThe example shown is Clifford error correction. This can be accomplished as part of a top-down extraction of the logic Toveley gate (described in more detail below), which utilizes the prepared Toveley magic state as input to the extraction process.

[0229] Top-down extraction process for generating low-error-rate Toveleyan.

[0230] As described above, Toveley gates, when combined with Clifford groups, form a universal set of gates for quantum computing. Alternatively, universality can be achieved by supplementing the Clifford group with numerous high-fidelity Toveley magic states encoded with suitable quantum error-correcting codes. For many high-threshold error-correcting codes, such as repetitive (for extremely biased noise) or surface codes, it is difficult to prepare high-fidelity Toveley magic states. A paradigm for magic state extraction uses encoded Clifford operations to extract higher-fidelity magic states from lower-fidelity magic states. For example, Toveley magic states prepared using the bottom-up approach described above can be used in the magic state extraction process to produce Toveley magic states with lower failure rates.

[0231] Conventional methods for magic state extraction use many low-fidelity T magic states as input to protocols that output other types of magic states, including TOFF states. However, in some architectures, many noisy TOFF states can be prepared with better fidelity than noisy T states. This is because all Calderbank-Shor-Steane (CSS) codes (e.g., surface codes and repeating codes) have lateral CNOTs, and this property can be used to robustly prepare TOFF states (as described above for bottom-up methods). However, the success rate of such "bottom-up preparation" protocols decreases as the target fidelity increases, thus requiring the design of magic extraction protocols that can further purify noisy TOFF states with low overhead. If a bottom-up TOFF protocol is used to prepare magic states with 10... -5 -10 -6 The TOFF state of the error rate means that for several quantum algorithms, only a single round of magic state extraction is needed to achieve 10. -9 -10 -10 Logical error rate. In contrast, for a ratio of 10... -3 -10 -4 To achieve a comparable logic error rate, the T-state preparation requires either two rounds of magic state extraction with quadratic error suppression or a single-round 15T→1T protocol with a low (1 / 15) rate.

[0232] In some implementations, to address these issues, a top-down extraction process is performed, which uses TOFF or CCZ states without using any T states as raw material for extraction or as a catalyst. Furthermore, triorthogonal codes are not used in the usual sense, but rather provide a new technique for protocol design by describing CCZ circuits according to cubic polynomials. Note that CCZ states are equivalent to Clifford states of TOFF states, and it is advantageous to work using the language of CCZ states when using cubic polynomial forms. As an example of these techniques, in some implementations it has been shown that 8CCZ→2CCZ extraction can be implemented, equivalent to 8TOFF→2TOFF for detecting faults on any single TOFF state. More compact and efficient protocols are possible in cases where noise on CCZ states is highly biased towards certain types of faults, and this will also be described.

[0233] In some implementations, various architectures can be used to implement the extraction process described herein, such as 2D architectures using repeating codes, asymmetric surface codes (for biased noise), or conventional square surface codes. 2D implementations use lattice manipulation to perform the required Clifford operations to achieve a suitable sequence of multi-qubit Pauli observables (also known as multi-patch measurements).

[0234] Figure 23 The following are examples of uses based on some implementation schemes. Figure 22 The high-level steps for extracting low-error-rate logic Toveli gates are described in the bottom-up method for preparing multiple logic Toveli gates.

[0235] For example, in box 2302, a physical Toveley magic state is generated, which may have approximately 2.8 × 10⁻⁶. -4 The error probability can be reduced by an order of magnitude or more by applying the STOP algorithm and error correction techniques described above for the bottom-up approach. For example, box 2304 illustrates the error rate reduction achieved using the bottom-up approach. However, a further reduction in the error rate can be achieved by performing a top-down extraction process. For example, box 2306 illustrates that performing a single round of extraction using the Toveley magic state prepared using the bottom-up approach as input can reduce the error probability to approximately 8 x 10^6. -10 .

[0236] Figure 24 The diagram illustrates a layout of multiple bottom-up Toveley gates for extracting low-error-rate logic Toveley gates according to some implementation schemes.

[0237] To provide an overall view of the extraction process, Figure 24The circuit 2400 is shown, comprising qubits that have been fabricated to implement bottom-up (e.g., "BU") magic states. Furthermore, other qubits of the circuit have also been fabricated to implement CCZ magic states (or low-error-rate Toveley magic states / gates). Additionally, some qubits implement error checking for CCZ magic states. For example, each set of check qubits may be associated with a pair of CCZ magic states.

[0238] comprehensive

[0239] First, observe the CCZ on qubits i, j, and k. i，j，k The door will execute:

[0240]

[0241] Where |x>=|x1, x2, x3, ..., x n > indicates that the description is a binary string x = (x1, x2, x3, ..., x...). n The ground state of ). More generally, consider combining these CCZ gates with CNOT circuits. For any invertible matrix J, there exists a CNOT circuit V such that:

[0242] V = ∑ x |x> <Jx|。

[0243] Combining these operations, the generalized CCZ gate is given by the following equation:

[0244]

[0245] J k Let J be the k-th column vector of J, and J k x=∑ α [J k ] α x α It is the dot product between the vector and the bit string vector x. Because J is invertible, J... k They must be linearly independent; otherwise, there are no constraints. Furthermore, only three column vectors are needed to describe the action of a single generalized CCZ gate.

[0246] Alternatively, you can use Figure 25 The single CCZ magic state shown in 2504 implements the generalized CCZ gate. The CCZ magic state is:

[0247]

[0248] And it can be used to inject CCZ gates, such as Figure 25As shown, and can be extended to a generalized CCZ gate by controlling the CNOT gate determined by the associated vectors J1, J2, and J3. Furthermore, the CNOT in CCZ injection can be replaced with a sequence of multi-qubit Pauli measurements, which are fundamental operations in an architecture based on lattice manipulation.

[0249] In some implementations, the unitary matrix shown below can be constructed using CCZ, CZ, Z, and CNOT gates:

[0250]

[0251] Where J is invertible, and f: These are Boolean functions that can be expressed as cubic polynomials. Formally, this can be represented as shown in Theorem 1 below:

[0252] Theorem 1: Let U be a unitary matrix of the form of the above equation, and let f be a function such that there exists a cubic polynomial representation:

[0253]

[0254] With integer F i，j，k Therefore, it can be concluded that polynomials have many different factorizations, as follows:

[0255]

[0256] in U is a binary vector (and therefore a linear function), and Q is a lower triangular binary matrix (representing a quadratic Boolean function). Then there exists a circuit consisting of {CCZ, CZ, Z, CNOT} that implements U using at most ζ copies of the CCZ gates. We call the smallest of these ζ the cubic rank of the polynomial.

[0257] CCZ Magic State Extraction

[0258] In some implementations, cubic polynomial forms are used to develop routines for extracting high-fidelity |CCZ> magic states. For example, given a source noisy |CCZ> state with Z-noise, a Clifford operation can be used to extract the noisy |CCZ> state to obtain a smaller number of |CCZ> states with less noise. Note that given any noise model, the |CCZ> magic state can be rotated such that the noise becomes pure Z-noise. Therefore, in some implementations, the circuit is designed to implement the target unitary matrix, i.e., It operates on 3k qubits plus a number of m check qubits. However, instead of minimizing the number of CCZ gates in the circuit, the proposed design allows Z errors in the |CCZ> magic states to propagate to the check qubits. Therefore, errors in noisy |CCZ> states can be detected by measuring the check qubits at the end of the circuit.

[0259] To more accurately understand the error-correcting properties of a circuit, for example, the following definition can be used:

[0260] Definition 1: Given two Boolean functions f and g that can be expressed as cubic polynomials, we can say that they are Clifford equivalents of f ~ g such that for all x, f(x) = g(x) + q(x).

[0261] If f ~ g, then they obviously also have the same cubic rank, and the associated unitary matrices have the same minimum CCZ count.

[0262] Definition 2: Given a set of column vectors used in the equations as described above in the synthesis discussion. Describes a series of ζ-generalized CCZ gates, a set of matrices J j Each matrix is ​​defined as having three columns, as follows:

[0263]

[0264] If the last qubit is considered a check qubit, then the matrix will be divided into C. j (bottom m row) and L j As shown in the figure.

[0265] Please note that C = (C 1 C 2 C 3 C ζ ) and L = (L 1 L 2 , ..., L ζ It functions similarly to the X-checksum and logical X-operator matrix in quantum codes. It also requires error symbols for error patterns on the initial magic state.

[0266] Definition 3: Given Magic state, if it is in a state It is then said to have an error mode. mistake

[0267] Given a ζ-generalized CCZ gate sequence, the notation used is Let |CCZ> represent the error of the j-th |CCZ> state, therefore the joint state is:

[0268]

[0269] If for w, e in the state |CCZ> j If the value is non-zero, then the error is said to have w fault locations.

[0270] The concepts of weight and concatenation strings used above are related to this. 1 , ..., e ζ The distinction between commonly used Hamming weights is important because many methods for preparing noisy |CCZ> states will result in errors similar to those of single-qubit states. A considerable probability of error, such as In fact, we are often interested in knowing how many |CCZ> states are affected by arbitrary errors, even assuming that errors are uncorrelated between different |CCZ> states. Regarding Figure 25 The observation of error propagation in [the context] can now be formalized as follows:

[0271] Given a unitary matrix U implemented by a series of generalized CCZ gates represented by matrices as in Definition 2, the magic state suffers from the Pauli error (e 1 , ..., e ζ Then, the resulting unitary matrix on the target qubit is UZ[w], where And vector yes

[0272]

[0273] The last qubit is designated as the check qubit. w can be divided into two parts, as follows:

[0274]

[0275]

[0276] Now that we know how errors typically propagate, this knowledge can be applied to specific protocols, such as extracting two low-error-rate logical Toveli gates from eight noisy Toveli magic states, or extracting one low-error-rate logical Toveli gate from two noisy Toveli magic states.

[0277] Consider a unitary matrix U implemented by a series of generalized CCZ gates as defined in Definition 2, where the last m qubits are identified as check qubits, and... Among them U C It is Clifford and This applies to the verification of quantum bits. Consider the following protocol:

[0278] 1.) Prepare all qubits in the state |+>;

[0279] 2.) Execute Clifford's Reverse and any Clifford corrections from gate injection;

[0280] 3.) Measure the last m qubits in the X basis.

[0281] Then, the X-basis measurement in step 4 will produce a +1 result, provided that the magic-state error mode satisfies the following equation:

[0282]

[0283] The protocol output has a mundane error Z[u] magic state. if only

[0284]

[0285] Example Protocol

[0286] Consider having J j Matrix 2CCZ→1CCZ protocol:

[0287]

[0288] The corresponding cubic polynomial can be directly verified as follows:

[0289]

[0290] Therefore, the circuit is implemented. This is a single CCZ gate and (until Clifford) its role on the check qubit is negligible. There is only one check qubit. Therefore, it will detect any error patterns, where It includes a single input magic state. Error. However, it cannot detect other single-fault error modes in a magic state, such as...

[0291] Now consider an 8CCZ→2CCZ protocol for detecting arbitrary errors in a single input CCZ state. A possible circuit 2602 implementation of this protocol is shown in... Figure 26 The protocol uses 3 check qubits and is associated with J. j The matrix is ​​shown in Figure 26 For example, matrix 2608 corresponds to the first CCZ, matrix 2610 corresponds to the second CCZ, matrix 2612 corresponds to the third CCZ, and matrix 2614 corresponds to the eighth CCZ. Note that there are a total of eight matrices, each corresponding to each of the eight CCZs. However, for ease of illustration, only the matrices for CCZs 1-3 and 8 are shown. Calculating the cubic polynomial yields:

[0292] f(x) = x1x2x3 + x4x5x6

[0293] It represents two CCZ gates and has a negligible effect on the check qubits. Note that this polynomial has no quadratic component, therefore an inverse Clifford's rule is not needed. Regarding error detection capability, note that each check matrix is ​​an identity, therefore the three-bit error corrector is v = ∑ j e j Given a fault in a single CCZ state, e j One of the vectors will be non-zero, therefore v will be non-zero and an error will be detected. Conversely, if both CCZ states have the same error pattern, then e j =e j′ If ≠0, the corrector will be canceled, and this will be an undetected error. However, not all two-fault errors go undetected. If magic states j and j′ fail, but e j ≠e j′ Then these two failure modes will be detected. The intuition that the above matrix has the expected properties relates to the fact that the matrix is ​​constructed using a subset of codewords from three copies of the Reed-Maller code.

[0294] Consider an error model where a single noisy magic state has an error pattern e. j Sum of probabilities We will use conventions The probability of success is:

[0295]

[0296] This involves summing all configurations with trivial correctors. To determine the fidelity of the output magic state, we should sum all configurations with trivial correctors that do not logically corrupt the state. For the leader, this is dominated by the "error-free" case, which effectively provides a definite lower bound for the fidelity, so...

[0297] f≥(1-∈) 8 / P suc

[0298] Now consider the depolarization error distribution:

[0299]

[0300] The contribution of the leading order to the success probability can be calculated as follows. The zero-failure contribution increases the success probability. We do not calculate any single-failure events because they are all detected. In a two-failure event, we need a pair of (j, j′) magic states (with 8 choices 2 = 28 combinations) to withstand the same nontrivial error pattern e.j There are 7 types of e j ≠ 0. This means there are 196 undetected two-fault error modes, which contribute 196 (∈ / 7) to the success probability. 2 (1-∈) 6 =(196 / 49)∈ 2 (1-∈) 6 However, not all undetected two-fault error modes lead to logic faults; the contribution to undetected logic faults is (184 / 49) ∈ 2 (1-∈) 6 This leads to the following approximate result:

[0301] P suc ≈1-8∈

[0302]

[0303] Please note that ∈ 2 The constant factor of 3.755 is very small for the extraction protocol. This is because the protocol detects the vast majority of all two fault events.

[0304] In some implementations, the above protocol can be summarized as 3k+2CCZ→kCCZ.

[0305] Exemplary implementation of lattice surgery

[0306] Figure 27 An exemplary implementation of the above protocol using lattice manipulation is shown. Throughout, we will refer to the input magic state error rate as ∈ and the output error rate simply as ∈. target ~O(∈ 2 As previously mentioned, generalized CCZ gates can be injected using only multi-qubit Pauli measurements. For many error-correcting codes, such as topological codes and repeating codes, lattice manipulation provides a natural way to measure multi-qubit Pauli operators. The following example involves using thin-surface codes with asymmetric distances to handle bit-flip and phase-flip noise. When asymmetry is present, we use the convention of smaller bit-flip distances. This also includes repeating codes as a constraint that the bit-flip distance is one.

[0307] The lattice surgery method uses some auxiliary qubits as communication paths between logic qubits. These qubits are temporarily incorporated into the error-correcting code during multi-patch measurements. m Error correction in rotation. d m The value of d must be large enough that the probability of error is sufficiently small during multi-patch measurements. m The larger the value, the better it prevents measurement errors. However, errors during measurement are equivalent to single-qubit Pauli errors in magic states. Therefore, d mIt must be large enough that the probability of a measurement error is less than O(∈). However, the probability of a measurement error does not necessarily have to be less than the expected unfidelity of the output magic state. However, the logical qubits labeled 1 to 6 need to have a distance d for bit flipping. x And it has a distance d for phase deflection z Encoding is done using codes where these distances are large enough that the logical error rate is below O(∈). 2 ).

[0308] The logical qubits labeled 7 through 9 are the check qubits of the protocol and have a distance d for bit flipping. x And it has a distance d′ for phase reversal z The code is used for encoding. If a Z logic error exists at any point on the check qubit, then this can be swapped to the end of the circuit and will be detected, provided it is a unique error. Therefore, we can set d′ z <d z Only d′ z Large enough that Z-logic may appear at a cost less than O(∈). In surface codes, the space / qubit cost is 2d. z d x Therefore, the total space cost of qubits 1 to 9 and the wiring auxiliary space is:

[0309] N1 = 14d x (2d x +2d z +d′ z )

[0310] Furthermore, the cost space of the L0 block responsible for preparing the input Toveli or CCZ states is N0. We will need 8 such CCZ states, but in Figure 27 In this process, the injection is divided into two batches of four CCZ states. Therefore, we need at least four L0 blocks. However, since the success probability (pf) of each L0 block is finite, some redundancy is required to ensure a high success probability (otherwise, there will be a slight time delay). Given a redundancy factor R, we use 4R copies of the L0 blocks, and the probability of all failures is approximately... The size of the L0 block will depend on the underlying protocol used, and in the case of the underlying protocol, it is 3d′. z If factor R redundancy is required, then the total L0 space requirement is:

[0311] N0=3Rd′ z

[0312] exist Figure 27 The layout is shown in the figure, where R = 3. Note that if 2Rd′ z =7d x ,like Figure 27 As shown, the L0 blocks are neatly aligned with the auxiliary wiring area. If none of the L0 blocks can be adjacent to the wiring area, a different layout (e.g., with two columns of L0 blocks) is required.

[0313] The entire extraction protocol has a time cost of 10 days. m Each code cycle. A large portion of this cost is due to multiple patch measurements. Recall that, in Figure 27 In this protocol, the injection process is divided into two batches of four CCZ states. Within each batch, several injection events are interleaved, which is possible because all involved gates are being swapped. Also note that the protocol uses both multi-patch and single-qubit measurements, but single-qubit measurements can be implemented within one code cycle, thus the cost is negligible. Assuming a surface code architecture where each code cycle uses 4tCNOT, where tCNOT is the CNOT gate time, a total of 40d is given. m tCNOT time cost.

[0314] Figure 28 The process for extracting low-error-rate logic Toveli gates from multiple noisy Toveli magic states / Toveli gates is illustrated according to some implementation schemes.

[0315] In box 2802, multiple Toveley magic states / noisy Toveley gates are prepared using a bottom-up approach or other suitable method. In box 2804, a low-error-rate logic Toveley gate is extracted from the multiple Toveley magic states / Toveley gates prepared in box 2802. In box 2806, a check qubit is measured to check for errors, wherein the check qubit is associated with the extracted low-error-rate logic Toveley gate. In box 2808, in response to the verification check qubit not indicating an error, a low-error-rate logic Toveley gate operation is performed using the extracted low-error-rate logic Toveley gate.

[0316] Figure 29A This illustrates the process of extracting two low-error-rate logic Toveli gates from eight noisy Toveli magic states / Toveli gates, according to some implementation schemes.

[0317] In box 2902, eight noisy Toveley magic states / Toveley gates are selected for extraction of a low-error-rate logic Toveley gate. In box 2904, a lattice operation is performed to extract a low-error-rate logic Toveley gate from the eight noisy Toveley magic states / Toveley gates. In box 2906, the extracted low-error-rate logic Toveley gate is used to perform a logic Toveley gate operation, wherein the error probability of the low-error-rate logic Toveley gate is quadratically suppressed compared to the error rates of the eight noisy Toveley magic states / Toveley gates.

[0318] Figure 29BThis illustrates a process for extracting a low-error-rate logic Toveli gate from two noisy Toveli magic states / Toveli gates, according to some implementation schemes.

[0319] In box 2952, two noisy Toveley magic states / Toveley gates are selected for extraction of a low-error-rate logic Toveley gate. In box 2954, a lattice operation is performed to extract a low-error-rate logic Toveley gate from the two noisy Toveley magic states / Toveley gates. In box 2956, the extracted low-error-rate logic Toveley gate is used to perform a logic Toveley gate operation, wherein the probability of extreme bias noise in the low-error-rate logic Toveley gate is quadratically suppressed compared to the extreme bias noise of the two noisy Toveley magic states / Toveley gates.

[0320] Figure 30 An exemplary method is shown, according to some implementations, for performing lattice operations to extract low-error-rate logic Toveli gates from multiple noisy Toveli magic states / Toveli gates.

[0321] In box 3002, multi-qubit Pauli operator measurements are performed during the lattice operation used to extract low-error-rate logic Toveli gates from noisy Toveli magic states / Toveli gates, where for each J k Where k = 1, 2, 3, ..., perform the following steps. For example, in box 3004, for each value of k, measure... The measurement of Z k Let Z denote the Pauli Z acting on the k-th qubit of the magic state, and Z[J] k ] is an action on the binary vector J k The algorithm indexes a string of Pauli operators for the qubits. Similarly, in box 3006, for each k, X on the k-th qubit of the magic state is measured. In box 3008, for each "-1" result measured in step 3006, Z[J] is used. k Update the Clifford correction coordinate system. Then, in box 3010, using the measurement results from step 3004, update the Clifford correction coordinate system with the corrections given in the figure.

[0322] High-fidelity measurement

[0323] In some implementations, low measurement error and / or faster error correction can be achieved by using an additional readout mode that is queryed during the next error correction cycle. For example, Figure 31 The circuit 3100 shown includes a readout qubit that enables measurement 3106 to be performed on the first error correction gate 3106 while the second error correction gate 3104 is being executed (e.g., simultaneously).

[0324] Please note that while some of the examples included here are for hybrid acoustic quantum bits and Figures 1 to 12, the actual results are different. Figure 30 The architecture described herein is used, but in some implementations, such measurement techniques can be applied to other architectures.

[0325] Consider the fault-tolerant operation of a quantum computer, where the properties of the data qubit (such as a stabilizer) are repeatedly measured. In a given error-correction cycle, this typically involves two steps. First, a gate acts between the data qubit and an auxiliary qubit, then the auxiliary qubit is measured. After the measurement of the auxiliary qubit, another error-correction cycle can be performed.

[0326] In some implementations, faster error correction cycles and lower measurement errors can be achieved by swapping an auxiliary qubit (which is typically directly queried) with an additional readout qubit (which could be some other gate that achieves the same purpose as SWAP, such as iSWAP, SWAP decomposition into CNOTS, etc.). The readout qubit is then read out while the rest of the error correction is performed.

[0327] This method not only reduces the error correction cycle time but also reduces idle errors on the data qubits. This is because the data qubits are only idle during the swapping period, which is typically the short duration required to perform a measurement. Furthermore, since idle time is not an issue when performing measurements on the readout qubits, more repeated measurements can be performed, which also improves measurement fidelity. For example, the full error correction cycle time can be used to collect as many measurements as possible to increase measurement fidelity or to perform a single measurement with a long integration time in the next cycle time.

[0328] For example, in traditional surface code architectures with transmon, measurements are typically much slower than gates. Using this scheme can speed up error correction loop time. Additionally, depending on the specific situation, one may have more time for driving / integrating, thus achieving higher fidelity measurements without compromising the threshold due to large idle errors.

[0329] In some implementations, the additional readout mode can be a boson mode. In such implementations, for the measurement of the readout mode, repeated individual parity checks are performed, and then the final result is determined by majority vote. The ability to perform more repeated measurements can improve the fidelity of the final result.

[0330] Figure 32 A more specific example is shown, where further compression is added. After the CNOT gate auxiliary qubit 3204 is entangled with the data qubit 3202, the auxiliary qubit is compressed. Compression involves reducing the steady-state α of the dissipatively stable auxiliary qubit from its initial |α|. initial | Decrease to a certain|α finalCompression prevents single-photon loss events, the occurrence rate of which is proportional to the average number of bosons in the readout mode. Once the mode is compressed, SWAP 3212 is performed, which transfers the excitation from auxiliary qubit 3204 to boson readout mode 3206 (which can be a phonon mode). To achieve high-fidelity readout, repeated QND parity checks are performed in boson readout mode 3206. Each individual parity check is implemented by dissipatively coupling the readout mode to transmon qubit 3208.

[0331] In some implementations, the objective during parity measurement in boson modes is to determine whether an even number of photons or an odd number of photons are present in the harmonic oscillator. Even during the measurement, the loss of a single photon can alter the parity, potentially leading to incorrect readouts. For dissipatively stable systems, a simple method to improve measurement fidelity is to perform a compression operation 3214 prior to the measurement.

[0332] In a specific case of a system stabilized by the dissipation of two photons, this involves the dissipation of the photons... Become Where |α final |<|α initial This is accomplished by changing α(t) from its initial value to its final value. In most cases, a sufficiently abrupt change is acceptable because it is not necessary to maintain phase coherence between parity states.

[0333] Without compression, it is evident that as the average photon number (α) increases... 2 With the increase of parity, the distortion is significantly reduced because the measurement is more sensitive to changes in single-photon loss due to parity. This problem is corrected by adding compression.

[0334] For example, Figure 33 The parity measurement 3302 performed after compression is shown.

[0335] In some implementations, where a is a qubit mode and b is another mode for readout, compression can follow the procedure below:

[0336] 1.) Compress the qubit to α = 0, map the +cat state to |0> and the -cat state to |1>.

[0337] 2.) In Hamiltonian The b-mode is evolved and measured (zero difference / heterodyne) to determine whether the qubit is in a +cat or -cat state. If the qubit is in a -cat state, there is drive in the b-mode realized by the Hamiltonian, while if the qubit is in a +cat state, there is no drive in the b-mode. This form of Hamiltonian can be resonantly and non-resonantly derived from a three-wave hybrid Hamiltonian of the following form:

[0338]

[0339] In some implementations, other Hamiltonian quantities can be used, such as or

[0340] In some implementations, boson modes can be read out in the ±|α> basis using a three-wavelength or higher-wavelength mixed Hamiltonian. In some implementations, the procedure for such readout can include the Hamiltonian... The evolution and measurement (zero-difference / heterodyne) b-mode are used to measure boson modes in the ±|α> basis. This form of Hamiltonian can be resonantly and non-resonantly derived from a three-wave hybrid Hamiltonian of the following form:

[0341]

[0342] In some implementations, other Hamiltonian quantities can be used, such as or wait.

[0343] Figure 34 This is a flowchart illustrating a process of using a switching operator to excite the readout qubit according to some implementation schemes, so that a subsequent round of error correction gates can be applied while performing the measurement of the readout qubit.

[0344] In box 3402, a set of error correction gates is applied between the data qubit storing quantum information and the auxiliary qubit. In box 3404, a swap is performed between the auxiliary qubit and the readout qubit. In box 3406, one or more measurements are performed on the readout qubit. Simultaneously or without waiting for the measurement at box 3406 to complete, in box 3408, another set of error correction gates is applied between the data qubit storing quantum information and the auxiliary qubit. In box 3410, after the measurement at box 3406 is completed, another swap is performed between the auxiliary qubit and the readout qubit. And, in box 3412, one or more measurements are performed on the readout qubit. Note that this process can be repeated for additional rounds of error correction.

[0345] Figure 35This is a flowchart illustrating a process for performing measurements of auxiliary qubits without requiring transmon qubits, according to some embodiments, using compressed or evolved three-wave or higher-wave hybrid Hamiltonians.

[0346] For example, one or more data qubits storing quantum information may be entangled with auxiliary qubits. In block 3502, the qubit (e.g., the auxiliary qubit) is compressed before a readout is performed on the qubit, causing phonons or photons to dissipate from the qubit while preserving the measurement observables of the qubit. Then, in block 3504, a readout is performed on the measurement observables of the compressed qubit.

[0347] Figure 36A This is a flowchart illustrating a process for compressing a cat qubit and measuring the b-mode of the compressed cat qubit to determine information about the first mode of the compressed cat qubit, according to some embodiments.

[0348] In box 3602, the cat qubit is compressed such that phonons or photons dissipate from the cat qubit. This can be achieved, for example, by adjusting the steady-state dissipation rate, which could be driven by an ATS. In box 3604, the cat qubit evolves under a Hamiltonian that couples multiple excitations of the cat qubit to a second mode (b mode) of the cat qubit. Then, in box 3606, the second mode (e.g., b mode) of the cat qubit is measured to determine information about the first mode (e.g., a mode) of the cat qubit.

[0349] Figure 36B This is a process flowchart illustrating another process for compressing qubits and measuring the “b” mode of the compressed cat qubits according to some embodiments to determine information about the first mode of the compressed cat qubits.

[0350] In box 3652, compression is performed in a system where mode "a" is the qubit mode and mode "b" is the readout mode. Compression involves compressing the qubits to α = 0, such that the +cat state maps to |0> and the -cat state maps to |1>. In box 3654, the system evolves under a Hamiltonian derived from a three-wave or higher hybrid Hamiltonian. For example, the Hamiltonian... In box 3656, a measurement in "b" mode is performed to determine whether the qubit is in a +cat or -cat state. For example, a (zero difference / heterodyne) measurement in b mode is performed to determine whether the qubit is in a +cat or -cat state. If the qubit is in a -cat state, there is a drive in the "b" mode implemented by the Hamiltonian, while if the qubit is in a +cat state, there is no drive in the "b" mode.

[0351] Figure 37This is a flowchart illustrating a process, according to some embodiments, for evolving a cat qubit via a three-wave or higher mixed Hamiltonian and performing null, heterodyne, or optical detection on the evolved cat qubit to measure the measurement properties of another boson mode of the cat qubit.

[0352] In block 3702, the cat qubit evolves under a Hamiltonian that couples the phase of the cat qubit to a measurable property of another boson mode of the cat qubit, wherein the Hamiltonian is selected from a three-wave or higher hybrid Hamiltonian. In block 3704, homodyne, heterodyne, or optical detection of the other boson mode is performed to determine the phase of the cat qubit.

[0353] Using a shifted Fock basis to simulate cat qubits

[0354] A Fockeki is an algebraic structure used to construct a quantum state space based on a single particle in Hilbert space for a variable or unknown number of identical particles. For example, a Fockeki can be used to simulate the behavior of a cavity or phonon harmonic oscillator using an n-dimensional state ladder. For example, a Fockeki can be used to simulate photon number states, where the ground state represents a vacuum condition in which no photons are present. However, by shifting the Fockeki, Hilbert space can be truncated to contain a finite (not infinite) number of photon number states. Therefore, simulations can be simplified to simulate truncated Hilbert spaces instead of infinite Hilbert spaces that cannot be efficiently simulated. For example, a shifted Fockeki simulation can replace the vacuum state with one or more coherent states. For example, a shift operator can be applied to the vacuum state condition such that the lowest shifted Fockeki state corresponds to the lowest operator of the lowest state of a cat qubit.

[0355] For example, due to the need to simulate a large (or even infinite) number of states, conventional (e.g., non-shift) Focke's algorithm is used to simulate big cat qubits (with large |α) 2 |>>1)) may be invalid. Instead, in some implementations, simulations can be performed using a shifted Fockeki, which can be used to describe bigcat states in a more compact way than in the case of a common Fockeki. More specifically, annihilation operators can be constructed in a shifted Fockeki.

[0356] Recall that the cat state consists of two coherent state components |±α>, which can be understood as displacement vacuum states. In a shifted Focke, the 2d shifted Focke state Let n be the ground state, where n ∈ {0, ..., d-1}. Note that although the displacement Fock states in each ±α branch are orthogonally normalized, the displacement Fock states in different branches are not necessarily orthogonal to each other. Therefore, orthogonal normalization of the displacement Fock states is required.

[0357] The non-orthogonal normalized ground state can be defined as follows:

[0358]

[0359] Where |φ n ,+> and |ψ n , -> have even and odd excitation numbers with parity checks, respectively. Note that non-orthogonal normalized states are grouped into even and odd branches instead of ±α branches. Therefore, in the ground state manifold (n=0), the normalized ground state This is equivalent to the complementary ground state of a cat qubit |±>, rather than calculating the ground state |0 / 1>. For example:

[0360]

[0361] The even / odd branching convention ensures that any two ground states in different branches are orthogonal to each other, allowing for independent orthogonal normalization within each parity sector. Please note:

[0362]

[0363] in It is a commonly used displacement operator in Focke's algorithm. Matrix elements:

[0364]

[0365] Here, It is a generalized Laguerre polynomial. Because If m+n << |α| 2 Then D m，n (2α) can be ignored. In this case, the ground state |φ n ±> is almost orthogonal normalized. To estimate the phase-flip (or Z) error rate within small multiplication errors, the state |φ can usually be ignored. n The non-orthogonality of ±> is a concern. However, this is generally not the case if you need to evaluate the Z error rate with very high precision, or if you need to estimate the bit flip (or X) error rate. In these cases, it may be necessary to consider the state |φ. n The nonorthogonality of ±>.

[0366] In such implementations, the ground state |φ is determined by applying the Gramm-Schmidt orthogonalization procedure. n ±> is orthogonally normalized. More specifically, given a non-orthogonal normalized ground state |φ n，± >, from the ground state |φ 0，± Start by constructing d orthogonal normalized ground states in each parity sector:

[0367]

[0368] The coefficients are determined inductively. In the basic case (k = 0),

[0369] For all 1≤m≤d-1,

[0370] Therefore, the logical |±> state of the cat qubit is given by the following equation:

[0371]

[0372] Typically, in the case of 1≤k≤d-1, the following is given: For all 0 ≤ m ≤ d⁻¹ and 0 ≤ n ≤ k⁻¹, therefore, at this point, c ± The first k columns are known. Let... It is a d×k matrix, which is obtained by obtaining matrix c. ± It is obtained from the first k columns. Given We assign c ± The k+1 column is as follows:

[0373]

[0374] For 0 ≤ m ≤ k-1,

[0375]

[0376] and For all m > k.

[0377] A 2d orthonormal shifted Fock ground state |ψ was constructed. n，± After that, it is necessary to determine the operators in the orthogonal normal basis. (For example The matrix elements of φ. Therefore, let |φ n >=|φ n ,+> and |φ n+d >=|φ n，- For ∈{0, ..., d-1}, we similarly define |ψ n > and |ψ n+d >. Assume the operator Normalize the non-orthogonal ground state |φ n The transformation is as follows:

[0378]

[0379] O m，n Non-orthogonal normal basis |φ n Operators in > The matrix elements. Therefore, in an orthogonal normal basis, the operator The matrix elements are given by the following formula:

[0380]

[0381] Where Φ and c are 2d×2d matrices, they are defined as follows:

[0382]

[0383] d×d matrix Φ ± and c ± The matrix elements are given above.

[0384] Consider annihilation operators And please note that it will be a non-orthogonal normalized ground state |φ n，± The transformation is as follows:

[0385]

[0386] Here, ± parity is inverted. Parity check. Therefore, in a non-orthogonal normal basis, the matrix elements of the annihilation operator are given by the following equation:

[0387]

[0388] in It is the Pauli X operator, and It is a truncation annihilation operator of size ×d. Therefore, orthogonal normalization...

[0389] base|ψ n，± The matrix elements of the annihilation operator in > can be obtained from the above regarding O′ m，n The given transformation is obtained.

[0390] Think back, |ψ n，± > is the complementary ground state. To find the matrix elements of the operators in the ground state, the matrix can be obtained through the Hadamard operator. Conjugate. Therefore, in the orthogonal normal computational basis, the annihilation operator is given by the following equation:

[0391]

[0392] Here, the subscript SF indicates the role of the annihilation operator in the shifted Focke's algorithm. Approximate expression It can be used to analyze big cat qubits in perturbation states (where |α| 2 The Z-error rate is >>1), where the cat qubit state may sometimes be excited to the first excited-state manifold (n=1), but will quickly decay back to the ground-state manifold (n=0). Finally, note the parity operator. Due to the way the ground state is defined, in shifted Focke's... Give it precisely, for example, |ψn，+ >(|φ n，- >) has even (odd) excitation numbers with parity.

[0393] Figure 38 This illustrates the use of shifted Focke's algorithm to simulate cat qubits (where |α|) according to some implementation schemes. 2 >>1) Process flowchart.

[0394] In box 3802, the nonorthogonal normalized ground state is defined as described above. In box 3804, the ground state is orthogonally normalized to construct the 2d orthogonally normalized shifted Fock ground state as described above. In box 3806, the matrix elements of the operators in the orthogonal normalized basis are determined as described above.

[0395] The implementation scheme disclosed herein may be described in accordance with the following provisions:

[0396] Clause 1. A method for simulating Tovelimen encoded with arbitrary Calderbank-Shor-Steane codes, the method comprising:

[0397] The computational ground state is prepared in a fault-tolerant manner by applying the STOP algorithm to determine when to stop the computation of the stabilizer of the repeating code of the ground state so that the failure probability of the computational ground state is below a threshold level.

[0398] The CNOT gate is applied laterally to the prepared computational ground state to prepare the |ψ1> state;

[0399] Clifford stabilizer g for measuring the state |ψ1> A And if Clifford stable subg A If the measurement result is -1, then logical Z-correction is applied, where the Clifford stabilizer g is measured. A And based on the Clifford stabilizer g A The measurement results are applied to the preparation state using logic Z-correction |ψ out >;

[0400] Clifford stabilizer g of repeating |ψ1> state A Number of times the threshold is measured;

[0401] In response to the determination that the Clifford stabilizer gA measurement is trivial, the Toveley magical state is prepared; and

[0402] Apply a series of Clifford gates to the logic input state ||ψ> L The prepared Toveley magic state is used to simulate the logic Toveley gate, wherein Clifford error correction is applied to the output of the series of Clifford gates applied to the logic input.

[0403] Clause 2. The method as described in Clause 1, wherein applying the STOP algorithm comprises:

[0404] Track continuous corrector results;

[0405] Calculate the minimum number of faults that can cause the tracked sequence of consecutive corrector results;

[0406] The STOP algorithm stops if any of the following conditions are met:

[0407] 1) The number of consecutive repetitions of the same corrector result, where the threshold is equal to the difference between the following:

[0408] The code distance of one of the calculated ground states is reduced by one, where the result of the subtraction is divided by two; and

[0409] The minimum number currently calculated that could cause a fault in the tracked sequence of consecutive corrector results; or

[0410] 2) The currently calculated minimum number that can cause a fault in the tracked successive compensator sequence is equal to the code distance of one of the calculated ground states being prepared minus one, wherein the result of the subtraction is divided by two, and wherein another round of compensator measurements is subsequently performed; and

[0411] If condition 1 is met, the repeating corrector is used; or if condition 2 is met, a corrector for subsequent corrector measurements is used, wherein the corrector used is used to correct one of the computational ground states being prepared.

[0412] Clause 3. As described in Clause 2, wherein:

[0413] Repeat the Clifford stabilizer g for the state |ψ1>. A The measurement threshold number includes repeating the measurement so that the Clifford stabilizer g A The number of measurements is equal to (d-1) / 2, where d is the code distance of one of the ground states in the fault-tolerant calculation of a.

[0414] Clause 4. The method as described in Clause 3, wherein the Clifford stabilizer g A Error detection is performed between the corresponding measurements.

[0415] Clause 5. The method as described in any one of Clauses 1 to 4, further comprising:

[0416] The Toveley magic state is increased from a first code distance to a second code distance, wherein the stabilizer is measured using the STOP algorithm, and the minimum weighted perfect match (MWPM) is applied to the measurement corrector history generated from the process of measuring the stabilizer to correct errors.

[0417] Clause 6. A method comprising:

[0418] The results of measuring the auxiliary qubits of arbitrary Calderbank-Shor Steane codes;

[0419] Track the continuous calibration results in the measurement calibration results;

[0420] Calculate the minimum number of faults that can cause the tracked sequence of consecutive corrector results;

[0421] The measurement of the corrector result shall be stopped if any of the following conditions are met:

[0422] 1) The number of consecutive repetitions of the same corrector result, where the threshold is equal to the difference between the following:

[0423] The code distance of any Calderbank-Shor-Steane code is reduced by one, where the result of the subtraction is divided by two; and

[0424] The minimum number currently calculated that could cause a fault in the tracked sequence of consecutive corrector results; or

[0425] 2) The currently calculated minimum number that can cause a fault in the tracked consecutive compensator sequence is equal to the code distance minus one, where the result of the subtraction is divided by two, and where another round of compensator measurements is subsequently performed; and

[0426] If condition 1 is met, the repeated corrector result is used; or if condition 2 is met, the corrector result used for subsequent corrector measurements is used, wherein the corrector result used is used to correct the arbitrary Calderbank-Shor-Steane code.

[0427] Clause 7. As described in Clause 6, wherein:

[0428] The arbitrary Calderbank-Shor-Steane code is an n-qubit repeating code;

[0429] Measuring the result of the compensator includes measuring Z at the auxiliary qubit of the n-qubit repeating code. L ;and

[0430] Error correction of an arbitrary Calderbank-Shor-Steane code of n qubits also includes the measurement of Z at the auxiliary qubits based on the repeated n-qubit code. L And application X L Correction,

[0431] The error correction process is performed to prepare the ground state for implementation of the Clifford gate.

[0432] Clause 8. The method described in Clause 6 or Clause 7, further comprising:

[0433] The arbitrary Calderbank-Shor-Steane code is increased from a first code distance to a second code distance, wherein the STOP algorithm is used to measure the stabilizer and the minimum weighted perfect match (MWPM) is applied to the measurement correction history generated from the measurement stabilizer process to correct errors, wherein the STOP algorithm includes the measurement correction result, the tracking of consecutive measurement results in the measurement result, the calculation of the minimum number of faults, the stopping of measurement if condition 1 or condition 2 is met, and the error correction.

[0434] Clause 9. The method as described in Clause 8, wherein increasing the arbitrary Calderbank-Shor-Steane code from the first code distance to the second code distance comprises:

[0435] A lattice operation is performed to merge two code blocks together, wherein the measurement includes measuring the boundary operator between the two code blocks being merged.

[0436] Clause 10. The method as described in any one of Clauses 6 to 9, further comprising:

[0437] The computational ground state is prepared in a fault-tolerant manner by applying the STOP algorithm to determine when to stop the computation of the stabilizer of the repeating code of the ground state so that the failure probability of the computational ground state is below a threshold level.

[0438] in:

[0439] The computational ground state is encoded using the arbitrary Calderbank-Shor-Steane code; and

[0440] The application of the STOP algorithm includes executing the measurement correction result, tracking the continuous measurement results in the measurement result, calculating the minimum number of faults, stopping the measurement if condition 1 or condition 2 is met, and error correction.

[0441] Clause 11. The method as described in Clause 10, further comprising:

[0442] The CNOT gate is applied laterally to the prepared computational ground state to prepare the |ψ1> state;

[0443] Clifford stabilizer g for measuring the state |ψ1> A And if Clifford stable subg AIf the measurement result is -1, then logical Z-correction is applied, where the Clifford stabilizer g is measured. A And based on the Clifford stabilizer g A The measurement results are applied to the preparation state using logic Z-correction |ψ out >;

[0444] Clifford stabilizer g of repeating |ψ1> state A Number of times the threshold is measured;

[0445] In response to determining the Clifford stabilizer g A Measurement is mundane, while the preparation of Toveley's magical state is commonplace; and

[0446] A series of Clifford gates are applied to the |ψ1> state and the prepared Toveley magic state to simulate the Toveley gate, wherein Clifford error correction is applied to the output of the series of Clifford gates applied to the logic input.

[0447] Clause 12. As described in Clause 11, wherein:

[0448] Repeat the Clifford stabilizer g for the state |ψ1>. A The measurement threshold number includes repeating the measurement so that the Clifford stabilizer g A The number of measurements is equal to (d-1) / 2, where d is the code distance of one of the ground states in the fault-tolerant calculation of a.

[0449] Clause 13. The method as described in Clause 12, wherein in the Clifford stable subg A Error detection is performed between the corresponding measurements.

[0450] Clause 14. The method as described in Clause 13, further comprising:

[0451] The Toveley magic state is increased from a first code distance to a second code distance, wherein the stabilizer is measured using the STOP algorithm, and the minimum weighted perfect match (MWPM) is applied to the measurement corrector history generated from the process of measuring the stabilizer to correct errors.

[0452] Clause 15. The method of any one of Clauses 6 to 14, wherein the arbitrary Calderbank-Shor-Steane code and auxiliary qubit are implemented using a system comprising:

[0453] Mechanical linear harmonic oscillator; and

[0454] The control circuit is coupled to the mechanical linear resonator.

[0455] The control circuit is configured to stabilize an arbitrary superposition of coherent states (cat states) of the mechanical linear harmonic oscillator to store the quantum information of the Calderbank-Shor-Steane code, wherein, in order to stabilize the arbitrary cat states, the control circuit is configured as follows:

[0456] Phonons are excited in the mechanical linear harmonic oscillator by driving the corresponding storage mode of the mechanical linear harmonic oscillator; and

[0457] Phonons from the mechanical linear resonator are dissipated via an open-circuit transmission line coupled to the control circuit, the open-circuit transmission line being configured to absorb photons from the dump mode of the control circuit.

[0458] Clause 16. The method as described in Clause 15, wherein the control circuit comprises:

[0459] A superconducting quantum interference device (ATS) with asymmetric threads, wherein the superconducting quantum interference device with asymmetric threads is coupled to the mechanical linear harmonic oscillator.

[0460] Clause 17. A system comprising:

[0461] Mechanical harmonic oscillator; and

[0462] A control circuit coupled to the mechanical resonator, wherein the control circuit is configured to stabilize an arbitrary superposition of coherent states (cat states) of the mechanical resonator to store quantum information; and

[0463] One or more computing devices, the one or more computing devices storing program instructions, which, when executed, cause the control circuitry to perform the following operations:

[0464] The result of measuring the collimator of an auxiliary qubit storing one or more qubits of quantum information, wherein the auxiliary qubit and the one or more qubits storing the quantum information are implemented via one or more of the mechanical resonator;

[0465] Track the continuous calibration results in the measurement calibration results;

[0466] Calculate the minimum number of faults that can cause the tracked sequence of consecutive corrector results;

[0467] The measurement of the corrector result shall be stopped if any of the following conditions are met:

[0468] 1) The number of consecutive repetitions of the same corrector result, where the threshold is equal to the difference between the following:

[0469] The code distance of the one or more qubits storing quantum information is reduced by one, wherein the result of the subtraction is divided by two; and

[0470] The minimum number currently calculated that could cause a fault in the tracked sequence of consecutive corrector results; or

[0471] 2) The currently calculated minimum number that can cause a fault in the tracked consecutive compensator sequence is equal to the code distance minus one, where the result of the subtraction is divided by two, and where another round of compensator measurements is subsequently performed; and

[0472] If condition 1 is met, the repeating calibrator is used; or if condition 2 is met, the calibrator result used for subsequent calibrator measurements is used, wherein the calibrator result used is used to correct errors in the stored quantum information.

[0473] Clause 18. The system as described in Clause 17, wherein said one or more computing devices are further configured to perform the following:

[0474] The computational ground state is prepared in a fault-tolerant manner by applying the STOP algorithm to the fault-tolerant computational ground state to determine when the stabilizer measurement of the repeating code of the computational ground state can be stopped so that the failure probability of the computational ground state is below a threshold level.

[0475] in:

[0476] The application of the STOP algorithm includes executing the measurement correction result, tracking the continuous measurement results in the measurement result, calculating the minimum number of faults, stopping the measurement if condition 1 or condition 2 is met, and error correction.

[0477] Clause 19. The system as described in Clause 17 or Clause 18, wherein said one or more computing devices are further configured to perform the following:

[0478] The CNOT gate is applied laterally to the prepared computational ground state to prepare the |ψ1> state;

[0479] Clifford stabilizer g for measuring the state |ψ1> A And if Clifford stable subg A If the measurement result is -1, then logical Z-correction is applied, where the Clifford stabilizer g is measured. A And based on the Clifford stabilizer g A The measurement results are applied to the preparation state using logic Z-correction |ψ out >;

[0480] Clifford stabilizer g of repeating |ψ1> state A Number of times the threshold is measured;

[0481] In response to determining the Clifford stabilizer g A Measurement is mundane, while the preparation of Toveley's magical state is commonplace; and

[0482] Apply a series of Clifford gates to the logic input state |ψ> L And a prepared Toveley magic state to simulate a Toveley gate, wherein Clifford error correction is applied to the output of the series of Clifford gates applied to the logic input.

[0483] Clause 20. The system as described in Clause 19, wherein said one or more computing devices are further configured to perform the following:

[0484] The Toveley magic state is increased from a first code distance to a second code distance, wherein the stabilizer is measured using the STOP algorithm, and the minimum weighted perfect match (MWPM) is applied to the measurement corrector history generated from the process of measuring the stabilizer to correct errors.

[0485] Clause 21. A method for preparing Toveley gates for use in quantum computing, the method comprising:

[0486] Multiple Toveley magic states are prepared, wherein the computational ground state used to prepare the Toveley magic states is encoded using a repeating code;

[0487] Extracting a Toveley gate from two or more of the prepared Toveley magic states, wherein extracting the Toveley gate includes preparing a check qubit associated with the Toveley gate, wherein the check qubit indicates whether an error exists in the extracted Toveley gate; and

[0488] In response to the verification that the check qubit does not indicate an error, a logical Toveley gate operation is performed using the extracted Toveley gate.

[0489] Clause 22. The method as described in Clause 21, wherein extracting the Toveli gate from two or more of the prepared Toveli magical states comprises:

[0490] A multi-round lattice manipulation operation is performed between the qubits of a selected set of Toveley magic states from the plurality of Toveley magic states and the qubits of the extracted Toveley gate; and

[0491] Each of the multiple lattice operations described therein acts on at least one check qubit in the check qubit that is associated with the extracted Toveley gate.

[0492] Clause 23. The method as described in Clause 21 or Clause 22, wherein the extracted Tovelimen has a size less than 1x10 -6 The failure rate.

[0493] Clause 24. The method of any one of Clauses 21 to 23, wherein the extracted Tovelimen is extracted using eight of the Tovelimen states.

[0494] Clause 25. The method as described in Clause 24, wherein the error probability of the two extracted Tovelimen is less than the highest error probability of the corresponding of the eight Tovelimen states minus a power of two.

[0495] Clause 26. The method as described in Clause 21, wherein the extracted Toveli gate is extracted using two of the Toveli magic states.

[0496] Clause 27. The method as described in Clause 26, wherein when the two Toveley magic states have high biased noise, the error probability of the extracted Toveley gate is reduced by a power of two compared to the corresponding error rates of the two Toveley magic states.

[0497] Clause 28. The method as described in Clause 21, wherein the extracted Tovelimen is extracted using eight of the Tovelimen magical states, and

[0498] When the eight Toveley magic states have high biased noise, the error probability of the extracted Toveley gate is reduced by a power of three compared to the error rate of the corresponding one of the eight Toveley magic states.

[0499] Clause 29. The method of Clause 21, wherein a single-round extraction is performed to extract the Toveley magic state, and wherein the single-round extraction includes performing multiple lattice surgical operations.

[0500] Clause 30. The method of any one of Clauses 21 to 29, wherein the Toveley magic state and the extracted Toveley gate are implemented using a system comprising:

[0501] Mechanical linear harmonic oscillator; and

[0502] One or more control circuits, said one or more control circuits being coupled to the mechanical linear resonator.

[0503] The one or more control circuits are configured to stabilize the arbitrary superposition of coherent states (cat states) of the mechanical resonator to store the quantum information of the Toveley magic state and the extracted Toveley gate, wherein, in order to stabilize the arbitrary cat states, the one or more control circuits are configured to:

[0504] Phonons are excited in the mechanical resonator by driving the corresponding storage mode of the mechanical resonator; and

[0505] Phonons from the mechanical resonator are dissipated via one or more corresponding open-circuit transmission lines coupled to the one or more control circuits of the mechanical resonator, wherein the open-circuit transmission lines are configured to absorb photons from the corresponding one or more control circuits.

[0506] Clause 31. A system comprising:

[0507] Mechanical harmonic oscillator; and

[0508] One or more control circuits coupled to the mechanical resonator, wherein the one or more control circuits are configured to stabilize an arbitrary superposition of coherent states (cat states) of the mechanical resonator to store quantum information; and

[0509] One or more computing devices, the one or more computing devices storing program instructions, which, when executed, cause the one or more control circuits to perform the following operations:

[0510] Prepare multiple Toveli magical states;

[0511] Extracting a Toveley gate from two or more of the prepared Toveley magic states, wherein extracting the Toveley gate includes preparing a check qubit associated with the Toveley gate, wherein the check qubit indicates whether an error exists in the extracted Toveley gate; and

[0512] In response to the verification that the check qubit does not indicate an error, a logical Toveley gate operation is performed using the extracted Toveley gate.

[0513] Clause 32. The system as described in Clause 31, wherein the extracted Toveli gate includes two extracted Toveli gates extracted using eight of the Toveli magic states.

[0514] Clause 33. The system as described in Clause 32, wherein the error probability of the two extracted Tovelimen is less than the highest error probability of the corresponding of the eight Tovelimen states minus a power of two.

[0515] Clause 34. The system as described in Clause 31, wherein the extracted Toveli gate is extracted using two of the Toveli gate states.

[0516] Clause 35. The system as described in Clause 34, wherein when the two Toveley magic states have high biased noise, the error probability of the extracted Toveley gate is reduced by a power of two compared to the corresponding error rates of the two Toveley magic states.

[0517] Clause 36. The system as described in Clause 31, wherein the extracted Toveli gate is extracted using eight of the Toveli magic states; and

[0518] When the eight Toveley magic states have high biased noise, the error probability of the extracted Toveley gate is reduced by a power of three compared to the error rate of the corresponding one of the eight Toveley magic states.

[0519] Clause 37. The system of any one of Clauses 31 to 36, wherein the plurality of Toveley magic states used as input are stabilized using the STOP algorithm, wherein, in order to apply the STOP algorithm, the one or more computing devices are configured to perform the following operations:

[0520] Track continuous corrector results;

[0521] Calculate the minimum number of faults that can cause the tracked sequence of consecutive corrector results;

[0522] The STOP algorithm stops if any of the following conditions are met:

[0523] 1) The number of consecutive repetitions of the same corrector result, where the threshold is equal to the difference between the following:

[0524] The fault-tolerant computation involves subtracting one from the code distance of one of the ground states, where the result of the subtraction is divided by two; and...

[0525] The minimum number currently calculated that could cause a fault in the tracked sequence of consecutive corrector results; or

[0526] 2) The currently calculated minimum number that can cause a fault in the tracked consecutive compensator sequence is equal to the code distance of one of the fault-tolerant computational ground states minus one, wherein the result of the subtraction is divided by two, and wherein another round of compensator measurements is subsequently performed; and

[0527] If condition 1 is met, the repeating corrector is used; or if condition 2 is met, a corrector for subsequent corrector measurements is used, wherein the corrector used is used to correct one of the fault-tolerant computation ground states.

[0528] Clause 38. The system as described in any one of Clauses 31 to 37, wherein the corresponding component of said one or more control circuits includes:

[0529] A superconducting quantum interference device (ATS) with asymmetric threads, the ATS being coupled to a counterpart in the mechanical harmonic oscillator.

[0530] Clause 39. A method for extracting logical Toveli gates from multiple Toveli magical states, the method comprising:

[0531] A multi-round lattice surgery operation is performed between the qubits of a selected set of Toveley magic states from the plurality of Toveley magic states and the qubits of the extracted Toveley gate; and

[0532] Each of the multiple lattice operations described therein acts on at least one check qubit in the check qubit that is associated with the extracted Toveley gate.

[0533] Clause 40. As described in Clause 39, wherein

[0534] The extracted Toveli gates are extracted using eight of the Toveli magic states; and

[0535] The error probability of the extracted Toveli gate is less than the highest error probability of the corresponding one among the eight Toveli gates minus a power of two.

[0536] Clause 41. A method for simulating a cat qubit, the method comprising:

[0537] Define the ground state of the cat qubit;

[0538] The defined ground state is orthogonally normalized to construct the 2d orthogonally normalized shifted Fock ground state of the cat qubit; and

[0539] Determine the matrix elements of the operators in the orthogonally normalized shifted Fock ground state.

[0540] Clause 42. The method as described in Clause 41, wherein prior to performing the orthogonal normalization, the defined ground state is defined such that the defined ground state is grouped into even and odd branches.

[0541] Clause 43. The method as described in Clause 42, wherein in the ground state, the orthogonalized version of the defined ground state is equivalent to the complementary ground state of the cat qubit expressed as |+> or |-> rather than the computational ground state expressed as |0> or |1>.

[0542] Clause 44. The method as described in Clause 43, wherein the defined ground states in different parity sectors are orthogonal to each other, such that the orthogonal normalization is performed in the respective parity sectors.

[0543] Clause 45. The method as described in Clause 41, further comprising:

[0544] The determined matrix elements of the operator are applied to simulate the cat qubit in the 2d orthogonally normalized shifted Fock ground state.

[0545] Clause 46. The method of any one of Clauses 41 to 45, wherein the simulated cat qubit is a hybrid acoustic-electric qubit implemented using a linear mechanical harmonic oscillator.

[0546] Clause 47. The method of any one of Clauses 41 to 45, wherein the simulated cat qubit is implemented using an electromagnetic resonator.

[0547] Clause 48. One or more non-transitory computer-readable media storing program instructions that, when executed on or across one or more processors, cause the one or more processors to perform the following operations:

[0548] Define the ground state of the cat qubit to be simulated;

[0549] The defined ground state is orthogonally normalized to construct the 2d orthogonally normalized shifted Fock ground state of the cat qubit; and

[0550] Determine the matrix elements of the operators in the orthogonally normalized shifted Fock ground state.

[0551] Clause 49. One or more non-transitory computer-readable media as described in Clause 48, wherein the program instructions, when executed on or across the one or more processors, also cause the one or more processors to perform the following operations:

[0552] The determined matrix elements of the operator are applied to simulate the cat qubit in the 2d orthogonally normalized shifted Fock ground state.

[0553] Clause 50. One or more non-transitory computer-readable media as described in Clause 48, wherein, prior to performing the orthogonal normalization, the defined ground state is defined such that the defined ground state is grouped into even and odd branches.

[0554] Clause 51. One or more non-transitory computer-readable media as described in Clause 48, wherein, in the ground state, the orthogonalized version of the defined ground state is equivalent to the complementary ground state of the cat qubit expressed as |+> or |-> rather than the computational ground state expressed as |0> or |1>.

[0555] Clause 52. One or more non-transitory computer-readable media as described in Clause 48, wherein the defined ground states are orthogonal to each other, such that the orthogonal normalization is performed individually in the respective parity sector.

[0556] Clause 53. A system comprising:

[0557] A memory, which stores program instructions; and

[0558] One or more processors, wherein the program instructions, when executed on or across the one or more processors, cause the one or more processors to perform the following operations:

[0559] Define the ground state of the cat qubit to be simulated;

[0560] The defined ground state is orthogonally normalized to construct the 2d orthogonally normalized shifted Fock ground state of the cat qubit; and

[0561] Determine the matrix elements of the operators in the orthogonally normalized shifted Fock ground state.

[0562] Clause 54. The system as described in Clause 53, wherein the program instructions, when executed on or across the one or more processors, also cause the one or more processors to perform the following operations:

[0563] The determined matrix elements of the operator are applied to simulate the cat qubit in the 2d orthogonally normalized shifted Fock ground state.

[0564] Clause 55. The system as described in Clause 53, wherein, prior to performing the orthogonal normalization, the defined ground state is defined such that the defined ground state is grouped into even and odd branches.

[0565] Clause 56. The system as described in Clause 53, wherein, in the ground state, the orthogonalized version of the defined ground state is equivalent to the complementary ground state of the cat qubit expressed as |+> or |-> rather than the computational ground state expressed as |0> or |1>.

[0566] Clause 57. The system as described in Clause 53, wherein the defined ground states are orthogonal to each other, such that the orthogonal normalization is performed separately in the respective parity sector.

[0567] Clause 58. The system of any one of Clauses 53 to 57, wherein the cat qubit to be simulated is implemented using a mechanical harmonic oscillator.

[0568] Clause 59. The system of any one of Clauses 53 to 57, wherein the cat qubit to be simulated is implemented using an electromagnetic resonator.

[0569] Clause 60. The system as described in any one of Clauses 53 to 57, wherein the cat qubit to be simulated is implemented in a system comprising one or more mechanical resonators and one or more electromagnetic resonators.

[0570] Clause 61. A method for measuring an auxiliary qubit while correcting errors in stored quantum information, wherein a set of one or more error-correcting gates is applied between one or more data qubits storing the quantum information and the auxiliary qubit to entangle the auxiliary qubit with the one or more data qubits, the method comprising:

[0571] The excitation of the auxiliary qubit is transferred to another readout qubit using a SWAP gate or another sequence of one or more gates that perform the swapping function;

[0572] Perform one or more measurements on the readout qubit; and

[0573] While performing at least some of the one or more measurements on the readout qubit, another set of one or more error correction gates are applied between the one or more data qubits storing the quantum information and the auxiliary qubits.

[0574] Clause 62. The method as described in Clause 61, wherein the data qubit, the auxiliary qubit, and the readout qubit are implemented using a mechanical harmonic oscillator.

[0575] Clause 63. The method as described in Clause 62, wherein the exchange gate is mediated by a superconducting quantum interference device (ATS) with asymmetric threads.

[0576] Clause 64. The method as described in Clause 61, wherein the data qubit, the auxiliary qubit, and the readout qubit are implemented using boson modes.

[0577] Clause 65. The method as described in Clause 61, wherein the amount of time the one or more data qubits are idle during the execution of the swap gate is less than the amount of time required to perform the one or more measurements on the readout qubits.

[0578] Clause 66. The method as described in Clause 65, wherein the one or more measurements of the readout qubit:

[0579] This includes multiple repeated measurements taken after the switching gate or other gates performing the switching function; and

[0580] This process repeats until approximately when a swap gate operation is performed for the next round of error correction, wherein the swap gate operation for the next round of error correction is performed after another set of one or more error correction gates has been applied.

[0581] Clause 67. The method as described in Clause 66, wherein the repeated measurements of the readout qubit include repeated QND (quantum nondestructive) parity checks of the readout qubit.

[0582] Clause 68. The method as described in Clause 65, wherein the readout qubit is a higher-order mode of the auxiliary oscillator of the auxiliary qubit.

[0583] Clause 69. The method as described in Clause 68, wherein the auxiliary oscillator is a λ / 2 oscillator, and wherein the mode of the readout qubit is twice the fundamental mode of the auxiliary oscillator.

[0584] Clause 70. A method for measuring boson qubits, wherein the measurement result is affected by a single-photon loss event, said method comprising:

[0585] Compressing the boson qubit before performing a readout, such that phonons or photons dissipate from the boson qubit while preserving the measurement observability of the boson qubit; and

[0586] Following the compression, the observable measurement of the compressed boson qubit is read out.

[0587] Clause 71. The method as described in Clause 70, wherein compressing the boson qubit comprises:

[0588] The dissipative subparameter is changed such that the average number of photons or average number of phonons (α) of the boson qubit changes from α... initial The value decreases to α final Value, where |α final |<|α initial |

[0589] Clause 72. As described in Clause 70, wherein:

[0590] Compressing the boson qubit involves altering the steady state of the two-photon dissipation process of the boson qubit; and

[0591] The measurement observability readout of the compressed boson qubit includes performing parity check readout on the compressed boson qubit.

[0592] Clause 73. The method of any one of Clauses 70 to 72, wherein the boson qubit is implemented using a system comprising:

[0593] Mechanical harmonic oscillator; and

[0594] The control circuit is coupled to the mechanical resonator.

[0595] The control circuit is configured to stabilize the arbitrary superposition of coherent states (cat states) of the mechanical resonator to store quantum information, wherein, in order to stabilize the arbitrary cat states, the control circuit is configured as follows:

[0596] Phonons are excited in the mechanical resonator by driving the corresponding storage mode of the mechanical resonator; and

[0597] Phonons are dissipated via an open transmission line coupled to the control circuit, the open transmission line being configured to absorb photons from the dump mode of the control circuit.

[0598] Clause 74. The method as described in Clause 73, wherein the control circuit comprises:

[0599] A superconducting quantum interference device (ATS) with asymmetric threads, wherein the ATS is coupled to the mechanical resonator, and

[0600] Compression of the boson qubits includes altering the steady state of two-photon dissipation controlled by the ATS.

[0601] Clause 75. A method for performing a measurement on a first mode (a) representing quantum information stored in a cat qubit, the method comprising:

[0602] Compress the cat qubit so that an even number of phonons or photons dissipate from the cat qubit;

[0603] The cat qubit is evolved under a Hamiltonian that couples multiple excitations of the cat qubit to a change in the measurable properties of another mode (b); and

[0604] Measure the other mode (b).

[0605] Clause 76. As described in Clause 75, wherein:

[0606] The measurement is to determine the parity of the cat qubit;

[0607] Compressing the cat qubit includes compressing the cat qubit such that the average number of photons or the average number of phonons (α) of the cat qubit is reduced to zero, wherein even-numbered cat states are mapped to |0> and odd-numbered cat states are mapped to |1>;

[0608] The Hamiltonian is selected from a three-wave or higher-wave mixed Hamiltonian that correlates the phonon number or photon number with the variation of the other mode (b); and

[0609] The other mode (b) is measured using null, heterodyne, or optical detection.

[0610] Clause 77. The method as described in Clause 75, wherein the Hamiltonian selected from the three-wave or higher mixed Hamiltonian includes

[0611] Clause 78. The method as described in Clause 75, wherein the Hamiltonian selected from the three-wave or higher mixed Hamiltonian includes

[0612] Clause 79. The method as described in Clause 75, wherein the Hamiltonian selected from the three-wave or higher mixed Hamiltonian includes The product of the terms that affect the other mode (b) in a measurable manner.

[0613] Clause 80. As described in Clause 75, wherein:

[0614] The cat qubit is realized via a mechanical harmonic oscillator;

[0615] The other mode (b) is the dump mode; and

[0616] The Hamiltonian is selected from the three-wave or higher-wave mixed Hamiltonian that relates the average phonon number or the average photon number to the variation of the other mode (b), wherein the three-wave mixing is mediated by ATS.

[0617] Clause 81. A method for performing a measurement on quantum information in a cat qubit, the method comprising:

[0618] Evolving under a Hamiltonian that couples the phase of the cat qubit's α ("a" mode) to a measurable property of another boson mode ("b" mode), wherein the Hamiltonian is implemented via a three-wave or higher hybrid Hamiltonian; and

[0619] Perform zero-difference, heterodyne, or optical detection on the "b" mode to determine the state of the "a" mode.

[0620] The cat qubits mentioned therein are implemented using a system that includes the following:

[0621] Mechanical harmonic oscillator; and

[0622] The system includes a control circuit for a superconducting quantum interference device (ATS) with asymmetric threads, which is coupled to the mechanical resonator.

[0623] The control circuit is configured to stabilize the arbitrary superposition of coherent states (cat states) of the mechanical resonator to store quantum information, wherein, in order to stabilize the arbitrary cat states, the control circuit is configured as follows:

[0624] Phonons are excited in the mechanical resonator by driving the corresponding storage mode of the mechanical resonator; and

[0625] Phonons are dissipated via an open transmission line coupled to the control circuit, the open transmission line being configured to absorb photons from the dump mode of the control circuit.

[0626] Clause 82. The method as described in Clause 81, wherein:

[0627] The Hamiltonian source is a free ATS-mediated three-wave hybrid Hamiltonian;

[0628] The "a" mode is implemented via a mechanically stored resonator; and

[0629] The “b” mode is achieved via an electromagnetic resonator.

[0630] Clause 83. The method as described in Clause 82, wherein the Hamiltonian used for reading includes:

[0631]

[0632] or

[0633]

[0634] Clause 84 A system comprising:

[0635] Mechanical linear harmonic oscillator; and

[0636] The control circuit is coupled to the mechanical linear resonator.

[0637] The control circuit is configured to stabilize the arbitrary superposition of coherent states (cat states) of the mechanical linear harmonic oscillator to store quantum information, wherein, in order to stabilize the arbitrary cat states, the control circuit is configured as follows:

[0638] Phonons are excited in the mechanical linear harmonic oscillator by driving its stored mode; and

[0639] Phonons from the mechanical linear resonator are dissipated via an open-circuit transmission line coupled to the control circuit, the open-circuit transmission line being configured to absorb photons from the dump mode of the control circuit.

[0640] Clause 85. The system as described in Clause 84, wherein the control circuitry comprises:

[0641] A superconducting quantum interference device (ATS) with asymmetric threads, wherein the superconducting quantum interference device with asymmetric threads is coupled to the mechanical harmonic oscillator.

[0642] Clause 86. The system as described in Clause 85, further comprising:

[0643] One or more additional mechanical linear resonators are coupled to the control circuit, wherein the control circuit is configured to stabilize the mechanical linear resonator and the corresponding cat states of the one or more additional mechanical linear resonators via a single ATS and a single open transmission line.

[0644] Clause 87. The system as described in Clause 86, wherein the storage mode of the corresponding mechanical linear harmonic oscillator is detuned such that phonons supplied to the corresponding mechanical linear harmonic oscillator are supplied in an incoherent manner.

[0645] Clause 88. The system as described in Clause 87, wherein the pump of the respective mechanical linear resonator is spaced at a frequency bandwidth greater than the two-phonon dissipation rate of the respective mechanical linear resonator.

[0646] Clause 89. The system as described in Clause 88, wherein the control circuitry further comprises:

[0647] One or more microwave filters are configured to filter out a correlated attenuation term, which, if not filtered out, causes the storage modes of two or more mechanical linear harmonic oscillators in the mechanical linear harmonic oscillator to flip simultaneously.

[0648] Clause 90. The system as described in any one of Clauses 85 to 89, wherein said control circuitry further comprises:

[0649] A high-impedance inductor, which serves as part of the ATS coupled to the mechanical linear resonator.

[0650] Clause 91. The system as described in Clause 90, wherein the high-impedance inductor comprises:

[0651] Planar zigzag or double-helix inductors;

[0652] A spiral inductor with one or more air bridges;

[0653] Josephson array; or

[0654] Thin-film superconductors with high dynamic inductance.

[0655] Clause 92. The system of any one of Clauses 85 to 91, wherein at least some of the mechanical linear resonators comprise three or more terminals, the system further comprising:

[0656] Two or more additional superconducting quantum interference devices (ATS) with asymmetric threads,

[0657] This includes a given mechanical linear resonator with three or more terminals coupled to three or more ATSs via corresponding three or more terminals.

[0658] Clause 93. A method for stabilizing the superposition of coherent states (cat states) of a mechanical harmonic oscillator, the method comprising:

[0659] Phonons are excited in the mechanical resonator by driving its stored mode; and

[0660] Phonons from the mechanical resonator are dissipated via an open transmission line coupled to the control circuit, the open transmission line being configured to absorb photons from the dump mode of the control circuit.

[0661] Clause 94. The method as described in Clause 93, wherein the phonon is excited in the mechanical harmonic oscillator and dissipates from the mechanical harmonic oscillator in the form of a pair of two phonons.

[0662] Clause 95. The method of Clause 94, wherein the excitation and dissipation of the phonon pair are induced by a nonlinear interaction between the storage mode of the mechanical resonator and the dump mode of the control circuit, wherein the square of the storage mode of the mechanical resonator is coupled to the dump mode of the control circuit via a two-phonon coupling ratio (g2), and wherein the attenuation rate of the phonons absorbed via the open transmission line is approximately ten times or greater than the coupling ratio (g2).

[0663] Clause 96. The method of Clause 94, wherein the control circuitry includes a superconducting quantum interference device (ATS) with asymmetric threads coupled to the mechanical resonator, wherein the ATS is configured to excite a pair of two phonons in the mechanical resonator.

[0664] Clause 97. The method as described in Clause 96, further comprising:

[0665] Phonons are excited in one or more additional mechanical resonators by driving the corresponding storage modes of one or more additional mechanical resonators; and

[0666] Phonons from the one or more additional mechanical resonators are dissipated via the open-circuit transmission line, which is configured to absorb photons from the dump mode of the control circuit.

[0667] The use of a single ATS causes the phonon to be excited in the mechanical resonator and the one or more additional mechanical resonators.

[0668] Clause 98. The method as described in Clause 97, wherein the storage mode of the corresponding mechanical resonator is detuned.

[0669] Clause 99. The method as described in Clause 98, wherein the storage modes of the respective mechanical resonators are spaced apart by a frequency bandwidth greater than the two-phonon dissipation rate of the dump mode of the control circuit.

[0670] Clause 100. The method described in Clause 99, further comprising:

[0671] The relevant attenuation terms of the storage modes of two or more mechanical resonators are filtered out via one or more microwave filters.

[0672] Clause 101. A method for stably storing the coherent superposition (cat state) of multiple harmonic oscillators of quantum information, the method comprising:

[0673] A single superconducting quantum interference device (ATS) with an asymmetric thread enables the excitation of pairs of phonons or pairs of photons in corresponding harmonic oscillators by driving corresponding storage modes of corresponding harmonic oscillators; and

[0674] Two photons in pairs are dissipated from a dump mode comprising the control circuitry of the ATS, wherein the control circuitry is coupled to a corresponding resonator, and wherein an open transmission line is coupled to the dump mode of the control circuitry.

[0675] Clause 102. The method as described in Clause 101, wherein the resonator is a mechanical resonator.

[0676] Clause 103. The method as described in Clause 101, wherein the resonator is an electromagnetic resonator.

[0677] Clause 104. A method comprising:

[0678] A multi-qubit gate is implemented between a control qubit and a target qubit in a system including a harmonic oscillator and a superconducting quantum interference device (ATS) with asymmetric threads, wherein implementing the multi-qubit gate includes:

[0679] Achieve linear actuation of the phonon mode of the cat qubit of the gate, wherein the cat qubit is realized via a harmonic oscillator of the system;

[0680] Coordinated Hamiltonian interactions, wherein the Hamiltonian interactions include a compensating Hamiltonian for a multi-qubit gate, and wherein the compensating Hamiltonian includes a frequency shift of a target mode and a control mode at a driven mechanical resonator, wherein the control mode and the target mode are coupled via optomechanical coupling.

[0681] Clause 105. The method as described in Clause 104, wherein the arrangement of the multi-qubit gate comprises a plurality of resonators coupled to the ATS, wherein the ATS is shared by the plurality of resonators in the resonator.

[0682] Clause 106. The method as described in Clause 104, wherein the optomechanical coupling is achieved by non-resonantly driving the resonator and the ATS.

[0683] Clause 107. The method as described in Clause 106, wherein the non-resonant driving of the resonator and the ATS avoids frequency conflict.

[0684] Clause 108. The method as described in Clause 104, wherein the multi-qubit gate is a CNOT gate.

[0685] Clause 109. The method as described in Clause 104, wherein the multi-qubit gate is a Toveley gate.

[0686] Clause 110. The method as described in Clause 104, wherein the resonator is a mechanical resonator.

[0687] Clause 111. The method as described in Clause 104, wherein the resonator is an electromagnetic resonator.

[0688] Explanatory computer system

[0689] Figure 39 This is a block diagram illustrating an exemplary computing device that can be used in at least some of the embodiments.

[0690] Figure 39 A general-purpose computing device 3900 that can be used in any of the embodiments described herein is illustrated. In the illustrated embodiment, the computing device 3900 includes one or more processors 3910, which are coupled to system memory 3920 (which may include non-volatile and volatile memory modules) via an input / output (I / O) interface 3930. The computing device 3900 also includes a network interface 3940 coupled to the I / O interface 3930.

[0691] In various implementations, computing device 3900 may be a single-processor system including one processor 3910, or a multiprocessor system including several processors 3910 (e.g., two, four, eight, or another suitable number). Processor 3910 may be any suitable processor capable of executing instructions. For example, in various implementations, processor 3910 may be a general-purpose or embedded processor implementing any of a variety of instruction set architectures (ISAs) (e.g., x86, PowerPC, SPARC, or MIPS ISA or any other suitable ISA). In a multiprocessor system, each processor 3910 may typically, but not necessarily, implement the same ISA. In some implementations, a graphics processing unit (GPU) may be used in place of or to supplement a conventional processor.

[0692] System memory 3920 can be configured to store instructions and data accessible by one or more processors 3910. In at least some embodiments, system memory 3920 may include volatile and non-volatile portions; in other embodiments, only volatile memory may be used. In various embodiments, the volatile portion of system memory 3920 may be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM, or any other type of memory. For the non-volatile portion of system memory (e.g., which may include one or more NVDIMMs), in some embodiments, flash-based memory devices, including NAND flash memory devices, may be used. In at least some embodiments, the non-volatile portion of system memory may include a power source, such as a supercapacitor or other power storage device (e.g., a battery). In various embodiments, any of memristor-based resistive random access memory (ReRAM), 3D NAND technology, ferroelectric RAM, magnetoresistive RAM (MRAM), or various types of phase-change memory (PCM) may be used at least for the non-volatile portion of system memory. In the illustrated embodiment, program instructions and data (such as the methods, techniques and data described above) that implement one or more desired functions are shown stored in system memory 3920 as code 3925 and data 3926.

[0693] In some embodiments, I / O interface 3930 may be configured to coordinate I / O traffic between processor 3910, system memory 3920, and any peripheral devices, including network interface 3940 or other peripheral interfaces such as various types of persistent and / or volatile storage devices. In some embodiments, I / O interface 3930 may perform any necessary protocols, timing, or other data transformations to convert data signals from one component (e.g., system memory 3920) into a format suitable for use by another component (e.g., processor 3910). In some embodiments, I / O interface 3930 may include support for devices attached via various types of peripheral buses (e.g., variants of the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard). In some embodiments, the functionality of I / O interface 3930 may be split into two or more separate components, such as a northbridge and a southbridge. Furthermore, in some embodiments, some or all of the functionality of I / O interface 3930 (e.g., the interface to system memory 3920) may be directly incorporated into processor 3910.

[0694] Network interface 3940 can be configured to allow data exchange between computing device 3900 and other devices 3960 (e.g., other computer systems or devices) attached to one or more networks 3950. In various embodiments, network interface 3940 can support communication via any suitable wired or wireless general-purpose data network (e.g., various types of Ethernet). Additionally, network interface 3940 can support communication via telecommunications / telephone networks (e.g., analog voice networks or digital fiber optic communication networks), via storage area networks (e.g., Fibre Channel SAN), or via any other suitable type of network and / or protocol.

[0695] In some embodiments, system memory 3920 may represent an embodiment of a computer-accessible medium configured to store information for implementation in Figures 1 to 1992. Figure 38The methods and apparatus discussed in the context of this document include at least a subset of program instructions and data. However, in other embodiments, program instructions and / or data may be received, transmitted, or stored on different types of computer-accessible media. Generally, computer-accessible media may include non-transitory storage media or memory media, such as magnetic or optical media, such as a disk or DVD / CD coupled to computing device 3900 via I / O interface 3930. Non-transitory computer-accessible storage media may also include any volatile or non-volatile media, such as RAM (e.g., SDRAM, DDR SDRAM, RDRAM, SRAM, etc.), ROM, etc., which may be included as system memory 3920 or another type of memory in some embodiments of computing device 3900. In some embodiments, multiple non-transitory computer-readable storage media may jointly store program instructions that implement at least a subset of the methods and techniques described above when executed on or across one or more processors. Computer-accessible media may also include transmission media or signals transmitted via communication media (e.g., networks and / or wireless links, such as those implemented via network interface 3940), such as electrical signals, electromagnetic signals, or digital signals. Multiple computing devices (e.g.) Figure 39 Part or all of the functions (shown in the diagram) can be used to implement the functions described in various embodiments; for example, software components running on various different devices and servers can cooperate with each other to provide the functions. In some embodiments, in addition to using a general-purpose computer system to implement or instead of using a general-purpose computer system, storage devices, network devices, or dedicated computer systems may be used to implement some of the described functions. As used herein, the term "computing device" refers to at least all of these types of devices, but is not limited to these types of devices.

[0696] in conclusion

[0697] Various implementations may also include receiving, transmitting, or storing instructions and / or data implemented as described above on a computer-accessible medium. Generally, a computer-accessible medium may include: storage media or memory media such as magnetic or optical media, such as magnetic disks or DVD / CD-ROMs; volatile or non-volatile media such as RAM (e.g., SDRAM, DDR, RDRAM, SRAM, etc.), ROM; and transmission media or signals (e.g., electrical signals, electromagnetic signals, or digital signals) that are transmitted via communication media such as networks and / or wireless links.

[0698] The various methods shown in the figures and described herein represent exemplary implementations of the methods. The methods can be implemented using software, hardware, or a combination thereof. The order of the methods can be varied, and various elements can be added, rearranged, combined, omitted, modified, etc.

[0699] Those skilled in the art who have read this disclosure will readily recognize that various modifications and changes may be made. It is intended to cover all such modifications and changes, and therefore the above description is to be regarded as illustrative rather than limiting.

Claims

1. A system comprising: Mechanical linear harmonic oscillator; as well as The control circuit is coupled to the mechanical linear resonator. The control circuit is configured to stabilize the arbitrary superposition of coherent states of the mechanical linear harmonic oscillator to store quantum information, wherein, in order to stabilize the arbitrary superposition of coherent states, the control circuit is configured as follows: Phonons are excited in the mechanical linear harmonic oscillator by driving the storage mode of the mechanical linear harmonic oscillator; as well as Phonons from the mechanical linear resonator are dissipated via an open-circuit transmission line coupled to the control circuit, the open-circuit transmission line being configured to absorb photons from the dump mode of the control circuit. The phonons are excited in the mechanical linear harmonic oscillator and dissipated from the mechanical linear harmonic oscillator in the form of a pair of two phonons.

2. The system of claim 1, wherein the control circuit comprises: A superconducting quantum interference device (ATS) with asymmetric threads coupled to the mechanical linear harmonic oscillator.

3. The system of claim 2, further comprising: One or more additional mechanical linear resonators are coupled to the control circuit, wherein the control circuit is configured to stabilize the superposition of the corresponding coherent states of the mechanical linear resonator and the one or more additional mechanical linear resonators via a single ATS and a single open transmission line.

4. The system of claim 3, wherein the storage mode of the corresponding mechanical linear resonator is detuned such that the phonons supplied to the corresponding mechanical linear resonator are supplied in an incoherent manner.

5. The system of claim 4, wherein the pump of the corresponding mechanical linear resonator is spaced at a frequency bandwidth greater than the two-phonon dissipation rate of the corresponding mechanical linear resonator.

6. The system of claim 5, wherein the control circuit further comprises: One or more microwave filters are configured to filter out a correlated attenuation term, which, if not filtered out, causes the storage modes of two or more mechanical linear harmonic oscillators in the mechanical linear harmonic oscillator to flip simultaneously.

7. The system of any one of claims 2 to 6, wherein the control circuit further comprises: A high-impedance inductor, which serves as part of the ATS coupled to the mechanical linear resonator.

8. The system of claim 7, wherein the high-impedance inductor comprises: Planar zigzag or double-helix inductors; A spiral inductor with one or more air bridges; Josephson array; or Thin-film superconductors with high dynamic inductance.

9. The system of any one of claims 2 to 6, wherein at least some of the mechanical linear resonators comprise three or more terminals, and the system further comprises: Two or more additional superconducting quantum interference devices (ATS) with asymmetric threads, This includes a given mechanical linear resonator with three or more terminals coupled to three or more ATSs via corresponding three or more terminals.

10. A method for superimposing coherent states of a stable mechanical harmonic oscillator, the method comprising: Phonons are excited in the mechanical harmonic oscillator by driving its storage mode; as well as Phonons from the mechanical resonator are dissipated via an open-circuit transmission line coupled to the control circuit, the open-circuit transmission line being configured to absorb photons from the dump mode of the control circuit. The phonons are excited in the mechanical harmonic oscillator and dissipated from the mechanical harmonic oscillator in the form of a pair of two phonons.

11. The method of claim 10, wherein the excitation and dissipation of the phonon pair are induced by a nonlinear interaction between the storage mode of the mechanical resonator and the dump mode of the control circuit, wherein the square of the storage mode of the mechanical resonator is coupled to the dump mode of the control circuit via a two-phonon coupling rate g2, and wherein the attenuation rate of photons absorbed via the open transmission line is ten times or greater than the coupling rate g2.

12. The method of claim 10 or claim 11, wherein the control circuitry comprises a superconducting quantum interference device (ATS) with asymmetric threads coupled to the mechanical resonator, wherein the ATS is configured such that a pair of two phonons is excited in the mechanical resonator.

13. The method of claim 12, further comprising: Phonons are excited in one or more additional mechanical resonators by driving the corresponding storage modes of the additional mechanical resonators; and Phonons from the one or more additional mechanical resonators are dissipated via the open-circuit transmission line, which is configured to absorb photons from the dump mode of the control circuit. The use of a single ATS causes the phonon to be excited in the mechanical resonator and the one or more additional mechanical resonators.

14. The method of claim 13, wherein the storage mode of the corresponding mechanical resonator is detuned.

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