Fault-tolerant T-gate via quasi-probabilistic decomposition

Abstract

Using a quasi-probabilistic decomposition approach, a technique combining quantum error correction and quantum error mitigation is used to simulate fault-tolerant T-gates with low sampling overhead. In some embodiments, the T-gate can be simulated using two logic bits and magic state preparation that reduces the need for magic state extraction and thus has low sampling overhead. Alternatively, the T-gate can be simulated based on code deformation performed on the surface code. Quasi-probabilistic decomposition is used to remove noise from the T-gate based on learned logical error rates.

Description

Technical Field

[0001] The subject disclosure relates to quantum computing and, more particularly, to techniques for facilitating error mitigation in quantum computing devices. Summary of the Invention

[0002] The following summary is provided to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements, or to delineate any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, devices, computer-implemented methods, and / or computer program products are described that facilitate error mitigation for quantum computing devices.

[0003] According to an embodiment, a system may include: a simulation component that simulates a coded T-gate using logical qubits encoded into an error correction code and at least one of a magic state or a code variation of a surface code; and a correction component that corrects noise on the coded T-gate using a quasi-probabilistic decomposition.

[0004] According to another embodiment, a computer-implemented method may include: simulating, by a system, a coded T-gate using logical qubits encoded into an error-correcting code and at least one of a magic state or a code deformation of a surface code; and correcting, by the system, noise on the coded T-gate using a quasi-probabilistic decomposition.

[0005] According to another embodiment, a computer program product may include a computer-readable storage medium having program instructions executable by a processor to cause the processor to simulate a coded T-gate using logical qubits encoded into an error-correcting code and at least one of a magic state or a code variation of a surface code; and to correct noise on the coded T-gate using a quasi-probabilistic decomposition. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An exemplary non-limiting implementation of a T-gate using a magic state and only Clifford operations is shown.

[0007] Figure 2 A block diagram of an exemplary, non-limiting system in which a fault-tolerant T-gate may be constructed is shown.

[0008] Figure 3 is a representation of a noisy T-gate, which can be considered equivalent to an ideal T-gate with noise N present across it.

[0009] Figure 4 is a representation of an example non-limiting circuit illustrating a quasi-probabilistic decomposition approach.

[0010] Figure 5a For ε i =ε1=0 and ε2=ε, a graph showing the sampling overhead γ of the surface coding T-gate simulation method as a function of the physical error rate ε.

[0011] Figure 5b For ε i =ε1=ε2 / 10 and ε2=ε, a graph of the sampling overhead γ of the surface coding T-gate simulation method as a function of the physical error rate ε.

[0012] Figure 6 The implementation of fault-tolerant T-gates through code deformation is shown.

[0013] Figure 7 is a representation of an example 5x5 surface encoding.

[0014] Figure 8 An exemplary, non-limiting sequence for implementing fault-tolerant T-gates using code deformation is shown.

[0015] Figure 9 A flow chart illustrating an exemplary, non-limiting computer-implemented method by which a fault-tolerant T-gate may be created.

[0016] Figure 10 A block diagram illustrating an example, non-limiting operating environment in which one or more embodiments described herein may be facilitated is shown.

[0017] Figure 11 A cloud computing environment is depicted according to one or more embodiments described herein.

[0018] Figure 12 Depicted are abstract model layers according to one or more embodiments described herein. DETAILED DESCRIPTION

[0019] The following detailed description is illustrative only and is not intended to limit the embodiments and / or the application or uses of the embodiments. In addition, it is not intended to be bound by any express or implied information presented in the previous background or summary or detailed description.

[0020] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to represent like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that in various cases, one or more embodiments described may be practiced without these specific details.

[0021] Conventional computers operate on binary digits (or bits), which store or represent information as binary states to perform computations and information processing functions. In contrast, quantum computing devices operate on quantum bits (or qubits), which store or represent information as both a binary state and a superposition of binary states. To do this, quantum computing devices exploit quantum mechanical phenomena such as entanglement and interference.

[0022] Quantum computing uses qubits as its basic unit, rather than classical computing bits. Qubits (e.g., quantum binary digits) are the quantum mechanical analog of classical bits. While classical bits can be used in only one of two basis states (e.g., 0 or 1), qubits can be used in a superposition of these basis states (e.g., α|0>+β|1>, where α and β are complex scalars such that |α| 2 +|β| 2 =1), allowing multiple qubits to theoretically hold exponentially more information than the same number of classical bits. Therefore, in theory, a quantum computer (e.g., a computer that employs qubits instead of or in addition to classical bits) can rapidly solve problems that would be extremely difficult for a classical computer. Since a classical computer's bits are simply binary digits with values ​​of either 0 or 1, nearly any device with two distinct states can be used to represent a classical bit; for example, a switch, valve, magnet, coin, or other such two-state device. Part of the quantum mystery is that a qubit can occupy a superposition of the 0 and 1 states. This is different from having an intermediate value between 0 and 1. When the state of a qubit is measured, the result is either 0 or 1. However, during a calculation, the qubit can behave as if it represents a mixture of the two states; for example, 63% 0 and 37% 1.

[0023] A general quantum program reconciles the quantum and classical parts of computation. When considering a general quantum program, it is helpful to identify the processes and abstractions involved in specifying a quantum algorithm, transforming the algorithm into an executable form, running experiments or simulations, and analyzing the results. These processes rely on an intermediate representation of the computation. An intermediate representation (IR) is neither its source language description nor the target machine instructions, but something in between. Compilers can use several IRs during the process of translating and optimizing programs. The input to these compilers is source code describing the quantum algorithm and compile-time parameters, and the output is a combined quantum / classical program expressed using a high-level IR. In contrast to classical computers, quantum computers are probabilistic, so measurements of the algorithm's output provide an appropriate solution within an algorithm-specific confidence interval. The computation is then repeated until a satisfactory certainty of possible solutions can be achieved.

[0024] Quantum computers are capable of performing tasks much faster than classical computing devices. However, due to the fragile nature of quantum information, quantum computers will be inherently noisy. The theory of quantum error correction and fault-tolerant quantum computing suggests how complex calculations can be performed reliably even with error-prone devices. The threshold theorem ensures that the noise level of a given physical gate is below a certain constant threshold greater than zero. Arbitrarily long computations are then possible at arbitrarily low error rates. The cost of implementing a fault-tolerant circuit for a given circuit is a polylogarithmic space overhead. More precisely, to guarantee the final failure probability δ for a circuit C with |C| locations, O(log log(|C| / δ)) levels of encoding may be required, which leads to Currently, this overhead hinders fault-tolerant quantum computing.

[0025] For gates that can be implemented transversely, the fault-tolerance overhead is relatively small, since these gates are, by definition, fault-tolerant, as they do not propagate substantial errors. However, the Eastin-Knill theorem shows that no quantum error-correcting code can implement a universal set of gates transversely. Furthermore, it is known that Clifford gates are transverse to (self-bi)CSS codes, such as surface codes. To obtain a universal gate set, Clifford gates must be combined with additional gates, such as T-gates (non-Clifford gates), which, according to Eastin-Knill, cannot implement CSS codes transversely.

[0026] Implementing fault-tolerant T-gates with minimal overhead is a nontrivial task. According to one approach, a technique called magic state distillation can be used to prepare a magic state with low noise in a fault-tolerant manner, which can then be converted into a T-gate using a Clifford circuit. Figure 1 An exemplary implementation of a T-gate 102 using a magic state and Clifford operations only is shown. This approach can reduce the problem of implementing a fault-tolerant T-gate (i.e., a T-gate that can reliably perform computations even on faulty devices) to the task of preparing a fault-tolerant magic state. The latter task can be achieved through magic state extraction, whereby several noisy magic states are converted into fewer, higher-fidelity magic states. However, while magic state extraction is a clever approach for achieving universal fault-tolerant quantum computation, the magic state extraction process for obtaining low-noise magic states can incur considerable overhead in practice.

[0027] To address these and other issues, one or more embodiments described herein relate to systems and methods for constructing fault-tolerant T-gates based on quasi-probabilistic decomposition (QPD) methods in a manner that reduces sampling overhead relative to current methods. These systems and methods can implement a combination of quantum error correction (QEC) and quantum error mitigation (QEM)—e.g., QPD methods—to simulate fault-tolerant T-gates. In some embodiments, the T-gate can be simulated using two logical bits and magic state preparation that avoids magic state extraction and thus has low sampling overhead. Alternatively, the T-gate can be simulated based on code deformation performed on a surface code. The latter method has slightly greater sampling overhead relative to the magic state method, but only utilizes a single logical qubit.

[0028] Using a quasi-probabilistic decomposition, fault-tolerant T-gates can be simulated using a rotation-based tomography step, where the sampling overhead roughly scales as (1+ε)t, where t is the number of T-gates and ε is the physical error rate.

[0029] Figure 2 A block diagram of an example non-limiting system 200 in which a fault-tolerant T-gate can be constructed according to one or more embodiments described herein is shown. The system 202 includes a memory 220 for storing computer-executable components and one or more processors 218 (e.g., one or more classical processors) operatively coupled to the memory 220 via one or more communication buses 216 for executing the computer-executable components stored in the memory 220. Figure 2 As shown, the computer-executable components include a simulation component 204 and a correction component 206 .

[0030] The simulation component 204 can simulate a quantum T-gate using at least one of a magic state or a code variation of a surface code. The correction component 206 can correct for noise on the quantum T-gate using a quasi-explorable decomposition. In general, the techniques implemented by embodiments of the system 202 can simulate fault-tolerant T-gates with relatively low sampling overhead, in part by eliminating the need to perform magic state extraction, because these techniques can produce fault-tolerant T-gates even when using a noisy magic state.

[0031] As mentioned above, sensitivity to noise and errors may prevent today's quantum computers from outperforming classical computers in performing computational tasks. Fault tolerance (FT) through quantum error correction (QEC) may provide a long-term solution for mitigating this noise and error sensitivity. However, FT to QEC typically consumes significant computational resources that are beyond the reach of today's quantum computers.

[0032] Quantum error mitigation (QEM) may provide an intermediate solution for mitigating noise and error sensitivity on near-term quantum computers without the promise of full FT. Quasi-probabilistic decomposition (QPD) is one such QEM technique.

[0033] The QPD method can realize linear operators such as More precisely, quasi-probabilistic methods give access to a random state that can be sampled independently in each run of the experiment, rather than to a quantum state. itself (where ρ in is the initial state of the N qubits). This random state behaves the same as the result of any measurement. Same expected value. However, this comes at a cost in the form of sampling overhead or C factor, which is described in terms of the number of additional triggers that must be performed.

[0034] According to the Gottesman-Knill theorem, any quantum circuit using only Clifford gates can be efficiently simulated on a classical computer. To fully exploit the power of quantum computing, quantum computers need to be able to implement a universal set of gates, including non-Clifford gates. However, implementing non-Clifford gates in a fault-tolerant manner is cost-intensive because non-Clifford gates cannot be implemented laterally. In some quantum circuits that include non-Clifford gates, 90%-99% of the available computing resources are dedicated to the task of achieving fault tolerance (for example, using magic state extraction).

[0035] According to the first step of the method applied by the system 202, a T-gate is implemented (e.g., by analog component 204). In one or more embodiments, the T-gate can be implemented by a Clifford circuit and the presence of a magic state given by

[0036]

[0037] like Figure 1 As shown. Since the techniques implemented by system 202 are capable of producing fault-tolerant T-gates even given noisy T-gates, the magic state itself can be noisy and can be prepared without magic state extraction. In this example, a noisy magic state represented by |π / 4> is prepared, and thereby the T-gate 102 is implemented laterally using Clifford gates; namely, a controlled NOT (CNOT) gate 108 and a controlled phase gate 110 (an S-gate in the example shown). In the example shown, a qubit 104 having a value ψ is provided to the CNOT gate 108, while a magic state qubit 106 is provided to the controlled phase gate 110. The analog component 204 can perform a measurement operation 112 on the output of the CNOT gate 108 and provide the measurement result to the controlled phase gate 110. The output 114 of the controlled phase gate 110 - represented by T|ψ> - serves as the output of the T-gate.

[0038] Some noise state preparation circuits can be designed to prepare the noise magic state ρ given by

[0039] ρ≈|π / 4><π / 4| (2)

[0040] Logic error rate

[0041]

[0042] is an upper bound bounded by a constant that is independent of the code distance. In this case, can be of the same order as the physical error rate. For example, assuming that ε1 and ε2 represent the error probabilities of one- and two-qubit gates, and ε1 represents the initialization error, for the surface code and depolarization error models, it can be shown that

[0043]

[0044] in is the Bachmann-Landau symbol.

[0045] For simplicity, it is assumed that the chosen code enables noiseless implementation of logic gates S = diag(1, i), X, CNOT, preparation of logical |0> and |+> states, and measurement of logical qubits in the basis Z and X. The state p can be rotated using the following series of Clifford gates A:

[0046] A:=e -iπ / 4 SX=|π / 4><π / 4|-|O> <O|, (5)

[0047] Among them, |0>:=Z|π / 4> is a state orthogonal to |π / 4>. Therefore, the rotation state becomes

[0048]

[0049] The second equation comes from the equation

[0050] A|π / 4> <O|A+|π / 4><O|=0 (7)

[0051] Therefore, the analog component 204 can prepare the rotation state τ by first preparing ρ and then applying the logic A gate with probability 1 / 2. Since |0>=Z|π / 4>, the handedness state τ can be regarded as being subjected to the probability The ideal magic state of the applied random Pauli Z error |π / 4>.

[0052] The CNOT gate 108 propagates the Pauli Z error from the magic state |π / 4> to the data qubit. The error has no effect on the measurement. Therefore, the twist state τ is used instead of Figure 1The ideal magic state |π / 4> within the T-gate 102 shown in FIG, analog component 204 can realize a noisy T-gate as given by

[0053]

[0054] in and denote quantum channels implementing ideal T and Z gates, respectively; for example, for any single qubit operator B, and Figure 3 is a representation of a noisy T-gate 302, which can be considered equivalent to an ideal T-gate 304 with noise N 306 present across it.

[0055] Next, error mitigation techniques can be used to reduce the The noise T gate 302 described is transformed into a channel A perfect T-gate 304 is depicted (without noise N 306). To this end, the calibration component 206 can determine the logic error rate A reasonable estimate of the logical error rate Generate a noise map N and apply the inverse N of the noise map by using the QPD method -1 To correct for noise on the noise T gate 302. In some embodiments, the correction component 206 can use tomography technology to estimate the logic error rate Alternatively, some embodiments of the calibration component 206 may use a value that can be measured experimentally. To estimate the logical error rate more efficiently According to this alternative approach, the phase-flip channel is defined as

[0056]

[0057] in represents the identity channel. and Exchange, then for any p∈N

[0058]

[0059] For p≡0(mod 8)

[0060] T p =id (11)

[0061] as well as

[0062]

[0063] Therefore, equation (10) ensures that

[0064]

[0065] Correction component 204 can then prepare the fault-tolerant logic state |+>, apply And measure the output based on {|+>,|->} to determine the logic error rate This produces a result of 1 or 0. The analog component 204 can repeat this circuit multiple times to estimate the expected value of the result, expressed as

[0066]

[0067] The final step can be checked with a simple iterative argument. By measuring f(p) for p = 8, 16, 24, 32, ..., an exponential fit can be used to obtain Estimates.

[0068] Once the logical error rate is known The correction component 206 can use various error mitigation techniques to correct the noisy T gate. Convert to ideal T-gate Two such techniques are discussed below.

[0069] The QPD method (sometimes also called probabilistic error cancellation) is a quantum error mitigation technique that allows the simulation of a desired quantum channel. (e.g., ideal quantum gates), while only accessing noisy quantum channels {ε i}'s quantum hardware. Figure 4 is a representation of an example circuit 402 illustrating the QPD method. Assuming that gate U 404 is to be executed, and a measurement represented by operator O 406 is to be performed, the expected value of the measurement result can be expressed as follows

[0070] Tr[O·[U](ρ)] (15)

[0071] In many quantum circuits, only the expected value is of interest. The QPD method allows estimating this expected value even if [U](ρ) cannot be realized exactly in hardware. According to the first step of the QPD method, if it is assumed that quantum hardware can realize quantum channels ε1, ε2, ε3, ..., ε M , then find the decomposition represented by

[0072]

[0073] Some of them a i is the quasi-probability coefficient, and M is the decomposition size. This decomposition can be rewritten as

[0074]

[0075] Used for

[0076]

[0077] as well as

[0078]

[0079] Given this decomposition, each time the quantum circuit is executed, according to the distribution p i Randomly select i∈{1,…,M}. In probability, use probability |a i | / One of the channels of γε i Instead of gate U 404 (block 306), where

[0080] γ:=∑ i |a i | (20)

[0081] And the measurement result (measured at block 408) is γsign(α i )weighted.

[0082] By correctly weighting the measurement results at the end of the circuit, the system 202 can obtain an unbiased estimate of the true expected value of the result of the ideal quantum circuit by performing Monte Carlo sampling. The number of samples performed to achieve a certain accuracy is scaled as In this case, γ is the sampling overhead of the QPD method.

[0083] Assuming that U is the unitary operator corresponding to the noisy T-gate 302, this method can be used by the correction component 206 to convert the noisy T-gate into Transformed into a perfect T-door

[0084]

[0085] This yields a QPD of the form of equation (16), where

[0086]

[0087]

[0088]

[0089] as well as

[0090]

[0091] In this case, the sampling overhead scales to

[0092]

[0093] Figure 5a For ε i =ε1=0 and ε2=ε, the sampling overhead γ given by equation (26) ε Graph 502 of φ as a function of the physical error rate ε via surface encoding described in equation (4). Figure 5b is ε i =ε1=ε2 / 10 and ε2=ε ε Graph 504 of .

[0094] In general, error mitigation using QPD methods can incur considerable sampling overhead, which scales as where t is the T count. In addition, combining the QPD method with fault tolerance can also lead to higher overhead. Consider a setting where magic state preparation is implemented for quantum circuits using a quasi-variable method. Assuming that all transverse operations are performed without error, the final circuit will be a quasi-probabilistic mixture given by

[0095]

[0096] However, even lateral manipulation will introduce errors, which can be arbitrarily suppressed. Therefore, the actual final state will be

[0097]

[0098] where ε k Includes the effect of noise from lateral doors.

[0099] The error is caused by

[0100]

[0101] It can be made arbitrarily small by increasing the code distance. By the triangle inequality, it can be obtained that

[0102]

[0103] where t denotes the T count. Therefore, to make the error on the output sufficiently small, ε can be chosen to be exponentially small as the number of T gates, such that ε = Δe - t. Recall that in the general fault-tolerant setting, one can choose

[0104] n=polylog(1 / ε, |C|)=polylog(e t / Δ,|C|)=poly(t,lot(1 / Δ),log(|C|))(31)

[0105] In the practical case where |C| = poly(t), the code size scales polynomially in the number of locations |C|, rather than polynomially as in the standard fault-tolerant setting. However, recalling the properties of the QPD method, only circuits where the sampling overhead γ is sufficiently small are considered. That is, γ ≤ κ, and for κ > 0, not too large, yielding ε ≥ Δ / κ, so

[0106] n=polylog(1 / ε,|C|)≤polylog(κ / Δ,|C|)=poly(κ+log(1 / Δ,|C|)≈polylog(1 / Δ,|C|) (32)

[0107] where the approximation step is accurate enough as long as κ is not too large. The scaling matches what would be expected from a standard fault-tolerant setting.

[0108] According to the above method, the simulation component 204 uses the magic state (as described above in conjunction with Figure 1 The T gate is simulated as described above, and the correction component 206 learns the logic error rate on the T gate (and the corresponding noise map N) and applies QPD to reduce this noise (as described above in conjunction with Figure 4 (As described above), this approach produces fault-tolerant T-gates even when the prepared magic state is noisy. Therefore, no magic state extraction is required to prepare the magic state, and thus the computational overhead is significantly reduced relative to methods that require magic state extraction to obtain a low-noise magic state.

[0109] The magic state method described above, which can be used by some embodiments of analog component 204 to simulate a T-gate using two logical qubits 104 and 106 encoded with an error-correcting code, can be used. As an alternative to this method, some embodiments of analog component 204 can use another method to implement a fault-tolerant T-gate using only a single logical qubit encoded with an error-correcting code. This can reduce the requirements for experimentally demonstrating fault-tolerant T. This alternative method is based on code deformation of the surface code. Figure 6 Implementation of fault-tolerant T-gates through code deformation is shown. According to this method, code deformation is performed on surface code 602a to expose a weight 1 logical Z-operator, the logical T-gate is simulated as a physical T-gate in the resulting deformed code 602b, and then the deformed code 602b is returned to its original form.

[0110] Figure 7 is a representation of an example 5x5 surface code 702 for distance d=3, including data cube 710 (black dots), syndrome qubit 708 (white dots), Z stabilizer 706, and X stabilizer 704. Thus, the surface code 702 uses 4d 2-4d+1 qubits, and with lateral X, Y, Z, S, and H gates. However, the methods described herein are essentially independent of the code to be used. In some cases, it may be beneficial to use other types of codes, such as rotational or dual-surface codes.

[0111] For noise models used for the CNOT, MeasX, MeasZ, PrepX, PrepZ, and idle operations, the depolarization channel can be applied in the form of CNOT output cubits.

[0112]

[0113] Then, the preparation gate outputs a state that is orthogonal to the ideal output with probability ε, and the measurement gate outputs an incorrect assignment with probability ε. Therefore, it can be seen that

[0114]

[0115] If εd<<1 and

[0116]

[0117] where ε th denotes the threshold of the surface code, and κ is a universal constant that is independent of the code size. The assumption εd<<1 is not restrictive in practice in fault-tolerant quantum computing given by d = polylog(C| / ε) (36).

[0118] Figure 8 An example sequence for implementing a fault-tolerant T-gate using code deformation is shown in accordance with one or more embodiments. In one or more embodiments, this sequence or another suitable code deformation sequence can be performed by simulation component 204. In this illustrated example, code deformation is performed for a 9×9 subsystem surface code at a distance d=5. In general, the execution of a coded T-gate can be simulated via code deformation of the surface code at a distance d according to the sequence described below.

[0119] In step 802a, each physical qubit can be initialized in the |+> state and a d syndrome readout cycle can be performed. This initializes the logical qubit in the |+> state. In step 802b, the stabilizer on the top boundary is turned off. Then in step 802c, a physical T gate is applied to the northwest corner. Then, in step 802d, the stabilizer on the top boundary is turned on and a D syndrome readout cycle is performed. Each physical qubit can then be measured on an X basis and the error-corrected eigenvalue of the logical X operator can be calculated. If the measured eigenvalue is -1, a logical Z error can be declared. For Figure 7Summarizing the numbers, this numerical simulation of κ yields κ ≈ 22.

[0120] The code deformation method can be applied in software by hiding the syndrome of the top boundary measurement round from the decoding algorithm. Therefore, the actual syndrome measurement circuit does not need to be modified.

[0121] By combining quantum error correction with quantum error correction via a QPD approach (also referred to as a QPD-assisted QEC approach), embodiments of system 202 described herein can construct fault-tolerant T-gates with a relatively low sampling overhead relative to current techniques. When the magic state approach described herein is used to simulate T-gates, applying the QPD approach to revert the effects of noise on the T-gates can produce fault-tolerant T-gates, even when using a noisy magic state, thereby eliminating the need to perform magic state extraction on the magic state and correspondingly reducing sampling overhead. Alternatively, if the code deformation approach described herein is used, fault-tolerant T-gates can be simulated using only one logical qubit, rather than two as in the magic state approach. Despite the increased sampling overhead relative to the magic state approach, the code deformation approach still produces low sampling overhead relative to current approaches. In terms of hardware, QPD-assisted QEC can be implemented using only fault-tolerant T-gates, and unlike conventional QEC, no magic state factory is required because magic state extraction is not required.

[0122] As in the case of classical simulation, the total simulation time overhead of QPD-assisted QEC scales exponentially as a function of the number of T-gates. The cost of the QPD-assisted QEC error mitigation technique is the sampling overhead γ ε ≥1, which depends on the physical error rate ε of the basic cates and is multiplicatively added as a function of the number of T gates or T count. For a circuit with T count t, the total sampling overhead is in

[0123]

[0124] The sampling cost roughly scales to γ ε ≈(1+ε), and is small enough for practical error rates to make it possible to simulate universal fault-tolerant quantum circuits with reasonable sampling overhead for large T counts on current devices.

[0125] Figure 9A method according to one or more embodiments of the present application is shown. Although the method shown here is shown and described as a series of actions for simplicity of explanation, it will be understood and appreciated that the present invention is not limited by the order of the actions, because according to the present invention, certain actions may occur in a different order than shown and described herein and / or occur simultaneously with other actions. For example, it will be understood and appreciated by those skilled in the art that the method may alternatively be represented as a series of interrelated states or events such as in a state diagram. In addition, not all of the actions shown are necessary to implement the method according to the present invention. In addition, according to the present disclosure, when different entities formulate different parts of the method, an interaction diagram may represent a method or method. In addition, two or more of the disclosed example methods may be implemented in combination with each other to achieve one or more features or advantages described herein.

[0126] Figure 9 An exemplary method 900 for creating a fault-tolerant T-gate, according to one or more embodiments described herein, is shown. Initially, at 902, a coded T-gate is simulated (e.g., by simulation component 204) using logical qubits encoded into an error-correcting code and at least one of a magic state or a code deformation of a surface code or another given code. In some embodiments where simulation is performed using a magic state, the magic state may be prepared without performing magic state extraction, thereby generating a noisy magic state. In some embodiments where simulation is performed via code deformation, code deformation may be performed on the code to exhibit, for example, a weight-1 logical Z operator, and the logical T-gate may be simulated as a physical T-gate in the resulting deformed code. At 904, noise is corrected using a quasi-probabilistic decomposition (e.g., by correction component 204) on the coded T-gate simulated in step 902.

[0127] To provide context for various aspects of the disclosed subject matter, Figure 10 The following discussion is intended to provide a brief, general description of a suitable environment in which various aspects of the disclosed subject matter can be implemented. Although the embodiments are described above in the general context of computer-executable instructions that can be executed on one or more computers, those skilled in the art will recognize that the embodiments can also be implemented in conjunction with other program modules and / or as a combination of hardware and software.

[0128] refer to Figure 10, an example environment 1000 for implementing various embodiments of aspects described herein includes a computer 1002, which includes a processing unit 1004, a system memory 1006, and a system bus 1008. The system bus 1008 couples system components including, but not limited to, the system memory 1006 to the processing unit 1004. The processing unit 1004 can be any of various commercially available processors. Dual microprocessors and other multi-processor architectures can also be used as the processing unit 1004.

[0129] The system bus 1008 may be any of several types of bus structures that may also interconnect to a memory bus (with or without a memory controller), a peripheral bus, and a local bus using any of a variety of commercially available bus architectures. The system memory 1006 includes ROM 1010 and RAM 1012. A basic input / output system (BIOS), containing the basic routines that help transfer information between elements within the computer 1002, such as during startup, may be stored in a nonvolatile memory such as ROM, an erasable programmable read-only memory (EPROM), or an EEPROM. RAM 1012 may also include high-speed RAM, such as static RAM, for caching data.

[0130] The computer 1002 also includes an internal hard disk drive (HDD) 1014 (e.g., EIDE, SATA), one or more external storage devices 1016 (e.g., a magnetic floppy disk drive (FDD) 1016, a memory stick or flash drive reader, a memory card reader, etc.), and an optical drive 1020 (e.g., which can read from or write to a CD-ROM disk, a DVD, a BD, etc.). Although the internal HDD 1014 is shown as being located within the computer 1002, the internal HDD 1014 can also be configured for external use in a suitable chassis (not shown). In addition, although not shown in the environment 1000, a solid-state drive (SSD) can be used in addition to or in place of the HDD 1014. The HDD 1014, the external storage device 1016, and the optical drive 1020 can be connected to the system bus 1008 via an HDD interface 1024, an external storage interface 1026, and an optical drive interface 1028, respectively. The interface 1024 for external drive implementations may include at least one or both of Universal Serial Bus (USB) and Institute of Electrical and Electronics Engineers (IEEE) 1394 interface technologies.Other external drive connection technologies are within the contemplation of the embodiments described herein.

[0131] The drives and their associated computer-readable storage media provide non-volatile storage of data, data structures, computer-executable instructions, and the like. For the computer 1002, the drives and storage media accommodate the storage of any data in a suitable digital format. Although the above description of computer-readable storage media refers to corresponding types of storage devices, those skilled in the art will appreciate that other types of computer-readable storage media, whether currently existing or developed in the future, may also be used in the example operating environment, and further, any such storage media may contain computer-executable instructions for performing the methods described herein.

[0132] A number of program modules may be stored in the drives and RAM 1012, including an operating system 1030, one or more application programs 1032, other program modules 1034, and program data 1036. All or portions of the operating system, application programs, modules, and / or data may also be cached in RAM 1012. The systems and methods described herein may be implemented using various commercially available operating systems or combinations of operating systems.

[0133] The computer 1002 may optionally include emulation technology. For example, a hypervisor (not shown) or other intermediary may emulate a hardware environment for the operating system 1030, and the emulated hardware may optionally be different from the hardware of the operating system 1030. Figure 10 . In such an embodiment, the operating system 1030 may comprise one of a plurality of virtual machines (VMs) hosted at the computer 1002. In addition, the operating system 1030 may provide a runtime environment, such as a Java runtime environment or a . NET framework, for the application 1032. The runtime environment is a consistent execution environment that allows the application 1032 to run on any operating system that includes a runtime environment. Similarly, the operating system 1030 may support containers, and the application 1032 may be in the form of a container, which is a lightweight, self-contained, executable software package that includes, for example, code, a runtime, system tools, system libraries, and settings for the application.

[0134] Furthermore, the computer 1002 can be enabled by a security module such as a Trusted Processing Module (TPM). For example, with a TPM, the boot component hashes the next boot component at the time of the boot component and waits for the result to match a security value before loading the next boot component. This process can occur at any layer in the code execution stack of the computer 1002, for example, at the application execution level or the operating system (OS) kernel level, thereby achieving security at any code execution level.

[0135] A user can enter commands and information into the computer 1002 through one or more wired / wireless input devices, such as a keyboard 1038, a touch screen 1040, and a pointing device such as a mouse 1042. Other input devices (not shown) may include a microphone, an infrared (IR) remote control, a radio frequency (RF) remote control, or other remote control, a joystick, a virtual reality controller and / or a virtual reality headset, a game pad, a stylus, an image input device (e.g., a camera), a gesture sensor input device, a visual movement sensor input device, an emotion or facial detection device, a biometric input device (e.g., a fingerprint or iris scanner), and the like. These and other input devices are typically connected to the processing unit 1004 through an input device interface 1044, which can be coupled to the system bus 1008, but may also be connected through other interfaces, such as a parallel port, an IEEE 1394 serial port, a game port, a USB port, an IR port, a port, and the like.

[0136] A monitor 1044 or other type of display device may also be connected to the system bus 1008 via an interface, such as a video adapter 1046. In addition to the monitor 1044, computers typically include other peripheral output devices (not shown) such as speakers, printers, and the like.

[0137] The computer 1002 can operate in a networked environment using logical connections to one or more remote computers, such as remote computer 1048, via wired and / or wireless communications. The remote computer 1048 can be a workstation, server computer, router, personal computer, portable computer, microprocessor-based entertainment device, peer device, or other common network node, and typically includes many or all of the elements described with respect to the computer 1002, although only a memory / storage device 1050 is shown for simplicity. The depicted logical connections include wired / wireless connections to a local area network (LAN) 1052 and / or a larger network, such as a wide area network (WAN) 1054. Such LAN and WAN networking environments are common in offices and companies and facilitate enterprise-wide computer networks, such as intranets, all of which can be connected to global communication networks such as the Internet.

[0138] When used in a LAN networking environment, the computer 1002 can be connected to the local area network 1052 through a wired and / or wireless communication network interface or adapter 1056. The adapter 1056 can facilitate wired or wireless communication with the LAN 1052 and can also include a wireless access point (AP) provided thereon for communicating with the adapter 1056 in a wireless mode.

[0139] When used in a WAN networking environment, the computer 1002 may include a modem 1058 or may be connected to a communications server on the WAN 1054 via other means for establishing communications over the WAN 1054, such as through the Internet. The modem 1058 may be internal or external, a wired or wireless device, and it may be connected to the system bus 1008 via the input device interface 1042. In a networked environment, program modules described relative to the computer 1002, or portions thereof, may be stored in the remote memory / storage device 1050. It will be appreciated that the network connections shown are examples and other means of establishing a communications link between the computers may be used.

[0140] When used in a LAN or WAN networking environment, computer 1002 can access a cloud storage system or other network-based storage system in addition to or in lieu of the external storage device 1016 described above. Typically, the connection between computer 1002 and the cloud storage system can be established over LAN 1052 or WAN 1054, for example, via adapter 1056 or modem 1058, respectively. When computer 1002 is connected to an associated cloud storage system, external storage interface 1026 can manage the storage provided by the cloud storage system, as it would other types of external storage, with the aid of adapter 1056 and / or modem 1058. For example, external storage interface 1026 can be configured to provide access to cloud storage sources as if those sources were physically connected to computer 1002.

[0141] The computer 1002 may be operable to communicate with any wireless device or entity that is operatively arranged in wireless communication, such as a printer, scanner, desktop and / or portable computer, portable data assistant, communication satellite, any device or location associated with a wirelessly detectable tag (e.g., a kiosk, a newsstand, a shelf, etc.), and a telephone. This may include Wireless Fidelity (Wi-Fi) and Wireless technology. Thus, the communication can be a predefined structure like a conventional network, or just an ad hoc communication between at least two devices.

[0142] Now refer to Figure 11, depicts an illustrative cloud computing environment 1100. As shown, the cloud computing environment 1100 includes one or more cloud computing nodes 1102 with which local computing devices used by cloud consumers can communicate, such as personal digital assistants (PDAs) or cellular phones 1104, desktop computers 1106, laptop computers 1108, and / or automobile computer systems 1110. Nodes 1102 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks, such as private clouds, community clouds, public clouds, or hybrid clouds, or combinations thereof, as described above. This allows the cloud computing environment 1100 to provide infrastructure, platforms, and / or software as services for which cloud consumers do not need to maintain resources on local computing devices. It should be understood that Figure 11 The types of computing devices 1104 and 1110 shown in FIG are illustrative only, and computing node 1102 and cloud computing environment 1100 may communicate with any type of computerized device over any type of network and / or network-addressable connection (eg, using a web browser).

[0143] Now refer to Figure 12 , showing a cloud computing environment 1000 ( Figure 11 ) provides a set of functional abstraction layers. For the sake of brevity, repeated descriptions of similar elements used in other embodiments described herein are omitted. It should be understood in advance that Figure 12 The components, layers, and functions shown in are intended to be illustrative only, and embodiments of the present invention are not limited thereto. As described, the following layers and corresponding functions are provided.

[0144] Hardware and software layer 1202 includes hardware and software components. Examples of hardware components include: host 1204; server 1206 based on RISC (Reduced Instruction Set Computer) architecture; server 1208; blade server 1210; storage device 1212; and network and networking components 1214. In some embodiments, software components include network application server software 1216 and database software 1218.

[0145] The virtualization layer 1220 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 1222 ; virtual storage 1224 ; virtual networks 1226 , including virtual private networks; virtual applications and operating systems 1228 ; and virtual clients 1230 .

[0146] In one example, the management layer 1232 may provide the functionality described below. Resource provisioning 1234 provides for dynamic procurement of computing and other resources used to perform tasks within a cloud computing environment. Metering and pricing 1236 provides for cost tracking when utilizing resources in a cloud computing environment, and for billing or invoicing for the consumption of those resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks, and protection for data and other resources. A user portal 1238 provides access to the cloud computing environment for consumers and system administrators. Service level management 1240 provides for allocation and management of cloud computing resources so that required service levels are met. Service level agreement (SLA) planning and fulfillment 1242 provides for the pre-arrangement and procurement of cloud computing resources, where future demand is anticipated based on the SLA.

[0147] The workload layer 1244 provides examples of functionality that can be utilized by a cloud computing environment. Examples of workloads and functionality that can be provided from this layer include: mapping and navigation 1246; software development and lifecycle management 1248; virtual classroom education delivery 1250; data analysis processing 1252; transaction processing 1254; and transfer learning processing 1256. Various embodiments of the present invention can utilize reference Figure 11 and 12 The described cloud computing environment determines the similarity between a given machine learning task and historical machine learning tasks, and performs a transfer learning process on an artificial intelligence model generated by automated machine learning based on the determined similarity.

[0148] What has been described above includes examples of the present invention. Of course, it is not possible to describe every conceivable combination of components or methods for purposes of describing the disclosed subject matter, but one skilled in the art will recognize that many further combinations and permutations of the present invention are possible. Therefore, the disclosed subject matter is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

[0149] In particular, with respect to the various functions performed by the aforementioned components, devices, circuits, systems, etc., unless otherwise indicated, the terms used to describe these components (including references to "means") are intended to correspond to any component that performs the designated function of the described component (e.g., a functional equivalent), even if not structurally equivalent to the disclosed structure, that performs the functions in the exemplary aspects of the disclosed subject matter shown herein. In this regard, it will also be recognized that the disclosed subject matter includes systems as well as computer-readable media having computer-executable instructions for performing the actions and / or events of the various methods of the disclosed subject matter.

[0150] Additionally, while particular features of the disclosed subject matter may be disclosed for only one of several implementations, such features may be combined with one or more other features of other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include" and "comprising" and variations thereof are used in the detailed description or claims, these terms are intended to be inclusive in a manner similar to the term "comprising."

[0151] In this application, the word "exemplary" is used to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs. Instead, the use of the word "exemplary" is intended to present concepts in a concrete manner.

[0152] Various aspects or features described herein may be implemented as methods, apparatus, or articles of manufacture using standard programming and / or engineering techniques. The term "article of manufacture," as used herein, is intended to encompass a computer program accessible from any computer-readable device, carrier, or medium. For example, computer-readable media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic strips, etc.), optical disks [e.g., compact disks (CDs), digital versatile disks (DVDs), etc.], smart cards, and flash memory devices (e.g., cards, sticks, key drives, etc.).

[0153] The present invention may be a system, method, apparatus, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present invention. A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media may also include the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card with instructions recorded thereon or a raised structure in a groove, and any suitable combination of the foregoing. Computer-readable storage media as used herein should not be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0154] Computer-readable program instructions described herein can be downloaded to corresponding computing / processing equipment from computer-readable storage media, or via a network, such as the Internet, local area network, wide area network and / or wireless network, downloaded to an external computer or external storage device. The network can include copper transmission cables, optical transmission optical fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. The network adapter card or the network interface in each computing / processing equipment receive computer-readable program instructions from the network, and forward computer-readable program instructions to be stored in the computer-readable storage media in the corresponding computing / processing equipment. The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of integrated circuits, or with one or more programming languages, including source code or object code written in any combination of object-oriented programming languages ​​(such as Smalltalk, C++ etc.) and procedural programming languages ​​(such as " C " programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform various aspects of the present invention, an electronic circuit comprising, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions to personalize the electronic circuit by utilizing the state information of the computer-readable program instructions.

[0155] Various aspects of the present invention are described herein with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to an embodiment of the present invention. It will be understood that each frame of the flowchart and / or block diagram and the combination of frames in the flowchart and / or block diagram can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the function / action specified in one or more frames of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide the computer, programmable data processing device and / or other equipment to work in a specific manner so that the computer-readable storage medium having instructions therein includes an article of manufacture, and the article of manufacture includes instructions for implementing various aspects of the function / action specified in one or more frames of the flowchart and / or block diagram. The computer-readable program instructions can also be loaded onto a computer, other programmable data processing device or other equipment so that a series of operational actions are performed on the computer, other programmable device or other equipment to produce a computer-implemented process so that the instructions executed on the computer, other programmable device or other equipment implement the function / action specified in one or more frames of the flowchart and / or block diagram.

[0156] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0157] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention. In this regard, each frame in the flow chart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for realizing the specified logical function. In some alternative embodiments, the function noted in the frame may not occur in the order noted in the figure. For example, the two frames shown in succession can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, depending on the function involved. It will also be noted that the combination of each frame of the block diagram and / or flow chart illustration and the frame in the block diagram and / or flow chart illustration can be realized by a dedicated hardware-based system that performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0158] Although the subject matter is described above in the general context of computer-executable instructions of a computer program product running on one and / or multiple computers, those skilled in the art will recognize that the present disclosure may also be implemented or may be implemented in conjunction with other program modules. Typically, program modules include routines, programs, components, data structures, etc. that perform specific tasks and / or implement specific abstract data types. In addition, those skilled in the art will appreciate that the computer-implemented methods of the present invention can be implemented using other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, etc. The various aspects shown can also be practiced in a distributed computing environment in which tasks are performed by remote processing devices linked via a communication network. However, some aspects of the present disclosure, if not all, can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in local and remote memory storage devices. For example, in one or more embodiments, computer-executable components can be executed from a memory that can include or consist of one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable. In addition, one or more embodiments described herein may execute code of computer-executable components in a distributed manner, for example, multiple processors combining or working in concert to execute code from one or more distributed memory units. As used herein, the term "memory" may encompass a single memory or memory unit at one location or multiple memories or memory units at one or more locations.

[0159] As used in this application, the terms "component", "system", "platform", "interface" and the like may refer to and / or may include computer-related entities or entities related to an operating machine having one or more specific functions. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program and / or a computer running on a processor. As an illustration, both an application running on a server and a server may be a component. One or more components may reside within a process and / or a thread of execution, and a component may be located on one computer and / or distributed between two or more computers. In another example, the corresponding component may be executed from various computer-readable media having various data structures stored thereon. These components may communicate via local and / or remote processes, for example, according to a signal having one or more data packets (e.g., data from a component, which interacts with another component in a local system, a distributed system and / or interacts with other systems via a network such as the Internet). As another example, a component may be a device having a specific functionality provided by mechanical parts operated by electrical or electronic circuitry, which is operated by a software or firmware application executed by a processor. In this case, the processor may be internal or external to the device and may execute at least a portion of the software or firmware application. As yet another example, a component may be a device that provides a specific functionality through electronic components rather than mechanical parts, where the electronic components may include a processor or other device to execute the software or firmware that at least partially imparts the functionality to the electronic components. In one aspect, the component may emulate the electronic component via a virtual machine, such as within a cloud computing system.

[0160] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive arrangement. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. In addition, unless otherwise specified or clear from the context to refer to the singular form, the articles "a" and "an" as used in this specification and the drawings should generally be interpreted to mean "one or more". As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to these examples. In addition, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to exclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0161] As used in this specification, the term "processor" may refer to essentially any computational processing unit or device, including but not limited to a single-core processor; a single processor with software multi-threaded execution capability; a multi-core processor; a multi-core processor with software multi-threaded execution capability; a multi-core processor with hardware multi-threading technology; a parallel platform; and a parallel platform with distributed shared memory. In addition, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. In addition, the processor may employ nanoscale architectures, such as, but not limited to, transistors, switches, and gates based on molecules and quantum dots, in order to optimize space usage or enhance the performance of user devices. The processor may also be implemented as a combination of computational processing units. In this disclosure, terms such as "storage," "memory," "data storage," "data repository," and substantially any other information storage component related to the operation and functionality of a component are used to refer to a "memory component," an entity embodied as "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein can be volatile memory or non-volatile memory, or can include both volatile and non-volatile memory. By way of illustration and not limitation, non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include RAM, which can be used as external cache memory, for example, which is available in many forms such as, by way of illustration and not limitation, synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), Direct Rambus Dynamic RAM (DRDRAM), and Rambus Dynamic RAM (RDRAM). In addition, the memory components of the systems or computer-implemented methods disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0162] The above description includes only examples of systems and computer-implemented methods. Of course, it is not possible to describe every conceivable combination of components or computer-implemented methods for purposes of describing the present disclosure, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. Furthermore, to the extent that the terms "including," "having," "having," and the like are used in the detailed description, claims, appendices, and figures, these terms are intended to be inclusive in a manner similar to that in which the term "comprising" is interpreted when used as a transitional word in the claims.

[0163] The description of various embodiments has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, practical applications, or improvements over existing technologies in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A system for constructing a fault-tolerant T-gate, comprising: a processor executing computer-executable components stored in memory, wherein the computer-executable components include: an analog component that simulates encoded T-gates using logical qubits encoded into an error-correcting code and a magic state prepared without using magic state extraction; and A correction component that uses a quasi-probabilistic decomposition to correct for noise on the encoded T gates.

2. The system according to claim 1, in, The simulation component simulates the encoded T-gate as a quantum circuit including a Clifford gate and employing two logical qubits; and Wherein, one of the two logical qubits includes the magic state.

3. The system according to claim 2, in, The quantum circuit includes a controlled NOT gate and a controlled phase-shift gate; wherein the first logical qubit of the two logical qubits including the magic state is provided to the controlled phase-shift gate and is provided as a control for the controlled NOT gate; wherein a second logical qubit of the two logical qubits is provided to the controlled NOT gate; and The measurement result of the output of the controlled NOT gate is provided as a control for the controlled phase-shift gate.

4. The system according to any one of claims 1 to 3, wherein: The simulation component further simulates the coded T-gate using a code deformation of the surface code, wherein the coded T-gate is simulated using the code deformation by the following steps: performing a first code transformation on a given code to exhibit a weight 1 logical Z operator to produce a transformed code; emulating logical T-gates as physical T-gates in the deformed code; and A second code transformation is performed on the transformed code to return the transformed code to its form before the execution of the first code transformation.

5. The system according to any one of claims 1 to 3, wherein: The correction component: learning an error rate of the encoded T-gate and generating a noise map N based on the error rate; and Apply the inverse of the noise map by quasi-probabilistic decomposition N -1 To correct the noise on the T gate of the code.

6. The system according to claim 5, wherein: The correction component calculates the decomposition of the quasi-probabilistic decomposition according to the following formula in: U is the unitary operator corresponding to the T-gate of the encoding; M is the decomposition size; α i is the quasi-probability coefficient; ε i is a quantum channel implemented on quantum hardware; and γ is the sampling overhead.

7. The system according to claim 6, wherein: For a corresponding execution of a quantum circuit comprising the encoded T-gate, the correction component: According to the distribution p i Randomly select i; Use ε i Replace gate U; and Use γsign(α i ) to weight the measurement results.

8. The system according to claim 4, wherein: Simulating the coded T-gate using at least one of the magic state or the code deformation and correcting the noise using quasi-probabilistic decomposition alleviates error-tolerant simulation of the coded T-gate using magic state extraction.

9. A computer-implemented method for constructing a fault-tolerant T-gate, comprising: The system simulates a coded T-gate using logical qubits encoded into an error-correcting code and a magic state prepared without using magic state extraction; as well as Quasi-probabilistic decomposition is used by the system to correct for noise on the encoded T-gates.

10. The computer-implemented method of claim 9, in, The simulation includes simulating the encoded T-gate as a quantum circuit including a Clifford gate and employing two logical qubits; and Wherein, one of the two logical qubits includes the magic state.

11. The computer-implemented method of claim 10, in, The quantum circuit includes a controlled NOT gate and a controlled phase-shift gate; wherein the first logical qubit of the two logical qubits including the magic state is provided to the controlled phase-shift gate and is provided as a control for the controlled NOT gate; wherein a second logical qubit of the two logical qubits is provided to the controlled NOT gate; and The measurement result of the output of the controlled NOT gate is provided as a control for the controlled phase-shift gate.

12. The computer-implemented method of any one of claims 9-11, further comprising simulating the coded T-gate using code deformation of a surface code, wherein Using the code deformation to simulate the coded T-gate includes: performing, by the system, a first code transformation on a given code to exhibit a weight 1 logical Z operator, thereby generating a transformed code; simulating, by the system, logical T-gates as physical T-gates in the deformed code; and A second code transformation is performed by the system on the transformed code to return the transformed code to its form before performing the first code transformation.

13. The computer-implemented method of any one of claims 9 to 11, wherein: The correction includes: learning, by the system, an error rate of the encoded T-gate and generating a noise map N based on the error rate; and The system is constructed by applying the inverse of the noise map N -1 , correcting the noise on the encoded T gate via the quasi-probabilistic decomposition.

14. The computer-implemented method of claim 13, wherein: The correction includes finding, by the system, a decomposition of the quasi-probabilistic decomposition according to in: U is the unitary operator corresponding to the T-gate of the encoding; M is the decomposition size; α i is the quasi-probability coefficient; ε i is a quantum channel implementable on quantum hardware; and γ is the sampling overhead.

15. The computer-implemented method of claim 14, wherein: The correction includes corresponding execution of a quantum circuit including the encoded T-gate: The system is distributed according to p i Randomly select i; The system uses ε i Replacement door U; and The system uses γsign(α i ) to weight the measurement results.

16. The computer-implemented method of any one of claims 12, wherein: Simulating the coded T-gate using at least one of the magic state or the code variation and correcting the noise using quasi-probabilistic decomposition alleviates error-tolerant simulation of the coded T-gate using magic state extraction.

17. The computer-implemented method of any one of claims 9-11, wherein: The system is a system according to any one of the preceding claims 1 to 8.

18. A computer program product comprising a computer-readable storage medium having program instructions embedded therein, the program instructions being executable by a processor to cause the processor to: simulating, by the processor, a coded T-gate using logical qubits encoded into an error correction code and a magic state prepared without using magic state extraction; and Quasi-probabilistic decomposition is used by the processor to correct noise on the encoded T-gate.

19. The computer program product of claim 18, wherein: The program instructions executable by the processor cause the processor to: The processor simulates the encoded T-gate as a quantum circuit including a Clifford gate and employing two logical qubits, wherein one of the two logical qubits includes the magic state.

20. The computer program product according to claim 19, in, The quantum circuit includes a controlled NOT gate and a controlled phase-shift gate; wherein the first logical qubit of the two logical qubits including the magic state is provided to the controlled phase-shift gate and is provided as a control for the controlled NOT gate; wherein a second logical qubit of the two logical qubits is provided to the controlled NOT gate; and The measurement result of the output of the controlled NOT gate is provided as a control for the controlled phase-shift gate.

21. The computer program product of any one of claims 18-20, the processor further emulating the coded T-gate using code deformation of a surface code, wherein The program instructions executable by the processor cause the processor to simulate the coded T-gate using the code deformation via the following steps: performing a first code transformation on a given code to exhibit a weight 1 logical Z operator to produce a transformed code; Simulating a logical T-gate as a physical T-gate in the deformed code; as well as A second code transformation is performed on the transformed code to return the code to its form before the execution of the first code transformation.

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