50 results about "Error mitigation" patented technology

A system (50) and method (300) for providing multipath error mitigation for real-time wireless tracking of an object (100) is disclosed herein. A plurality of sensor readings are obtained from a tag (60) attached to an object (100) within an indoor facility (70). A plurality of reading sets are generated and sorted by zones. A zone with the highest average reading is preferably selected and the location of the object (100) is calculated based on the selected zone readings. In this manner, faulty position readings are eliminated from the location calculation thereby allowing for more accurate tracking of the object (100) within the indoor facility (70).

In an advanced adaptive modulation and coding (AMC) scheme, the code rate and the parity-check matrix (PCM) for low-density parity-check (LDPC) codes are adapted according to modulation formats and variable-iteration receivers. The degree distribution for the PCM adaptation is designed by heuristic optimization to minimize the required SNR via an extrinsic information transfer (EXIT) trajectory analysis for finite-iteration decoding. The method uses dynamic window decoding by generating spatially coupled PCM for quasi-cyclic LDPC convolutional coding. The method also provides a way to jointly optimize labeling and decoding complexity for high-order and high-dimensional modulations. The problem to use a large number of different LDPC codes for various modulation formats and variable-iteration decoding is also dealt with by linearly dependent PCM adaptation across iteration count to keep using a common generator matrix. This PCM adaptation can improve a convergence speed of belief propagation decoding and mitigate an error floor issue.

Embodiments of apparatuses and methods for selective activation of error mitigation based on bit level error counts are disclosed. In one embodiment, an apparatus includes a plurality of state elements, an error counter, and activation logic. The error counter is to count the number of bit level errors in the state elements. The activation logic is to increase error mitigation if the number of bit level errors exceeds a threshold value.

The present invention determines a situational awareness for alerting, mitigating error, distortion or failures, and managing the Internet (or equally component intranets), connected networks and cloud infrastructure. Specifically, this invention focuses on determining who originates messages, from what system, and the path taken, thereby analyzing the reputation of all the nodes and links through which data passes.

It can provide a mechanism determine the ongoing veracity of the “purported” device, and maintain a reputation database of devices, data, applications and networks for analysis of how the Internet is being used or potentially subverted—effectively creating a score indicating component and total system integrity. It can calculate a correlation of risk analysis of all adjacent data describing the universe of the Internet. This invention will be particularly useful for helping detect and mitigate compromises to data, networks, systems and other assets within the Internet and Cloud.

WaveSmooth™ is a technique to mitigate inherent measurement error for GNSS signals. The WaveSmooth™ technique can be applied for single-frequency or multi-frequency GNSS users. For single-frequency GNSS users, WaveSmooth™ enables smoothing of GNSS measurements, in real-time using wavelets without introducing significant ionosphere divergence. For multi-frequency GNSS users, the WaveSmooth™ technique effectively mitigates multipath error in a real-time fashion. The WaveSmooth™ techniques utilizes wavelet aided methods and operate on the GNSS Code minus Carrier (CmC) signal to mitigate inherent GNSS measurement errors in a real-time fashion to improve the performance of these GNSSs. The WaveSmooth™ error mitigated pseudorange measurement can be used, along with the original carrier phase measurement for a high performance user solution.

A method, process and apparatus for automating software record creation are disclosed. In a preferred embodiment of the present invention, although not limited thereto, the present invention uses a unique email address as a proxy for and to correspond to a specific database table that in turn is associated with a specific user. In the context of an inventory system and this preferred embodiment the present invention enables an information object, such as a photograph, to be captured remotely and transmitted over a communications network to a proxy email address where it is automatically processed into an inventory record on the desired inventory list without the user needing to have any further interaction with the inventory system than the transmission of the object. Additionally, in this preferred embodiment that utilizes email as the transportation method, inclusion filtering is employed to restrict data submission thereby preventing or greatly mitigating false record entries.

Systems and methods for enhancing reliability are presented. In one embodiment, a system comprises a processor configured to execute program instructions and contemporaneously perform reliability enhancement operations (e.g., fault checking, error mitigation, etc.) incident to executing the program instructions. The fault checking can include: identifying functionality of a particular portion of the program instructions; speculatively executing multiple sets of operations contemporaneously; and comparing execution results from the multiple sets of operations. The multiple sets of operations are functional duplicates of the particular portion of the program instructions. If the execution results have a matching value, then the value can be made architecturally visible. If the execution results do not have a matching value, the system can be put in a safe mode. An error mitigation operation can be performed can include a corrective procedure. The corrective procedure can include rollback to a known valid state.

The self-healing system comprises a self-healing processor and an error mitigation system. The self-healing processor includes a code block associated with the operation of a portion of digital logic. The self-healing processor also includes a dynamic signature analysis circuit. The processor executes the code block. The dynamic signature analysis circuit creates a dynamic signature representing the operation of the portion of digital logic associated with the code block. The error mitigation system receives the dynamic signature from the dynamic signature analysis circuit. The error mitigation system compares the dynamic signature to a static signature to determine if the signatures match. If the signatures do not match, then the digital logic associated with the code block has an error. The error mitigation system retries execution of the code block. The error mitigation system stores log information describing the above events.

A system and method for transmitting data over a channel, in which the data are categorized in at least two different categories. For example, the data are categorized according to the effect on perceived degradation on the data when error mitigation is performed on the data. Corrupted data of the first category are replaced using a first replacement method, such as retransmission and forward error correction. The corrupted data of the second category are replaced using a second replacement method different from the first replacement method, e.g., error mitigation or interpolation.

In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.

A controller of a non-volatile memory manages each of multiple disjoint sets of physical pages as a respective page group. The controller mitigates errors by repetitively performing background mitigation reads of each of the plurality of blocks including, in order, performing a background mitigation read of a first physical page in a first page group in a first block; prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a first page group in each other of the plurality of blocks; performing a background mitigation read of a first physical page in a second page group in the first block; and prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a second page group in each other of the plurality of blocks.

Apparatus and methods for autonomously identifying and mitigating soft-errors affecting integrated circuit memory storage devices are provided. A soft-error mitigation process is invoked upon finding that an integrated circuit memory device is affected by a parity error. In a staged approach, unused memory regions of the integrated circuit memory device are reinitialized; if a redundant deployment prevails, the subsystem corresponding to the affected integrated circuit memory device is reset; memory regions having copies of contents thereof stored at remote locations are rewritten with obtained copies of the contents; and memory regions storing contents which are generated at run-time are reinitialized. Directed parity error scans are employed at each stage. If the parity error persists, one of the apparatus, and the subsystem corresponding to the affected silicon memory device is reset during a maintenance window. Advantages are derived from a run-time soft-error mitigation process which increases availability, and reduces maintenance overheads and the need for hardware replacement.

The present invention facilitates efficient and effective information storage device operations. In one embodiment, a storage device comprises: a plurality of storage cells configured to store information; a plurality of word lines coupled to the plurality of storage cells; and a plurality of bit lines coupled to the plurality of storage cells, wherein the plurality of bit lines are configured to enable writing of the plurality of storage cells and the plurality of word lines are configured to enable reading of the storage cells. The information is configured in a plurality of information first type portions (e.g., codewords) which respectively include a plurality of second type portions (e.g., data chunks), and the information is stored by the plurality of storage cells in a distribution that ensures two second type portions from a respective first type portion are not stored in storage cells adjacent to one another.

The invention relates to a decision feedback type equalizer, capable of better reducing error dissemination. The decision feedback type equalizer comprises a storage device, a logarithm likelihood ratio calculating part, a logarithm likelihood ratio evaluation part, a decrement calculating part, and a logarithm likelihood ratio attenuation part, wherein the storage device is used for keeping input signals that make the decision responding to multiple signs to be repeatedly operated; the logarithm likelihood ratio calculating part is used for calculating the logarithm likelihood ratio according to the signals obtained by deducting the output of the feedback filter from the input signals kept in the storage device; the logarithm likelihood ratio evaluation part, according to the absolute value of the logarithm likelihood ratio, carries out confirmation over the signals transmitting the bit that is evaluated with low reliability; the decrement calculating part calculates and keeps the logarithm likelihood ratio attenuation amount corresponding to the whole or part of bits of the signals affected by the feedback filter; and the logarithm likelihood ratio attenuation part makes the logarithm likelihood ratio carry out attenuation according to the logarithm likelihood ratio attenuation amount calculated in the previous decision feedback cycle.

There is provided a storage apparatus capable of relieving an error region and a control apparatus thereof.

A storage apparatus connectable to a host includes a host interface section 20 that notifies the host that data cannot be read out in the case where there is an error sector from which data cannot be read out by a read retry operation and acquires an instruction from the host; an MPU 12 that performs adjustment of a read parameter which is a parameter for data reading when the host interface section 20 acquires the error sector recovery instruction from the host; and a read channel 16 that uses a parameter that has been adjusted by the MPU 12 to read out data from the error sector.