A complex waveform generating device against active jamming

Abstract

The present application relates to a kind of complex waveform generating device of anti-active jamming, belong to radar detection guidance and electronic countermeasure technical field, solve the problem that the existing radar main signal is higher in the probability of being detected and intercepted by jammer.One kind of complex waveform generating device of anti-active jamming, including control unit, direct digital frequency synthesizer and signal output unit, the control unit is connected with signal output unit by direct digital frequency synthesizer.The complex waveform generating device of anti-active jamming of the present application, the complex waveform main signal of emission and cover signal random arrangement, cover signal generation time, pulse width, signal bandwidth, emission frequency point, frequency modulation slope and signal number are random, difficult to predict.The signal output by complex waveform generating device is more difficult to distinguish, greatly reduce the probability of main signal interception and the difficulty of correct implementation of jammer, increase the means and strategy of anti-jamming, improve the performance of radar anti-jamming and radar tracking stability.

Description

TECHNICAL FIELD

[0001] The present application belongs to the radar detection guidance and electronic countermeasure technical field, and particularly relates to a complex waveform generating device resisting active jamming. BACKGROUND

[0002] With the development of military electronic technology, the application of various active jamming is increased, the current radar waveform generating device can only emit a single main signal or can emit a cover signal, but the cover signal is single, so the probability of the radar main signal being detected and intercepted by the jammer is high. In order to increase the difficulty of the radar main signal being intercepted and improve the ability of the radar itself resisting active jamming, a complex waveform generating device resisting active jamming is urgently needed. SUMMARY

[0003] In view of the above analysis, the present application aims to provide a complex waveform generating device resisting active jamming to solve the problem that the current radar main signal is detected and intercepted by the jammer with a high probability.

[0004] The purpose of the present application is mainly realized through the following technical solutions:

[0005] A complex waveform generating device resisting active jamming comprises a control unit, a direct digital frequency synthesizer and a signal output unit, the control unit is connected with the signal output unit through the direct digital frequency synthesizer, the characteristic parameters of the main signal and the cover signal are written in the control unit, the direct digital frequency synthesizer outputs a sine signal meeting the signal characteristics according to the characteristic parameters of the main signal and the cover signal, and the signal output unit outputs the responsive main signal and cover signal after processing the sine signal output by the direct digital frequency synthesizer.

[0006] Further, the control unit comprises a buffer channel and a register channel, the number of the buffer channel and the register channel corresponds to the number of the cover signal.

[0007] Further, it further comprises a phase-locked loop, the phase-locked loop is connected with the control unit and the direct digital frequency synthesizer.

[0008] Further, it further comprises a crystal oscillator and a power divider, the input end of the power divider is connected with the crystal oscillator, and the output end is connected with the control unit and the direct digital frequency synthesizer respectively.

[0009] Further, the direct digital frequency synthesizer comprises a frequency control register, the frequency control register can load the pulse width, frequency, bandwidth and frequency modulation slope input by the register control unit.

[0010] Further, the direct digital frequency synthesizer further comprises a high-speed phase accumulator, which is capable of phase accumulation according to register writing pulse width, frequency, bandwidth, frequency modulation slope.

[0011] Further, the direct digital frequency synthesizer further comprises a sine calculator, which calculates sine wave amplitude according to the phase accumulation value output by the high-speed phase accumulator, and outputs a digitized sine wave.

[0012] Further, the signal output unit comprises a band-pass filter, which is connected with the direct digital frequency synthesizer, and the band-pass filter corresponds to the buffer channel one by one.

[0013] Further, the signal output unit further comprises an attenuator, which is connected with the band-pass filter, and the attenuator is capable of adaptive attenuation of the output signal.

[0014] Further, the signal output unit further comprises a single-pole double-throw switch, and each single-pole double-throw switch is connected with two attenuators.

[0015] The present application can achieve the following beneficial effects:

[0016] (1) The complex waveform generating device of the present application can output signals that are difficult to distinguish between true and false, greatly reduce the probability of the jammer intercepting the main signal and the difficulty of correctly implementing the jamming, increase the anti-jamming means and strategies, and improve the performance of radar anti-jamming and the stability of radar tracking.

[0017] The above technical solutions can be combined with each other in the present application to realize more preferred combination schemes. Other features and advantages of the present application will be described in the subsequent specification, and some advantages will become apparent from the specification or be understood by implementing the present application. The purposes and other advantages of the present application can be realized and obtained from the contents specifically pointed out in the specification and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the application, and are incorporated herein and constitute a part of the detailed description. The drawings illustrate embodiments of the application and, together with the description, serve to explain the principles of the application. In the drawings:

[0019] Fig. 1 A schematic diagram of the complex waveform generating device with 2-3 cover signals of the embodiment of the present application;

[0020] Fig. 2Fig. 1 is a schematic diagram of a complex waveform generating device with 4-7 cover signals according to an embodiment of the present application. DETAILED DESCRIPTION

[0021] The preferred embodiments of the present application will be described in detail with reference to the drawings, in which:

[0022] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the term "connected" should be understood in a broad sense, for example, it can be fixedly connected, or detachably connected, or integrally connected, it can be mechanically connected, or electrically connected, it can be directly connected, or indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above-mentioned term in the present application can be understood according to the specific circumstances.

[0023] The terms "top", "bottom", "above", "under" and "on" used throughout the description are relative positions of the components of the device, for example, the relative positions of the top and bottom substrates inside the device. It can be understood that the device is multifunctional, regardless of their orientation in space.

[0024] One embodiment of the present application, as shown in Figs. 1-2 An anti-active interference complex waveform generating device is disclosed, the anti-active interference complex waveform is composed of a main signal and n cover signals i, the main signal is unique, the number of cover signals n is at least 2, that is, i = 2,..., n. The main signal and the cover signal are randomly arranged, and the more cover signals selected, the better the cover effect on the main signal.

[0025] In this embodiment, the waveform generating device includes a control unit, a direct digital synthesizer (DDS) and a signal output unit, the control unit is connected with the signal output unit through the direct digital synthesizer. The characteristic parameters of the main signal and the cover signal are written in the control unit, the direct digital synthesizer outputs a sinusoidal signal meeting the signal characteristics of signal pulse width, signal frequency, signal bandwidth and frequency modulation slope according to the characteristic parameters of the main signal and the cover signal written in the control unit. The signal output unit outputs the responsive main signal and cover signal after processing the sinusoidal signal output by the direct digital synthesizer.

[0026] Specifically, the control unit adopts an FPGA (Field Programmable Gate Array) chip. The characteristic parameters of the complex waveform include time domain characteristic parameters and frequency domain characteristic parameters, the time domain characteristic parameters include signal amplitude, signal delay and signal pulse width, etc.; the frequency domain characteristic parameters include: signal frequency, signal bandwidth and frequency modulation slope, etc. According to the time of issuing the instruction, the control unit outputs all the time domain and frequency domain parameters to the direct digital frequency synthesizer.

[0027] Further, the control unit includes a buffer channel and a register channel, and the buffer channel and the register channel in the chip of the control unit meet the quantity requirement of the shield signals.

[0028] Further, the number of shield signals needs to consider the duty cycle of the overall signal, and the duty cycle refers to the ratio of the duration of a positive pulse in a pulse sequence (such as a square wave) to the total period of the pulse.

[0029] Suppose that the pulse width of the main signal is τ0, the pulse width of the shield signal i is τi, and the period of the radar synchronization signal pulse is T, then the duty cycle D is: i c

[0030]

[0031] Due to the power limitation of the transmitter, the duty cycle of the missile-borne radar is usually selected between 20% and 30%, and under the condition of meeting the duty cycle, as many shield signals as possible are selected to determine the number of shield signals, and the pulse width τi of each shield signal. i The pulse widths can be unequal in design.

[0032] Exemplarily, when the number of shield signals is 2-3, the FPGA selects a chip with 4 buffer channels and 4 register channels; the buffer channels include buffer channels 0, 1, 2 and 3; the register channels include register channels 0, 1, 2 and 3. The buffer channels and the register channels are one-to-one corresponding.

[0033] If the number of shield signals in the device is 4-7, the FPGA selects a chip with 8 buffer channels and 8 register channels; the buffer channels include buffer channels 0, 1, 2, …, and 7; the register channels include register channels 0, 1, 2, …, and 7. The buffer channels and the register channels are one-to-one corresponding.

[0034] Further, the buffer channels and the register channels are one-to-one corresponding to the DDS and the signal output unit.

[0035] ​​Specifically, the characteristic parameters of the main signal are written into the buffer channel of the control unit, including the main signal amplitude, main signal delay, main signal pulse width, main signal frequency, main signal bandwidth and main signal frequency modulation slope.

[0036] The remaining buffer channels are each written with the characteristic parameters of the shielding signal, including the shielding signal amplitude, shielding signal delay, shielding signal pulse width, shielding signal frequency, shielding signal bandwidth, and shielding signal frequency modulation slope.

[0037] Furthermore, if there are two cover signals, they are placed in two buffer channels controlled by the same single-pole double-throw switch, and do not share a delay switch with the main signal to avoid mutual interference between the main signal and the cover signal. Fig. 1 The cover signal 1 and cover signal 2 are shown.

[0038] In this embodiment, the amplitude A of each cover signal i All are greater than or equal to the amplitude A0 of the main signal, i.e., A i ≥A0, thereby reducing the probability of the interfering party detecting the radar main signal and effectively protecting the main signal.

[0039] Furthermore, the shielding signal pulses of the input control unit do not overlap with the main signal pulses, thus avoiding mutual interference between the main signal and the shielding signal.

[0040] For example, if there are two cover signals, the typical design is to place the main signal in the middle and have one cover signal before and after it. This can effectively hide the radar main signal and reduce the probability of the interfering party detecting the main signal. At the same time, it is necessary to ensure that the cover signals do not overlap with the main signal.

[0041] To ensure that the cover signal and the main signal do not overlap, the delay of the main signal and the cover signal relative to the synchronization pulse, as well as the pulse width of the main signal and the cover signal, must simultaneously meet the following requirements:

[0042]

[0043] This ensures that the waveforms of both the main signal and the cover signal are not distorted.

[0044] Furthermore, in order to ensure the main signal has the strongest energy and facilitate reception after transmission, the pulse width of the main signal is greater than that of the cover signal, and the overall signal meets the technical parameter requirements for duty cycle.

[0045] For example, the pulse widths of the main signal and the cover signal follow the principles below:

[0046]

[0047] Wherein, n is the number of cover signals, i.e. the main signal pulse width needs to be greater than or equal to the sum of all cover signal pulse widths.

[0048] Further, the main signal and the cover signal of the write control unit are inconsistent in frequency, facilitating the reception of the main signal.

[0049] Further, the bandwidth B0 of the main signal of the write control unit is less than the bandwidth B i , thereby effectively reducing the probability of the radar main signal being detected by the interference party, effectively protecting the main signal.

[0050] In the embodiment, the bandwidths of the main signal and the cover signal follow the following principles:

[0051]

[0052] i.e. the cover signal bandwidth B i is at least greater than or equal to twice the main signal bandwidth B0, so that the clutter signal entering the receiving channel is less, and the probability of the main signal frequency being detected by the interference party is smaller. The main signal and the cover signal bandwidths are selected in the entire working bandwidth, and the signals do not overlap in the frequency domain.

[0053] Exemplarily, if the number of cover signals is 2, the main signal bandwidth is B0, and the bandwidth of the cover signal is B i , the complex waveform frequency domain needs to satisfy:

[0054]

[0055] , thereby ensuring that the cover signal and the main signal also do not overlap in the frequency domain.

[0056] Further, at least one cover signal and the main signal of the write control unit are different in frequency modulation slope, so as to enhance the anti-interference effect of the cover signal.

[0057] When the control unit receives the instruction of issuing the signal, the buffer writes the characteristic parameters of the main signal and the cover signal in the buffer into the corresponding registers, and the registers output the characteristic parameters of the main signal and the cover signal to the DDS.

[0058] The complex waveform generating device of the embodiment further comprises a phase-locked loop, which is connected to the control unit and the direct digital frequency synthesizer. The phase-locked loop can unify the clock signal and ensure the normal operation of each device of the complex waveform generating device. The phase-locked loop can realize stable and high-frequency clock signals, provide clock signals for the control unit and the direct digital frequency synthesizer, and serve as the time reference of the complex waveform generating device.

[0059] Further, the complex waveform generating device of the embodiment further comprises a crystal oscillator, which can generate oscillation current in the circuit, provide stable and accurate single-frequency oscillation, and send a clock signal, thereby providing a standard time for the complex waveform generating device.

[0060] Further, the complex waveform generating device of the embodiment further comprises a power divider, which can divide an input signal into several output signals.

[0061] In the embodiment, the input end of the power divider is connected with the crystal oscillator, and the output end is connected with the control unit and the DDS, thereby enabling the crystal oscillator to provide a standard clock for the control unit and the DDS.

[0062] Further, since the DDS chip can independently generate four point-frequency, sweep-frequency and base-band signals, for a complex waveform generating device with 2-3 cover signals, one DDS chip is included, as shown in FIG. 2; for a complex waveform generating device with 4-7 cover signals, two DDS chips are included. Fig. 1

[0063] Further, the DDS chip comprises a frequency control register, a high-speed phase accumulator and a sine calculator. The DDS chip can output a sine signal with a signal pulse width, a signal frequency, a signal bandwidth and a frequency modulation slope according to the characteristic parameters of the main signal and the cover signals output by the register channel of the control unit.

[0064] Specifically, the frequency control register can load and register the frequency control code input by the control unit in a serial or parallel manner. In the embodiment, the frequency control register can load and register the pulse width, the frequency, the bandwidth and the frequency modulation slope input by the control unit; the high-speed phase accumulator can perform phase accumulation according to the DDS frequency control code in each clock cycle to obtain a phase value, and perform phase accumulation according to the pulse width, the frequency, the bandwidth and the frequency modulation slope written by the register; and the sine calculator calculates the sine amplitude according to the phase accumulation value output by the high-speed phase accumulator, and outputs a digital sine wave.

[0065] Further, the signal output unit comprises a band-pass filter, an attenuator and a single-pole double-throw switch. The band-pass filter and the attenuator correspond to the main signal and the cover signal one by one, that is, correspond to the buffer channels one by one, and each single-pole double-throw switch corresponds to two buffer channels.

[0066] Specifically, the band-pass filter is connected with the DDS, and the sine signal output by the DDS can reduce quantization noise and solve the stray on the signal link after being filtered by the band-pass filter.

[0067] ​Further, the attenuator is connected with the band-pass filter, the attenuator can adaptively attenuate the output signal, prevent signal saturation distortion, thereby outputting the signal meeting the amplitude requirement.

[0068] Further, each single-pole double-throw switch is connected with two attenuators, the signal output from the attenuator opens the single-pole double-throw delay switch according to the delay time requirement, and outputs the corresponding main signal and cover signal.

[0069] The complex waveform generating device of the embodiment can output complex waveforms when the radar is powered on in the interference countermeasure environment, the main signal and the cover signal are randomly arranged, the cover signal generation time, pulse width, signal bandwidth, transmission frequency point, frequency modulation slope and signal number are random, and it is difficult to predict. The signal output by the complex waveform generating device is more difficult to distinguish between true and false, greatly reduces the probability of the jammer intercepting the main signal and the difficulty of correctly implementing the interference, increases the anti-interference means and strategy, and improves the radar anti-interference performance and radar tracking stability.

[0070] The above is only the preferred specific embodiment of the present application, but the protection scope of the present application is not limited to this, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A complex waveform generator resistant to active interference, characterized in that, The system includes a control unit, a direct digital frequency synthesizer (DDS), and a signal output unit. The control unit is connected to the signal output unit via the DDS. Characteristic parameters of the main signal and the cover signal are written into the control unit. The DDS output unit outputs a sinusoidal signal that satisfies the signal characteristics based on these parameters. The signal output unit processes the sinusoidal signal output by the DDS and outputs the corresponding main signal and cover signal. The control unit includes buffer channels and register channels, the number of which corresponds to the number of cover signals. The main signal and the cover signal are randomly arranged; The pulse width of the main signal is Cover signal The pulse width is The period of the radar synchronization signal pulse is Then the duty cycle for: Under the condition of satisfying the duty cycle, select as many cover signals as possible; the main signal is unique, and the number of cover signals is limited. At least 2; The amplitude of each cover signal is greater than or equal to the amplitude of the main signal; when the main signal is in the middle, with one cover signal before and after it, the following conditions must be met: ;in, , , These represent the delays of the main signal, cover signal 1, and cover signal 2 relative to the synchronization pulse, respectively. , These are the pulse widths of the main signal and cover signal 1, respectively; where cover signal 1 comes first and cover signal 2 comes last, and the pulse width of the main signal is greater than or equal to the sum of the pulse widths of all cover signals; The main signal bandwidth written to the control unit is When there are two cover signals, the bandwidth of cover signal 1 is... The bandwidth of cover signal 2 is ;satisfy: , At least one of the shielding signals and the main signal written into the control unit have different frequency modulation slopes; The signal output unit includes a bandpass filter and a single-pole double-throw switch. The bandpass filter is connected to a direct digital frequency synthesizer and corresponds one-to-one with a buffer channel. Each single-pole double-throw switch corresponds to two buffer channels. When there are two cover signals, the two cover signals are placed in the two buffer channels controlled by the same single-pole double-throw switch and do not share a delay switch with the main signal.

2. The complex waveform generator with resistance to active interference according to claim 1, characterized in that, It also includes a phase-locked loop (PLL) that connects the control unit and the direct digital frequency synthesizer.

3. The complex waveform generator with resistance to active interference according to claim 2, characterized in that, It also includes a crystal oscillator and a power divider, wherein the input of the power divider is connected to the crystal oscillator and the output is connected to the control unit and the direct digital frequency synthesizer, respectively.

4. The complex waveform generator with resistance to active interference according to claim 1, characterized in that, The direct digital frequency synthesizer includes a frequency control register, which can be loaded with pulse width, frequency, bandwidth and modulation slope input from the control unit.

5. The complex waveform generator with resistance to active interference according to claim 4, characterized in that, The direct digital frequency synthesizer also includes a high-speed phase accumulator, which can perform phase accumulation based on the pulse width, frequency, bandwidth, and frequency modulation slope written to the register.

6. The complex waveform generator with resistance to active interference according to claim 5, characterized in that, The direct digital frequency synthesizer also includes a sine calculator, which calculates the sine wave amplitude based on the phase accumulation value output by the high-speed phase accumulator and outputs a digital sine wave.

7. The complex waveform generator with resistance to active interference according to claim 6, characterized in that, The signal output unit also includes an attenuator connected to a bandpass filter, which is capable of adaptively attenuating the output signal.

8. The complex waveform generator with resistance to active interference according to claim 7, characterized in that, Each of the single-pole double-throw switches is connected to two attenuators.

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