Accelerating system and dynamic configuration method thereof

Abstract

An acceleration system includes a plurality of modules. Each of the plurality of modules includes at least one central processing unit, at least one graphics processing unit, at least one field programmable gate array, or at least one application specific integrated circuit. At least one of the plurality of modules includes at least one other of the plurality of modules such that the acceleration system is structured in a nested hierarchy.

Description

Technical Field

[0001] This invention refers to an acceleration system and its dynamic configuration method, particularly an acceleration system and its dynamic configuration method that can reduce hardware acceleration costs and improve performance. Background Technology

[0002] Based on the known operation of network devices, network devices can be classified as Radio Units (RU), Distributed Units (DU), Central Units (CU), or Core Network Servers, but are not limited to these.

[0003] Fifth-generation mobile networks (5G) employ different types of hardware acceleration across different network devices. For example, radio units and distribution units require baseband processing cards (such as forward error correction (FEC) accelerators) and security cards (such as TLS / IPSec); central units require security cards; and core network servers require security cards (such as TLS accelerators) and next-generation firewall cards (such as Layer 5 and above scanning acceleration cards).

[0004] However, there is a need to improve the hardware acceleration of existing network devices in terms of reducing hardware acceleration costs and improving performance. Summary of the Invention

[0005] Therefore, the present invention mainly provides an acceleration system and its dynamic configuration method to reduce hardware acceleration costs and improve performance.

[0006] The present invention also discloses an acceleration system comprising a plurality of modules, wherein each of the plurality of modules includes at least a central processing unit, at least a graphics processing unit, at least a field-programmable gate array, or at least an application-specific integrated circuit, wherein at least one of the plurality of modules includes at least another of the plurality of modules, such that the acceleration system is structured and nested.

[0007] The present invention also discloses an acceleration system, comprising a cyclic causal model providing first information based on a first sequence of data, the first sequence of data including a first input data at a first point in time; and configuring the number, hierarchy, or type of a plurality of modules of the acceleration system based on the first information to accelerate the processing of a second input data at a second point in time. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the acceleration system according to Embodiment 1 of the present invention.

[0009] Figure 2 and Figure 3 These are schematic diagrams of the cyclic structure causal model of Embodiment 1 of the present invention.

[0010] Figure 4 This is a flowchart of the optimization method according to Embodiment 1 of the present invention.

[0011] Figure 5 This is a schematic diagram of the dynamic configuration method according to Embodiment 1 of the present invention.

[0012] Figure 6 This is a schematic diagram of the implementation method of Embodiment 1 of the present invention.

[0013] Figure 7 This is a schematic diagram of the communication system according to Embodiment 1 of the present invention.

[0014] Explanation of reference numerals in the attached figures:

[0015] 10: Acceleration System

[0016] 110-140: Modules

[0017] 110b~130b: Bus

[0018] 110CPUhw: Central Processing Unit

[0019] 120 GPU: Graphics Processing Unit

[0020] 130FPGA: Field Programmable Gate Array

[0021] 140ASIC: Application-Specific Integrated Circuit

[0022] 210Pt+2: Labels

[0023] 210Pt-n~210Pt+1: Input

[0024] 220SCM1~220SCM3,320SCM2-n~320SCM2: Structural Causal Layer

[0025] 220X2-n~220X3: Input layer

[0026] 220Y2-n~220Y3: Output Layer

[0027] 230M1, 230M2, 330M2-n~330M2: Parameters

[0028] 40: Optimization Methods

[0029] 50: Dynamic Configuration Method

[0030] 60: Implementation Methods

[0031] 602: Solid State Drive

[0032] 604: Mapped main memory

[0033] 606: Hardware Description Language

[0034] 608: Hardware Acceleration Simulation Layer

[0035] CU: Central Unit

[0036] DU: Distribution Unit

[0037] RU: Radio Unit

[0038] S400~S410, S500~S510: Steps Detailed Implementation

[0039] The terms "first," "second," etc., used throughout this specification are merely for distinguishing different components and do not impose any restrictions on their order. The described embodiments can be combined in various ways without contradiction.

[0040] Figure 1 This is a schematic diagram of the acceleration system 10 according to an embodiment of the present invention. The acceleration system 10 can dynamically adjust the hardware acceleration type and hierarchy according to the input data to reduce hardware acceleration costs and improve performance.

[0041] A device (such as a network device mentioned in the prior art, but not limited thereto) may correspond to an acceleration system 10 of the present invention. The hardware and software of the device may be configured according to the acceleration type and hierarchy of the acceleration system 10 (i.e. how input data is processed by the hardware and software of the device).

[0042] The acceleration system 10 can be structured. For example... Figure 1 As shown, an acceleration system 10 may contain multiple modules 110 to 140, forming a hierarchy or sequence. For example, the acceleration system 10 may be divided into at least one module 110, and each module 110 to 130 may contain at least one module 120 to 140. In other words, the acceleration system 10 is structured and nested in layers.

[0043] A module may contain (or correspond to) at least one Central Processing Unit (CPU) 110CPUhw, at least one Graphics Processing Unit (GPU) 120GPU, at least one Field Programmable Gate Array (FPGA) 130FPGA, or at least one Application Specific Integrated Circuit (ASIC) 140ASIC.

[0044] Therefore, on the other hand, at the same level, some modules (e.g., module 110) use slower hardware (e.g., CPU 110 CPUhw) at the current level for acceleration, while other modules (e.g., another module 110) use faster hardware (e.g., graphics processing unit 120 GPU) at the next lower level for acceleration. In other words, the processing that a module can perform can be divided into processing that can be performed by at least two different types of hardware. For example, the processing that module 110 can perform can be divided into processing that can be performed by CPU 110 CPUhw and processing that can be performed by GPU 120.

[0045] The device receives input data, and the acceleration system 10 can accelerate the processing of the input data. For example, the acceleration system 10 can perform pure software processing on the input data (e.g., using the pure software instruction 110CPUsw of the acceleration system 10) or hardware processing (e.g., using the hardware-accelerated instructions of the central processing unit 110CPUhw).

[0046] The input data can be structured. In this invention, a clustering algorithm can be used to group the structured input data into different groups. The clustering algorithm can be, for example, K-Means, but is not limited to this. The number of groups can be related to the total number of the central processing unit 110 CPUhw, graphics processing unit 120 GPU, field-programmable gate array 130 FPGA, and application-specific integrated circuit 140 ASIC. For example, the number of groups can be less than or equal to the total number of the central processing unit 110 CPUhw, graphics processing unit 120 GPU, field-programmable gate array 130 FPGA, and application-specific integrated circuit 140 ASIC, but is not limited to this.

[0047] Each group can be associated with a module of the acceleration system 10, thus the input data can be processed by different modules. For example, some input data can be processed using the pure software instruction 110 CPUsw of the acceleration system 10, some input data can be associated with module 110 (i.e., assigned to module 110) and processed by the central processing unit 110 CPUhw, some input data can be associated with module 120 (i.e., assigned to module 120) and processed by the graphics processing unit 120 GPU, some input data can be associated with module 130 (i.e., assigned to module 130) and processed by the field-programmable gate array 130 FPGA, and some input data can be associated with module 140 (i.e., assigned to module 140) and processed by the application-specific integrated circuit 140 ASIC. Since different hardware has different processing speeds, for example, the graphics processing unit 120 GPU is advantageous for accelerating image processing operations, so the module and hardware used for acceleration can be determined according to the type of input data. Thus, the structure of the modules of the acceleration system 10 can be associated with the structured information of the input data.

[0048] In order to dynamically adjust the acceleration type and hierarchical structure in response to structured input data, the acceleration system 10 can dynamically configure the acceleration type and hierarchical structure of the acceleration system 10 based on the recurrent structural causal model (RNN) combined with the structural causal model (SCM), thereby utilizing different modules of the acceleration system 10 to process input data divided into different groups.

[0049] The cyclic causal model is based on causal relationships rather than just statistical associations. Because the cyclic causal model can find structured causal relationships in the input data, it can more accurately determine the better acceleration type and hierarchy, so that the acceleration type and hierarchy of the acceleration system 10 can ensure lower acceleration costs and higher performance.

[0050] The cyclic causal model analyzes input data at different points in time, rather than just processing the current input data, thus providing more accurate predictions. This allows the acceleration type and hierarchical structure of the acceleration system 10 to ensure lower acceleration costs and higher performance at different points in time.

[0051] For example, Figure 2This is a schematic diagram of a cyclic causal model 20 according to an embodiment of the present invention. The cyclic causal model 20 can provide structured information to describe the acceleration system 10. The cyclic causal model 20 may include input layers 220X1 to 220X3, structural causal layers 220SCM1 to 220SCM3, and output layers 220Y1 to 220Y3. Input layer 220X1 can receive input 210Pt-1, which may be related to the input data of the device at time t-1. Input layer 220X2 can receive input 210Pt output by output layer 220Y1, which may be related to the input data of the device at time t. Input layer 220X3 can receive input 210Pt+1 output by output layer 220Y2 and output label 210Pt+2. Label 210Pt+2 can contain information about the acceleration type and hierarchical structure of the acceleration system 10 at time t+1. Therefore, the cyclic causal model 20 can dynamically configure the acceleration type and hierarchical structure of the acceleration system 10, thereby using different modules of the acceleration system 10 to process different groups of input data.

[0052] In one embodiment, time point t is the current time point. Inputs 210Pt-1 and 210Pt are related to the input data of the device at the previous time point and the input data at the current time point, respectively. Tag 210Pt+2 may contain information about the acceleration type and hierarchical structure of the acceleration system 10 at the next time point (i.e., time point t+1), but is not limited thereto. In other words, the cyclic causal model 20 can predict the acceleration type and hierarchical structure of the acceleration system 10 at the next time point (i.e., time point t+1) to pre-configure the acceleration type and hierarchical structure of the acceleration system 10. Before the input data at the next time point (i.e., time point t+1) is input to the device, the device's hardware and software can be pre-configured according to the acceleration type and hierarchical structure of the acceleration system 10 corresponding to the next time point (i.e., time point t+1). After the input data at the next time point (i.e., time point t+1) is input to the device, the device's hardware and software can be slightly adjusted according to the acceleration type and hierarchical structure of the acceleration system 10 corresponding to the next time point (i.e., time point t+1) or need not be reconfigured because there is no change.

[0053] In another embodiment, time point t+1 can also be the current time point. Inputs 210Pt-1, 210Pt, and 210Pt+1 are respectively related to the input data of the device at the previous time point, the input data at the previous time point, and the input data at the current time point. Tag 210Pt+2 may contain information about the acceleration type and hierarchy of the acceleration system 10 at the current time point.

[0054] Figure 3This is a schematic diagram of a cyclic causal model 30 according to an embodiment of the present invention. The cyclic causal model 30 may include an input layer 220X2-n~220X3, a structural causal layer 320SCM2-n~320SCM3, and an output layer 220Y2-n~220Y3, where n is a positive integer.

[0055] exist Figure 3 The inputs 210Pt-n to 210Pt can be associated with the device's input data at time points tn to t, respectively. In one embodiment, one of the inputs 210Pt-n to 210Pt can be the device's input data at one of the time points tn to t. In another embodiment, one of the inputs 210Pt-n to 210Pt can be a correlation structure diagram of the input data at time points tn to t, grouped into different groups.

[0056] Inputs 210Pt-1 and 210Pt are related to the input data of the device at time t-1 and time t, respectively. Therefore, input 210Pt-n is at least related to the input data of the device at time t-1 and time t. In other words, the cyclic causal model 30 can receive time series data, that is, it can receive input data at multiple time points.

[0057] The structural causal layers 320SCM2-n to 320SCM2 can involve causal relationships. Figure 3 The structural causal layers 320SCM2-n to 320SCM2 respectively pass parameters 330M2-n to 330M2 to the adjacent structural causal layers 320SCM3-n to 320SCM3. In other words, a parameter at a certain point in time can be passed to the next point in time. In one embodiment, the parameters 330M2-n to 330M2 can be probabilities rather than weights, but are not limited to this.

[0058] exist Figure 3 The label 210Pt+2 may contain information about the acceleration type and hierarchical structure of the acceleration system 10 at time point t+1. In one embodiment, label 210Pt+2 may be a graph. In another embodiment, label 210Pt+2 may contain a structural diagram of the acceleration system 10. For example, label 210Pt+2 may contain information about what each module corresponds to, the number of corresponding central processing units 110 (CPUhw), the number of corresponding graphics processing units 120 (GPU), the number of corresponding field-programmable gate arrays 130 (FPGA), the number of corresponding application-specific integrated circuits 140 (ASIC), or the connection or nesting method between modules 110-140. Label 210Pt+2 may contain structured information that offers lower acceleration costs and higher performance.

[0059] Further, please refer to Figure 4 . Figure 4 This is a flowchart of an optimization method 40 according to an embodiment of the present invention. The optimization method 40 can be compiled into program code and executed by a processing circuit, and stored in a storage circuit. The optimization method 40 may include the following steps:

[0060] Step S400: Begin.

[0061] Step S402: Use the causal discovery algorithm to generate a causal graph.

[0062] Step S404: Verify the cause-effect graph.

[0063] Step S406: Use the validated causal graph to train the cyclic causal model 20 or 30.

[0064] Step S408: Make predictions using the trained cyclic causal model 20 or 30.

[0065] Step S410: End.

[0066] In detail, the causal discovery algorithm can extract causal relationships from the input data. In step S402, a causal graph can be generated from the input data to the device using the causal discovery algorithm. The causal discovery algorithm can be, for example, Fast Causal Inference (FCI) or Fast Greedy Equivalence Search (FGES), but is not limited to these.

[0067] The causal graph generated in step S402 can be a hypothesized causal relationship, and therefore can be verified in step S404. In one embodiment, a structural causal model can be used to verify the causal graph, thus leaving only the true causal relationships. In another embodiment, a first number of samples (e.g., 20) can be used to verify whether the first variable is a cause of the second variable, and a second number of samples (e.g., 400) can be used to verify whether the second variable is a cause of the first variable. If the second number is much larger than the first number, it means that the first variable should be a cause of the second variable, and the second variable should not be a cause of the first variable. That is, if the required number of samples is small, it can be determined that the direction of the causal graph is correct. In another embodiment, if the ground-truth data of the causal graph is available, the ground-truth data can be used to determine whether the causal graph generated in step S402 is correct.

[0068] In step S406, the validated causal graph can be input into the untrained recurrent causal model 20 or 30, and the output of the recurrent causal model 20 or 30 can be compared with the known basis data. For example, the error between the output of the recurrent causal model 20 or 30 and the known basis data can be minimized (e.g., minimizing the mean squared error), so that the output of the recurrent causal model 20 or 30 gradually approaches the known basis data, thereby optimizing the parameters and completing the training. The known basis data may correspond to a low-cost and high-performance target output.

[0069] In step S408, prediction can be made using the trained recurrent causal model 20 or 30. The prediction (i.e., label 210Pt+2) based on the output of the recurrent causal model 20 or 30 can contain information about the acceleration type and hierarchical structure of the acceleration system 10. The recurrent causal model 20 or 30 can dynamically configure the acceleration type and hierarchical structure of the acceleration system 10, thereby using different modules of the acceleration system 10 to process different groups of input data.

[0070] In one embodiment, one of steps S402 to S408 may be selectively omitted.

[0071] Further, please refer to Figure 5 . Figure 5 This is a flowchart of a dynamic configuration method 50 according to an embodiment of the present invention. The dynamic configuration method 50 can be compiled into program code and executed by a processing circuit, and stored in a storage circuit. The dynamic configuration method 50 may include the following steps:

[0072] Step S500: Begin.

[0073] Step S502: The cyclic causal model 20 or 30 provides first information based on a first sequence of data, wherein the first sequence of data includes a first input data at a first point in time.

[0074] Step S504: Based on the first information, configure the number, hierarchy, or type of modules 110 to 140 of the acceleration system 10 to accelerate the processing of a second input data at a second time point.

[0075] Step S506: The cyclic causal model 20 or 30 provides a second piece of information based on a second sequence of data, wherein the second sequence of data contains second input data at a second point in time.

[0076] Step S508: Based on the second information, configure the number, hierarchy, or type of modules 110 to 140 of the acceleration system 10 to accelerate the processing of a third input data at a third time point.

[0077] Step S510: End.

[0078] As can be seen from the dynamic configuration method 50, the acceleration system 10 is used to accelerate the processing of the first input data, the second input data, or the third input data, and the number, hierarchy, or type of the modules 110 to 140 of the acceleration system 10 can be dynamically configured according to the cyclic structure causal model 20 or 30.

[0079] In detail, in steps S502 and S506, as described above, the input to the cyclic causal model 20 or 30 can be time series data at multiple time points. For example, the first sequence data includes first input data at a first time point and third input data at a third time point, where the third time point is earlier than the first time point; similarly, the second sequence data includes first input data at a first time point and second input data at a second time point, where the first time point is earlier than the second time point.

[0080] The first information output by the cyclic causal model 20 or 30 may correspond to a second time point, and the first information may include the number, hierarchical structure, or type of modules 110-140 corresponding to the second time point. Similarly, the second information output by the cyclic causal model 20 or 30 may correspond to a fourth time point, and the second information may include the number, hierarchical structure, or type of modules 110-140 corresponding to the fourth time point, where the second time point is earlier than the fourth time point. Therefore, the acceleration system 10 can be dynamically configured according to the first or second information. In one embodiment, the hierarchical structure may relate to the connection relationship, hierarchical relationship, or nesting relationship of modules 110-140. In one embodiment, the type may relate to the type of circuit, such as a central processing unit or a graphics processing unit.

[0081] In steps S504 and S508, as described above, the first input data, the second input data, or the third input data can be divided into multiple groups. These groups correspond to modules 110 to 140 of the acceleration system 10, and modules 110 to 140 of the acceleration system 10 process the corresponding groups. For example, please refer to... Figure 1 Module 110 includes module 120. Therefore, module 110 can perform different processes, which can be divided into processes that can be performed by the central processing unit 110 (CPU) and processes that can be performed by the graphics processing unit 120 (GPU). A first group of these groups can, for example, correspond to module 110. Input data (e.g., second input data) can be assigned to a first group, a portion of which can be processed by module 110, and another portion of which can be processed by module 120. The processing speed of module 110 can be faster than that of module 120.

[0082] In one embodiment, one of steps S502 to S508 may be selectively omitted.

[0083] Figure 6 This is a schematic diagram of method 60 in Embodiment 1 of the present invention.

[0084] In one embodiment, each of modules 110-140 may be described by a hardware description language (HDL) 606. After performing a hardware design using the hardware description language 606, an integrated circuit can be manufactured or programmed accordingly. The hardware description language 606 may be, for example, VHDL or Verilog, but is not limited to these.

[0085] The hardware description language 606 of the files in the solid-state disk (SSD) 602 can be mapped to the main memory 604 and read by the hardware acceleration simulation layer 608 to implement the acceleration system 10.

[0086] Therefore, the acceleration system 10 corresponds to a circuit board equipped with a central processing unit 110CPUhw, a graphics processing unit 120GPU, a field-programmable gate array 130FPGA, and an application-specific integrated circuit 140ASIC. The central processing unit 110CPUhw supports both pure software instructions 110CPUsw and hardware acceleration instructions. While the arrangement of the central processing unit 110CPUhw, graphics processing unit 120GPU, field-programmable gate array 130FPGA, and application-specific integrated circuit 140ASIC on the circuit board cannot be adjusted over time, the structuring of these components into the acceleration system 10 can be adjusted over time. This allows the acceleration type and hierarchical structure of the acceleration system 10 to be dynamically configured over time, thereby reducing acceleration costs and improving performance while distributing input data between the device's hardware and software for processing.

[0087] The acceleration system 10 of this invention is an embodiment of the invention, and those skilled in the art can make different changes and modifications accordingly. For example, Figure 1 and Figure 6As shown, the central processing unit 110 CPUhw and the graphics processing unit 120 GPU can be connected by a bus 110b, which can be a memory bus. The graphics processing unit 120 GPU and the field-programmable gate array 130 FPGA can be connected by a bus 120b, and the field-programmable gate array 130 FPGA and the application-specific integrated circuit 140 ASIC can be connected by a bus 130b. Buses 120b and 130b can be PCI Express (PCIe) buses, but are not limited to these.

[0088] Figure 7 This is a schematic diagram of the communication system 70 according to Embodiment 1 of the present invention.

[0089] The apparatus of the present invention can be a network device, for example... Figure 7 The radio unit (RU), distributed unit (DU), central unit (CU), or core network server shown, but not limited to these, are examples.

[0090] In 5G mobile networks, the types of input data can differ between different network devices. Taking the uplink as an example, the input data of the radio unit (RU) is individually encrypted and demodulated; the input data of the distributed unit (DU) is doubly encrypted and modulated; the input data of the central unit (CU) is doubly encrypted and demodulated; and the input data of the core network server is individually encrypted and demodulated. Because the types of input data can differ between different network devices, different network devices may require different acceleration types and hierarchical structures, corresponding to different acceleration systems 10. A cyclic causal model 20 or 30 can ensure that each network device has a suitable acceleration type and hierarchical structure.

[0091] On the other hand, the types of input data for different network devices may differ; however, the types of input data for a single network device may be the same at different times. The type of input data for a network device can be related to the source device of the input data. For example, in Figure 7 The source device for input data is a camera. However, if the source device is changed to a wearable device, the type of input data may change, which in turn changes the acceleration type and hierarchy of the acceleration system 10 corresponding to the input data.

[0092] In summary, the acceleration system of this invention can dynamically provide hardware acceleration types and hierarchical structures according to user scenarios, thereby reducing hardware acceleration costs and improving performance. The prediction of the cyclic causal model of this invention can include the acceleration type and hierarchical structure of the acceleration system with optimal cost and performance. The cyclic causal model of this invention can be trained using time series data to predict which acceleration type and hierarchical structure of the acceleration system is most suitable for the input data at a given time point, thereby reducing costs and optimizing performance.

[0093] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. An acceleration system, comprising: Multiple modules, wherein each of the multiple modules includes at least one central processing unit, at least one graphics processing unit, at least one field-programmable gate array, or at least one application-specific integrated circuit. Wherein, at least one of the plurality of modules includes at least another of the plurality of modules, such that the acceleration system is structured and nested in layers; The number, hierarchy, or type of the multiple modules of the acceleration system is dynamically configured according to a cyclic causal model; The acceleration system is used to accelerate the processing of input data. The input of the cyclic causal model is related to the input data at a first point in time. The output of the cyclic causal model corresponds to information at a second point in time. The information includes the number, hierarchy, or type of the multiple modules. The acceleration system is dynamically configured based on this information.

2. The acceleration system as claimed in claim 1, wherein, Input data is divided into multiple groups, which correspond to multiple modules of the acceleration system. Each module of the acceleration system processes the corresponding multiple groups.

3. The acceleration system as described in claim 2, wherein, The input data is divided into multiple groups based on a clustering algorithm.

4. The acceleration system as described in claim 2, wherein, The first module of the plurality of modules includes a second module of the plurality of modules, a first group of the plurality of groups corresponds to the first module, the input data of the first group of the input data is assigned to the first group, a part of the input data of the first group is processed by the first module, and another part of the input data of the first group is processed by the second module.

5. The acceleration system as described in claim 4, wherein, The first module processes data faster than the second module.

6. The acceleration system as claimed in claim 1, wherein, The input to the cyclic causal model is a time series data, which includes the input data at the first time point and a third input data at a third time point, which is earlier than the first time point.

7. The acceleration system as claimed in claim 6, wherein, The second point in time is later than the first point in time.

8. The acceleration system as claimed in claim 1, wherein, A causal graph is generated and verified using a causal discovery algorithm. The verified causal graph is then used to train the causal model of the loop structure.

9. A dynamic configuration method for an acceleration system, comprising: A cyclic causal model provides first information based on a first sequence of data, which includes first input data at a first point in time. as well as Based on the first information, the number, hierarchy, or type of multiple modules of the acceleration system are configured to accelerate the processing of a second input data at a second time point. The first information includes the number, hierarchy, or type of the multiple modules corresponding to the second time point. The recurrent structural causal model is a combination of a recurrent neural network and a structural causal model, used to dynamically configure the acceleration type and hierarchical structure of the acceleration system. The training process of the cyclic causal model includes: Generate a causal graph using a causal discovery algorithm; Verify the causal graph; Use the validated causal graph to train the causal model of the loop structure.

10. The dynamic configuration method as described in claim 9, wherein, Each of the plurality of modules in the acceleration system includes at least one central processing unit, at least one graphics processing unit, at least one field-programmable gate array, or at least one application-specific integrated circuit. At least one of the plurality of modules includes at least another of the plurality of modules, such that the acceleration system is structured and nested.

11. The dynamic configuration method as described in claim 9, wherein, The second input data is divided into multiple groups, which correspond to multiple modules of the acceleration system. The multiple modules of the acceleration system process the corresponding multiple groups respectively.

12. The dynamic configuration method as described in claim 11, wherein, The second input data is divided into multiple groups according to the clustering algorithm.

13. The dynamic configuration method as described in claim 11, wherein, The first module of the plurality of modules includes a second module of the plurality of modules, a first group of the plurality of groups corresponds to the first module, the input data of the first group of the second input data is assigned to the first group, a part of the input data of the first group is processed by the first module, and another part of the input data of the first group is processed by the second module.

14. The dynamic configuration method as described in claim 13, wherein, The first module processes data faster than the second module.

15. The dynamic configuration method as described in claim 9, further comprising: The cyclic causal model provides a second piece of information based on a second sequence of data, which includes the second input data at the second point in time. as well as Based on the second information, the number, hierarchy, or type of the multiple modules of the acceleration system are configured to accelerate the processing of a third input data at a third point in time.

16. The dynamic configuration method as described in claim 15, wherein, The first sequence data includes the first input data at the first time point and the third input data at the third time point. The second sequence data includes the first input data at the first time point and the second input data at the second time point. The third time point is earlier than the first time point.

17. The dynamic configuration method as described in claim 15, wherein, The second information includes the number, hierarchy, or type of the multiple modules corresponding to the third point in time.

18. The dynamic configuration method as described in claim 9, wherein, A causal graph is generated and verified using a causal discovery algorithm. The verified causal graph is then used to train the causal model of the loop structure.

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