A method and apparatus for texture mapping hardware acceleration

Abstract

In order to further improve the quality of texture mapping and solve the problem of large dynamic random memory bandwidth consumption and data efficiency bottleneck, the application provides a method and device for texture mapping hardware acceleration, which improves the method of output pixel texture mapping to texture pixel points, replaces the bilinear interpolation with bicubic interpolation, and designs a static memory as a multi-path group associative cache, which can set different cache layers according to different application scenarios to reduce the consumption of memory resources, and effectively reduce the redundant bandwidth. The application can flexibly configure the texture cache hierarchy size according to the required texture mapping scene, realize the hardware acceleration of texture mapping through bicubic interpolation, and is suitable for various types of three-dimensional graphics systems.

Description

A method and apparatus for hardware acceleration of texture mapping Technical Field

[0001] This invention relates to the field of computer graphics, and more particularly to a method for using hardware acceleration for texture mapping and an apparatus for implementing this method. Background Technology

[0002] Texture mapping is a concept introduced in computer graphics to provide a high degree of visual realism in certain desired scenarios, such as game backgrounds that only provide visual context. Drawing drawing elements with realistic effects may not be a necessary task in these cases. Instead, image fragments representing the elements can be used to create the illusion that the elements are drawn into the scene. The simplicity and popularity of this technique have made it a favorite of graphics software developers and graphics hardware manufacturers.

[0003] Texture mapping is defined as a method for altering surface properties point-to-point to provide the appearance of surface details that do not actually exist in the surface geometry. Texture mapping uses texture coordinates to find one or more texel values ​​within the texture map. The mapped pixel values ​​are then interpolated from these texel values ​​to update fragments. The update method is determined by the current texture environment mode; depending on the filtering method, the memory and computational costs of texture mapping operations vary. In texture filtering, the lookup pattern is irregular, requiring separate calculations of samples, which makes reconstructing filters extremely expensive. Typically, filters used in texture mapping employ bilinear interpolation. In many systems, retrieving four texel values ​​from texture data presents memory and time latency bottlenecks. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and apparatus for hardware acceleration of texture mapping, so as to better reduce the problem of large redundant bandwidth in existing texture mapping.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] In a first aspect, the present invention provides a method for hardware acceleration of texture mapping, comprising:

[0007] The texture coordinates are calculated sequentially by using the texture coordinate function to map the texture coordinates of each point of the output coordinates to the texture image, thus obtaining the interpolated coordinates after texture mapping.

[0008] The interpolated coordinates after texture mapping are first matched with the address labels of the texture cache. For valid matches, the corresponding data is retrieved from the matched texture cache. For unmatched or invalid matches, the corresponding data is retrieved from the dynamic random access memory. At the same time, the retrieved data is stored in the texture cache with the corresponding updated address label. Finally, the interpolated pixel points are calculated by outputting the texture pixel data of the sixteen neighboring points.

[0009] Therefore, it can be seen that by using the texture mapping relationship from two-dimensional image to three-dimensional image, the texture pixels required for texture coordinate interpolation are retrieved from random access dynamic memory and stored in texture cache memory. If the texture coordinate interpolation point matches the address stored in texture cache memory, it is possible to access the sixteen texture pixels required for bicubic interpolation in only one cycle, thereby realizing hardware-accelerated texture mapping.

[0010] Furthermore, the matching is divided into two levels, including matching of multi-level inter-group aligned addresses and matching of intra-group offset addresses. Both the outer layer and the intra-group have valid flag bits, indicating that the read data command corresponding to the address has been sent to the dynamic random access memory. The condition for a neighboring point to match is that both flag bits are valid.

[0011] Therefore, it can be seen that using a hierarchical matching method can effectively reduce the layer overhead of the texture cache memory and improve the utilization of each layer of memory.

[0012] Furthermore, the address tags of the texture cache are updated using the least recently used method, and a counter is set for each address tag;

[0013] The memory address tag update status is determined by adjusting the size of the counter for different matching scenarios.

[0014] Furthermore, the step of adjusting the counter size to determine the memory address tag update status for different matching conditions includes:

[0015] If both the outer layer and the group address match and are valid, take the counter value of the corresponding address label. Decrement the counter value of the address label with a value greater than the value by one, and keep the counter value with a value less than the value unchanged. Then set the value of the counter to the maximum.

[0016] If the outer layer fails to match or the match is invalid, take the address tag whose current counter is zero, decrement all other counter values ​​by one, set the counter value to the maximum, and then send the address to the dynamic random access memory. If the command is sent effectively, update the address tag to the currently unmatched address, and the corresponding outer layer and group flag positions are valid.

[0017] If the outer address matches and is valid, but the address within the group does not match, the method for adjusting the counter value is the same as if both the outer and group addresses match and are valid. In addition, the corresponding unmatched address needs to be sent to the dynamic random access memory. If the command is sent validly, the group flag of the corresponding address tag will be set to valid.

[0018] Therefore, it can be seen that by updating the address tag counter of each layer, the value of the least frequently used value in the recent period can be used each time an unmatched address tag is updated, which effectively improves the update efficiency of the texture cache memory.

[0019] Furthermore, when an unmatched address needs to be sent to the dynamic random access memory (DRAM), it is necessary to determine whether the transmission can proceed normally. A set of data command judgment conditions is used, and a first-in-first-out (FIFO) data buffer is used to store the data retrieved from the DRAM. The real-time depth of the command and data is calculated. If it is less than the depth of the buffer, the read command is sent to the DRAM normally.

[0020] Furthermore, the matching results are all determined by a numerical comparator comparing the addresses of the currently aligned neighboring points with the address tags of the texture cache memory. The number of address tags depends on the different texture mapping complexities.

[0021] Furthermore, the texture cache memories are all multi-way set-associative cache memories, and their address mapping method is: fully associative mapping between groups and direct mapping within groups.

[0022] In a second aspect, the present invention provides an apparatus for hardware acceleration of texture mapping, comprising:

[0023] The calculation unit is used to calculate the coordinate points of the output image through texture mapping and bicubic interpolation to obtain sixteen interpolated texture coordinate points, and to perform alignment processing on these interpolated neighboring points;

[0024] The matching unit is used to match the coordinates of adjacent points after alignment with the address tags in the texture cache memory. It is divided into outer layer matching and intra-group matching.

[0025] The update unit is used to update the counter values ​​of different address tags for different matching situations. It processes the matching situation of sixteen texture coordinate interpolation neighbor points in the same cycle, updates the address tags, and retrieves the corresponding data from the dynamic random access memory according to the unmatched address information and updates the texture cache memory of the corresponding address tag.

[0026] The output unit is used to output the data of image pixels. The data of the image pixels is calculated as follows: each address tag corresponds to a different texture cache memory unit, the matching information of the neighboring points is obtained, the data of the neighboring points is obtained from the texture cache memory of the corresponding address tag, and the data of the output image pixels is obtained by interpolation calculation.

[0027] Therefore, it can be seen that the number of address tags in the matching unit is consistent with the number of layers in the set-associative multiplexed cache unit, which can adapt to texture mapping of different complexities. The texture caches mentioned above are all set-associative multiplexed caches, and their address mapping method is: fully associative mapping between groups and direct mapping within groups.

[0028] Furthermore, the aforementioned texture mapping hardware acceleration device also includes:

[0029] The matching status storage unit is used to record information such as the updated address label and offset address that were matched or not matched;

[0030] The address command storage unit is used to cache data request commands that are not matched due to untimely bus response;

[0031] Unmatched data storage unit, used to temporarily store unmatched data retrieved from random access memory;

[0032] The matching status storage unit, address command storage unit, and unmatched data storage unit are all first-in-first-out data caches.

[0033] Furthermore, the texture cache memory is a type of multiplexed set-associative cache memory, and its address mapping method is as follows: fully associative mapping is used between sets, and direct mapping is used within sets.

[0034] Compared with the prior art, the advantages of this invention are as follows:

[0035] To further improve the quality of texture mapping and address the bottlenecks of high bandwidth consumption and data efficiency in dynamic random access memory, this invention improves the method of mapping textures from output pixels to texture pixels by replacing bilinear interpolation with bicubic interpolation and designing the static memory as a multi-way set-associative cache. This not only allows for setting different cache layers according to different application scenarios to reduce memory resource consumption, but also effectively reduces redundant bandwidth. Attached Figure Description

[0036] Figure 1 is a flowchart illustrating an embodiment of the texture mapping hardware acceleration method of the present invention;

[0037] Figure 2 illustrates the equivalent calculation method for sixteen neighboring points provided in an embodiment of the hardware acceleration method for texture mapping of the present invention.

[0038] Figure 3 illustrates an LRU update method 1 provided in an embodiment of the hardware acceleration method for texture mapping according to the present invention.

[0039] Figure 4 illustrates the LRU update method two provided in the embodiment of the texture mapping hardware acceleration method of the present invention;

[0040] Figure 5 is a schematic diagram of the structure of an embodiment of the hardware acceleration device for texture mapping of the present invention. Detailed Implementation

[0041] Example:

[0042] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0043] The general overview of the texture mapping hardware acceleration method provided in this embodiment is as follows: When the image coverage area is smaller than the texture pixels, the texture mapping hardware acceleration process first calculates the coordinates of each point mapped to the texture image using texture coordinate functions. To improve the quality of the interpolated image, the commonly used bilinear interpolation is replaced with bicubic interpolation. The interpolated coordinates after texture mapping are first matched with the address tags of a set-associative cache (NAS). For valid matches, the corresponding data is retrieved from the matched NAS. For unmatched or invalid matches, the corresponding data is retrieved from dynamic random access memory (DRAM). Simultaneously, the address tags are updated using the least recently used algorithm, and the retrieved data is stored in the NAS corresponding to the updated address tag. Finally, the interpolated pixel points are calculated using the sixteen neighboring texture pixel data. The set-associative cache is configured with eight cache lines within a set, each 32 bytes in size. The texture cache mentioned in this application is an abbreviation for set-associative cache.

[0044] Specifically, as shown in Figure 1, step S101 is first executed. Sixteen neighboring points corresponding to the equivalent coordinates of the texture vector coordinates are calculated using bicubic interpolation. These sixteen neighboring points are then aligned, with the horizontal coordinates aligned to 32 and the vertical coordinates aligned to 4, resulting in sixteen aligned neighboring points. After optimization, four equivalent neighboring point values ​​are obtained. The specific method is as follows: The coordinates of the center point are taken as (u, v). The coordinates of the sixteen neighboring points are shown in Figure 2a. The bit width of the horizontal and vertical coordinates is set to 12 bits, with the horizontal coordinates aligned to 32. For the four interpolated horizontal coordinates, u and u+1 will both belong to the values ​​of u-1 or u+2 after 32 alignment, as shown in Figure 2b. This reduces to eight horizontal coordinate aligned points. These points are then aligned to 4 for the vertical coordinates, similar to the horizontal coordinates, resulting in four equivalent aligned neighboring point values ​​as shown in Figure 2c, which are used to match the address tags of the texture cache memory.

[0045] In the above steps, if any of the sixteen neighboring points of the texture coordinate point have horizontal or vertical coordinates that exceed the image width and height boundaries, their values ​​are assigned to the values ​​closest to those that do not exceed the boundaries. For example, if the center point is (0, 0) and the image width and height are both greater than 2, then the coordinate points containing (u-1) and (v-1) are assigned 0, and the remaining values ​​maintain the normal calculation logic.

[0046] Next, step S102 is executed, matching the four equivalent alignment points with the outer address tags of the texture cache memory. Step S103 needs to determine the matching situation. If all four points have a matching address and the bit representing the existence of the address is in a valid state, then step S106 is executed. If none of the four points match or only partially match the valid address of the cache outer layer, then step S105 is executed, recording the unmatched outer layer address and the corresponding address position within the group.

[0047] For updating the outer address of the cache, each address that fails to match a neighbor is written to the outer address tag of the cache, and a 1-bit position is used to indicate whether the address exists. Since the number of cache layers is limited, there will always be times when an address that fails to match needs to be updated into the cache. Since the address of each cache layer is valid, it is necessary to update the address of a certain layer to the currently unmatched address. LRU (Least Recently Used) is introduced to update the required address tag.

[0048] Execute step S106, compare the inner offset address with the information in the cache corresponding layer address group, considering that step S107 needs to determine the matching situation. If the inner addresses corresponding to the four equivalent points can all exist effectively in the corresponding cache layer, then proceed to step S110. If only part of the inner addresses corresponding to the four neighboring points can be found in the corresponding cache layer, then proceed to step S109, and record the cache layer address labels that could not be matched in the group.

[0049] Based on a comprehensive analysis of the information in S105 and S109, the update method for a single aligned address is divided into two categories and three cases: one is when the outer address does not match, and the other is when the outer address matches but the address within the group either matches or does not match. Except for the case where both the outer address and the address within the group match, the other two cases require retrieving the corresponding data block from the dynamic random access memory. LRU updates are then performed on the addresses that do not match at the outer or within the group.

[0050] The specific update method is as follows: A counter is placed for each outer address label. The value of the register is initialized to the sorted value of the corresponding address label. When updating an outer address that does not match, the address label with a counter of zero is updated to the unmatched outer address value, and the value of the counter corresponding to that address label is set to the maximum. The remaining counter values ​​are all decremented by one, and the bits representing the outer address value and the valid address within the corresponding group are set to 1. When updating an outer address that matches, the counter of the address label corresponding to the matched outer address is first checked. The counter values ​​larger than this counter are decremented by one, while the counter values ​​smaller than this counter remain unchanged. Then, the value of this counter is set to the maximum. For addresses within the group that have already matched, this remains unchanged. For addresses within the group that have not matched, the valid bits of that address within the group are set to 1.

[0051] Further interpolation of the four equivalent points requires simultaneous matching and updating of all four points. Each point has three matching scenarios: Scenario A: The point does not match the outer address label; Scenario B: The point matches the outer address label but does not match the address within the group; Scenario C: The point matches both the outer address label and the address within the group. The permutations and combinations of these four points yield 81 (3^4) possible matching scenarios. Clearly, simply arranging these 81 scenarios would significantly increase the complexity of the hardware circuit structure. Therefore, two update methods for 16-neighbor interpolation matching are proposed.

[0052] As shown in Figure 3, Method 1 involves executing step S301 to adjust the arrangement order of the four equivalent points after alignment, sorting them according to the matching case CBA, and recording the original arrangement distribution corresponding to each point. Then, step S302 is performed. First, case C is processed. The number of occurrences of C can be 0-4, determining the number of occurrences of case C and the size of its corresponding counter. All counter values ​​are iterated through, comparing these counter values ​​with the counter values ​​corresponding to all cases C. If a value is larger, the counter value is decremented by one. The counter value corresponding to case C is assigned the maximum value and then decremented according to the number of occurrences of C. For example, if the number of occurrences of case C is 3, then excluding the counters for these three cases C, all counter values ​​are iterated through and compared with the values ​​of these three counters. If a value is larger than all three values, the counter value is decremented by three; if larger than two values, it is decremented by two; if larger than only one value, it is decremented by one; if smaller than all three counters, it remains unchanged. The three matched counters are assigned the maximum value MAX, MAX-1, and MAX-2 in sequence. The maximum value is the corresponding cache layer value minus one, i.e., MAX is 31. Then, step S303 is performed to process case B. Similarly, B also has five possibilities. The counter is updated sequentially, all registers are traversed, and the counter value that is larger than the counter value corresponding to the current case B is decremented by one. Then, the counter value corresponding to case B is set to the maximum value, and the unmatched group address record is sent to the bus, and the group address valid bit in the address tag is updated to 1. Finally, step S304 is performed to process case A. The address tag with the current counter of 0 is obtained and the matching case A is updated. The content of the address tag is updated to the outer address corresponding to case A, and the outer address valid bit and the corresponding inner address valid bit are set to 1. At the same time, the corresponding address is sent to the bus.

[0053] As shown in Figure 3, Method 2 involves executing step S401 to process the update of the counters and address tags according to the fixed order of the four equivalent points after alignment. Then, step S402 analyzes the matching situation as outer address matching, i.e., cases B and C. The corresponding counters for these two types are pre-processed: first, all outer address matches that are valid are processed. The number of occurrences of this case is similar, ranging from 0 to 4. The number of occurrences of B and C and the corresponding counter values ​​are counted. All counter values ​​are iterated through, and these counter values ​​are compared with the counter values ​​of cases B and C. Counters larger than any of the B or C case values ​​are decremented by one. The register values ​​of cases B and C are assigned the maximum value in sequence, followed by values ​​decreasing from the maximum value. For example, if the matching order of the four equivalent neighbor points is BACA, then the occurrence of B and C is counted twice. The values ​​of the counters corresponding to the first point B and the third point C are recorded. All counters are compared with these two values. The counter value of the counter that is greater than both of these values ​​is decremented by two. The counter value that is only greater than one of these values ​​is decremented by one. The counter value of the counter that is less than both of these values ​​remains unchanged. Then, the counter corresponding to the first point B is assigned the value of 31, and the counter corresponding to the third point C is assigned the value of 30. Next, step S403 processes the matching cases A and B that need to be updated in sequence. It determines whether the current case is matching case A. If so, step S404 is executed, which is the same as step S304 in method one. If the current case is not A, step S405 is executed. If the matching case is C, it is skipped. If it is B, the corresponding group address label valid value is updated, and the counter value is not updated. After step S404 or S405, step S406 is executed to determine whether the current matching sequence has been completed. If it has not been completed, step S403 is executed again to determine the current matching case. If it has been completed, the matching update of the current four equivalent points ends.

[0054] Specifically, considering the matching of the sixteen neighboring points of bicubic interpolation with the address labels of the texture cache, matching each neighboring point one by one would consume a significant number of comparators and increase hardware area. Therefore, the above scheme uses an equivalent point processing method. The outer address matching is all neighbor-aligned address matching. In Figure 2c, the top-left and top-right points among the four equivalent points are considered identical if their horizontal coordinates are aligned. Similarly, the top-left and bottom-left points are considered identical if their vertical coordinates are aligned. Three situations arise when matching the four equivalent interpolation points: first, all four points are different, belonging to different aligned coordinates; second, two points are identical, meaning either the horizontal or vertical equivalent point is the same; third, all four points are identical, meaning both the horizontal and vertical coordinates of the four equivalent points are the same. For cases where equivalent points are identical, the identical values ​​can be masked when matching with the cache address labels, and only different equivalent points are compared. When it comes to address matching within a group, it is important to note that there are 8 cache lines within the group. When processing neighboring points for equivalent alignment, the offset information of these points is recorded. The offset information corresponding to the equivalent points matched in the outer layer is compared with the valid information within the address label group. Only when all points contained in the offset are validly present in the corresponding address label group can it be determined that the addresses within the group are all matched. If the points in the offset are not validly present, the addresses corresponding to these points need to be recorded.

[0055] Figure 3 shows that different processing methods have different requirements for circuit logic complexity. By executing step S108 through the LRU update method, the updated storage block location label S104 is obtained. Then, it is compared with the next four neighboring points in step S103. The unmatched address information is obtained from the matching cases A and B and sent to the dynamic random access memory to retrieve the image information and store it in the corresponding storage block, corresponding to step S111.

[0056] Furthermore, during the process of sending address information to the dynamic random access memory (DRAM), the command to send the read data request is first stored in the address command buffer. This buffer is a first-in, first-out (FIFO) buffer to reduce the impact of bus bandwidth constraints. At the read data receiving point, there is also a FIFO unmatched data buffer to temporarily store the image data retrieved from DRAM. This buffer has a bit width of 16 bytes. Whether a read data command is sent depends on the empty / full state of the unmatched data buffer. A data command depth register is set up. Each time a command is sent to the address command buffer, the register value is incremented by two. Each time data is written to the unmatched data buffer, the register value is decremented by one. When the register value is less than the depth of the unmatched data buffer minus one, a command can be written to the address command buffer normally; otherwise, the matching of the current neighbor point with the cache address tag is stopped.

[0057] During the matching process, the corresponding address labels that are matched to the cache and the address labels that have not yet been matched and need to be retrieved from the dynamic random access memory and updated, as well as the offset information of the corresponding equivalent point, are recorded. This information is temporarily stored in the first-in-first-out matching status cache.

[0058] Finally, step S112 is executed to match the equivalent four neighbor points with the address locations within the storage block, and step S113 is executed to retrieve the address tags of the outer layer and group from the matching status cache. If there is a matching cache line for the current point, the data is retrieved from the corresponding cache. If not, the corresponding data is retrieved sequentially from the unmatched data cache and stored in the corresponding cache line according to the corresponding tags of the outer layer and group.

[0059] Accordingly, this embodiment also provides a texture mapping hardware acceleration device, as shown in FIG5, which is a schematic structural diagram of a texture mapping hardware acceleration method device. The device includes a computing unit 500, a matching unit 501, an address command storage unit 502, a random access dynamic memory 503, a matching information storage unit 504, an update unit 505, a high-speed buffer unit 506, an unmatched data storage unit 507, and an output unit 508.

[0060] The calculation unit 500 is used to calculate the coordinates of the output image. The texture coordinates corresponding to the original image are obtained through the texture mapping function, and the equivalent sixteen neighbor coordinates are calculated by bicubic interpolation.

[0061] The matching unit 501 and the updating unit 505 are the core components of the entire device. The matching unit is used to match the equivalent sixteen neighbor coordinates with the address tags of the multi-way group-associated cache. It is divided into two parts: outer address matching and group-wide valid address matching. Multiple neighbor points need to be matched simultaneously. For outer-layer unmatched addresses and invalid addresses within the matching group, they are sent to the address command storage unit 502. The updating unit updates the unmatched outer-layer and group-wide address tags and sends the updated address tags to the matching unit for matching the next sixteen neighbor points. At the same time, the matched address tags, the unmatched address tags that need to be updated, and the offset information of the sixteen neighbor points are stored in the matching information storage unit 504.

[0062] Address command storage unit 502 caches unmatched address commands. Before writing an address command into this first-in-first-out address command buffer, the relationship between the command and data commands must be determined, and the real-time depth of the command and data must be calculated. Only when this value is less than the depth of the unmatched data buffer can the read command be written into the address command buffer. When the address command buffer is not empty, the command request is sent to the random access memory 503. After the bus responds, the corresponding data is sent back to the unmatched data storage unit 507.

[0063] The high-speed buffer unit 506 is used to store data of the multiplexed group-associated high-speed buffer memory. By reading the address tag information from the matching information storage unit, the unmatched data is synchronized from the cache unit to the high-speed buffer.

[0064] The output unit 508 determines the data source of the current sixteen neighboring points through the matching information storage unit, retrieves the matched data from the high-speed buffer, and retrieves the unmatched data from the unmatched data buffer, and outputs it synchronously to the subsequent processing unit.

[0065] In this invention, by accelerating texture mapping in hardware and eliminating redundant data using a multi-way inter-group associative cache memory, the consumption of static memory resources during row-based storage and the waste of dynamic random access memory bandwidth when adjacent blocks are relatively discrete during block-based storage can be reduced. Furthermore, the memory can be flexibly configured with different layers and group sizes as needed for different application scenarios, which can effectively save hardware circuit area. By updating cache storage blocks through two configurable LRU update methods, the bandwidth usage can be better saved compared to the commonly used first-in-first-out update method.

[0066] The above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made based on the essence of the content of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for hardware acceleration of texture mapping, characterized in that, include: The texture coordinates are calculated sequentially using a texture coordinate function to map each point of the texture to the texture image, resulting in interpolated coordinates. These interpolated coordinates are first matched against the address tags of the texture cache. For valid matches, the corresponding data is retrieved from the matched texture cache. For unmatched or invalid matches, the corresponding data is retrieved from dynamic random access memory (DRAM) and stored in the texture cache corresponding to the updated address tag. Finally, the interpolated pixel data from the sixteen neighboring texture pixels is output. The address tags of the texture cache are updated using a least recently used (LRU) method, with a counter set for each address tag. The counter size is adjusted based on different matching conditions to determine the address tag update status: If both outer and group addresses match and are valid, the counter value for the corresponding address tag is taken, the counter values ​​for address tags with larger values ​​are decremented, and the counter values ​​for smaller values ​​remain unchanged. The counter value is then set to its maximum. If the outer layer fails to match or the match is invalid, the address tag with a current counter of zero is taken. The remainder counter value is decremented by one, the counter value is set to its maximum, and the address is sent to the dynamic random access memory (DRAM). If the command is sent validly, the address tag is updated to the currently unmatched address, and the corresponding outer and group flag positions are set to valid. For cases where the outer address matches and is valid, but the group does not match, the counter value adjustment method is the same as when both the outer and group addresses match and are valid. Additionally, the corresponding unmatched address is sent to DRAM. If the command is sent validly, the group flag position of the corresponding address tag is set to valid. The matching is divided into two levels: matching of multi-level inter-group aligned addresses and matching of intra-group offset addresses. Both the outer and group have valid flag bits, indicating that the read data command corresponding to the address has been sent to DRAM. The condition for a match between adjacent points is that both flag bits are valid. When an unmatched address needs to be sent to DRAM, it is necessary to determine whether normal transmission is possible. A set of data command judgment conditions is used, and a first-in-first-out (FIFO) data buffer is used to store the data retrieved from DRAM. The real-time depth of the command and data is calculated. If it is less than the depth of the buffer, the read command is sent to DRAM normally.

2. The method for hardware acceleration of texture mapping as described in claim 1, characterized in that: The texture cache memories are all multi-way set-associative cache memories, and their address mapping method is: fully associative mapping between groups and direct mapping within groups.

3. A device for hardware acceleration of texture mapping, characterized in that, include: The calculation unit is used to calculate the coordinate points of the output image through texture mapping and bicubic interpolation to obtain sixteen interpolated texture coordinate points, and to perform alignment processing on these interpolated neighboring points; The matching unit matches the aligned neighboring point coordinates with the address tags in the texture cache, and performs outer-layer and intra-group matching. The update unit updates the counter values ​​for different address tags based on different matching conditions. It processes the matching of sixteen texture coordinate interpolation neighboring points in the same cycle, updates the address tags, and retrieves the corresponding data from the dynamic random access memory (DRAM) for any unmatched address information, updating the texture cache for the corresponding address tag. The address tags in the texture cache are updated using the least recently used method, with a counter set for each address tag. Different matching conditions are addressed using this method. Furthermore, by adjusting the counter size, the address tag update status of the memory is determined, including: if both the outer layer and the group address match and are valid, the counter value of the corresponding address tag is taken, the counter values ​​of address tags with larger values ​​are decremented by one, the counter values ​​of address tags with smaller values ​​remain unchanged, and then the counter value is set to the maximum; if the outer layer fails to match or matches but is invalid, the address tag with a current counter of zero is taken, the counter values ​​of all other tags are decremented by one, the counter value is set to the maximum, and then the address is sent to the dynamic random access memory. If the command is sent validly, the address tag is updated to the currently unmatched address, along with the corresponding outer layer and group flag bits. Set to valid; if the outer address matches and is valid, but the group does not match, the counter value is adjusted in the same way as if both the outer and group addresses match and are valid. Additionally, the corresponding unmatched address needs to be sent to the dynamic random access memory (DRAM). If the command is sent validly, the group flag of the corresponding address tag is set to valid. When an unmatched address needs to be sent to DRAM, it is necessary to determine if normal transmission is possible. A set of data command judgment conditions is used, and a first-in-first-out (FIFO) data buffer is used to store the data retrieved from DRAM. The real-time depth of the command and data is calculated. If it is less than the depth of the buffer, the read command is sent to DRAM normally. Output single... The unit is used to output image pixel data. The image pixel data is calculated as follows: each address tag corresponds to a different texture cache memory unit, the matching information of neighboring points is obtained, the data of neighboring points is obtained from the texture cache memory of the corresponding address tag, and the data of the output image pixel is obtained by interpolation calculation; it also includes: a matching status storage unit, used to record information on matched or unmatched updated address tags and offset addresses; an address command storage unit, used to cache data request commands that are not matched due to untimely bus response; and an unmatched data storage unit, used to temporarily store unmatched data retrieved from random access memory.

4. The apparatus for hardware acceleration of texture mapping as described in claim 3, characterized in that, The matching status storage unit, address command storage unit, and unmatched data storage unit are all first-in-first-out data caches.

5. The apparatus for hardware acceleration of texture mapping as described in claim 4, characterized in that, The texture cache memory is a multi-way set-associative cache memory, and its address mapping method is as follows: fully associative mapping is used between groups, and direct mapping is used within groups.

Images