Method for generating pixel control signals

Abstract

The present invention provides a method for generating a pixel control signal, which generates the pixel control signal more quickly and at less cost. The pixel control signal is used to control a pixel block, and the pixel block has a first pixel and a second pixel. The method includes: generating a basic control signal shared by the pixel block; generating a first sharpening control signal for the first pixel and generating a second sharpening control signal for the second pixel; generating a first pixel control signal using the first sharpening signal and the basic control signal; generating a second pixel control signal using the second sharpening signal and the basic control signal. The basic control signal is stored in a first memory cell; the first sharpening control signal is stored in a second memory cell; and the second sharpening control signal is stored in a third memory cell.

Description

Technical Field

[0001] The present invention relates to display technology. More specifically, the present invention relates to a digital backplane for controlling light modulation elements, spatial light modulators, and light sources. Background Art

[0002] Microdisplays typically include a light modulation backplane and a light modulation unit or a light emitting unit. The light modulation unit includes technologies such as liquid crystal on silicon (LCOS) and digital micromirrors device (DMD). The light emitting unit includes technologies such as Organic lightemitting diodes (OLED) and Micro LED (μLED). The technologies used in such microdisplays can also be used to manufacture larger display units.

[0003] Figure 1 A simplified architecture of a display 100 having a controller 110 and a display panel 150 is shown. The controller 110 includes a dual-frame buffer 112 and a logic block 118. The display panel 150 includes a pixel array 152, a pixel processor 155, and a field buffer 158. A video stream VS is received by the controller 110 and stored in the dual-frame buffer 112 by the logic block 118. The dual-frame buffer 112 can load an upcoming frame while storing the previous frame displayed by the display panel 150. The logic block 118 controls the dual-frame buffer 112 to store image frames and transfer image fields to the field buffer 158. An image field used herein is a component of an image frame. Typically, an image frame can be divided into three image fields, most commonly a red image field, a green image field, and a blue image field. Generally, each pixel of an image frame will have an 8-bit red component, an 8-bit green component, and an 8-bit blue component. Therefore, each pixel of an image frame requires 24 bits of data, and each pixel of an image field requires 8 bits of data.

[0004] The display panel 150 uses a field-sequential color system (FSC) in which different color image fields are displayed on the pixel array 152 very quickly in succession. However, the present invention is also applicable to other types of color display systems. The field-sequential color system relies on the human visual system to fuse the successive image fields into a very close copy of the original image frame. In addition, the display 100 uses a single control signal digital driving scheme for each pixel. Each pixel is either on (control signal at logic high) or off (control signal at logic low) at any given point in time. Specifically, each field is displayed for a field time period FT; the field time period FT has 256 possible update times for the pixel control signal. The brightness of each pixel of each color field is controlled by the duration that the control signal is at logic high. Generally, each pixel has a memory cell that drives the pixel control signal. The memory cell is controlled by the pixel processor to generate the pixel control signal. Generally, the pixel processor 155 includes a pixel processor for each row of the pixel array 152. At each pixel update time, each of the pixel processors updates all the pixels in the associated row.

[0005] Figure 2 Shows three pixel control signals PCS_1, PCS_2, and PCS_3. Specifically, the pixel control signal PCS_1 controls a pixel at maximum brightness and thus turns on (rises to logic high) at update time 0 (labeled UT_0 in Figure 2 ), and remains on (at logic high) throughout the field time period FT. In some embodiments of the display panel 150, the pixel control signal is always turned off (lowered to logic low) at the end of the field time period FT. While in other embodiments it remains on when the pixel control signal is at maximum brightness. The pixel control signal PCS_2 is for a brightness value 155, so the pixel control signal PCS_2 turns on (rises to logic high) at update time 0 (labeled UT_0 in Figure 2 ), and remains on (at logic high) until update time 155 (labeled UT_155 in Figure 2 ) when the pixel control signal PCS_2 is turned off (lowered to logic low). The pixel control signal PCS_3 is for a brightness value 57, so the pixel control signal PCS_3 turns on (rises to logic high) at update time 0 (labeled UT_0 in Figure 2 ), and remains on (at logic high) until update time 57 (labeled UT_57 in Figure 2 ) when the pixel control signal PCS_2 is turned off (lowered to logic low).

[0006] As the resolution of video systems has increased, a major problem with displays such as display 100 is the large memory requirements of the dual frame buffer 112 and the field buffer 158. Additionally, the time required to transfer image fields between the dual frame buffer 112 and the field buffer 158 can degrade the performance of the display for higher resolutions. Compression schemes can be used to address these problems. Figure 3 is a block diagram of a compression scheme that can be used with display 100. As Figure 3 shown, each image frame I_Fr is fed into a low-pass filter 310 and a subtractor 320. The low-pass filter 310 creates a low-frequency image L_F_I from the image frame I_Fr. The subtractor 320 subtracts the low-frequency image L_F_I from the image frame I_Fr to create a high-frequency image H_F_I. Since the high-frequency image H_F_I is created by a subtraction operation, the high-frequency image H_F_I can have positive and negative values, and thus will require a sign bit for each of the eight-bit color components. Therefore, the high-frequency image H_F_I requires 27 bits per pixel (9 bits per color component). However, the human visual system is insensitive to chrominance information at high spatial frequencies. Therefore, image compression is achieved using a luminance converter 340 that converts the high-frequency image H_F_I into a luminance image LUM_I. The luminance image is often referred to as a grayscale image. Thus, three color image fields (each of which requires 9 bits per pixel (27 bits per pixel total)) are reduced to a single luminance-based image that requires 9 bits per pixel. Quantization can be used to achieve further compression using a well-known phenomenon called masking. In the high-frequency luminance image created from an input image, flat or smooth (slowly varying) regions of the input image will produce values of the high-frequency luminance difference components that are small or zero in magnitude. However, in the high-frequency image, edge or texture regions of the input image will produce larger magnitudes. In general, for larger variations in the high-frequency luminance components, larger quantization errors are acceptable because these errors are less likely to be detected in the edges or textures of the input image. Therefore, a logarithmic scale quantization of the high-frequency luminance difference-image introduces image errors that may not be perceptible. Thus, as Figure 3As shown, the luminance image LUM_I is processed by a quantizer 360 to form a sharpened image SH, which is a quantized version of the luminance image LUM_I. Specifically, each pixel of the luminance image LUM_I is quantized to a value in the set {-192, -96, -48, -24, -12, -6, -3, -1, 0, 2, 5, 11, 23, 47, 95, and 191}. Since the quantizer 360 uses 16 values, each pixel of the sharpened image SH only requires 4 bits. Different values and sets of different sizes can be used in different embodiments of the quantizer 360.

[0007] The decimation filter 330 decimates the low-frequency image L_F_I to form a base image B. The decimation filter 330 independently subsamples each image field of the low-frequency image L_F_I to create a base image B. The base image B is one quarter the size of the low-frequency image L_F_I. Specifically, each 2×2 pixel block of the low-frequency image L_F_I is replaced by a single pixel in the base image B. The pixels in the base image B are shown as a simple average of the 2×2 pixel block. However, other methods can be used to calculate the pixels in the base image B. Thus, the base image B is only one quarter the size of the low-frequency image L_F_I. Therefore, when expanded to the size of the input image frame I_FR, since the pixels in each 2×2 pixel block will be the same and thus equal to one quarter of the original value, the base image B will only use 6 bits per pixel instead of 24 bits per pixel.

[0008] By adding the base image B and the sharpened image SH, a very close approximation of the input image frame I_Fr can be created. As described above, the base image B uses 6 bits per pixel, and the sharpened image SH uses 4 bits per pixel. Thus, the base image B and the sharpened image SH together use a combined 10 bits per pixel instead of the original 24 bits per pixel of the input image frame I_Fr. Figure 4 A method of combining the base image B and the sharpened image SH to form a decompressed image D_IMG is shown. For clarity, a base image pixel B_P(X, Y) includes a red component B_R(X, Y), a green component B_G(X, Y), and a blue component B_B(X, Y). A decompressed image pixel D_P(I, J) has a red component D_R(I, J), a green component D_G(I, J), and a blue component D_B(I, J). Since the sharpener SH is a luminance image, each sharpener pixel S_P(M, N) is a single component (as described above, which is a 4-bit value representing one of 16 quantized values).

[0009] In Figure 4 the base image pixel B_P(0, 0) (in Figure 4(not specifically marked in the figure) includes a red component B_R(0, 0) with a value of 149, a green component B_G(0, 0) with a value of 191, and a blue component B_B(0, 0) with a value of 85. A quantization value of the sharpener pixel S_P(0, 0) is 0, a quantization value of the sharpener pixel S_P(0, 1) is 95, a quantization value of the sharpener pixel S_P(1, 0) is -96, and a quantization value of the sharpener pixel S_P(1, 1) is 47.

[0010] As described above, the decompressed image D_IMG is created by expanding the base image B and adding the sharpener SH. A base image pixel B_P(X, Y) is used to calculate the decompressed image pixels D_P(2*X, 2*Y), D_P(2*X + 1, 2*Y), D_P(2*X, 2*Y + 1), and D_P(2*X + 1, 2*X + 1), which respectively have sharpener pixels SH_P(2*X, 2*Y), SH_P(2*X + 1, 2*Y), SH_P(2*X, 2*Y + 1), and SH_P(2*X + 1, 2*X + 1). A decompressed pixel D_P(I, J) has a red component D_R(I, J), a green component D_R(I, J), and a blue component D_B(I, J). Specifically, a red component D_R(I, J) of a decompressed pixel D_P(I, J) is equal to the red component B_R(int(I / 2), int(J / 2)) of a base pixel B_P(int(I / 2), int(J / 2)) plus the quantization value of a sharpener pixel S_P(I, J), where I and J are integers. The "int(num)" used herein is an integer function that returns the integer closest to and less than or equal to the number num. Thus, for example, if I is equal to 5 and J is equal to 10, the red component D_R(5, 10) of the decompressed pixel D_P(5, 10) is equal to the red component B_R(2, 5) of a base pixel B_P(2, 5) plus the quantization value of the sharpener pixel S_P(5, 10). Similarly, a green component D_G(I, J) of a decompressed pixel D_P(I, J) is equal to the green component B_G(int(I / 2), int(J / 2)) of a base pixel B_P(int(I / 2), int(J / 2)) plus the quantization value of a sharpener pixel S_P(I, J). In addition, a blue component D_B(I, J) of a decompressed pixel D_P(I, J) is equal to the blue component B_B(int(I / 2), int(J / 2)) of a base pixel B_P(int(I / 2), int(J / 2)) plus the quantization value of a sharpener pixel S_P(I, J). However, all values of the color components of the decompressed image D_IMG are bounded by 0 and 255 (including 0 and 255). Therefore, negative values are set to be equal to 0, and values greater than 255 are set to be equal to 255.

[0011] Therefore, as Figure 4 shown, the red component D_R(0, 0) is equal to the red component B_R(0, 0) plus the quantization value of the sharpener pixel S_P(0, 0) which is equal to 149 + 0 (which is equal to 149). The green component D_G(0, 0) is equal to the green component B_G(0, 0) plus the quantization value of the sharpener pixel S_P(0, 0) which is equal to 191 + 0 (which is equal to 191). The blue component D_B(0, 0) is equal to the blue component B_B(0, 0) plus the quantization value of the sharpener pixel S_P(0, 0) which is equal to 85 + 0 (which is equal to 85).

[0012] The red component D_R(0, 1) is equal to the red component B_R(0, 0) plus the quantization value of the sharpener pixel S_P(0, 1) which is equal to 149 + -96 (which is equal to 53). The green component D_G(0, 1) is equal to the green component B_G(0, 0) plus the quantization value of the sharpener pixel S_P(0, 1) which is equal to 191 + -96 (which is equal to 95). The blue component D_B(0, 1) is equal to the blue component B_B(0, 0) plus the quantization value of the sharpener pixel S_P(0, 1) which is equal to 85 + -96 (which is less than zero and thus set to be equal to 0).

[0013] The red component D_R(1, 0) is equal to the red component B_R(0, 0) plus the quantization value of the sharpener pixel S_P(1, 0) which is equal to 149 + 95 (which is equal to 244). The green component D_G(1, 0) is equal to the green component B_G(0, 0) plus the quantization value of the sharpener pixel S_P(1, 0) which is equal to 191 + 95 (which is greater than 255 and thus will be set to be equal to 255). The blue component D_B(1, 1) is equal to the blue component B_B(0, 0) plus the quantization value of the sharpener pixel S_P(1, 0) which is equal to 85 + 95 (which is equal to 180).

[0014] The red component D_R(1, 1) is equal to the red component B_R(0, 0) plus the quantization value of the sharpener pixel S_P(1, 1) which is equal to 149 + 47 (which is equal to 196). The green component D_G(1, 1) is equal to the green component B_G(0, 0) plus the quantization value of the sharpener pixel S_P(1, 1) which is equal to 191 + 47 (which is equal to 238). The blue component D_B(1, 1) is equal to the blue component B_B(0, 0) plus the quantization value of the sharpener pixel S_P(1, 1) which is equal to 85 + 47 (which is equal to 132). The other pixels of the decompressed image are calculated in the same way as above.

[0015] As described above, the display 100 uses a field-sequential color scheme such that each color component is displayed sequentially. Each field is displayed in the same manner. Thus, for simplicity, only the display of the red field using the decompressed video stream's red component is explained in detail. The display of the green and blue fields will be performed in the same manner. Also as described above, a single pixel control signal is used to control each pixel of the pixel array 152. Each field is displayed for a field time period FT, and the field time period FT is divided into 256 possible update times for the pixel control signal. The luminance of each pixel of each color field is controlled by the duration for which the pixel control signal is at a logical high (also referred to as on). In a conventional display, a single 1-bit memory cell is used for each pixel to drive the pixel control signal. One way to display the decompressed image D_IMG is to calculate D_IMG as described above and use the values of the color components of the decompressed D_IMG to drive the pixel control signal as explained above with respect to Figure 2 However, this approach would require the inclusion of adders in the pixel processor 155, which would increase the complexity of the pixel processor beyond that of a simple comparator.

[0016] Another approach is to indirectly add a base value B_V and a quantization value QV from the sharpener through scheduling conditions that compare both the base value B_V and the quantization value Q_V at the update times and directly adjust the pixel control signal PCS value. In this method, if the quantization value QV of the sharpener is positive, the base value B_V is represented by a logical high pulse starting at the update time UT_0 and ending at the update time UT_BV. For example, for a base value BV150, the pixel control signal will start at a logical high at the update time UT_0 and transition to a logical low at the update time UT_150. (In a manner similar to that described above with reference to Figure 2 However, for the decompressed image, we need to add the quantization value QV of the sharpener pixel. If the quantization value QV is positive, the luminance of the displayed pixel will only increase relative to the base value B_V. Thus, the pixel control signal will need to be at a logical high for an additional quantization value QV update times. This additional quantization value QV update time can be added at the end of the field time period FT by unconditionally driving the pixel control signal to a logical high for the quantization value QV update times at the end of the field time period FT. Thus, if the quantization value QV of the sharpener pixel plus the base value B_V is greater than or equal to 255, the transition to a logical low at the update time UT_BV will be prevented, such that the pixel control signal remains at a logical high throughout the field time period FT. Therefore, at all update times after the first quantization addition (maximum addition), the base value B_V must be measured to determine whether the pixel control signal should be turned off, and the quantization value QV must be measured to determine whether the pixel control signal should replace any base value and remain on.

[0017] Conversely, if the quantization value QV of the sharpener pixel is negative, the pixel control signal should not be at logic high as long as it is indicated by the base value B_V. Thus, the logic high transition of the pixel control signal is unconditionally suspended until the magnitude (or absolute value) of the quantization value QV has been satisfied. Thus, if the quantization value QV of the sharpener pixel plus the base value B_V is less than or equal to 0, the transition to logic high will be prevented, such that the pixel control signal remains at logic low throughout the field time period FT. Further, at each subtraction end time where the update time is equal to the quantization subtraction value, the quantization value QV is measured to determine if the subtraction time has ended and the pixel control signal should be allowed to conduct, and the base value B_V is measured to check if the subtraction value has exceeded the base value B_V and overridden the pixel control signal being conducted to maintain a turned-off position.

[0018] Figure 5 Shows the pixel control signal for the red field of the decompressed image D_IMG corresponding to Figure 4 The pixel control signal PCS_R(0, 0) represents the red component D_R(0, 0) of the decompressed image D_IMG. Specifically, since the quantization value of the sharpener pixel S_P(0, 0) is greater than or equal to zero and the red component B_R(0, 0) of the base image B is greater than zero, the pixel control signal PCS_R(0, 0) is driven to logic high at the update time UT_0. The pixel control signal PCS_R(0, 0) is driven to logic low at the update time 149 because the red component B_R(0, 0) has a value of 149. The pixel control signal PCS_R(0, 0) remains at logic low throughout the remaining field time period FT because the quantization value QV of the sharpener pixel S_P(0, 0) is zero.

[0019] The pixel control signal PCS_R(0, 1) represents the red component D_R(0, 1) of the decompressed image D_IMG. Specifically, since the quantization value of the sharpener pixel S_P(0, 1) is less than zero, the transition of the pixel control signal PCS_R(0, 1) to logic high is delayed by the magnitude of the quantization value QV of the sharpener pixel S_P(0, 1). Since the magnitude of the QV quantization value of the sharpener pixel S_P(0, 1) is -96, the pixel control signal PCS_R(0, 1) transitions to logic high at the update time UT_96. The pixel control signal PCS_R(1, 0) is driven to logic low at the update time 149 because the red component B_R(0, 0) has a value of 149. The pixel control signal PCS_R(0, 1) remains at logic low throughout the remaining field time period FT. Since the pixel control signal PCS_R(0, 1) remains at logic high between the update time UT_96 and the update time UT_149, the pixel control signal PCS_R(0, 1) is at logic high for a total of 53 update times, and the 53 update times are equal to the value of the color component D_R(0, 1) of the decompressed image D_IMG.

[0020] The pixel control signal PCS_R(1, 0) represents the red component D_R(1, 0) of the decompressed image D_IMG. Specifically, since the quantization value QV of the sharpener pixel S_P(1, 0) is greater than zero and the color component B_R(0, 0) is greater than zero, the pixel control signal PCS_R(1, 0) transitions to logic high at the update time UT_0. The pixel control signal PCS_R(1, 0) is driven to logic low at the update time 149 because the red component B_R(0, 0) has a value of 149. Since the quantization value of the sharpener pixel S_P(1, 0) is positive, the pixel control signal is driven to logic high before the end of the field time period FT. Specifically, the magnitude of the quantization value of the sharpener pixel S_P(1, 0) is 95, so the pixel control signal PCS_R(1, 0) transitions 95 update times before the end of the field time period FT. As described above, there are 256 update times in the field time period FT (i.e., update times UT_0 to UT_255). Therefore, the pixel control signal PCS_R(1, 0) transitions to logic high at the update time UT_160 and remains at logic high throughout the remaining field time period FT. Since the pixel control signal PCS_R(1, 0) is at logic high between the update time UT_0 and the update time UT_149 and between the update time UT_160 and the update time UT_255, the pixel control signal PCS_R(0, 1) is at logic high for a total of 244 update times, and the 244 update times are equal to the value of the color component D_R(1, 0) of the decompressed image D_IMG.

[0021] The pixel control signal PCS_R(1, 1) represents the red component D_R(1, 1) of the decompressed image D_IMG. Specifically, since the quantization value of the sharpener pixel S_P(1, 1) is greater than zero and the color component B_R(0, 0) is greater than zero, the pixel control signal PCS_R(1, 0) transitions to a logic high at the update time UT_0. The pixel control signal PCS_R(1, 1) is driven to a logic low at the update time 149 because the red component B_R(0, 0) has a value of 149. Since the quantization value QV of the sharpener pixel S_P(1, 1) is positive, the pixel control signal is driven to a logic high before the end of the field time period FT. Specifically, the magnitude of the quantization value of the sharpener pixel S_P(1, 1) is 47, so the pixel control signal PCS_R(1, 1) transitions 47 update times before the end of the field time period FT. As described above, there are 256 update times (i.e., update times UT_0 to UT_255) in the field time period FT. Therefore, the pixel control signal PCS_R(1, 1) transitions to a logic high at the update time UT_208 and remains at a logic high for the remaining field time period FT. Since the pixel control signal PCS_R(1, 1) is at a logic high between the update time UT_0 and the update time UT_149 and between the update time UT_208 and the update time UT_255, the pixel control signal PCS_R(1, 1) is at a logic high for a total of 196 update times, and the 196 update times is equal to the value of the color component D_R(1, 1) of the decompressed image D_IMG.

[0022] The above process for generating the pixel control signal is used for each pixel of the pixel array 152. A one-bit memory cell is used to store a pixel control signal for each pixel of the pixel array 152. The pixel control signal is controlled by a pixel processor 155, and the pixel processor 155 includes a pixel processor for each row of the pixel array 152. At each pixel update time, each of the pixel processors must determine whether to cause a logic transition in the memory cells of each of the pixels in the associated row. At the end of a field time period FT, the next color field is displayed in the same manner. For each frame of the video stream, each color field should be displayed multiple times.

[0023] Common methods for improving video quality are to increase the display resolution (i.e., increase the number of pixels), increase the bit depth, increase the scan rate, and increase the frame update rate. Increasing the display resolution increases the workload and power consumption of each pixel processor, because there are more pixels per row that need to be controlled by each pixel processor. In addition, increasing the frame rate reduces the field time, and thus reduces the pixel update time, which reduces the time during which each pixel control signal can be updated. Therefore, a method and system are needed to update the pixel control signal faster to support higher resolutions, higher frame rates, and higher bit depths. Summary of the Invention

[0024] The object of the present invention is to use various novel techniques to reduce the area and processing requirements of pixel processors, so as to allow each pixel processor to process more pixels and process each pixel faster, which allows the display to have a higher resolution and a faster frame rate.

[0025] An embodiment of the present invention provides a method for generating a pixel control signal for achieving lower power consumption and higher bit depth. The method includes: generating a basic control signal shared by the pixel blocks; generating a first shaper control signal for the first pixel; generating a second shaper control signal for the second pixel; using the first shaper control signal and the basic control signal to generate a first pixel control signal; using the second shaper control signal and the basic control signal to generate a second pixel control signal.

[0026] Optionally, in an embodiment of the present invention, the using the first shaper control signal and the basic control signal to generate a first pixel control signal further includes: generating a first shaper sign bit signal; combining the first shaper control signal and the basic control signal to form a first logical OR signal; combining the first shaper control signal and the basic control signal to form a first logical AND signal.

[0027] Optionally, in an embodiment of the present invention, the using the first shaper control signal and the basic control signal to generate a first pixel control signal further includes: when the first shaper sign bit signal is in a first logical state, selecting the first logical OR signal as the first pixel control signal; and when the first shaper sign bit signal is in a second logical state, selecting the first logical AND signal as the first pixel control signal.

[0028] Optionally, in an embodiment of the present invention, generating a second pixel control signal using the second shaper control signal and the basic control signal further includes: generating a second shaper sign bit signal; combining the second shaper control signal and the basic control signal to form a second logical OR signal; combining the second shaper control signal and the basic control signal to form a second logical AND signal; when the second shaper sign bit signal is in a first logical state, selecting the second logical OR signal as the second pixel control signal; and when the second shaper sign bit signal is in a second logical state, selecting the second logical AND signal as the second pixel control signal.

[0029] Optionally, in an embodiment of the present invention, the basic control signal is stored in a first memory cell; the first shaper control signal is stored in a second memory cell; the first shaper sign bit signal is stored in a third memory cell; the second shaper control signal is stored in a fourth memory cell; and the second shaper sign bit signal is stored in a fifth memory cell.

[0030] Optionally, in an embodiment of the present invention, the basic control signal starts a field time period with a logic high and transitions to a logic low at a basic value update time; and wherein the first shaper control signal starts the field time period with a logic low and transitions to a logic high at a transition value update time, the transition value update time being a first shaper value from the end of the field time period.

[0031] Optionally, in an embodiment of the present invention, the first pixel control signal starts the field time period with a logic high, transitions to a logic low at the basic value update time, and transitions to a logic high at the transition value update time, the transition value update time being the first shaper value from the end of the field update time.

[0032] Optionally, in an embodiment of the present invention, the basic control signal starts a field time period with a logic high and transitions to a logic low at a basic value update time; and wherein the first shaper control signal starts the field time period with a logic low and transitions to a logic high at a transition value update time, the transition value update time being the absolute value of a first shaper value from the start of the field time period.

[0033] Optionally, in an embodiment of the present invention, the first pixel control signal starts the field time period with a logic low, transitions to a logic high at the transition value update time, the transition value update time being the absolute value of the first shaper value from the start of the field time period, and transitions to a logic low at the basic value update time.

[0034] Optionally, in an embodiment of the present invention, the generating a first pixel control signal using the first shaper control signal and the basic control signal further includes: generating a first inverted shaper sign bit signal; when the first shaper control signal is in a first logic state, selecting the basic control signal as the first pixel control signal; and when the first shaper control signal is in a second logic state, selecting the first inverted shaper sign bit signal as the first pixel control signal.

[0035] Optionally, in an embodiment of the present invention, the first logic state is logic low, and the second logic state is logic high.

[0036] Optionally, in an embodiment of the present invention, the basic control signal starts a field time period with logic high and changes to logic low at a basic value update time; and wherein the first shaper control signal starts the field time period with logic high and changes to logic low at a transition value update time, the transition value update time being the absolute value of a first shaper value from the start of the field time period.

[0037] Optionally, in an embodiment of the present invention, the first pixel control signal starts the field time period with logic low, changes to logic high at the transition value update time, the transition value update time being the absolute value of the first shaper value from the start of the field time period, and changes to logic low at the basic value update time.

[0038] Optionally, in an embodiment of the present invention, the generating a second pixel control signal using the second shaper control signal and the basic control signal further includes: generating a second inverted shaper sign bit signal; when the second shaper control signal is in a first logic state, selecting the basic control signal as the second pixel control signal; and when the second shaper control signal is in a second logic state, selecting the second inverted shaper sign bit signal as the second pixel control signal.

[0039] Optionally, in an embodiment of the present invention, the basic control signal is stored in a first memory cell; the first shaper control signal is stored in a second memory cell; and the second shaper control signal is stored in a third memory cell.

[0040] Optionally, in an embodiment of the present invention, the generating a first pixel control signal using the first shaper control signal and the basic control signal further includes: generating a global input signal; when the first shaper control signal is in a first logic state, selecting the basic control signal as the first pixel control signal; and when the first shaper control signal is in a second logic state, selecting the global input signal as the first pixel control signal.

[0041] Optionally, in an embodiment of the present invention, the generating a second pixel control signal using the second shaper control signal and the basic control signal further includes: when the second shaper control signal is in a first logic state, selecting the basic control signal as the second pixel control signal; and when the second shaper control signal is in a second logic state, selecting the global input signal as the second pixel control signal.

[0042] Optionally, in an embodiment of the present invention, the basic control signal starts a field time period with a logic high and transitions to a logic low at a basic value update time; and wherein the global input signal starts the field time period with a logic low and transitions to a logic high at a global transition time.

[0043] Optionally, in an embodiment of the present invention, the global transition time is close to the middle of the field time period.

[0044] Optionally, in an embodiment of the present invention, the generating a first pixel control signal using the first shaper signal and the basic control signal further includes: generating an inverted basic control signal; when the first shaper control signal is in a first logic state, selecting the basic control signal as the first pixel control signal; and when the first shaper control signal is in a second logic state, selecting the inverted basic control signal as the first pixel control signal.

[0045] Optionally, in an embodiment of the present invention, the generating a second pixel control signal using the second shaper signal and the basic control signal further includes: when the second shaper control signal is in the first logic state, selecting the basic control signal as the second pixel control signal; and when the second shaper control signal is in the second logic state, selecting the inverted basic control signal as the second pixel control signal.

[0046] Optionally, in an embodiment of the present invention, the generating a first pixel control signal using the first sharpener signal and the basic control signal further includes: generating a quantized local input signal; when the first sharpener control signal is in a first logic state, selecting the basic control signal as the first pixel control signal; and when the first sharpener control signal is in a second logic state, selecting the quantized local input signal as the first pixel control signal.

[0047] Optionally, in an embodiment of the present invention, the generating a second pixel control signal using the second sharpener signal and the basic control signal further includes: when the second sharpener control signal is in the first logic state, selecting the basic control signal as the second pixel control signal; and when the second sharpener control signal is in the second logic state, selecting the quantized local input signal as the second pixel control signal.

[0048] Optionally, in an embodiment of the present invention, the first basic control signal is stored in a first memory cell; the quantized local input signal is stored in a second memory cell; the first sharpener control signal is stored in a third memory cell; and the second sharpener control signal is stored in a fourth memory cell.

[0049] Optionally, in an embodiment of the present invention, the generating a first pixel control signal using the first sharpener control signal and the basic control signal further includes: generating an inverted basic control signal; generating a global input signal; generating a global control signal; generating a sharpener correction signal through the following steps: when the global control signal is in a first logic state, selecting the inverted basic control signal as the sharpener correction signal; and when the global control signal is in a second logic state, selecting the global input signal as the sharpener control signal; when the first sharpener control signal is in the first logic state, selecting the basic control signal as the first pixel control signal; and when the first sharpener control signal is in the second logic state, selecting the sharpener correction signal as the first pixel control signal.

[0050] Optionally, in an embodiment of the present invention, the generating a second pixel control signal using the second sharpener control signal and the basic control signal further includes: when the second sharpener control signal is in the first logic state, selecting the basic control signal as the second pixel control signal; and when the second sharpener control signal is in the second logic state, selecting the sharpener correction signal as the second pixel control signal.

[0051] Optionally, in an embodiment of the present invention, the basic control signal starts a field time period with a logic high and transitions to a logic low at a basic value update time; wherein the global input signal starts the field time period with a logic low and transitions to a logic high at a global transition time; and wherein the global control signal starts the field time period with a logic high and transitions to a logic low at a sharpening minimum update time and transitions to a logic high at a sharpening maximum update time. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A simplified block diagram illustrating a portion of a conventional display.

[0053] Figure 2 Illustrating pixel control signals.

[0054] Figure 3 A diagram of a conventional video compression system.

[0055] Figure 4 Illustrating a portion of an image generated using a conventional video compression system.

[0056] Figure 5 Illustrating a pixel control system used in a conventional display system.

[0057] Figure 6A A schematic diagram of a novel system for generating pixel control signals according to an embodiment of the present invention.

[0058] Figure 6B A schematic diagram of a novel system for generating pixel control signals according to an embodiment of the present invention.

[0059] Figures 7A to 7B Showing signals of a novel system for generating pixel control signals according to an embodiment of the present invention.

[0060] Figures 7C to 7E Showing signals of a novel system for generating pixel control signals according to an embodiment of the present invention.

[0061] Figure 8 A schematic diagram of a novel system for generating pixel control signals according to an embodiment of the present invention.

[0062] Figures 9A to 9B Showing signals of a novel system for generating pixel control signals according to an embodiment of the present invention.

[0063] Figure 10 A schematic diagram of a novel system for generating pixel control signals according to an embodiment of the present invention.

[0064] Figures 11A to 11BSignals showing a novel system for generating pixel control signals according to an embodiment of the present invention.

[0065] Figure 12 Is a schematic diagram of a novel system for generating pixel control signals according to an embodiment of the present invention.

[0066] Figures 13A to 13B Signals showing a novel system for generating pixel control signals according to an embodiment of the present invention.

[0067] Figure 14 Is a schematic diagram of a novel system for generating pixel control signals according to an embodiment of the present invention.

[0068] Figures 15A to 15D Signals showing a novel system for generating pixel control signals according to an embodiment of the present invention.

[0069] Description of main reference numerals:

[0070] 0: Update time / Storage logic / Logic

[0071] 1: Storage logic / Logic

[0072] 100: Display

[0073] 110: Controller

[0074] 112: Dual-frame buffer

[0075] 118: Logic block

[0076] 150: Display panel / Display / Basic value BV

[0077] 152: Pixel array

[0078] 155: Pixel processor / Luminance value / Update time

[0079] 158: Field buffer

[0080] 310: Low-pass filter

[0081] 320: Subtractor

[0082] 330: Decimation filter

[0083] 340: Luminance converter

[0084] 360: Quantizer

[0085] 610, 615, 810, 1010, 1210, 1410: Basic image memory cells

[0086] 620: Sharpening image memory cell / Memory cell

[0087] 625, 820, 1030, 1230, 1430: Sharper image memory cells

[0088] 630: Sharper sign bit memory cell

[0089] 635: Inverted sharper sign bit memory cell

[0090] 640: OR gate

[0091] 650: AND gate

[0092] 660, 665, 860, 1060, 1260, 1460, 1470: Multiplexer

[0093] 1015, 1415: Inverter

[0094] 1216: Inverted quantization local memory cell / local input memory cell

[0095] AND_S, OR_S: Signals

[0096] B: Basic image

[0097] B_B(0, 0), D_B(0, 0), D_B(0, 1), D_B(1, 1): Blue component

[0098] B_CS: Basic image control signal / basic control signal / image control signal

[0099] !B_CS: Inverted basic image control signal / inverted basic image signal / inverted basic control signal

[0100] B_G(0, 0), D_G(0, 1), D_G(1, 0), D_G(1, 1): Green component

[0101] B_R(0, 0), D_R(0, 1), D_R(1, 0), D_R(1, 1): Red component / color component

[0102] D_R(0, 0): Red component

[0103] D_IMG: Decompressed image

[0104] FT: Field time period / remaining frame update period / frame update period / field update period

[0105] GC: Global control signal

[0106] GI, GI_2: Global input signals

[0107] H_F_I: High-frequency image

[0108] I_Fr: Image Frame

[0109] L_F_I: Low-Frequency Image

[0110] LUM_I: Luminance Image

[0111] PCS, PCS_1, PCS_2, PCS_3, PCS_R(0, 0), PCS_R(0, 1), PCS_R(1, 0), PCS_R(1, 1): Pixel Control Signal

[0112] Q_LI: Quantized Local Input Signal

[0113] S_P(0, 0), S_P(0, 1), S_P(1, 0), S_P(1, 1): Sharpening Pixel

[0114] SCS: Sharpening Corrector Signal / Sharpening Correction Signal / Sharpening Control Signal

[0115] SH: Sharpening Image / Sharpening Unit

[0116] SH_CS: Sharpening Control Signal

[0117] SH_CS2, SH_CS4, SH_CS5: Sharpening Image Control Signal / Sharpening Control Signal

[0118] SH_CS3: Sharpening Image Control Signal / Sharpening Control Signal / Sharpening Control Signal

[0119] SH_SB: Sharpening Sign Bit Signal

[0120] !SH_SB: Inverted Sharpening Sign Bit Signal

[0121] UT_0, UT_57, UT_96, UT_149, UT_155, UT_160, UT_208, UT_A_QV, UT_GT, UT_Q_LV, UT_T_V: Update Time

[0122] UT_BV: Update Time / Time

[0123] UT_SCS_Max: Maximum Sharpening Update Time

[0124] UT_SCS_Min: Minimum Sharpening Update Time

[0125] VS: Video Stream Detailed Implementation Manner

[0126] As described above, increasing the resolution, bit depth, scan rate, and frame rate of a display can improve the quality of the display. To support higher resolutions and frame rates, a faster method for generating pixel control signals is needed. The present invention uses various novel techniques to reduce the area and processing requirements of pixel processors, allowing each pixel processor to process more pixels and process each pixel more quickly, which allows the display to have a higher resolution and a faster frame rate.

[0127] Figure 6A is a novel circuit that uses a single control signal digital drive scheme for each pixel to generate a pixel control signal for a display. Figure 6A The circuit of uses three memory bits of the pixel control signal instead of using a single memory bit. Although using additional memory bits for each pixel control signal seems to increase the processing load on each pixel processor compared to a single memory bit, the present invention manages to reduce the processing load with the additional memory bits, as described below. Figure 6A The circuit of can be used for a display using the compression scheme referred to above Figures 3 to 5 described. Thus, Figure 6A the description of assumes Figure 6A the circuit of is used to drive a color component D_C(X, Y) of a pixel D_P(X, Y) of a decompressed image. The color component is typically red, green, or blue, but some embodiments of the present invention may use other color components or even other color schemes. The color component D_C(X, Y) is equal to the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of a base image B plus a quantization value QV of a sharpening pixel S_P(X, Y). Figure 7A and Figure 7B show the signals generated by the circuit of. Specifically, Figure 6A illustrates the signal when the quantization value QV of the sharpening pixel S_P(X, Y) is positive, and Figure 7A illustrates the signal when the quantization value QV of the sharpening pixel S_P(X, Y) is negative. Figure 7B

[0128] Figure 6A Figure 6A includes a base image memory cell 610, a sharpening image memory cell 620, and a sharpening sign bit memory cell 630, an OR gate 640, an AND gate 650, and a multiplexer 660. The base image memory cell 610 outputs a base image control signal B_CS. Using Figure 6AThe pixel processor of the circuit controls the basic image memory cell 610 based on the basic value BV in the color component B_C(int(X / 2), int(Y / 2)). Specifically, if the basic value BV is greater than 0, the basic image control signal B_CS will be at logic high starting from the update time U_0 and turn to logic low at the update time U_BV during the field time period FT. (See Figure 7A and Figure 7B ) If the basic value BV is equal to zero, the basic image control signal B_CS remains at logic low throughout the field time period. The basic image control signal B_CS is applied to one input terminal of the OR gate 640 and one input terminal of the AND gate 650.

[0129] The pixel processor controls the shaper image memory cell 620 based on the quantization value QV of the shaper pixel S_P(X, Y) to output a shaper control signal SH_CS. Specifically, if the quantization value QV of the shaper pixel S_P(X, Y) is less than zero, the shaper control signal starts at logic zero and turns to logic high after the absolute value of the quantization value QV update time. In other words, if the quantization value QV of the shaper pixel S_P(X, Y) is less than zero, if the value A_QV is equal to the absolute value of the quantization value QV of the shaper pixel S_P(X, Y), the shaper control signal starts at logic low at the update time UT_0 and turns to logic high at the update time UT_A_QV (as Figure 7B shown). If the quantization value QV of the shaper pixel S_P(X, Y) is greater than zero, the shaper control signal starts at logic zero and turns to logic high at the quantization value QV update time before the end of the field time period FT. In other words, if the quantization value QV of the shaper pixel S_P(X, Y) is greater than zero, if the transition value T_V is equal to 255 minus the quantization value QV of the shaper pixel S_P(X, Y), the shaper control signal starts at logic low at the update time UT_0 and turns to logic high at the update time UT_T_V (as Figure 7A shown), where the transition value T_V is equal to 255 minus the quantization value QV of the shaper pixel S_P(X, Y). If the quantization value QV of the shaper pixel S_P(X, Y) is equal to zero, the shaper control signal remains at logic low throughout the field update period FT. The shaper control signal SH_CS is applied to one input terminal of the OR gate 640 and one input terminal of the AND gate 650.

[0130] The OR gate 640 performs a logical OR function on the basic image control signal B_CS and the shaper control signal SH_CS (which is equivalent to a mathematical addition function of the pixel control signal) and outputs a signal OR_S, and the signal OR_S is applied to the logic low (i.e., "0") input terminal of the multiplexer 660. In Figure 7A and Figure 7BExemplified is a signal OR_S, which is a logical OR signal combining the basic image control signal B_CS and the sharper control signal SH_CS. The AND gate 650 performs a logical AND function on the basic image control signal B_CS and the sharper control signal SH_CS (which is equivalent to a mathematical subtraction function of the pixel control signal), and outputs a signal AND_S, and the signal AND_S is applied to the logical high (i.e., "1") input terminal of the multiplexer 660. At Figure 7A and Figure 7B shown is the signal AND_S, which is a logical AND signal combining the basic image control signal B_CS and the sharper control signal SH_CS. The sharper sign bit memory cell 630 stores the sign bit from the sharper pixel S_P(X, Y). Thus, if the quantization value QV of the sharper pixel S_P(X, Y) is greater than or equal to zero, the sharper sign bit memory cell 630 stores a logic 0 for the field time period FT. If the quantization value QV of the sharper pixel S_P(X, Y) is less than zero, the sharper sign bit memory cell 630 stores a logic 1 for the field time period FT. The sharper sign bit memory cell outputs a sharper sign bit signal SH_SB, and the sharper sign bit signal SH_SB is applied to the control terminal of the multiplexer 660. When the sharper sign bit signal SH_SB is at a logical low, the multiplexer 660 outputs the signal OR_S as the pixel control signal PCS. When the sharper sign bit signal SH_SB is at a logical high, the multiplexer 660 outputs the signal AND_S as the pixel control signal PCS. Regardless of whether a zero value of the sharper is regarded as a positive number or a negative number, Figure 6A the embodiments of

[0131] Figure 7A and Figure 7B exemplify Figure 6A the signals of the embodiments of the present invention. Figure 7A shows the signal when the quantization value QV of the sharper pixel S_P(X, Y) is greater than or equal to zero; while Figure 7B shows the signal when the quantization value QV of the sharper pixel S_P(X, Y) is less than zero. As described above, the basic image memory cell 610 outputs the basic image control signal B_CS, and the basic image control signal B_CS is driven to a logical high at the update time UT_0, and changes to a logical low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of the pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The sharper image memory cell 620 outputs the sharper control signal SH_CS. For Figure 7A, the quantization value QV of the sharpener pixel S_P(X, Y) is positive. Therefore, the sharpener control signal SH_CS starts at logic low at the update time UT_0 and transitions to logic high at the update time UT_T_V, where the transition value T_V is equal to 255 minus the quantization value QV of the sharpener pixel S_P(X, Y). In other words, the quantization value QV comes from the end of the field time period FT. The signal OR_S is the output of the OR gate 640 and is the logical OR of the basic image control signal B_CS and the sharpener control signal SH_CS. Therefore, the signal OR_S is at logic high at the update time UT_0, transitions to logic low at the update time UT_BV, and then transitions to logic high at the update time UT_T_V. The signal AND_S is the output of the AND gate 650 and is the logical AND of the basic image control signal B_CS and the sharpener control signal SH_CS. Therefore, the signal AND_S is at logic low throughout the field time period FT. The sharpener sign bit signal SH_SB is the output signal of the sharpener sign bit memory cell 630 and is at logic low throughout the field time period FT because Figure 7A shows the signals when the quantization value QV of the sharpener pixel S_P(X, Y) is positive. The multiplexer 660 drives the pixel control signal PCS. Since the sharpener sign bit control signal (which is at logic low for Figure 7A ) is applied to the control terminal of the multiplexer 660, the multiplexer 660 outputs the signal provided to the logic low input terminal of the multiplexer 660. Therefore, the pixel control signal PCS is a copy of the signal OR_S. Therefore, the pixel control signal PCS is at logic high at the update time UT_0, transitions to logic low at the update time UT_BV, and transitions to logic high at the update time UT_T_V, and remains at logic high during the remaining frame update period FT. Therefore, Figure 7A 's pixel control signal PCS achieves the same result as Figures 3 to 5 shown by adding the quantization value QV of a sharpener pixel to the color component of a basic pixel (specifically, see Figure 5 's pixel control signals PCS_R(1, 0) and PCS_R(1, 1)).

[0132] Figure 7BShows a signal when the quantization value QV of the sharpener pixel S_P(X, Y) is less than zero. The basic image memory cell 610 outputs a basic image control signal B_CS, which is driven to logic high at the update time UT_0 and transitions to logic low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The sharpener image memory cell 620 outputs a sharpener control signal SH_CS. For Figure 7B , the quantization value QV of the sharpener pixel S_P(X, Y) is negative. Thus, the sharpener control signal SH_CS starts at logic low at the update time UT_0 and transitions to logic high at the update time UT_A_QV, where the transition value A_QV is equal to the absolute value of the quantization value QV of the sharpener pixel S_P(X, Y). The signal OR_S is the output of the OR gate 640 and is the logical OR of the basic image control signal B_CS and the sharpener control signal SH_CS. Thus, the signal OR_S is at logic high throughout the field time period FT. The signal AND_S is the output of the AND gate 650 and is the logical AND of the basic image control signal B_CS and the sharpener control signal SH_CS. Thus, the signal AND_S is at logic low at the update time UT_0, transitions to logic high at the update time UT_A_QV, and then transitions to logic low at the update time UT_BV. The sharpener sign bit signal SH_SB is the output signal of the sharpener sign bit memory cell 630 and is at logic high throughout the field time period FT because Figure 7B Shows a signal when the quantization value QV of the sharpener pixel S_P(X, Y) is negative. The multiplexer 660 drives the pixel control signal PCS. Since the sharpener sign bit control signal (which is at logic high for Figure 7B ) is applied to the control terminal of the multiplexer 660, the multiplexer 660 outputs the signal provided to the logic high input terminal of the multiplexer 660. Thus, the pixel control signal PCS is a copy of the signal AND_S. Thus, the pixel control signal PCS is at logic low at the update time UT_0, transitions to logic high at the update time UT_A_QV, and then transitions to logic low at the update time UT_BV and remains at logic low during the remaining frame update period FT. Thus, Figure 7B 's pixel control signal PCS achieves the same result as Figure 7B by adding the quantization value QV of a sharpener pixel (negative in Figures 3 to 5 ) to the color component of a basic pixel, specifically, see Figure 5 's pixel control signal PCS_R(0, 1).

[0133] The object of the present invention is to reduce the processing load on the pixel processor to allow for higher resolutions and higher frame rates, as well as to reduce power consumption. In traditional systems, the main task of the pixel processor is to update the memory cells that provide the pixel control signals. In traditional systems, each pixel has a single memory cell that outputs the pixel control signal. Thus, at first glance Figure 6A the embodiments of the present invention in

[0134] In Figure 6A the embodiments, the basic image information and the sharpener image information are kept separate. As described above, a single basic pixel is used for four decompressed pixels. Thus, four pixels can share the same basic image memory cell. Therefore, the 256 meta-actions required for the basic image memory cell can be shared by four pixels. Thus, for the basic image memory cell, the processor only needs the equivalent of 64 processor meta-actions per pixel. The sharpener sign bit memory cell does not change during the field time period FT and thus only requires a single processor meta-action per pixel to set the value at or before the update time UT_0. Each pixel does require a different sharpener image memory cell, but since the quantization value QV of the sharpener pixel S_P(X, Y) can only have one of 16 fixed values, the sharpener image memory cell can only change at one of 16 fixed update times. Thus, during the field time period FT, the pixel processor only needs to check the sharpener image memory cell at 16 update times. Thus, each pixel processor only needs to spend 16 processor meta-actions on the sharpener image memory cell. Thus, compared to the traditional system which requires 256 processor meta-actions per pixel, Figure 6A the embodiments of the present invention shown in

[0135] Figure 6B show another embodiment of the present invention which eliminates the need for associated comparison logic blocks (i.e., AND gates and OR gates). Figure 6Bincluding a basic image memory cell 615 that generates a basic image control signal B_CS, a sharpener image memory cell 625 that generates a sharpener image control signal SH_CS2, an inverter sharpener sign bit memory cell 635 that generates an inverter sharpener sign bit signal!SH_SB, and a multiplexer 665 that outputs a pixel control signal PCS. The basic image memory cell 615 is controlled in the same manner as described above for the basic image memory cell 610 to generate the basic image control signal. For simplicity, it will not be described again. The inverter sharpener sign bit memory cell 635 stores the inverted sign bit from the sharpener pixel S_P(X, Y). Thus, if the quantization value QV of the sharpener pixel S_P(X, Y) is greater than or equal to zero, the inverter sharpener sign bit memory cell 635 stores a logic 1 for the field time period FT. If the quantization value QV of the sharpener pixel S_P(X, Y) is less than zero, the inverter sharpener sign bit memory cell 635 stores a logic 0 for the field time period FT. The sharpener sign bit memory cell outputs an inverter sharpener sign bit signal!SH_SB, and the inverter sharpener sign bit signal!SH_SB is applied to the logic high input terminal of the multiplexer 660.

[0136] Compared with Figure 6A the memory cell 620, the operation of the sharpener image memory cell 625 is slightly changed. The pixel processor controls the sharpener image memory cell 625 based on the quantization value QV of the sharpener pixel S_P(X, Y) to output a sharpener control signal SH_CS2, and the sharpener control signal SH_CS2 is slightly different from the sharpener control signal SH_CS of the embodiment for Figure 6A . Specifically, if the quantization value QV of the sharpener pixel S_P(X, Y) is less than zero, the sharpener control signal SH_CS2 starts with a logic high and changes to a logic low after the absolute value of the quantization value QV update time. In other words, if the quantization value QV of the sharpener pixel S_P(X, Y) is less than zero, if the value A_QV is equal to the absolute value of the quantization value QV of the sharpener pixel S_P(X, Y), the sharpener control signal SH_CS2 starts with a logic high at the update time UT_0 and changes to a logic low at the update time UT_A_QV (as Figure 7DAs shown). If the quantization value QV of the sharpener pixel S_P(X, Y) is greater than zero, the sharpener control signal SH_CS2 starts with a logical zero and changes to a logical high at the quantization value QV update time before the end of the field time period FT. In other words, if the quantization value QV of the sharpener pixel S_P(X, Y) is greater than zero, if the transition value T_V is equal to 255 minus the quantization value QV of the sharpener pixel S_P(X, Y), the sharpener control signal SH_CS2 starts with a logical low at the update time UT_0 and changes to a logical high at the update time UT_T_V (as Figure 7C shown).

[0137] In Figure 6B , the basic image control signal B_CS is applied to the logical low input terminal of the multiplexer 665. The inverted sharpener sign bit signal!SH_SB is applied to the logical high input terminal of the multiplexer 665. The sharpener image control signal SH_CS2 is applied to the control terminal of the multiplexer 665. Refer to Figure 7C and Figure 7D for a more detailed explanation of the operation of the embodiment of Figure 6B .

[0138] Figure 7C and Figure 7E illustrate Figure 6B of the operation of the embodiment. Figure 7C Illustrates the signals when the quantization value QV of the sharpener pixel S_P(X, Y) is positive. As described above, the basic image memory cell 615 outputs the basic image control signal B_CS, which is driven to a logical high at the update time UT_0 and changes to a logical low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The inverted sharpener sign bit memory cell 635 stores the inverted sign bit of the quantization value QV of the pixel S_P(X, Y). In Figure 7C , the quantization value QV of the sharpener pixel S_P(X, Y) is positive. Therefore, the sign bit of the quantization value is zero and the inverted sign bit is one. Therefore, the inverted sharpener sign bit signal!SH_SB is at a logical high during the frame update period FT. The sharpener image memory cell 625 outputs the sharpener control signal SH_CS2. For Figure 7C, the quantization value QV of the sharper pixel S_P(X, Y) is positive; thus, the sharper control signal SH_CS2 starts at logic low at the update time UT_0 and transitions to logic high at the update time UT_T_V, where the transition value T_V is equal to 255 minus the quantization value QV of the sharper pixel S_P(X, Y). The sharper image control signal SH_CS2 controls the multiplexer 665 that drives the pixel control signal PCS. When the sharper image control signal SH_CS2 is at logic low, the multiplexer outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the sharper image control signal SH_CS2 is at logic high, the multiplexer 665 outputs a copy of the inverted sharper sign bit signal!SH_SB as the pixel control signal PCS. Thus, the pixel control signal PCS is at logic high at the update time UT_0, transitions to logic low at the update time UT_BV, and transitions to logic high at the update time UT_T_V, and remains at logic high during the remaining frame update period FT. Thus, Figure 7C the pixel control signal PCS of Figures 3 to 5 achieves the same result as shown in Figure 5 by adding the quantization value QV of a sharper pixel to the color component of a basic pixel (specifically, see

[0139] Figure 7D the pixel control signals PCS_R(1, 0) and PCS_R(1, 1) of Figure 7D . Illustrated are the signals when the quantization value QV of the sharper pixel S_P(X, Y) is negative. As described above, the basic image memory cell 615 outputs the basic image control signal B_CS, which is driven to logic high at the update time UT_0 and transitions to logic low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The sharper image memory cell 625 outputs the sharper control signal SH_CS2. For Figure 7D , the quantization value QV of the sharper pixel S_P(X, Y) is negative, so the sharper control signal SH_CS2 starts at logic high at the update time UT_0 and transitions to logic low at the update time UT_A_QV, where the transition value A_QV is equal to the absolute value of the quantization value QV of the sharper pixel S_P(X, Y). At Figure 7DAmong them, the quantization value QV of the sharpener pixel S_P(X, Y) is negative. Therefore, the sign bit of the quantization value is one, and the inverted sign bit is zero. Therefore, the inverted sharpener sign bit signal!SH_SB is at logic low during the frame update period FT. The sharpener image control signal SH_CS2 controls the multiplexer 665 that drives the pixel control signal PCS. When the sharpener image control signal SH_CS2 is at logic low, the multiplexer outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the sharpener image control signal SH_CS2 is at logic high, the multiplexer 665 outputs a copy of the inverted sharpener sign bit signal!SH_SB as the pixel control signal PCS. Therefore, the pixel control signal PCS is at logic low at the update time UT_0, turns to logic high at the update time UT_A_QV, and turns to logic low at the update time UT_BV, and remains at logic low during the remaining frame update period FT. Therefore, Figure 7D the pixel control signal PCS of Figure 7D is achieved by adding the quantization value QV of a sharpener pixel (which is negative in Figures 3 to 5 ) to the color component of a basic pixel to obtain the same result as shown in Figure 5 (specifically, refer to the pixel control signal PCS_R(0, 1) of

[0140] Figure 7E This again illustrates the signal when the quantization value QV of the sharpener pixel S_P(X, Y) is negative. However, in Figure 7E , the magnitude of the quantization value QV of the sharpener pixel S_P(X, Y) is greater than the magnitude of the basic value BV. Just as in Figure 7D , the image control signal B_CS is driven to logic high at the update time UT_0 and turns to logic low at the update time UT_BV; the sharpener control signal SH_CS2 starts at logic high at the update time UT_0 and turns to logic low at the update time UT_A_QV; and the inverted sharpener sign bit signal!SH_SB is at logic low during the frame update period FT. However, in Figure 7EIn it, the update time UT_A_QV occurs after the update time UT_BV because the magnitude of the quantization value QV of the sharpener pixel S_P(X, Y) is greater than the magnitude of the base value BV. Therefore, within the continuous frame update period FT, the pixel control signal should be at logic low. The sharpener image control signal SH_CS2 controls the multiplexer 665 that drives the pixel control signal PCS. When the sharpener image control signal SH_CS2 is at logic low, the multiplexer outputs a copy of the base image control signal B_CS as the pixel control signal PCS. However, when the sharpener image control signal SH_CS2 is at logic high, the multiplexer 665 outputs a copy of the inverted sharpener sign bit signal!SH_SB as the pixel control signal PCS. Therefore, the pixel control signal PCS is at logic low at the update time UT_0 and remains at logic low during the remaining frame update period FT. Therefore, Figure 7E the pixel control signal PCS is achieved by adding the quantization value QV of a sharpener pixel (which is negative in Figure 7E ) to the color component of a base pixel to obtain the same result as that shown in Figures 3 to 5 (specifically, refer to the blue component D_B(0, 1) in Figure 4 ).

[0141] Figure 8 FIG. shows another embodiment of the present invention, which eliminates the Figure 6B inverted sharpener sign bit memory cell. Although eliminating the inverted sharpener sign bit memory cell saves only one processor element operation per field time period FT, eliminating the memory cell allows for more dense packaging of display pixels. Figure 8 It includes a base image memory cell 810 that generates a base image control signal B_CS, a sharpener image memory cell 820 that generates a sharpener image control signal SH_CS2, and a multiplexer 860 that outputs the pixel control signal PCS. The base image memory cell 810 is controlled in the same manner as described above for the base image memory cells 610 and 615 to generate the base image control signal. For the sake of brevity, it will not be elaborated further. Similarly, the sharpener image memory cell 820 is controlled in the same manner as described above for the sharpener image memory cell 625 to generate the sharpener image control signal SH_CS2.

[0142] In Figure 8In it, a basic image control signal B_CS is applied to the logic low input terminal of a multiplexer 860. A global input signal GI is applied to the logic high input terminal of the multiplexer 860. A sharpener image control signal SH_CS2 is applied to the control terminal of the multiplexer 860. Since the subtraction of the quantization value QV of the sharpener pixel S_P(X, Y) will occur at the start of the field time period, and the addition of the quantization value of the quantization value QV of the sharpener pixel S_P(X, Y) occurs at the end of the field time period FT, the global input signal GI starts at logic low at the update time UT_0, and transitions to logic high at a certain point called the global transition time GT of the update time UT_GT, and the global input signal GI remains at logic high within the remaining field update period FT. In most embodiments of the present invention, the global transition time GT is set to 128, i.e., the middle of the frame update period. However, some embodiments of the present invention will use a different fixed global transition time, and other embodiments of the present invention may have a dynamic global transition time, which may vary from field to field, or even vary between columns, rows, or other groupings within the same field. Refer to Figure 9A and Figure 9B explain in more detail Figure 8 the operation of the embodiment of

[0143] Figure 9A and Figure 9B illustrate Figure 8 the operation of the embodiment of Figure 9A Illustrate the signal when the quantization value QV of the sharpener pixel S_P(X, Y) is positive. As described above, the basic image memory cell 810 outputs a basic image control signal B_CS, which is driven to logic high at the update time UT_0 and transitions to logic low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The global input signal GI is at logic low at the update time UT_0 and transitions to logic high at the update time UT_GT, where GT is the global transition time. The sharpener image memory cell 820 outputs a sharpener control signal SH_CS2. For Figure 9A, the quantization value QV of the sharpener pixel S_P(X, Y) is positive; thus, the sharpener control signal SH_CS2 starts at logic low at the update time UT_0 and transitions to logic high at the update time UT_T_V, where the transition value T_V is equal to 255 minus the quantization value QV of the sharpener pixel S_P(X, Y). The sharpener image control signal SH_CS2 controls the multiplexer 860 that drives the pixel control signal PCS. When the sharpener image control signal SH_CS2 is at logic low, the multiplexer outputs a copy of the base image control signal B_CS as the pixel control signal PCS. However, when the sharpener image control signal SH_CS2 is at logic high, the multiplexer 860 outputs a copy of the global input signal GI as the pixel control signal PCS. Thus, the pixel control signal PCS is at logic high at the update time UT_0, transitions to logic low at the update time UT_BV, and transitions to logic high at the update time UT_T_V, and remains at logic high for the remaining frame update period FT. Thus, Figure 9A the pixel control signal PCS is achieved by adding the quantization value QV of a sharpener pixel to the color component of a base pixel and is the same as Figures 3 to 5 that shown (specifically, see Figure 5 the pixel control signals PCS_R(1, 0) and PCS_R(1, 1)).

[0144] Figure 9B illustrates the signals when the quantization value QV of the sharpener pixel S_P(X, Y) is negative. As described above, the base image memory cell 810 outputs the base image control signal B_CS, which is driven to logic high at the update time UT_0 and transitions to logic low at the update time UT_BV, where the base value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the base image B (as described above). The global input signal GI is at logic low at the update time UT_0 and transitions to logic high at the update time UT_GT, where GT is the global transition time. The sharpener image memory cell 820 outputs the sharpener control signal SH_CS2. For Figure 9B, the quantization value QV of the sharpener pixel S_P(X, Y) is negative. Therefore, the sharpener control signal SH_CS2 starts at logic high at the update time UT_0 and transitions to logic low at the update time UT_A_QV, where the transition value A_QV is equal to the absolute value of the quantization value QV of the sharpener pixel S_P(X, Y). The sharpener image control signal SH_CS2 controls the multiplexer 860 that drives the pixel control signal PCS. When the sharpener image control signal SH_CS2 is at logic low, the multiplexer outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the sharpener image control signal SH_CS2 is at logic high, the multiplexer 860 outputs a copy of the global input signal GI as the pixel control signal PCS. Thus, the pixel control signal PCS is at logic low at the update time UT_0, transitions to logic high at the update time UT_A_QV, and transitions to logic low at the update time UT_BV, and remains at logic low for the remaining frame update period FT. Therefore, Figure 9B the pixel control signal PCS of Figure 9B is achieved by adding the quantization value QV of a sharpener pixel (which is negative in Figures 3 to 5 ) to the color component of a basic pixel to obtain the same result as that shown in Figure 5 (specifically, refer to the pixel control signal PCS_R(0, 1) of

[0145] Although not shown in Figure 9A and Figure 9B , there are limitations to the embodiment of Figure 8 . Specifically, for the embodiment of Figure 8 , the addition is limited by the number of update times remaining after the update time UT_GT (i.e., the number of update times when the global input signal GI is at logic high). For example, if in Figure 9A , the update time UT_GT at which the global input signal GI transitions to logic high occurs after the update time UT_T_V at which the sharpener control signal SH_CS2 transitions to logic high, the pixel control signal PCS will not transition to logic high again before the update time UT_GT, which will result in the decompressed pixel being darker than desired.

[0146] In addition, the subtraction is limited by the number of update times before the update time UT_GT (i.e., the number of update times when the global input signal GI is at logic low). For example, if in Figure 9BIn the case where the update time UT_GT at which the global input signal GI transitions to logic high occurs before the update time UT_T_V at which the sharpener control signal SH_CS2 transitions to logic high, the pixel control signal PCS will transition to logic high at the update time UT_GT, which will cause the decompressed pixel to be brighter than desired. Therefore, for pixels where the magnitude of the quantization value QV of the sharpener pixel S_P(X, Y) is high relative to the global transition time GT, the image quality of the decompressed image will be degraded. However, as described above, generally larger quantization errors are acceptable for larger variations in the high-frequency luminance components, since such errors are less likely to be detected at the edges or in the texture of the input image.

[0147] Some embodiments of the present invention improve by selecting a column of sharpener values within a known range of the correction capabilities provided by the global input signal GI Figure 8 the results of the embodiments. For example, in one embodiment of the present invention, the maximum positive sharpener value is less than or equal to the number of the update time when the global input is at logic high (i.e., 256 minus UT_GT). The maximum magnitude of the negative sharpener value is less than or equal to the number of the update time when the global input signal GI is at logic low (i.e., UT_GT). Other embodiments of the present invention expand Figure 8 the embodiments by dividing the display into a set of regions. Each region uses a region input signal instead of using a global input signal for the entire display.

[0148] However, Figure 10 shows an embodiment of the present invention that solves Figure 8 the scope limitation problem of the embodiments. Figure 10Including a basic image memory cell 1010 that generates a basic image control signal B_CS, a sharpener image memory cell 1030 that generates a sharpener image control signal SH_CS3, and a multiplexer 1060 that outputs a pixel control signal PCS. The basic image memory cell 1010 is controlled in the same manner as described above for the basic image memory cell 610 to generate the basic image control signal B_CS. For the sake of brevity, it will not be elaborated further. The basic image control signal B_CS is applied to an input terminal of an inverter 1015, and the inverter 1015 outputs an inverted basic image control signal!B_CS. The sharpener image memory cell 1030 is controlled in a manner similar to that described above for the sharpener image memory cell 625 to generate the sharpener image control signal SH_CS3. However, the sharpener image control signal SH_CS3 is configured to transition at a reasonable update time relative to the basic value BV and the inverted basic image control signal!B_CS. Specifically, the combination of the basic value BV and the quantization value QV of the sharpener pixel should be within the range of 0 to 255 + / - an acceptable variance. Some embodiments of the present invention select the quantization value QV when generating the sharpener value such that the quantization value QV of the sharpener is limited to an additive value approximately less than or equal to 255 - the basic value BV and a subtractive value approximately less than or equal to the basic value BV. In other embodiments, the generation of the sharpener control signal SH_CS3 is tested for the sharpener and the basic value to determine the correct transition time. Additional sharpener comparison times can be generated for the sharpener quantization value and the basic value to further improve the image performance. In Figure 10 , the basic image control signal B_CS is applied to the logic low input terminal of the multiplexer 1060. The inverted basic image control signal!B_CS from the output terminal of the inverter 1015 is applied to the logic high input terminal of the multiplexer 1060 instead of using the global input signal GI. In some embodiments of the present invention, the basic image memory cell 1010 can directly output the inverted basic image control signal!B_S without using the inverter 1015. The multiplexer 1060 outputs the pixel control signal PCS. Refer to Figure 11A and Figure 11B for a more detailed explanation of Figure 10 the operation of the embodiment.

[0149] Figure 11A and Figure 11B illustrate Figure 10 the operation of the embodiment. Figure 11AIllustrate the signal when the quantization value QV of the sharpener pixel S_P(X, Y) is positive. As described above, the basic image memory cell 1010 outputs a basic image control signal B_CS, which is driven to logic high at the update time UT_0 and transitions to logic low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The inverted basic image control signal!B_CS is at logic low at the update time UT_0 and transitions to logic high at the update time UT_BV. The sharpener image memory cell 1030 outputs a sharpener control signal SH_CS3. For Figure 11A , the quantization value QV of the sharpener pixel S_P(X, Y) is positive, so the sharpener control signal SH_CS3 starts at logic low at the update time UT_0 and transitions to logic high at the update time UT_T_V, where the transition value T_V is equal to 255 minus the quantization value QV of the sharpener pixel S_P(X, Y). In Figure 11A , the update time UT_T_V is earlier than Figure 9A to better illustrate Figure 10 's advantages of the embodiment over Figure 8 's embodiment. Similarly, the update time UT_BV is also earlier (indicating that the smaller the value of the basic value BV, the greater the addition ability of the quantization value QV). The sharpener image control signal SH_CS3 controls the multiplexer 1060 that drives the pixel control signal PCS. When the sharpener image control signal SH_CS3 is at logic low, the multiplexer 1060 outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the sharpener image control signal SH_CS3 is at logic high, the multiplexer 1060 outputs a copy of the inverted basic image control signal!B_CS as the pixel control signal PCS. Therefore, the pixel control signal PCS is at logic high at the update time UT_0, transitions to logic low at the update time UT_BV, and transitions to logic high at the update time UT_T_V, and remains at logic high during the remaining frame update period FT. Therefore, Figure 11A 's pixel control signal PCS achieves the same result as Figures 3 to 5 by adding the quantization value QV of a sharpener pixel to the color component of a basic pixel (specifically, see Figure 5 's pixel control signals PCS_R(1, 0) and PCS_R(1, 1)). If the methods such as Figure 9A and Figure 9BReplace the inverted basic image signal!B_CS with the global input signal GI shown. Then, the resulting pixel control signal PCS will be logic high at the update time UT_0, turn logic low at the update time UT_BV, and turn logic high at the update time UT_GT, and remain logic high during the remaining frame update period FT. This will result in more time being logic low than desired because the update time UT_GT will be later than the update time UT_BV.

[0150] Figure 11B An example of the signal when the quantization value QV of the sharpener pixel S_P(X, Y) is negative. As described above, the basic image memory cell 1010 outputs the basic image control signal B_CS, which is driven to logic high at the update time UT_0 and turns logic low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The inverted basic image control signal!B_CS is logic low at the update time UT_0 and turns logic high at the update time UT_BV. The sharpener image memory cell 1030 outputs the sharpener control signal SH_CS3. For Figure 11B , the quantization value QV of the sharpener pixel S_P(X, Y) is negative, so the sharpener control signal SH_CS3 starts at logic high at the update time UT_0 and turns logic low at the update time UT_A_QV, where the transition value A_QV is equal to the absolute value of the quantization value QV of the sharpener pixel S_P(X, Y). In Figure 11B , the update time UT_A_QV is later than in Figure 9B to better illustrate Figure 10 the advantages of the embodiment of Figure 8 over the embodiment of Figure 11BThe pixel control signal PCS is achieved by adding the quantization value QV of a sharpened pixel (which is negative in Figure 11B ) to the color component of a basic pixel to achieve the same result as shown in Figures 3 to 5 (specifically, see the pixel control signal PCS_R(1, 1)). If a global input signal GI as shown in Figure 9A and Figure 9B is used to replace the inverted basic image signal!B_CS, the resulting pixel control signal PCS will be logic low at the update time UT_0, turn to logic high at the update time UT_GT, turn to logic low at the update time UT_BV, and remain logic low within the remaining frame update period FT, which will be at logic high for more time than desired because the update time UT_GT will be earlier than the update time UT_BV; thus, an additional range of UT_A_QV showing a basic bit control correction range is shown.

[0151] Figure 12 Figure 11C shows another embodiment of the present invention, in which an inverted quantization local memory cell 1216 is used to generate a quantization local input signal Q_LI to replace the global input signal GI ( Figure 8 , Figure 9A and Figure 9B ) or the inverted basic image control signal!B_CS ( Figure 10 , Figure 11A , Figure 11B and Figure 11C). Figure 12 It also includes a basic image memory cell 1210 that generates a basic image control signal B_CS, a sharpened image memory cell 1230 that generates a sharpened image control signal SH_CS4, and a multiplexer 1260 that outputs the pixel control signal PCS. The basic image memory cell 1210 is controlled in the same manner as described above for the basic image memory cells 615, 810, or 1010 to generate the basic image control signal B_CS. For the sake of brevity, it will not be elaborated further. Similarly, the sharpened image memory cell 1230 is controlled in a similar manner as described above for the sharpened image memory cell 1030 to generate the sharpened image control signal SH_CS4. For the sake of brevity, it will not be elaborated further. In Figure 12In [the figure], inverting the quantized local input memory cell 1216 generates a quantized local input signal Q_LI, and the quantized local input signal Q_LI is applied to the logic low input terminal of the multiplexer 1260. Similar to the basic image memory cells (610, 810, 1010, and 1210), the local input memory cell 1216 is shared by the basic pixel blocks, which reduces the number of processor element operations required to operate the memory cells. In contrast, to invert the basic image control signal!B_CS, the inverted quantized basic memory cell changes only at specific fixed update times (similar to the way the quantized values of the shaper image memory cells are used). In a specific embodiment of the present invention, the inverted quantized basic memory cell uses several of the same quantized values as the shaper image memory cell 625 to align the switching time of the quantized local input signal Q_LI with the update time of the shaper image control signal SH_CS4. However, other embodiments of the present invention may use different quantized values.

[0152] Generally, the quantized local input signal Q_LI will start with a logic low, remain low for a predetermined minimum time, and transition to a logic high at the update time UT_Q_LV during the frame update period FT. The update time UT_Q_LV is selected based on a basic value or a predetermined maximum time when UT_Q_LV is driven high. Generally, in such cases, the maximization of image quality is achieved by minimizing the possible error generated by combining the basic value and the shaper value during the generation of the pixel control signal. By forcing Q_LI to be low for a defined time and high for a defined time, smaller shaper values (which are more susceptible to higher visual inspection) will be presented in an ideal manner. The update time UT_Q_LV (when the quantized local input signal Q_LI transitions to a logic high) is generally close to the update time UT_BV (the update time when the basic control signal B_CS transitions to a logic low), but can be before or after the update time UT_BV.

[0153] Figure 6B Embodiments of Figure 12 and Figure 12 Embodiments of each are shown as having 3 memory cells. However, Figure 12 The quantized local input memory cell 1216 of the Figure 6B embodiment is shared by all the pixels of the block. In contrast, there is an inverted shaper sign bit memory cell 635 for each pixel of the block. Therefore, the display using the

[0154] Figure 13A and Figure 13B Embodiments Figure 12 illustrate the operation of the Figure 13AAn example of a signal when the quantization value QV of the sharpener pixel S_P(X, Y) is positive. As described above, the basic image memory cell 1210 outputs a basic image control signal B_CS, which is driven to a logic high at the update time UT_0 and transitions to a logic low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The quantized local input signal Q_LI is at a logic low at the update time UT_0 and transitions to a logic high at the update time UT_Q_LI. As described above, the quantized local input signal Q_LI transitions only at preselected quantization values, and thus the transition of the quantized local input signal Q_LI is selected to match the desired correction range of the sharpener pixel S_P(X, Y) associated with the color component B_C(int(X / 2), int(Y / 2)). The sharpener image memory cell 1230 outputs a sharpener control signal SH_CS4. For Figure 13A , the quantization value QV of the sharpener pixel S_P(X, Y) is positive, so the sharpener control signal SH_CS4 starts at a logic low at the update time UT_0 and transitions to a logic high at the update time UT_T_V, where the transition value T_V is equal to 255 minus the quantization value QV of the sharpener pixel S_P(X, Y). The sharpener image control signal SH_CS4 controls the multiplexer 1260 that drives the pixel control signal PCS. When the sharpener image control signal SH_CS4 is at a logic low, the multiplexer 1260 outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the sharpener image control signal SH_CS4 is at a logic high, the multiplexer 1260 outputs a copy of the quantized local input signal Q_LI as the pixel control signal PCS. Thus, the pixel control signal PCS is at a logic high at the update time UT_0, transitions to a logic low at the update time UT_BV, and transitions to a logic high at the update time UT_T_V, and remains at a logic high during the remaining frame update period FT. Thus, Figure 13A the pixel control signal PCS of Figures 3 to 5 achieves the same result as that shown in Figure 5 by adding the quantization value QV of a sharpener pixel to the color component of a basic pixel (specifically, see the pixel control signals PCS_R(1, 0) and PCS_R(1, 1) of

[0155] Figure 13BIllustrate the signal when the quantization value QV of the sharpener pixel S_P(X, Y) is negative. As described above, the basic image memory cell 1210 outputs a basic image control signal B_CS, which is driven to logic high at the update time UT_0 and transitions to logic low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The quantized local input signal Q_LI is at logic low at the update time UT_0 and transitions to logic high at the update time UT_Q_LI. As described above, the quantized local input signal Q_LI transitions only at preselected quantization values. The sharpener image memory cell 1230 outputs a sharpener control signal SH_CS4. For Figure 13B , the quantization value QV of the sharpener pixel S_P(X, Y) is negative, so the sharpener control signal SH_CS4 starts at logic high at the update time UT_0 and transitions to logic low at the update time UT_A_QV, where the transition value A_QV is equal to the absolute value of the quantization value QV of the sharpener pixel S_P(X, Y). The sharpener image control signal SH_CS4 controls the multiplexer 1260 that drives the pixel control signal PCS. When the sharpener image control signal SH_CS4 is at logic low, the multiplexer outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the sharpener image control signal SH_CS4 is at logic high, the multiplexer 1260 outputs a copy of the inverted quantized local input signal Q_LI as the pixel control signal PCS. Thus, the pixel control signal PCS is at logic low at the update time UT_0, transitions to logic high at the update time UT_A_QV, transitions to logic low at the update time UT_BV, and remains at logic low during the remaining frame update period FT. Thus, Figure 13B 's pixel control signal PCS achieves the same result as Figure 13B (specifically, see the pixel control signal PCS_R(1, 1)) by adding the quantization value QV of a sharpener pixel (which is negative in Figures 3 to 5 ) to the color component of a basic pixel.

[0156] Some embodiments of the present invention improve the results of the embodiments of Figure 8 , Figure 10 and Figure 12 by combining the preferred qualities of each of the embodiments of Figure 8 , Figure 10 and Figure 12 into a single embodiment. Since the inverted basic control signal!B_CS( Figure 10)'s hardwired nature, when applied to extremely bright or extremely dark base values (i.e., when the update time UT_BV is early or late in the frame update period FT), may not ideally reproduce small sharpener values (which tend to represent smooth contouring and subtle shading transitions). This is because the inverted base control signal!B_CS transitions during these fine-tuning adjustment times, which is a result of its direct inversion of the base video control signal B_CS. In contrast, Figure 12 corrects this anomaly but requires maintaining the inversion of the quantized local memory cell 1216 during the frame update time, which increases the complexity of both the driver hardware and the scheduling compared to other embodiments of the present invention.

[0157] Figure 14 The embodiments of the present invention shown in Figure 10 utilize the automatic update quality of a sharpener correction signal SCS for a better support of large sharpener value offsets while supporting the ideal reproduction of small fine-tuning sharpener correction values, as in Figure 6A 、 Figure 6B 、 Figure 8 and Figure 12 embodiments. Figure 14 includes a base video memory cell 1410 that generates a base video control signal B_CS, a sharpener video memory cell 1430 that generates a sharpener video control signal SH_CS5, an inverter 1415 that outputs an inverted base control signal!B_CS, a multiplexer 1470 that outputs a sharpener control signal SCS, and a multiplexer 1460 that outputs a pixel control signal PCS. The base video memory cell 1410 is controlled in the same manner as described above for the base video memory cell 1210 to generate the base video control signal B_CS. For the sake of brevity, it will not be described again. Similarly, the sharpener video memory cell 1430 is controlled in a manner similar to that described above for the sharpener video memory cell 1230 to generate the sharpener video control signal SH_CS5. For large sharpener offsets, the combination of the base value BV and the quantized value QV of the sharpener pixel should be within the range of 0 to 255 + / - an acceptable variance. Some embodiments of the present invention enforce this condition when generating the sharpener value. In other embodiments, the generation of the sharpener control signal SH_CS5 is tested for the sharpener value and the base value, or only for the sharpener when the setting of the global control signal GC is set to logic high. Additional sharpener comparison times can be generated for the sharpener quantized value and the base value to further improve the image performance. In Figure 14In this case, the basic image control signal B_CS is applied to the logic low input terminal of the multiplexer 1460 and one input terminal of the inverter 1415. The inverter 1415 outputs the inverted basic image control signal!B_CS, and the inverted basic image control signal!B_CS is applied to the logic low input terminal of the multiplexer 1470. In some embodiments of the present invention, the basic image memory cell 1410 can directly output the inverted basic image control signal!B_S without using the inverter 1415. A global input signal GI_2 is applied to the logic high input terminal of the multiplexer 1470. The control of the global input signal GI_2 is the same as that described previously for the global input signal GI. For the sake of brevity, it will not be elaborated here. A global control signal GC is applied to the control terminal of the multiplexer 1470 and controls which signal is selected as the sharpener correction signal SCS at the output terminal of the multiplexer 1470. The sharpener correction signal SCS is applied to the logic high input terminal of the multiplexer 1460.

[0158] Conceptually, by allowing the pixel control signal PCS to be formed by the global input signal GI_2 and the inverted basic control signal and the basic control signal under the control of the global control signal GC and the sharpener control signal SH_CS5, Figure 14 the embodiments of Figure 8 incorporate Figure 10 the features of the embodiments of Figure 10 One of the problems of the embodiments of Figure 10 is that if the basic value is extremely large or extremely small, the inverted basic control signal!B_CS will change extremely early or extremely late in the frame update cycle FT. Therefore, the ability of the sharpener control signal SH_CS3 ( Figure 14An embodiment controls the sharpener control signal such that the transition of the sharpener control signal SCS from logic low to logic high occurs between the minimum sharpener update time UT_SCS_Min and the maximum sharpener update time UT_SCS_Max. Specifically, if the inverted basic control signal!B_CS transitions from logic low to logic high before the minimum sharpener update time UT_SCS_Min, the sharpener correction signal SCS transitions from logic low to logic high at the minimum sharpener update time UT_SCS_Min. If the inverted basic control signal!B_CS transitions from logic low to logic high after the maximum sharpener update time UT_SCS_Max, the sharpener correction signal SCS transitions from logic low to logic high at the maximum sharpener update time UT_SCS_Max. Specifically, if the inverted basic control signal!B_CS transitions from logic low to logic high between the minimum sharpener update time UT_SCS_Min and the maximum sharpener update time UT_SCS_Max, the sharpener correction signal SCS transitions from logic low to logic high while the inverted basic control signal!B_CS transitions. In one embodiment of the present invention, the update time SCS_Min is approximately 25% of the frame update time period, and SCS_Max is approximately 75% of the frame update time period. However, other embodiments of the present invention allocate the minimum sharpener update time SCS_MIN and the maximum sharpener update time SCS_Max based on the quantized sharpness value used.

[0159] Figure 15A , Figure 15B , Figure 15C and Figure 15D illustrates Figure 14 the operation of an embodiment. Figure 15A Illustrates the signal when the quantized value QV of the sharpener pixel S_P(X, Y) is small but positive. As described above, the basic image memory cell 1410 outputs the basic image control signal B_CS, which is driven to logic high at the update time UT_0 and transitions to logic low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The global input signal GI_2 is at logic low at the update time UT_0 and transitions to logic high at the update time UT_GT, where GT is the global transition time. For Figure 14 an embodiment, the global transition time can be any time between the minimum sharpener update time UT_SCS_Min and the maximum sharpener update time UT_SCS_Max. The sharpener image memory cell 1430 outputs the sharpener control signal SH_CS5. For Figure 15A, the quantization value QV of the sharpener pixel S_P(X, Y) is positive; thus, the sharpener control signal SH_CS5 starts at logic low at the update time UT_0 and transitions to logic high at the update time UT_T_V, where the transition value T_V is equal to 255 minus the quantization value QV of the sharpener pixel S_P(X, Y). The global control signal GC controls the multiplexer 1470 that drives the sharpener correction signal SCS. When the global control signal GC is at logic low, the multiplexer 1470 outputs a copy of the inverted basic image control signal!B_CS as the sharpener correction signal SCS. However, when the global control signal GC is at logic high, the multiplexer 1470 outputs a copy of the global input signal GI_2 as the sharpener correction signal SCS. In Figure 15A , the global control signal GC starts at logic high, transitions to logic low at the sharpener minimum update time UT_SCS_Min, and transitions to logic high at the sharpener maximum update time UT_SCS_Max. Since the update time UT_BV is between the sharpener minimum update time UT_SCS_Min and the sharpener maximum update time UT_SCS_Max, the sharpener correction signal SCS transitions at the same time as the inverted basic control signal!B_CS transitions. Thus, the sharpener correction signal SCS starts at logic low and transitions to logic high at the update time UT_BV.

[0160] The sharpener control signal SH_CS5 controls the multiplexer 1460 that drives the pixel control signal PCS. When the sharpener control signal SH_CS5 is at logic low, the multiplexer 1460 outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the sharpener image control signal SH_CS5 is at logic high, the multiplexer 1460 outputs a copy of the sharpener correction signal SCS as the pixel control signal PCS. Thus, the pixel control signal PCS is at logic high at the update time UT_0, transitions to logic low at the update time UT_BV, and transitions to logic high at the update time UT_T_V, and remains at logic high during the remaining frame update period FT. Thus, Figure 15A the pixel control signal PCS achieves the same result as Figures 3 to 5 shown by adding the quantization value QV of a sharpener pixel to the color component of a basic pixel (specifically, see Figure 5 the pixel control signals PCS_R(1, 0) and PCS_R(1, 1)).

[0161] Figure 15BIllustrate the signal when the quantization value QV of the sharpener pixel S_P(X, Y) is small but negative. As described above, the basic image memory cell 1410 outputs a basic image control signal B_CS, which is driven to logic high at the update time UT_0 and transitions to logic low at the update time UT_BV, where the basic value BV is the value of the color component B_C(int(X / 2), int(Y / 2)) of a pixel B_P(int(X / 2), int(Y / 2)) of the basic image B (as described above). The global input signal GI is at logic low at the update time UT_0 and transitions to logic high at the update time UT_GT, where GT is the global transition time. The sharpener image memory cell 1430 outputs a sharpener control signal SH_CS5. For Figure 15B , the quantization value QV of the sharpener pixel S_P(X, Y) is negative; thus, the sharpener control signal SH_CS5 starts at logic high at the update time UT_0 and transitions to logic low at the update time UT_A_QV, where the transition value A_QV is equal to the absolute value of the quantization value QV of the sharpener pixel S_P(X, Y). The global control signal GC controls the multiplexer 1470 that drives the sharpener correction signal SCS. When the global control signal GC is at logic low, the multiplexer 1470 outputs a copy of the inverted basic image control signal!B_CS as the sharpener correction signal SCS. However, when the global control signal GC is at logic high, the multiplexer 1470 outputs a copy of the global input signal GI as the sharpener correction signal SCS. The global control signal GC starts at logic high and transitions to logic low at the sharpener minimum update time UT_SCS_Min and transitions to logic high at the sharpener maximum update time UT_SCS_Max. Since the update time UT_BV is between the sharpener minimum update time UT_SCS_Min and the sharpener maximum update time UT_SCS_Max, the sharpener correction signal SCS transitions at the same time as the inverted basic control signal!B_CS transitions. Thus, the sharpener correction signal SCS starts at logic low and transitions to logic high at the update time UT_BV.

[0162] The shaper image control signal SH_CS5 controls the multiplexer 1460 that drives the pixel control signal PCS. When the shaper image control signal SH_CS5 is at a logical low, the multiplexer outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the shaper image control signal SH_CS5 is at a logical high, the multiplexer 1460 outputs a copy of the shaper correction signal SCS as the pixel control signal PCS. Thus, the pixel control signal PCS is at a logical low at the update time UT_0, transitions to a logical high at the update time UT_A_QV, and transitions to a logical low at the update time UT_BV, and remains at a logical low during the remaining frame update period FT. Thus, Figure 15B the pixel control signal PCS is achieved by adding the quantization value QV of a shaper pixel (which is negative in Figure 15B ) to the color component of a basic pixel to obtain the same result as that shown in Figures 3 to 5 (specifically, see the pixel control signal PCS_R(0, 1) in Figure 5 ).

[0163] Except when the basic value is extremely large so that the update time UT_BV is greater than the shaper maximum update time UT_SCS_Max, Figure 15C it is similar to Figure 15A . In addition, the basic value plus the shaper value is greater than 255. For the sake of brevity, only the changes between Figure 15C and Figure 15A are described in detail. The basic image control signal B_CS is driven to a logical high at the update time UT_0 and transitions to a logical low at the update time UT_BV, where the update time UT_BV is after the shaper maximum update time UT_SCS_Max as shown in Figure 15C . The inverted basic image control signal!B_CS is at a logical low at the update time UT_0 and transitions to a logical high at the update time UT_BV. The shaper control signal SH_CS5 starts at a logical low at the update time UT_0 and transitions to a logical high at the update time UT_T_V. The global input signal GI_2 is at a logical low at the update time UT_0 and transitions to a logical high at the update time UT_GT. The global control signal GC starts at a logical high and transitions to a logical low at the shaper minimum update time UT_SCS_Min and transitions to a logical high at the shaper maximum update time UT_SCS_Max. As described above, Figure 14 the embodiments of Figure 15CIn this case, the shaper correction signal SCS starts at a logic low and transitions to a logic high at the shaper maximum update time UT_SCS_Max. The shaper control signal SH_CS5 controls the multiplexer 1460 that drives the pixel control signal PCS. When the shaper control signal SH_CS5 is at a logic low, the multiplexer 1460 outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the shaper image control signal SH_CS5 is at a logic high, the multiplexer 1460 outputs a copy of the shaper correction signal SCS as the pixel control signal PCS. Thus, in Figure 15C the pixel control signal PCS is at a logic high at the update time UT_0 and remains at a logic high for the remainder of the frame update period FT. If the Figure 10 embodiment is used instead of the Figure 14 embodiment, and the timing allowed by SH_CS5 is replaced by SH_CS3, the pixel control signal PCS would have incorrectly transitioned to a logic low at the update time UT_T_V and then transitioned to a logic high at the time UT_BV due to an overflow error. However, by using the shaper correction signal SCS instead of just using the inverted basic control signal!B_CS, this type of overflow error can be handled by the Figure 14 embodiment without having to check the basic value. In other words, for shaper additions with values less than 255 - UT_SCS_Max, the shaper value itself is sufficient to determine the switching time of the shaper control signal SH_CS5.

[0164] Except when the basic value is extremely small such that the update time UT_BV is less than the shaper minimum update time UT_SCS_Min, Figure 15D similar to Figure 15B . Additionally, the basic value minus the absolute shaper value is less than 0. For the sake of brevity, only the changes between Figure 15D and Figure 15B are described in detail. The basic image control signal B_CS is driven to a logic high at the update time UT_0 and transitions to a logic low at the update time UT_BV, where the update time UT_BV is before the shaper minimum update time UT_SCS_Min as shown in Figure 15D . The inverted basic image control signal!B_CS is at a logic low at the update time UT_0 and transitions to a logic high at the update time UT_BV. The shaper control signal SH_CS5 starts at a logic high at the update time UT_0 and transitions to a logic low at the update time UT_A_QV. The global input signal GI_2 is at a logic low at the update time UT_0 and transitions to a logic high at the update time UT_GT. The global control signal GC starts at a logic high and transitions to a logic low at the shaper minimum update time UT_SCS_Min and transitions to a logic high at the shaper maximum update time UT_SCS_Max. As described above,Figure 14 The embodiment allows the sharpening control signal to transition to logic high only between the minimum sharpening update time UT_SCS_Min and the maximum sharpening update time UT_SCS_Max (including the two times). Therefore, in Figure 15D , the sharpener correction signal SCS starts at logic low and transitions to logic high at the minimum sharpening update time UT_SCS_Min. The sharpener control signal SH_CS5 controls the multiplexer 1460 that drives the pixel control signal PCS. When the sharpener control signal SH_CS5 is at logic low, the multiplexer 1460 outputs a copy of the basic image control signal B_CS as the pixel control signal PCS. However, when the sharpener image control signal SH_CS5 is at logic high, the multiplexer 1460 outputs a copy of the sharpener correction signal SCS as the pixel control signal PCS. Therefore, in Figure 15D , the pixel control signal PCS is at logic low at the update time UT_0 and remains at logic low during the remaining frame update period FT. If the Figure 10 embodiment is used instead of the Figure 14 embodiment, and the timing allowed for SH_CS5 is replaced with SH_CS3, the pixel control signal PCS would have transitioned to logic high erroneously at the update time UT_BV and then transitioned to logic low at the update time UT_A_QV due to an underflow error. However, by using the sharpener correction signal SCS instead of just using the inverted basic control signal!B_CS, this type of underflow error can be handled by the Figure 14 embodiment without checking the basic value. In other words, for sharpener subtractions with values less than UT_SCS_Min, the sharpener value itself is sufficient to determine the switching time of the sharpener control signal SH_CS5.

[0165] As described above, overflow (when the basic value plus the sharpener value is greater than 255) and underflow (when the basic value minus the sharpener value is negative) situations can lead to errors that degrade image quality. Some embodiments of the present invention take proactive steps to minimize such errors. Generally, there are two main types of overflow situations that deserve attention. In the first type of overflow situation, the sharpener value is large; in the second type of overflow situation, the sharpener value is small. Prior art that contains a single memory bit is vulnerable to both types of overflow situations. To correct overflow situations and in all cases, prior art-based systems must measure the basic value and the sharpener value to determine the transition time of the pixel control signal PCS. Based on Figure 6A or Figure 6B embodiments of the present invention are not vulnerable to overflow situations. The Figure 8 embodiments of the present invention as described above should not have a large sharpener value determined by the GI signal and are not affected by type 1 overflow situations. Additionally, based onFigure 8 The embodiments based on Figure 10 the present invention are vulnerable to two types of overflow situations. To minimize the error of the overflow situation, based on Figure 10 the embodiments can detect when the overflow situation can occur and can modify the sharpener value so that the sharpener control signal SH_CS3 can transition only according to a sharpener value that reduces or eliminates the error. One method for these situations is to always measure the base value and the sharpener value to determine a good transition time for the sharpener control signal SH_CS3; using this method, good image control can be obtained by adding instruction times that exceed the number of unique quantization values. Based on Figure 12 the embodiments of the present invention based on Figure 12 are not vulnerable to type 2 overflow situations. But to minimize the error of type 1 overflow situations, based on Figure 14 the embodiments can detect when the overflow situation can occur and can modify the sharpener value so that the sharpener control signal SH_CS4 transitions only according to a sharpener value that reduces or eliminates the overflow situation. One method for these situations is to measure the base value and the sharpener value to determine a good transition time for the sharpener control signal SH_CS4; using this method, good image control can be obtained by adding instruction times that exceed the number of unique quantization values. Based on Figure 14 the embodiments of the present invention based on Figure 14 are not vulnerable to type 2 overflow situations. But to minimize the error of type 1 overflow situations, based on Figure 14 the embodiments can detect when the overflow situation can occur and can modify the sharpener value so that the sharpener control signal SH_CS5 transitions only according to a sharpener value that reduces or eliminates the error. One method for these situations is to measure the base value and the sharpener value to determine a good transition time for the sharpener control signal SH_CS5; using this method, better image control can be obtained by adding instruction times that exceed the number of unique quantization values.

[0166] Generally speaking, there are two main types of underflow situations worthy of attention. In the first type of underflow situation, the magnitude of the sharpener value is large; in the second type of underflow situation, the magnitude of the sharpener value is small. The prior art containing a single memory bit is vulnerable to both types of underflow situations. To correct the underflow situation and in all cases, the embodiments based on the prior art must measure the base value and the sharpener value to determine the transition time of the pixel control signal PCS. Based on Figure 6A or Figure 6B the embodiments of the present invention are not vulnerable to underflow situations. As described above, the embodiments of the present invention based on Figure 8 should not have a large sharpener magnitude value determined by the GI signal and are not affected by type 1 underflow situations. In addition, based on Figure 8[[The embodiments do not have the problem of type 2 underflow. Based on ​ The embodiments of the present invention are susceptible to two types of underflow situations. To minimize the error of the underflow situation, based on ​ The embodiments can detect when the underflow situation can occur and can modify the sharpener value so that the sharpener control signal SH_CS3 can transition only according to a sharpener value that reduces or eliminates the error. One method for such situations is to always measure the base value and the sharpener value to determine a good transition time for the sharpener control signal SH_CS3; using this method, good image control can be obtained by adding instruction times that exceed the number of unique quantization values. Based on ​ The embodiments of the present invention are not susceptible to type 2 underflow situations. But to minimize the error of type 1 underflow situations, based on ​ The embodiments can detect when the underflow situation can occur and can modify the sharpener value so that the sharpener control signal SH_CS4 transitions only according to a sharpener value that reduces or eliminates the error. One method for such situations is to measure the base value and the sharpener value to determine a good transition time for the sharpener control signal SH_CS4; using this method, good image control can be obtained by adding instruction times that exceed the number of unique quantization values. Based on ​ The embodiments of the present invention are not susceptible to type 2 underflow situations. But to minimize the error of type 1 underflow situations, based on ​ The embodiments can detect when the underflow situation can occur and can modify the sharpener value so that the sharpener control signal SH_CS5 transitions only according to a sharpener value that reduces or eliminates the error. One method for such situations is to measure the base value and the sharpener value to determine a good transition time for the sharpener control signal SH_CS5; using this method, good image control can be obtained by adding instruction times that exceed the number of unique quantization values.

[0167] In various embodiments of the present invention, novel structures and methods for generating a pixel control signal have been described. The various embodiments of the structures and methods of the present invention described above only illustrate the principles of the present invention and are not intended to limit the scope of the present invention to the specific embodiments described. For example, in view of this disclosure, those skilled in the art can define other update times, global input signals, global control signals, sharpener control signals, base control signals, pixel control signals, field time periods, control signals, base images, sharpener images, color components, light modulation units, gamma corrections, etc., and use these alternative features to create a method or system according to the principles of the present invention. Therefore, the present invention is only limited by the following patent scope of the invention.

Claims

1. A method for generating a pixel control signal for controlling a pixel block having a first pixel and a second pixel, characterized in that, The method includes: generating a basic control signal shared by the pixel blocks; generating a first shaper control signal for the first pixel; generating a second shaper control signal for the second pixel; using the first shaper control signal and the basic control signal to generate a first pixel control signal; using the second shaper control signal and the basic control signal to generate a second pixel control signal.

2. The method for generating a pixel control signal according to claim 1, wherein The using the first shaper control signal and the basic control signal to generate a first pixel control signal further includes: generating a first shaper sign bit signal; combining the first shaper control signal and the basic control signal to form a first logical OR signal; combining the first shaper control signal and the basic control signal to form a first logical AND signal.

3. The method for generating a pixel control signal according to claim 2, wherein The using the first shaper control signal and the basic control signal to generate a first pixel control signal further includes: when the first shaper sign bit signal is in a first logic state, selecting the first logical OR signal as the first pixel control signal; and when the first shaper sign bit signal is in a second logic state, selecting the first logical AND signal as the first pixel control signal.

4. The method for generating a pixel control signal according to claim 2, wherein The using the second shaper control signal and the basic control signal to generate a second pixel control signal further includes: generating a second shaper sign bit signal; combining the second shaper control signal and the basic control signal to form a second logical OR signal; combining the second shaper control signal and the basic control signal to form a second logical AND signal; when the second shaper sign bit signal is in a first logic state, selecting the second logical OR signal as the second pixel control signal; and when the second shaper sign bit signal is in a second logic state, selecting the second logical AND signal as the second pixel control signal.

5. The method for generating a pixel control signal according to claim 4, wherein, The basic control signal is stored in a first memory cell; The first shaper control signal is stored in a second memory cell; The first shaper sign bit signal is stored in a third memory cell; The second shaper control signal is stored in a fourth memory cell; and The second shaper sign bit signal is stored in a fifth memory cell.

6. The method for generating a pixel control signal according to claim 1, wherein The basic control signal starts a field time period with a logic high and transitions to a logic low at a basic value update time; and wherein the first shaper control signal starts the field time period with a logic low and transitions to a logic high at a transition value update time, the transition value update time being a first shaper value from the end of the field time period.

7. The method for generating a pixel control signal according to claim 6, wherein The first pixel control signal starts the field time period with a logic high, transitions to a logic low at the basic value update time, and transitions to a logic high at the transition value update time, the transition value update time being the first shaper value from the end of the field time period.

8. The method for generating a pixel control signal according to claim 1, wherein The basic control signal starts at a logic high for a field time period and transitions to a logic low at a basic value update time; and wherein the first shaper control signal starts at a logic low for the field time period and transitions to a logic high at a transition value update time, the transition value update time being the absolute value of a first shaper value from the start of the field time period.

9. The method for generating a pixel control signal according to claim 8, wherein, The first pixel control signal starts at a logic low for the field time period, transitions to a logic high at the transition value update time, the transition value update time being the absolute value of the first shaper value from the start of the field time period, and transitions to a logic low at the basic value update time.

10. The method for generating a pixel control signal according to claim 1, wherein, The generating of a first pixel control signal using the first shaper control signal and the basic control signal further comprises: generating a first inverted shaper sign bit signal; selecting the basic control signal as the first pixel control signal when the first shaper control signal is in a first logic state; and selecting the first inverted shaper sign bit signal as the first pixel control signal when the first shaper control signal is in a second logic state.

11. The method for generating a pixel control signal according to claim 10, wherein The first logic state is a logic low, and the second logic state is a logic high.

12. The method for generating a pixel control signal according to claim 10, wherein The basic control signal starts at a logic high for a field time period and transitions to a logic low; and wherein the first shaper control signal starts at a logic high for the field time period and transitions to a logic low at a transition value update time, the transition value update time being the absolute value of a first shaper value from the start of the field time period.

13. The method for generating a pixel control signal according to claim 12, wherein The first pixel control signal starts at a logic low for the field time period, transitions to a logic high at the transition value update time, the transition value update time being the absolute value of the first shaper value from the start of the field time period, and transitions to a logic low at the basic value update time.

14. The method for generating a pixel control signal according to claim 10, wherein The generating of a second pixel control signal using the second shaper control signal and the basic control signal further comprises: generating a second inverted shaper sign bit signal; selecting the basic control signal as the second pixel control signal when the second shaper control signal is in a first logic state; and selecting the second inverted shaper sign bit signal as the second pixel control signal when the second shaper control signal is in a second logic state.

15. The method for generating a pixel control signal according to claim 1, wherein The basic control signal is stored in a first memory cell; The first shaper control signal is stored in a second memory cell; and The second shaper control signal is stored in a third memory cell.

16. The method of generating a pixel control signal according to claim 1, wherein the generating of a first pixel control signal using the first shaper control signal and the basic control signal further comprises: generating a global input signal; selecting the basic control signal as the first pixel control signal when the first shaper control signal is in a first logic state; and When the first shaper control signal is in a second logic state, the global input signal is selected as the first pixel control signal.

17. The method for generating a pixel control signal according to claim 16, wherein The generating a second pixel control signal using the second shaper control signal and the basic control signal further comprises: when the second shaper control signal is in a first logic state, selecting the basic control signal as the second pixel control signal; and when the second shaper control signal is in a second logic state, selecting the global input signal as the second pixel control signal.

18. The method of generating a pixel control signal as claimed in claim 16, wherein the basic control signal starts a field time period with a logic high and transitions to a logic low at a basic value update time; and wherein the global input signal starts the field time period with a logic low and transitions to a logic high at a global transition time.

19. The method for generating a pixel control signal according to claim 18, wherein, The global transition time is close to the middle of the field time period.

20. The method for generating a pixel control signal according to claim 1, wherein, The generating a first pixel control signal using the first shaper control signal and the basic control signal further comprises: generating an inverted basic control signal; when the first shaper control signal is in a first logic state, selecting the basic control signal as the first pixel control signal; and when the first shaper control signal is in a second logic state, selecting the inverted basic control signal as the first pixel control signal.

21. The method for generating a pixel control signal according to claim 20, wherein The generating a second pixel control signal using the second shaper control signal and the basic control signal further comprises: when the second shaper control signal is in the first logic state, selecting the basic control signal as the second pixel control signal; and when the second shaper control signal is in the second logic state, selecting the inverted basic control signal as the second pixel control signal.

22. The method for generating a pixel control signal according to claim 1, wherein, The generating a first pixel control signal using the first shaper control signal and the basic control signal further comprises: generating a quantized local input signal; when the first shaper control signal is in a first logic state, selecting the basic control signal as the first pixel control signal; and when the first shaper control signal is in a second logic state, selecting the quantized local input signal as the first pixel control signal.

23. The method for generating a pixel control signal according to claim 22, wherein The generating a second pixel control signal using the second shaper control signal and the basic control signal further comprises: when the second shaper control signal is in the first logic state, selecting the basic control signal as the second pixel control signal; and when the second shaper control signal is in the second logic state, selecting the quantized local input signal as the second pixel control signal.

24. The method for generating a pixel control signal according to claim 22, wherein The basic control signal is stored in a first memory cell; The quantized local input signal is stored in a second memory cell; The first shaper control signal is stored in a third memory cell; and The second shaper control signal is stored in a fourth memory cell.

25. The method for generating a pixel control signal according to claim 1, wherein Generating a first pixel control signal using the first sharpener control signal and the basic control signal further includes: Generating an inverted basic control signal; Generating a global input signal; Generating a global control signal; Generating a sharpener correction signal through the following steps When the global control signal is in a first logic state, selecting the inverted basic control signal as the sharpener correction signal; and When the global control signal is in a second logic state, selecting the global input signal as the sharpener control signal; When the first sharpener control signal is in the first logic state, selecting the basic control signal as the first pixel control signal; and When the first sharpener control signal is in the second logic state, selecting the sharpener correction signal as the first pixel control signal.

26. The method for generating a pixel control signal according to claim 25, wherein Generating a second pixel control signal using the second sharpener control signal and the basic control signal further includes: When the second sharpener control signal is in the first logic state, selecting the basic control signal as the second pixel control signal; and When the second sharpener control signal is in the second logic state, selecting the sharpener correction signal as the second pixel control signal.

27. The method for generating a pixel control signal according to claim 25, wherein The basic control signal starts a field time period with a logic high and transitions to a logic low at a basic value update time; Wherein the global input signal starts the field time period with a logic low and transitions to a logic high at a global transition time; and Wherein the global control signal starts the field time period with a logic high and transitions to a logic low at a sharpener minimum update time and transitions to a logic high at a sharpener maximum update time.

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