Battery pack and equalization sampling circuit thereof

Abstract

The application discloses a battery pack and an equalization sampling circuit thereof, wherein the equalization sampling circuit comprises a first operational amplifier, a first triode, a second operational amplifier, a single-chip microcomputer and the like; wherein a positive power supply end of the first operational amplifier is electrically connected to a positive electrode of an N+1th string of battery cells in the battery pack; an emitter of the first triode is connected to the positive electrode of the N+1th string of battery cells in the battery pack, and a collector of the first triode is electrically connected to; a positive power supply end of the second operational amplifier is electrically connected to a direct-current power supply, a positive input end of the second operational amplifier is electrically connected to a negative input end of the second operational amplifier, and an output end of the second operational amplifier is electrically connected to the single-chip microcomputer through a ninth resistor. The application has the beneficial effect of providing a battery pack and an equalization sampling circuit thereof capable of effectively reducing sampling power consumption and thus making battery cells relatively equalize discharge.

Description

Technical Field

[0001] This application relates to the field of battery pack technology, and more specifically, to a battery pack and its equalization sampling circuit. Background Technology

[0002] A battery pack typically contains multiple sets of battery cells, each consisting of one or more cells. During normal use, the battery pack's BMS (Battery Management System) controls charging and discharging through individual semiconductor switches.

[0003] Due to the increasing demands on battery pack performance, the number of cells in series within existing battery packs is constantly increasing. In current technology, the voltage detection chip (microcontroller) in the battery pack's BMS typically has a fixed number of detection ports to detect the positive terminals of different cell series combinations to achieve voltage sampling. When the number of cell series combinations exceeds the number of detection ports on the voltage detection chip, the number of voltage detection chips is often increased or their detection ports are reused. Increasing the number of voltage detection chips undoubtedly increases costs, while using semiconductor switches such as MOSFETs to switch a detection port to different cell combinations increases additional power output. In some cases, the power consumption may even exceed the power consumption required to add a single voltage detection chip. This can lead to uneven discharge of cells in some cell series over the long term. Summary of the Invention

[0004] The summary section of this application is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0005] Some embodiments of this application propose a battery pack and its equalization sampling circuit to solve the technical problems mentioned in the background section above.

[0006] As a first aspect of this application, some embodiments of this application provide an equalization sampling circuit suitable for voltage sampling of multiple series-connected cell combinations in a battery pack; the equalization sampling circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a DC power supply, a first operational amplifier, a first transistor, a first diode, a second operational amplifier, and a microcontroller; wherein, the positive power supply terminal of the first operational amplifier is electrically connected to the positive terminal of the (N+1)th series of cell combinations in the battery pack through the first resistor, the negative power supply terminal of the first operational amplifier is electrically connected to the positive terminal of the Nth series of cell combinations in the battery pack, and the positive input terminal of the first operational amplifier is electrically connected to the positive terminal of the Nth series of cell combinations and the (N+1)th series of cell combinations in the battery pack through the second resistor and the third resistor, respectively. The positive terminal of the first operational amplifier is electrically connected to the positive terminal of the (N+1)th series of cells in the battery pack via resistors four, five, and six. The output terminal of the first operational amplifier is electrically connected to the base of the first transistor via resistor seven. The emitter of the first transistor is electrically connected to the positive terminal of the (N+1)th series of cells in the battery pack via resistors five and six. The collector of the first transistor is electrically connected to the anode of the first diode via resistor eight. The positive power supply terminal of the second operational amplifier is electrically connected to a DC power supply, the negative power supply terminal of the second operational amplifier is grounded, the positive input terminal of the second operational amplifier is electrically connected to the cathode of the first diode, the negative input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is electrically connected to the microcontroller via resistor nine.

[0007] Furthermore, the first transistor was constructed as a PNP transistor.

[0008] Furthermore, the equalization sampling circuit also includes: a tenth resistor and an eleventh resistor connected in series; the second operational amplifier is grounded through the tenth resistor and the eleventh resistor.

[0009] Furthermore, the equalization sampling circuit also includes: a first capacitor; the first capacitor is connected in series with the tenth resistor and the eleventh resistor to form a parallel circuit.

[0010] Furthermore, the equalization sampling circuit also includes: a second capacitor; and a ninth resistor grounded through the second capacitor.

[0011] Furthermore, the equalization sampling circuit also includes: a third capacitor; the positive power supply terminal of the second operational amplifier is grounded through the third capacitor.

[0012] Furthermore, the equalization sampling circuit also includes: a Zener diode; the positive terminal of the Zener diode is electrically connected to the positive terminal of the Nth series of cells in the battery pack, and the positive terminal of the Zener diode is electrically connected to one end of the first resistor connected to the positive power supply terminal of the first operational amplifier.

[0013] Furthermore, the equalization sampling circuit also includes: an optocoupler, a second transistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor; wherein, the anode of the optocoupler is electrically connected to the DC power supply, the cathode of the optocoupler is electrically connected to the positive terminal of the (N+1)th string of cells in the battery pack through the twelfth resistor, the collector of the optocoupler is electrically connected to the positive terminal of the (N+1)th string of cells in the battery pack through the twelfth resistor, and the emitter of the optocoupler is electrically connected to the base of the second transistor through the thirteenth resistor; the collector of the third diode is electrically connected to the positive terminal of the (N+1)th string of cells in the battery pack through the fourteenth resistor, and the emitter of the third diode is electrically connected to the positive terminal of the Nth string of cells in the battery pack.

[0014] Furthermore, the second transistor is constructed as an NPN transistor.

[0015] As a second aspect of this application, some embodiments of this application provide a battery pack including the above-described equalization sampling circuit.

[0016] The beneficial effects of this application are: it provides a battery pack and its equalization sampling circuit that can effectively reduce sampling power consumption so that the cells can be discharged relatively evenly. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of the application and to make other features, objects, and advantages of the application more apparent. The illustrative embodiments and descriptions of this application are used to explain the application and do not constitute an undue limitation of the application.

[0018] Furthermore, throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the elements are not necessarily drawn to scale.

[0019] In the attached diagram: Figure 1 This is a schematic diagram of a portion of the circuitry in a battery pack according to an embodiment of this application; Figure 2 This is a schematic diagram of another part of the circuitry in a battery pack according to one embodiment of this application; Figure 3 This is a schematic diagram of a portion of the circuitry in a battery pack according to one embodiment of this application.

[0020] Meaning of the reference numerals in the diagram: BT17, the seventeenth series of battery cells; BT18, the eighteenth series of battery cells; R1, the first resistor; R2, the second resistor; R3, the third resistor; R4, the fourth resistor; R5, the fifth resistor; R6, the sixth resistor; R7, the seventh resistor; R8, the eighth resistor; R9, the ninth resistor; R10, the tenth resistor; R11, the eleventh resistor; R12, the twelfth resistor; R13, the thirteenth resistor; R14, the fourteenth resistor; U1, the first operational amplifier; U2, the second operational amplifier; U3, microcontroller; Q1, the first transistor; Q2, the second transistor; D1, the first diode; C1, the first capacitor; C2, the second capacitor; C3, the third capacitor; OC, optocoupler; ZG, Zener diode. Implementation

[0021] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0022] It should also be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. Unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0023] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0024] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0025] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0026] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] This application's battery pack comprises several cell combinations, such as a 24-cell series combination, where each cell combination contains several parallel-connected cell units. For ease of explanation, in... Figures 1 to 3 The image only shows the seventeenth and eighteenth cell combinations, BT17 and BT18, which are equivalent to the Nth and N+1th cell combinations, respectively.

[0028] Specifically, such as Figure 1 As shown, the equalization circuit in the battery pack of this application includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a DC power supply, a first operational amplifier U1, a first transistor Q1, a first diode D1, a second operational amplifier U2, and a microcontroller U3.

[0029] Specifically, the positive power supply terminal of the first operational amplifier U1 is electrically connected to the positive terminal of the eighteenth cell assembly BT18 in the battery pack through the first resistor R1. The negative power supply terminal of the first operational amplifier U1 is electrically connected to the positive terminal of the seventeenth cell assembly BT17 in the battery pack. The positive input terminal of the first operational amplifier U1 is electrically connected to the positive terminals of the seventeenth cell assembly BT17 and the eighteenth cell assembly BT18 in the battery pack through the second resistor R2 and the third resistor R3, respectively. The negative input terminal of the first operational amplifier U1 is electrically connected to the positive terminal of the eighteenth cell assembly BT18 in the battery pack through the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6. The output terminal of the first operational amplifier U1 is connected to the positive terminal of the eighteenth cell assembly BT18 in the battery pack through the seventh resistor R4. Resistor R7 is electrically connected to the base of the first transistor Q1; the emitter of the first transistor Q1 is electrically connected to the positive terminal of the eighteenth cell assembly BT18 in the battery pack through resistors R5 and R6; the collector of the first transistor Q1 is electrically connected to the positive terminal of the first diode D1 through resistor R8; the positive power supply terminal of the second operational amplifier U2 is electrically connected to the DC power supply, the negative power supply terminal of the second operational amplifier U2 is grounded, the positive input terminal of the second operational amplifier U2 is electrically connected to the negative terminal of the first diode D1, the negative input terminal of the second operational amplifier U2 is electrically connected to the output terminal of the second operational amplifier U2, and the output terminal of the second operational amplifier U2 is electrically connected to the microcontroller U3 through resistor R9.

[0030] It should be noted that the DC power supply can be a power chip or an external circuit, and its main output is a potential point of 3.3V. Only this potential point is shown in the figure.

[0031] By configuring the resistor values ​​at the positive, negative, and output terminals of the first operational amplifier U1, primarily the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6, the first operational amplifier U1 can function as an operational amplifier, amplifying the voltage difference between its positive and negative input terminals as its output. The resistors at the positive and negative input terminals are not exactly the positive voltage of the eighteenth cell assembly BT18, but rather the voltage after resistor division. This results in a voltage at the output of the first operational amplifier U1 that is coupled to the positive voltage of the eighteenth cell assembly BT18. The current generated by this voltage is input to the first transistor Q1, amplified, and then input to the first diode D1. This means that the voltage input to the second operational amplifier U2 through the first diode D1 is a voltage value coupled to the positive voltage of the eighteenth cell assembly BT18.

[0032] At this point, the peripheral circuit of the second operational amplifier U2 is used as a voltage follower, which can achieve load isolation and reduce the load generated by the voltage collected by the microcontroller U3. This is much lower than the previous method of directly inputting the positive voltage of the eighteenth series of battery cells BT18 to the load generated by the microcontroller U3 (there is still a step-down resistor between the microcontroller U3 and this point).

[0033] In a specific design, the first transistor Q1 is configured as a PNP transistor. The equalization sampling circuit also includes: a tenth resistor R10 and an eleventh resistor R11 connected in series; the second operational amplifier U2 is grounded through the tenth and eleventh resistors R10 and R11. The equalization sampling circuit also includes: a first capacitor; the first capacitor, the tenth resistor R10, and the eleventh resistor R11 are connected in series to form a parallel circuit. This serves to buffer current surges.

[0034] The equalization sampling circuit also includes: a second capacitor and a third capacitor; the ninth resistor R9 is grounded through the second capacitor C2. The positive power supply terminal of the second operational amplifier U2 is grounded through the third capacitor C3. The second and third capacitors here also serve to buffer impacts.

[0035] As a preferred option, such as Figure 2 As shown, the equalization sampling circuit also includes: optocoupler OC, second transistor Q2, twelfth resistor R12, thirteenth resistor R13 and fourteenth resistor R14.

[0036] In this configuration, the anode of the optocoupler OC is electrically connected to a DC power supply, the cathode of the optocoupler OC is electrically connected to the positive terminal of the (N+1)th string of cells in the battery pack via the twelfth resistor R12, the collector of the optocoupler OC is electrically connected to the positive terminal of the (N+1)th string of cells in the battery pack via the twelfth resistor R12, and the emitter of the optocoupler OC is electrically connected to the base of the second transistor Q2 via the thirteenth resistor R13. The collector of the third diode is electrically connected to the positive terminal of the (N+1)th string of cells in the battery pack via the fourteenth resistor R14, and the emitter of the third diode is electrically connected to the positive terminal of the Nth string of cells in the battery pack. The second transistor Q2 is configured as an NPN transistor.

[0037] This circuit section can provide a branch for current flow between the nineteenth cell assembly (not shown in the figure) and the seventeenth cell assembly BT17 through the second transistor Q2 when the positive terminal voltage of the eighteenth cell assembly BT18 is less than 3.3V (for example, when the connection is damaged). This prevents the eighteenth cell assembly from causing an imbalance in the overall battery pack under low voltage conditions such as being depleted.

[0038] As a preferred option, such as Figure 3 As shown, the equalization sampling circuit also includes: a Zener diode; the positive terminal of the Zener diode is electrically connected to the positive terminal of the Nth cell assembly in the battery pack, and the positive terminal of the Zener diode is electrically connected to one end of the first resistor R1 connected to the positive power supply terminal of the first operational amplifier U1. This is to protect the circuit containing the cell assembly when a problem occurs in the eighteenth cell assembly BT18 (such as an open circuit) causing its positive voltage to be lower than the positive terminal of the seventeenth cell assembly BT17.

[0039] It should be noted that, Figure 1 The output of the second operational amplifier is electrically connected to the microcontroller U3 through the ninth resistor R9. In fact, it can also be connected to the microcontroller U3 through some switching circuits with MOSFETs. This allows the detection ports of the microcontroller U3 to be multiplexed. For example, if the microcontroller U3 only has 16 detections, some of its detection ports can be shared by the seventeenth cell combination BT17 and the eighteenth cell combination BT18 through the switching circuit.

[0040] It should also be noted that Figure 1 The example shown only illustrates the seventeenth cell string combination BT17 and the eighteenth cell string combination BT18. In reality, the sixteenth cell string combination and the seventeenth cell string combination BT17 in this battery pack also have a similar relative relationship and peripheral circuitry as the seventeenth cell string combination BT17 and the eighteenth cell string combination BT18. That is to say, similar circuit schemes can be set between the Nth and N+1th cell string combinations.

[0041] The above description is merely a selection of preferred embodiments of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in the embodiments of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in the embodiments of this disclosure.

Claims

1. An equalization sampling circuit, suitable for voltage sampling of multiple series-connected battery cells in a battery pack; characterized in that: The equalization sampling circuit includes: First resistor, second resistor, third resistor, fourth resistor, fifth resistor, sixth resistor, seventh resistor, eighth resistor, ninth resistor, DC power supply, first operational amplifier, first transistor, first diode, second operational amplifier, microcontroller; The positive power supply terminal of the first operational amplifier is electrically connected to the positive terminal of the (N+1)th cell assembly in the battery pack via the first resistor. The negative power supply terminal of the first operational amplifier is electrically connected to the positive terminal of the Nth cell assembly in the battery pack. The positive input terminal of the first operational amplifier is electrically connected to the positive terminals of the Nth and (N+1)th cell assemblies in the battery pack via the second and third resistors, respectively. The negative input terminal of the first operational amplifier is electrically connected to the positive terminal of the (N+1)th cell assembly in the battery pack via the fourth, fifth, and sixth resistors. The output terminal of the first operational amplifier is electrically connected to the... The base of the first transistor is connected to the base of the first transistor; the emitter of the first transistor is electrically connected to the positive terminal of the (N+1)th series of cells in the battery pack through the fifth and sixth resistors; the collector of the first transistor is electrically connected to the positive terminal of the first diode through the eighth resistor; the positive power supply terminal of the second operational amplifier is electrically connected to the DC power supply, the negative power supply terminal of the second operational amplifier is grounded, the positive input terminal of the second operational amplifier is electrically connected to the negative terminal of the first diode, the negative input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is electrically connected to the microcontroller through the ninth resistor.

2. The equalization sampling circuit according to claim 1, characterized in that: The first transistor is configured as a PNP transistor.

3. The equalization sampling circuit according to claim 2, characterized in that: The equalization sampling circuit also includes: a tenth resistor and an eleventh resistor connected in series; The second operational amplifier is grounded through the tenth resistor and the eleventh resistor.

4. The equalization sampling circuit according to claim 3, characterized in that: The equalization sampling circuit further includes: a first capacitor; The first capacitor is connected in series with the tenth and eleventh resistors to form a parallel circuit.

5. The equalization sampling circuit according to claim 4, characterized in that: The equalization sampling circuit further includes: a second capacitor; The ninth resistor is grounded through the second capacitor.

6. The equalization sampling circuit according to claim 5, characterized in that: The equalization sampling circuit also includes: a third capacitor; The positive power supply terminal of the second operational amplifier is grounded through the third capacitor.

7. The equalization sampling circuit according to any one of claims 1 to 6, characterized in that: The equalization sampling circuit also includes: a Zener diode; The positive terminal of the Zener diode is electrically connected to the positive terminal of the Nth cell assembly in the battery pack, and the positive terminal of the Zener diode is electrically connected to one end of the first resistor connected to the positive power supply terminal of the first operational amplifier.

8. The equalization sampling circuit according to any one of claims 1 to 6, characterized in that: The equalization sampling circuit also includes: an optocoupler, a second transistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor; The anode of the optocoupler is electrically connected to the DC power supply; the cathode of the optocoupler is electrically connected to the positive terminal of the (N+1)th string of cells in the battery pack via the twelfth resistor; the collector of the optocoupler is electrically connected to the positive terminal of the (N+1)th string of cells in the battery pack via the twelfth resistor; the emitter of the optocoupler is electrically connected to the base of the second transistor via the thirteenth resistor; the collector of the second transistor is electrically connected to the positive terminal of the (N+1)th string of cells in the battery pack via the fourteenth resistor; and the emitter of the second transistor is electrically connected to the positive terminal of the Nth string of cells in the battery pack.

9. The equalization sampling circuit according to claim 8, characterized in that: The second transistor is configured as an NPN transistor.

10. A battery pack, comprising: A combination of several series-connected battery cells and the equalization sampling circuit according to any one of claims 1 to 9.

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