Channel coding method and device based on reconfigurable processor architecture design

Abstract

The application relates to a channel coding method and device based on a reconfigurable processor architecture design. The method comprises the following steps: determining an intermediate variable submatrix corresponding to a row check submatrix according to each sub-information codeword included in a to-be-coded information codeword and the row check submatrix corresponding to each sub-information codeword; determining a sub-check bit codeword corresponding to each intermediate variable submatrix according to the relationship between each row check submatrix and a coded information codeword corresponding to the to-be-coded information codeword and each intermediate variable submatrix; and obtaining the coded information codeword corresponding to the to-be-coded information codeword according to the sub-check bit codeword corresponding to each intermediate variable submatrix and each sub-information codeword. The method can improve the efficiency of channel coding.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of channel coding, in particular to a channel coding method and device based on reconfigurable processor architecture design. BACKGROUND

[0002] For a long time, human beings have been pursuing efficient, reliable and safe information communication methods, and a variety of communication tools and means have been born, which have been constantly promoting the development and progress of human society. In a communication system, in order to enhance the ability of data to resist various interference when transmitted in the channel of the communication system and improve the reliability of the communication system, channel coding needs to be performed on the communication system.

[0003] In the traditional technology, a parity check matrix coding method with quasi-cyclic characteristics is used for channel coding. This method uses the quasi-cyclic characteristics of the parity check matrix for channel coding, and the operation complexity is high. Therefore, the efficiency of implementing channel coding is low. SUMMARY

[0004] Therefore, it is necessary to provide a channel coding method and device based on reconfigurable processor architecture design, which can improve the efficiency of channel coding.

[0005] In a first aspect, the present application provides a channel coding method based on reconfigurable processor architecture design. The method comprises:

[0006] According to each sub-information codeword included in the to-be-encoded information codeword and the row check submatrix corresponding to each sub-information codeword, an intermediate variable submatrix corresponding to the row check submatrix is determined;

[0007] According to the relationship between each row check submatrix and the encoded information codeword corresponding to the to-be-encoded information codeword, and each intermediate variable submatrix, a sub-check bit codeword corresponding to each intermediate variable submatrix is determined;

[0008] According to the sub-check bit codeword corresponding to each intermediate variable submatrix and each sub-information codeword, an encoded information codeword corresponding to the to-be-encoded information codeword is obtained.

[0009] In one embodiment, the determination of the sub-check bit codeword corresponding to each intermediate variable submatrix according to the relationship between each row check submatrix and the encoded information codeword corresponding to the to-be-encoded information codeword, and each intermediate variable submatrix comprises:

[0010] determine a first target expression according to a relationship between each row check sub-matrix and the encoding information code word corresponding to the to-be-encoded information code word; the first target expression is used to represent a relationship between a sub-check bit code word corresponding to a current first intermediate variable sub-matrix, a sub-check bit code word corresponding to a last intermediate variable sub-matrix of the first intermediate variable sub-matrix, and the first intermediate variable sub-matrix, the first intermediate variable sub-matrix being a first intermediate variable sub-matrix in the current to-be-determined intermediate variable sub-matrices;

[0011] determine the sub-check bit code word corresponding to each intermediate variable sub-matrix according to the first target expression.

[0012] In one embodiment, the determination of the sub-check bit code word corresponding to each sub-information code word according to the relationship between each row check sub-matrix and the encoding information code word corresponding to the to-be-encoded information code word, and the intermediate variable sub-matrix corresponding to each sub-information code word comprises:

[0013] determine a second target expression according to a relationship between each row check sub-matrix and the encoding information code word corresponding to the to-be-encoded information code word; the second target expression is used to represent a relationship between a sub-check bit code word corresponding to a current second intermediate variable sub-matrix, a last intermediate variable sub-matrix of the second intermediate variable sub-matrix, and a sub-check bit code word corresponding to the last intermediate variable sub-matrix of the second intermediate variable sub-matrix, the second intermediate variable sub-matrix being a last intermediate variable sub-matrix in the current to-be-determined intermediate variable sub-matrices;

[0014] determine the sub-check bit code word corresponding to each sub-information code word according to the second target expression.

[0015] In one embodiment, the determination of the intermediate variable sub-matrix corresponding to each row check sub-matrix comprises:

[0016] perform cyclic shift on each sub-information code word according to the row check sub-matrix to obtain a cyclic shift result corresponding to each sub-information code word;

[0017] perform bitwise XOR on the cyclic shift result corresponding to each sub-information code word to determine the intermediate variable sub-matrix corresponding to the row check sub-matrix.

[0018] In a second aspect, the present application further provides a channel coding device based on a reconfigurable processor architecture design. The device comprises a first calculator, a second calculator, and an output device.

[0019] The first calculator is configured to determine an intermediate variable syndrome matrix corresponding to each row check syndrome matrix according to each sub-information codeword included in the to-be-encoded information codeword and the row check syndrome matrix corresponding to each sub-information codeword.

[0020] The second calculator is configured to determine a sub-check bit codeword corresponding to each intermediate variable syndrome matrix according to a relationship between each row check syndrome matrix and an encoded information codeword corresponding to the to-be-encoded information codeword and each intermediate variable syndrome matrix.

[0021] The output device is configured to obtain the encoded information codeword corresponding to the to-be-encoded information codeword according to the sub-check bit codeword corresponding to each intermediate variable syndrome matrix and each sub-information codeword.

[0022] In one of the embodiments, the second calculator is configured to determine a first target expression according to a relationship between each row check syndrome matrix and an encoded information codeword corresponding to the to-be-encoded information codeword; the first target expression is used to represent a relationship between a sub-check bit codeword corresponding to a current first intermediate variable syndrome matrix, a sub-check bit codeword corresponding to a previous intermediate variable syndrome matrix of the first intermediate variable syndrome matrix, and the first intermediate variable syndrome matrix, the first intermediate variable syndrome matrix being a first intermediate variable syndrome matrix in the intermediate variable syndrome matrices to be determined currently.

[0023] The second calculator is configured to determine the sub-check bit codeword corresponding to each intermediate variable syndrome matrix according to the first target expression.

[0024] In one of the embodiments, the second calculator is configured to determine a second target expression according to a relationship between each row check syndrome matrix and an encoded information codeword corresponding to the to-be-encoded information codeword; the second target expression is used to represent a relationship between a sub-check bit codeword corresponding to a current second intermediate variable syndrome matrix and a previous intermediate variable syndrome matrix of the second intermediate variable syndrome matrix and a sub-check bit codeword corresponding to the previous intermediate variable syndrome matrix of the second intermediate variable syndrome matrix, the second intermediate variable syndrome matrix being a last intermediate variable syndrome matrix in the intermediate variable syndrome matrices to be determined currently.

[0025] The second calculator is configured to determine the sub-check bit codeword corresponding to each sub-information codeword according to the second target expression.

[0026] In one of the embodiments, the first calculator is configured to perform cyclic shift on each sub-information codeword according to the row check syndrome matrix to obtain a cyclic shift result corresponding to each sub-information codeword.

[0027] The first calculator is configured to perform bitwise XOR on the cyclic shift result corresponding to each sub-information codeword to determine the intermediate variable syndrome matrix corresponding to the row check syndrome matrix.

[0028] In one of the embodiments, the device further comprises an intermediate variable register and a controller, the intermediate variable register being connected with the first calculator, the second calculator and the controller;

[0029] The intermediate variable register is configured to receive a first instruction sent by the controller, and obtain the intermediate variable sub-matrix in the first calculator according to the first instruction, and store the intermediate variable sub-matrix.

[0030] The second calculator is configured to obtain the intermediate variable sub-matrix in the intermediate variable register.

[0031] In one of the embodiments, the device further comprises a check bit code word register, a row check sub-matrix register and a sub-information code word register, the check bit code word register being connected with the second calculator, the output device and the controller, the row check sub-matrix register being connected with the first calculator and the controller, and the sub-information code word register being connected with the controller, the first calculator and the output device.

[0032] The check bit code word register is configured to receive a second instruction sent by the controller, and obtain the sub-check bit code word in the second calculator according to the second instruction, and send the sub-check bit code word to the output device.

[0033] The row check sub-matrix register is configured to receive a third instruction sent by the controller, and send the row check sub-matrix to the first calculator according to the third instruction.

[0034] The sub-information code word register is configured to receive a fourth instruction sent by the controller, receive the to-be-encoded information code word according to the fourth instruction, split the to-be-encoded information code word into each sub-information code word, and send each sub-information code word to the output device and the first calculator.

[0035] In a third aspect, the present application further provides a computer device. The computer device comprises a memory and a processor, the memory stores a computer program, and the processor realizes the following steps when executing the computer program:

[0036] According to each sub-information code word included in the to-be-encoded information code word and the row check sub-matrix corresponding to each sub-information code word, the row check sub-matrix corresponding intermediate variable sub-matrix is determined.

[0037] According to the relationship between each row check sub-matrix and the to-be-encoded information code word, and each intermediate variable sub-matrix, the sub-check bit code word corresponding to each intermediate variable sub-matrix is determined.

[0038] According to the sub-check bit code word corresponding to each intermediate variable sub-matrix and each sub-information code word, the encoded information code word corresponding to the to-be-encoded information code word is obtained.

[0039] In a fourth aspect, the present application provides a computer readable storage medium. The computer readable storage medium has a computer program stored thereon, and the computer program, when executed by a processor, implements the following steps:

[0040] determining an intermediate variable syndrome matrix corresponding to each of the row check syndrome matrices according to each of the sub-information codewords included in the to-be-encoded information codeword and the row check syndrome matrix corresponding to each of the sub-information codewords;

[0041] determining a sub-check bit codeword corresponding to each of the intermediate variable syndrome matrices according to the relationship between each of the row check syndrome matrices and the encoded information codeword corresponding to the to-be-encoded information codeword, and each of the intermediate variable syndrome matrices;

[0042] obtaining the encoded information codeword corresponding to the to-be-encoded information codeword according to the sub-check bit codeword corresponding to each of the intermediate variable syndrome matrices and each of the sub-information codewords.

[0043] In a fifth aspect, the present application provides a computer program product. The computer program product includes a computer program, and the computer program, when executed by a processor, implements the following steps:

[0044] determining an intermediate variable syndrome matrix corresponding to each of the row check syndrome matrices according to each of the sub-information codewords included in the to-be-encoded information codeword and the row check syndrome matrix corresponding to each of the sub-information codewords;

[0045] determining a sub-check bit codeword corresponding to each of the intermediate variable syndrome matrices according to the relationship between each of the row check syndrome matrices and the encoded information codeword corresponding to the to-be-encoded information codeword, and each of the intermediate variable syndrome matrices;

[0046] obtaining the encoded information codeword corresponding to the to-be-encoded information codeword according to the sub-check bit codeword corresponding to each of the intermediate variable syndrome matrices and each of the sub-information codewords.

[0047] The channel coding method and device based on the reconfigurable processor architecture design, by determining the intermediate variable matrix corresponding to each row check submatrix according to each sub-information code word included in the to-be-encoded information code word and the row check submatrix corresponding to each sub-information code word, further determining the sub-check bit code word corresponding to each intermediate variable matrix according to the relationship between each row check submatrix and the encoding information code word corresponding to the to-be-encoded information code word, the intermediate variable matrix, obtaining the encoding information code word corresponding to the to-be-encoded information code word according to the sub-check bit code word corresponding to each intermediate variable matrix and each sub-information code word. In the prior art, the check matrix coding method with quasi-cyclic characteristics is used for channel coding. The method determines the check bit code word by using the quasi-cyclic characteristics of the check matrix, has high computational complexity, and has low efficiency of realizing channel coding. In the present application, the to-be-encoded information, the check matrix and the intermediate variable are split, the sub-check bit code word corresponding to each intermediate variable matrix is determined according to the relationship between each row check submatrix obtained after splitting and the to-be-encoded information code word, the intermediate variable matrix, the complexity of calculating the sub-check bit code word is reduced, and the efficiency of channel coding is improved. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 is one of the structural block diagrams of the channel coding device provided by the embodiments of the present application;

[0049] Figure 2 is a flowchart of a channel coding method provided by the embodiments of the present application;

[0050] Figure 3 is one of the flowcharts of the sub-check bit code word determination method provided by the embodiments of the present application;

[0051] Figure 4 is the second flowchart of the sub-check bit code word determination method provided by the embodiments of the present application;

[0052] Figure 5 is a flowchart of an intermediate variable matrix determination method provided by the embodiments of the present application;

[0053] Figure 6 is the second structural block diagram of the channel coding device provided by the embodiments of the present application;

[0054] Figure 7 is the third structural block diagram of the channel coding device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0056] The channel coding method provided by the embodiments of the present application can be applied to the channel coding device 100 as shown in the figure. Figure 1 The device 100 includes a first calculator 101, a second calculator 102, an output device 103, a controller 104, an intermediate variable register 105, a check bit code word register 106, a row check submatrix register 107, and a sub-information code word register 108. The first calculator 101 is connected to the sub-information code word register 108, the row check submatrix register 107, and the intermediate variable register 105, and is configured to obtain the sub-information code word stored in the sub-information code word register 108 and the row check submatrix stored in the row check submatrix register 107, and determine an intermediate variable submatrix according to the sub-information code word and the row check submatrix. The intermediate variable register 105 is configured to obtain the intermediate variable submatrix calculated by the first calculator 101. The second calculator 102 is connected to the intermediate variable register 105 and the check bit code word register 106, and is configured to obtain the intermediate variable submatrix stored in the intermediate variable register, and determine a sub-check bit code word according to the intermediate variable submatrix. The check bit code word register 106 is configured to obtain the sub-check bit code word determined by the second calculator, and store the sub-check bit code word. The controller 104 is connected to each register and the output device 103, and is configured to send a control instruction to each register and the output device 103. The output device 103 is connected to the sub-information code word register 108, the controller 104, and the check bit code word register 106, and is configured to obtain the sub-information code word stored in the sub-information code word register 108 and the sub-check bit code word stored in the check bit code word register 106, and obtain the coded information code word corresponding to the to-be-coded information code word according to each sub-check bit code word and each sub-information code word. The channel coding method provided in the present application splits the to-be-coded information, the check matrix, and the intermediate variable, determines the sub-check bit code word corresponding to each intermediate variable submatrix according to the relationship between each row check submatrix obtained after the splitting and the to-be-coded information code word, and each intermediate variable submatrix, and obtains the coded information code word corresponding to the to-be-coded information code word according to each sub-check bit code word and each sub-information code word. The channel coding device 100 designed based on the method can reconstruct the first calculator and the second calculator according to the number of each row check submatrix and the number of intermediate variable submatrices, and then process each to-be-coded information code word to determine the sub-check bit code word, so that the flexibility of channel coding is relatively strong.

[0057] In one embodiment, as shown in the figure, Figure 2 Figure 2 is a flowchart of a channel coding method provided by the embodiments of the present application. The method is applied to the channel coding device 100 in the figure as an example, and can include the following steps: Figure 1

[0058] ​​S201, determining an intermediate variable sub-matrix corresponding to a row check sub-matrix according to each sub-information codeword of the to-be-encoded information codeword and the row check sub-matrix corresponding to each sub-information codeword.

[0059] The to-be-encoded information codeword is an original information codeword obtained by the channel coding device from a communication device of a communication system. The row check sub-matrix represents a row sub-matrix in a check matrix corresponding to the to-be-encoded information. The check matrix is a matrix set in advance.

[0060] In this embodiment, the to-be-encoded information codeword can be split according to a first preset splitting rule to determine each sub-information codeword. For example, the to-be-encoded information codeword is denoted as s, and s can be split into k sub-information codewords according to the preset splitting rule, which can be denoted as s = (s1, s2, …, sk). b The check matrix is denoted as H, and a sub-matrix of the i+1th row of the check matrix H constitutes a matrix L i,j , which is a row check sub-matrix. The minimum value of i is 0, and the maximum value of i is the total number of rows of the check matrix H minus 1. For example, if the check matrix H has a total of 20 rows, the value range of i is (0, 19). A sub-matrix composed of elements in each column of the row check sub-matrix corresponds to each sub-information codeword. For example, the sub-matrix L i,j in the j+1th column of the row check sub-matrix corresponds to the sub-information codeword s j , and the value range of j is (0, k b -1).The intermediate variable sub-matrix can be expressed by the following relationship:

[0061]

[0062] , where b i is the intermediate variable sub-matrix, m b is the total number of row check sub-matrices L i,j , and is also the total number of intermediate variable sub-matrices. One row check sub-matrix corresponds to one intermediate variable sub-matrix.

[0063] Alternatively, the product obtained by multiplying b i by a first preset coefficient can be used as the intermediate variable sub-matrix.

[0064] S202, determining a sub-check bit codeword corresponding to each intermediate variable sub-matrix according to the relationship between each row check sub-matrix and the encoding information codeword corresponding to the to-be-encoded information codeword, and each intermediate variable sub-matrix.

[0065] According to the above example, the encoding information codeword corresponding to the to-be-encoded information codeword s is denoted as c, and the sub-check bit codeword is denoted as p i . c is determined by each sub-information codeword s j and each sub-check bit codeword pi The embodiment, it needs to be explained that the check matrix H and the encoding information code word c satisfy the check relation H x c = 0; because H is composed of each row check submatrix L T i,j , and c is composed of each sub information code word s j and each sub check bit code word p i , so, according to the relation between each row check submatrix L i,j And the encoding information code word c, the relation between the encoding information code word c and b i Is deduced, and then according to the relation between c and b i And each intermediate variable submatrix b i , determine the corresponding sub check bit code word p i Of each intermediate variable submatrix b i .

[0066] S203, according to the corresponding sub check bit code word of each intermediate variable submatrix and each sub information code word, get the corresponding encoding information code word of the to be encoded information code word.

[0067] Combined with the above example, the encoding information code word c = [s, p], wherein s represents the to be encoded information code word, s is composed of each sub information code word s j , p represents the check bit code word, p is composed of each sub check bit code word p i , so the encoding information code word can also be expressed as If it is necessary to determine the encoding information code word, only need to determine each sub check bit code word p i , then each sub information code word s j And each sub check bit code word p i According to the preset merging rule is merged.

[0068] ​The channel coding method determines the intermediate variable matrix corresponding to each row check sub-matrix according to each sub-information code word included in the to-be-encoded information code word and the row check sub-matrix corresponding to each sub-information code word, further determines the sub-check bit code word corresponding to each intermediate variable matrix according to the relationship between each row check sub-matrix and the encoding information code word corresponding to the to-be-encoded information code word, the intermediate variable matrix, and obtains the encoding information code word corresponding to the to-be-encoded information code word according to the sub-check bit code word corresponding to each intermediate variable matrix and each sub-information code word. In the prior art, the check matrix coding method with quasi-cyclic characteristics is used for channel coding. The check bit code word is determined by using the quasi-cyclic characteristics of the check matrix, the operation complexity is high, and the efficiency of channel coding is low. In the present application, the to-be-encoded information, the check matrix and the intermediate variable are split, the sub-check bit code word corresponding to each intermediate variable matrix is determined according to the relationship between each row check sub-matrix obtained after splitting and the to-be-encoded information code word, the relationship between each intermediate variable matrix, and the complexity of calculating the sub-check bit code word is reduced, and the efficiency of channel coding is improved.

[0069] Figure 3 is one of the flowcharts of the sub-check bit code word determination method provided by the embodiments of the present application. The present embodiment relates to one possible implementation manner of how to determine the sub-check bit code word corresponding to each intermediate variable matrix according to the relationship between each row check sub-matrix and the encoding information code word corresponding to the to-be-encoded information code word, and the relationship between each intermediate variable matrix. On the basis of the above-mentioned embodiment, as shown in Figure 3 , the S201 can include the following steps.

[0070] S301, determining a first target expression according to the relationship between each row check sub-matrix and the encoding information code word corresponding to the to-be-encoded information code word. The first target expression is used to represent the relationship between the sub-check bit code word corresponding to the current first intermediate variable matrix, the sub-check bit code word corresponding to the last intermediate variable matrix of the first intermediate variable matrix, and the first intermediate variable matrix. The first intermediate variable matrix is the first intermediate variable matrix in the current to-be-determined intermediate variable matrix.

[0071] In combination with the above example, it is introduced that the check matrix H and the encoding information code word c satisfy the check relationship H×c T =0. Because H is composed of each row check sub-matrix L i,j , and c is composed of each sub-information code word s j and each sub-check bit code word p i , therefore, according to the above check relationship, the following relationship can be derived:

[0072] b i +p i +p i+1 =0 (1≤i≤mb -2,i≠x) (2)

[0073]

[0074] wherein p0 (1) represents a vector of p0cyclically shifted for l times, and the value of l can be preset. According to the above relation (2), the following can be obtained:

[0075] p i+1 = p i + b i (4)

[0076] The expression (4) is taken as the first target expression.

[0077] In S302, according to the first target expression, the sub-check bit code word corresponding to each intermediate variable sub-matrix is determined.

[0078] When i = 0, the first target expression can be expressed as:

[0079] p1= p0 (1) + b0 (5)

[0080] p0 (1) may also be expressed by the cumulative sum of each intermediate variable sub-matrix b i .

[0081]

[0082] According to the expression (6), p0 (1) is determined, and p0 (1) and b0determined by the expression (1) are substituted into the expression (5) to determine p1, and in this way, according to the first target expression, the first intermediate variable sub-matrix b i+1 of each time corresponding to the sub-check bit code word p i+1 is determined. Alternatively, the process of determining the intermediate variable sub-matrix according to the expression (1) and the process of determining the sub-check bit code word according to the first target expression can be performed simultaneously to improve the efficiency of channel coding.

[0083] In the embodiments of the present application, the first target expression is determined according to the relationship between the encoding information code word corresponding to each row of the check sub-matrix and the to-be-encoded information code word, and further, the sub-check bit code word corresponding to each intermediate variable sub-matrix is determined according to the first target expression. Because each sub-check bit code word is determined, the computational complexity is reduced, and thus the efficiency of channel coding is improved.

[0084] Figure 4This is a second flowchart illustrating the sub-check bit codeword determination method provided in this application embodiment. This application embodiment relates to a possible implementation of how to determine the sub-check bit codeword corresponding to each sub-information codeword based on the relationship between the row check sub-matrix corresponding to each sub-information codeword and the encoded information codeword corresponding to the information codeword to be encoded, and the intermediate variable sub-matrix corresponding to each sub-information codeword. Based on the above embodiment, such as... Figure 4 As shown, the above S202 may further include:

[0085] S401, determine the second target expression value based on the relationship between the codewords corresponding to the parity submatrix and the codewords to be encoded; the second target expression is used to characterize the relationship between the codewords corresponding to the current second intermediate variable submatrix and the codewords corresponding to the previous intermediate variable submatrix of the second intermediate variable submatrix, and the codewords corresponding to the previous intermediate variable submatrix of the second intermediate variable submatrix. The second intermediate variable submatrix is ​​the last intermediate variable submatrix in the current intermediate variable submatrix to be determined.

[0086] S402, determine the sub-check bit codeword corresponding to each sub-information codeword according to the second target expression.

[0087] For example, the second objective expression can be obtained according to equation (2):

[0088] p i =p i+1 +b i (7)

[0089] for p0 (l) And the following relation holds:

[0090]

[0091] Among them, p0 (1) Based on each intermediate variable submatrix b i The summation and determination, It can be based on each sub-information codeword and the row check submatrix. Therefore, it can be determined based on the above relationship. At this point, let i = m b -2, which can be obtained from the second objective expression:

[0092]

[0093] It can be based on each sub-information codeword and the row check submatrix. Sure Will and Substituting into the above formula will determine the result. By analogy, the second objective expression and each intermediate variable submatrix are recursively calculated forward to determine each sub-check bit codeword.

[0094] Alternatively, bidirectional recursive operations can be performed based on the first target expression and the second target expression to determine each sub-check bit codeword. Specifically, referring to the example above, p1 can be determined according to equation (5), and p1 can be determined according to equation (8). If m b If the number is odd, then substitute the determined p1 into the first objective expression, and recursively determine p2 and so on. Will Substituting into the second objective expression, the sub-check bit codewords are determined recursively forward. arrive If m b If the number is even, substitute the determined p1 into the first objective expression, and recursively determine p2 and so on. Will Substituting into the second objective expression, the sub-check bit codewords are determined recursively forward. arrive Recursive operations based on the first objective expression and recursive operations based on the second objective expression can be performed simultaneously to improve the efficiency of determining the sub-check bit codeword.

[0095] In this embodiment, the second target expression value is determined based on the relationship between each row parity submatrix and the corresponding encoded information codewords of the information to be encoded. Furthermore, based on the second target expression, the sub-parity bit codewords corresponding to each sub-information codeword are determined. Because each sub-parity bit codeword is determined, the computational complexity is reduced. Moreover, by simultaneously performing bidirectional recursive operations based on the first and second target expressions, the time required to compute the sub-parity bit codewords can be further reduced, improving the efficiency of channel coding.

[0096] Figure 5 This is a flowchart illustrating a method for determining an intermediate variable submatrix according to an embodiment of this application. This embodiment relates to a possible implementation of how to determine the intermediate variable submatrix corresponding to the row check submatrix based on each sub-information codeword included in the codeword to be encoded and the row check submatrix corresponding to each sub-information codeword. Based on the above embodiment, such as... Figure 5 As shown, the above S201 may include:

[0097] S501, based on the row check submatrix, perform cyclic shifting on each sub-information codeword to obtain the cyclic shift result corresponding to each sub-information codeword.

[0098] To reduce resource consumption and improve computational efficiency during channel coding, Figure 1In the channel encoding device 100, for the calculation of the intermediate variable sub-matrix, first, according to the row check sub-matrix L i,j The cyclic shift is performed on each sub-information code word s j to determine the cyclic shift result corresponding to each sub-information code word. The multiplication operation in the process of calculating the intermediate variable sub-matrix by using formula (1) is replaced by the cyclic shift operation.

[0099] S502, the cyclic shift result corresponding to each sub-information code word is subjected to bitwise XOR to determine the intermediate variable sub-matrix corresponding to the row check sub-matrix.

[0100] The cyclic shift result corresponding to each sub-information code word is subjected to bitwise XOR in the channel encoding device 100, and the multiplexing superposition in the time sequence is used to replace the accumulation operation in the process of calculating the intermediate variable sub-matrix by using formula (1) to determine the intermediate variable sub-matrix b i,x corresponding to the row check sub-matrix L i .

[0101] In the embodiment of the application, the cyclic shift is performed on each sub-information code word according to the row check sub-matrix to obtain the cyclic shift result corresponding to each sub-information code word, and the cyclic shift result corresponding to each sub-information code word is subjected to bitwise XOR to determine the intermediate variable sub-matrix corresponding to the row check sub-matrix. The multiplication operation is replaced by the cyclic shift operation, and the accumulation operation is replaced by the bitwise XOR, thereby reducing the resource consumption in the channel encoding process and further improving the efficiency of the channel encoding.

[0102] In one embodiment, as shown in Figure 6 , a channel encoding device 600 is provided, which comprises a first calculator 601, a second calculator 602, and an output device 603.

[0103] The first calculator 601 is configured to determine the intermediate variable sub-matrix corresponding to the row check sub-matrix according to each sub-information code word included in the information code word to be encoded and the row check sub-matrix corresponding to each sub-information code word.

[0104] The second calculator 602 is configured to determine the sub-check bit code word corresponding to each intermediate variable sub-matrix according to the relationship between each row check sub-matrix and the code information code word corresponding to the information code word to be encoded and each intermediate variable sub-matrix.

[0105] The output device 603 is configured to obtain the code information code word corresponding to the information code word to be encoded according to the sub-check bit code word corresponding to each intermediate variable sub-matrix and each sub-information code word.

[0106] In one embodiment, the second calculator 602 is configured to determine the first target expression according to the relationship between each row check sub-matrix and the information code word to be encoded.

[0107] The second calculator 602 is configured to determine the sub-check code word corresponding to each intermediate variable sub-matrix according to the first target expression.

[0108] In one of the embodiments, the second calculator 602 is configured to determine the second target expression value according to the relationship between the row check sub-matrix and the information code word to be encoded.

[0109] The second calculator 602 is configured to determine the sub-check code word corresponding to each sub-information code word according to the second target expression.

[0110] In one of the embodiments, the first calculator 601 is configured to cyclically shift each sub-information code word according to the row check sub-matrix to obtain the cyclic shift result corresponding to each sub-information code word.

[0111] The first calculator 601 is configured to perform bitwise XOR operation on the cyclic shift results corresponding to each sub-information code word to determine the intermediate variable sub-matrix corresponding to the row check sub-matrix.

[0112] In one of the embodiments, the channel coding device 600 further comprises an intermediate variable register and a controller, and the intermediate variable register is connected with the first calculator 601, the second calculator 602 and the controller 603.

[0113] The intermediate variable register is configured to receive the first instruction sent by the controller, and obtain the intermediate variable sub-matrix in the first calculator 601 according to the first instruction, and store the intermediate variable sub-matrix.

[0114] The second calculator 602 is configured to obtain the intermediate variable sub-matrix in the intermediate variable register.

[0115] In the embodiment, after the first calculator 601 determines each intermediate variable sub-matrix, the controller can send the first instruction to the intermediate variable register to instruct the intermediate variable register to obtain the intermediate variable sub-matrix in the first calculator 601 and store the intermediate variable sub-matrix. Alternatively, the intermediate variable sub-matrix can actively send the intermediate variable sub-matrix to the second calculator 602, and the second calculator 602 can also actively obtain the intermediate variable sub-matrix from the intermediate variable register.

[0116] In the embodiment, by adding the intermediate variable register and the controller in the channel coding device, the intermediate variable sub-matrix generated in the channel coding process is effectively stored, and the reliability and security of the channel coding device are increased.

[0117] In one of the embodiments, the channel coding device 600 further comprises a check code word register, and the check code word register is connected with the second calculator 602, the output device 603 and the controller.

[0118] The parity check code word register is configured to receive the second instruction sent by the controller, and obtain the sub-parity check code word in the second calculator 602 according to the second instruction, and store the sub-parity check code word.

[0119] The output device 603 is configured to obtain the sub-parity check code word in the parity check code word register.

[0120] In the embodiment, after the second calculator 602 determines the sub-parity check code word, the parity check code word register can obtain the sub-parity check code word in the second calculator 602 according to the second instruction sent by the controller, and store the sub-parity check code word, and the output device 603 can obtain the sub-parity check code word from the parity check code word register. Alternatively, the output device 603 can also receive the sub-parity check code word sent by the parity check code word register.

[0121] In the embodiment, the sub-parity check code word register is added to effectively store the sub-parity check code word generated in the channel coding process, and the reliability and security of the channel coding device are increased.

[0122] In one of the embodiments, the device further includes a row check sub-matrix register, and the row check sub-matrix register is connected with the first calculator 601 and the controller.

[0123] The row check sub-matrix register is configured to receive the third instruction sent by the controller, and send the row check sub-matrix to the first calculator according to the third instruction.

[0124] The first calculator 601 is configured to receive the row check sub-matrix sent by the row check sub-matrix register.

[0125] Alternatively, the row check sub-matrix register can also store the check matrix, and split the check matrix to obtain the row check sub-matrix according to the second preset splitting rule.

[0126] In the embodiment, the row check sub-matrix register is arranged in the channel coding device to effectively store the check matrix and the row check sub-matrix required in the channel coding process, and the reliability and security of the channel coding device are increased.

[0127] In one of the embodiments, the device 600 further includes a sub-information code word register, and the sub-information code word register is connected with the controller, the first calculator 601 and the output device 603.

[0128] The sub-information code word register is configured to receive the fourth instruction sent by the controller, receive the to-be-coded information code word according to the fourth instruction, split the to-be-coded information code word into sub-information code words, and send the sub-information code words to the output device and the first calculator.

[0129] The first calculator 601 is configured to acquire each sub-information code word in the sub-information code word register.

[0130] In this embodiment, the first calculator 601 can acquire each sub-information code word from the sub-information code word register. Alternatively, the first calculator 601 can also receive the sub-information code word sent by the sub-information code word register.

[0131] In this embodiment, the sub-information code word register is arranged in the channel coding device, and the sub-information code words required in the channel coding process are effectively stored, thereby increasing the reliability and security of the channel coding device.

[0132] Alternatively, the structure of the channel coding device can also be Figure 7 The device 700 provided in this embodiment has the structure shown in the figure, which includes a first calculator 701, a second calculator 702, an output device 703, a controller 704, an intermediate variable register 705, a check bit code word register 706, a row check sub-matrix register 707, and a sub-information code word register 708. In the channel coding device 700, the first calculator 701 can include m first calculation units configured to calculate each intermediate variable sub-matrix; the second calculator 702 can include m second calculation units configured to calculate each sub-check bit code word, and the second calculation units can perform the above-mentioned bidirectional recursive operation to calculate the sub-check bit code word, and the plurality of second calculation units can perform the calculation synchronously; the intermediate variable register 705 can include m intermediate variable register units configured to store each intermediate variable sub-matrix; and the check bit code word register 706 can include m check bit code word register units configured to store each sub-check bit code word.

[0133] In the channel coding device, the process of calculating the intermediate variable sub-matrix by each first calculation unit and the process of calculating the sub-check bit code word by each second calculation unit can be performed simultaneously. For example, after a part of the intermediate variable sub-matrix b i is calculated by the first calculation unit, the part of the intermediate variable sub-matrix b i is sent to the intermediate variable register 705, and each second calculation unit in the second calculator 702 acquires the b i stored in the intermediate variable register 705 to start the calculation of the sub-check bit code word, while the first calculation unit in the first calculator continues to calculate the remaining intermediate variable sub-matrix b i , and each calculator and register works simultaneously, thereby further improving the efficiency of the channel coding. Moreover, when different information code words to be coded are coded, the number of the first calculation units and the second calculation units can be reconfigured according to the number of the intermediate variable sub-matrices and the sub-check bit code words, thereby improving the flexibility of using the channel coding device 700 to code.

[0134] It should be understood that although the steps in the flowcharts involved in the above embodiments are shown in sequence according to the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts involved in the above embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of the steps or stages is not necessarily sequential, but can be alternately executed with at least some of the other steps or the steps or stages in the other steps.

[0135] In an embodiment, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program:

[0136] According to the sub-information code words included in the to-be-encoded information code word and the row check sub-matrices corresponding to the sub-information code words, determine intermediate variable sub-matrices corresponding to the row check sub-matrices;

[0137] According to the relationship between the row check sub-matrices and the encoded information code words corresponding to the to-be-encoded information code word, and the intermediate variable sub-matrices, determine sub-check bit code words corresponding to the intermediate variable sub-matrices;

[0138] According to the sub-check bit code words corresponding to the intermediate variable sub-matrices and the sub-information code words, obtain the encoded information code word corresponding to the to-be-encoded information code word.

[0139] In an embodiment, the processor, when executing the computer program, further implements the following steps:

[0140] According to the relationship between the row check sub-matrices and the encoded information code words corresponding to the to-be-encoded information code word, determine a first target expression; the first target expression is used to represent the relationship between the sub-check bit code word corresponding to the current first intermediate variable sub-matrix, the sub-check bit code word corresponding to the last intermediate variable sub-matrix of the first intermediate variable sub-matrix, and the first intermediate variable sub-matrix, the first intermediate variable sub-matrix being the first intermediate variable sub-matrix in the current to-be-determined intermediate variable sub-matrices;

[0141] According to the first target expression, determine the sub-check bit code words corresponding to the intermediate variable sub-matrices.

[0142] In an embodiment, the processor, when executing the computer program, further implements the following steps:

[0143] determine a second target expression according to a relationship between each row check sub-matrix and a corresponding coded information code word of the to-be-encoded information code word; the second target expression is used to represent a relationship between a sub-check bit code word corresponding to a current second intermediate variable sub-matrix and a previous intermediate variable sub-matrix of the second intermediate variable sub-matrix and a sub-check bit code word corresponding to the previous intermediate variable sub-matrix of the second intermediate variable sub-matrix, the second intermediate variable sub-matrix being the last intermediate variable sub-matrix in the intermediate variable sub-matrices to be determined currently;

[0144] determine a sub-check bit code word corresponding to each sub-information code word according to the second target expression.

[0145] In an embodiment, the processor, when executing the computer program, further implements the following steps:

[0146] perform cyclic shift on each sub-information code word according to the row check sub-matrix to obtain a cyclic shift result corresponding to each sub-information code word;

[0147] perform bitwise XOR on the cyclic shift results corresponding to each sub-information code word to determine an intermediate variable sub-matrix corresponding to the row check sub-matrix.

[0148] In an embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the following steps:

[0149] determine an intermediate variable sub-matrix corresponding to the row check sub-matrix according to each sub-information code word included in the to-be-encoded information code word and the row check sub-matrix corresponding to each sub-information code word;

[0150] determine a sub-check bit code word corresponding to each intermediate variable sub-matrix according to a relationship between each row check sub-matrix and a corresponding coded information code word of the to-be-encoded information code word and each intermediate variable sub-matrix;

[0151] obtain a coded information code word corresponding to the to-be-encoded information code word according to the sub-check bit code word corresponding to each intermediate variable sub-matrix and each sub-information code word.

[0152] In an embodiment, the processor, when executing the computer program, further implements the following steps:

[0153] determine a first target expression according to a relationship between each row check sub-matrix and a corresponding coded information code word of the to-be-encoded information code word; the first target expression is used to represent a relationship between a sub-check bit code word corresponding to a current first intermediate variable sub-matrix, a sub-check bit code word corresponding to a previous intermediate variable sub-matrix of the first intermediate variable sub-matrix and the first intermediate variable sub-matrix, the first intermediate variable sub-matrix being the first intermediate variable sub-matrix in the intermediate variable sub-matrices to be determined currently;

[0154] According to the first target expression, the sub-parity bit code word corresponding to each intermediate variable sub-matrix is determined.

[0155] In one embodiment, the computer program, when executed by the processor, further implements the following steps:

[0156] According to the relationship between the encoding information code word corresponding to each row check sub-matrix and the to-be-encoded information code word, the second target expression value is determined; the second target expression is used to represent the relationship between the sub-parity bit code word corresponding to the current second intermediate variable sub-matrix and the sub-parity bit code word corresponding to the previous intermediate variable sub-matrix of the second intermediate variable sub-matrix, the previous intermediate variable sub-matrix of the second intermediate variable sub-matrix; the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the current to-be-determined intermediate variable sub-matrix;

[0157] According to the second target expression, the sub-parity bit code word corresponding to each sub-information code word is determined.

[0158] In one embodiment, the computer program, when executed by the processor, further implements the following steps:

[0159] According to the row check sub-matrix, each sub-information code word is circularly shifted to obtain a circularly shifted result corresponding to each sub-information code word;

[0160] The circularly shifted results corresponding to each sub-information code word are subjected to bitwise XOR to determine the intermediate variable sub-matrix corresponding to the row check sub-matrix.

[0161] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0162] According to the to-be-encoded information code word, the sub-information code word included in each sub-information code word and the row check sub-matrix corresponding to each sub-information code word are determined; the intermediate variable sub-matrix corresponding to the row check sub-matrix is determined;

[0163] According to the relationship between the encoding information code word corresponding to each row check sub-matrix and the to-be-encoded information code word, the second target expression value is determined; the second target expression is used to represent the relationship between the sub-parity bit code word corresponding to the current second intermediate variable sub-matrix and the sub-parity bit code word corresponding to the previous intermediate variable sub-matrix of the second intermediate variable sub-matrix, the previous intermediate variable sub-matrix of the second intermediate variable sub-matrix; the second intermediate variable sub-matrix is the last intermediate variable sub-matrix in the current to-be-determined intermediate variable sub-matrix;

[0164] According to the sub-parity bit code word corresponding to each intermediate variable sub-matrix and each sub-information code word, the encoding information code word corresponding to the to-be-encoded information code word is obtained.

[0165] In one embodiment, the computer program, when executed by the processor, further implements the following steps:

[0166] According to a relationship between the check sub-matrices of each row and the encoding information code words corresponding to the to-be-encoded information code words, a first target expression is determined; the first target expression is used to represent a relationship between a sub-check code word corresponding to a current first intermediate variable sub-matrix, a sub-check code word corresponding to a previous intermediate variable sub-matrix of the first intermediate variable sub-matrix, and the first intermediate variable sub-matrix, the first intermediate variable sub-matrix being a first intermediate variable sub-matrix in the to-be-determined intermediate variable sub-matrices;

[0167] According to the first target expression, the sub-check code words corresponding to the intermediate variable sub-matrices are determined.

[0168] In an embodiment, the computer program, when executed by the processor, further implements the following steps:

[0169] According to a relationship between the check sub-matrices of each row and the encoding information code words corresponding to the to-be-encoded information code words, a second target expression is determined; the second target expression is used to represent a relationship between a sub-check code word corresponding to a current second intermediate variable sub-matrix, a previous intermediate variable sub-matrix of the second intermediate variable sub-matrix, and a sub-check code word corresponding to the previous intermediate variable sub-matrix of the second intermediate variable sub-matrix, the second intermediate variable sub-matrix being a last intermediate variable sub-matrix in the to-be-determined intermediate variable sub-matrices;

[0170] According to the second target expression, the sub-check code words corresponding to the sub-information code words are determined.

[0171] In an embodiment, the computer program, when executed by the processor, further implements the following steps:

[0172] According to the row check sub-matrix, each sub-information code word is cyclically shifted to obtain a cyclic shift result corresponding to each sub-information code word;

[0173] The cyclic shift results corresponding to the sub-information code words are subjected to bitwise XOR to determine the intermediate variable sub-matrix corresponding to the row check sub-matrix.

[0174] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties.

[0175] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric memory (Ferroelectric Random Access Memory, FRAM), phase change memory (Phase Change Memory, PCM), graphene memory, etc. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0176] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0177] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A channel coding method based on a reconfigurable processor architecture, characterized in that, The method includes: Based on each sub-information codeword included in the codeword to be encoded and the row check sub-matrix corresponding to each sub-information codeword, determine the intermediate variable sub-matrix corresponding to the row check sub-matrix; Based on the relationship between each row check submatrix and the encoded information codeword corresponding to the codeword to be encoded, and each intermediate variable submatrix, determine the sub-check bit codeword corresponding to each intermediate variable submatrix; Based on the sub-check bit codewords corresponding to each of the intermediate variable sub-matrices and each of the sub-information codewords, the encoded information codewords corresponding to the information codewords to be encoded are obtained.

2. The method according to claim 1, characterized in that, The step of determining the sub-parity codeword corresponding to each intermediate variable submatrix based on the relationship between each row check submatrix and the encoded information codeword corresponding to the information codeword to be encoded, and each intermediate variable submatrix, includes: Based on the relationship between each row check submatrix and the encoded information codeword corresponding to the codeword to be encoded, a first target expression is determined; the first target expression is used to characterize the relationship between the sub-check bit codeword corresponding to the current first intermediate variable submatrix, the sub-check bit codeword corresponding to the previous intermediate variable submatrix of the first intermediate variable submatrix, and the first intermediate variable submatrix, wherein the first intermediate variable submatrix is ​​the first intermediate variable submatrix in the current intermediate variable submatrix to be determined; Based on the first target expression, determine the sub-check bit codewords corresponding to each of the intermediate variable sub-matrices.

3. The method according to claim 1, characterized in that, The step of determining the sub-check bit codeword corresponding to each sub-information codeword based on the relationship between the row check sub-matrix corresponding to each sub-information codeword and the encoded information codeword corresponding to the information codeword to be encoded, and the intermediate variable sub-matrix corresponding to each sub-information codeword, includes: Based on the relationship between each row check submatrix and the encoded information codeword corresponding to the codeword to be encoded, a second target expression is determined; the second target expression is used to characterize the relationship between the sub-check codeword corresponding to the current second intermediate variable submatrix and the previous intermediate variable submatrix of the second intermediate variable submatrix, and the sub-check codeword corresponding to the previous intermediate variable submatrix of the second intermediate variable submatrix, wherein the second intermediate variable submatrix is ​​the last intermediate variable submatrix in the current intermediate variable submatrix to be determined; Based on the second target expression, determine the sub-check bit codeword corresponding to each of the sub-information codewords.

4. The method according to any one of claims 1-3, characterized in that, The step of determining the intermediate variable submatrix corresponding to the row check submatrix based on each sub-information codeword included in the codeword to be encoded and the row check submatrix corresponding to each sub-information codeword includes: Based on the row check submatrix, each of the sub-information codewords is cyclically shifted to obtain the cyclic shift result corresponding to each of the sub-information codewords; Perform a bitwise XOR operation on the cyclic shift results corresponding to each of the sub-information codewords to determine the intermediate variable submatrix corresponding to the row check submatrix.

5. A channel coding device based on a reconfigurable processor architecture, characterized in that, The device includes a first calculator, a second calculator, and an output device; The first calculator is used to determine the intermediate variable submatrix corresponding to the row check submatrix based on each sub-information codeword included in the codeword to be encoded and the row check submatrix corresponding to each sub-information codeword; The second calculator is used to determine the sub-check bit codeword corresponding to each of the intermediate variable sub-matrices based on the relationship between each of the row check sub-matrices and the encoded information codeword corresponding to the information codeword to be encoded, and each of the intermediate variable sub-matrices; The output device is used to obtain the encoded information codeword corresponding to the information codeword to be encoded based on the sub-check bit codeword corresponding to each of the intermediate variable sub-matrices and each of the sub-information codewords.

6. The apparatus according to claim 5, characterized in that, The second calculator is used to determine a first target expression based on the relationship between each row check submatrix and the codeword to be encoded; the first target expression is used to characterize the relationship between the codeword corresponding to the current first intermediate variable submatrix, the codeword corresponding to the previous intermediate variable submatrix of the first intermediate variable submatrix, and the first intermediate variable submatrix, wherein the first intermediate variable submatrix is ​​the first intermediate variable submatrix in the current intermediate variable submatrix to be determined; The second calculator is used to determine the sub-check codewords corresponding to each of the intermediate variable sub-matrices based on the first target expression.

7. The apparatus according to claim 5, characterized in that, The second calculator is used to determine a second target expression based on the relationship between each row check submatrix and the codeword to be encoded; the second target expression is used to characterize the relationship between the codeword corresponding to the current second intermediate variable submatrix and the codeword corresponding to the previous intermediate variable submatrix of the second intermediate variable submatrix, and the codeword corresponding to the previous intermediate variable submatrix of the second intermediate variable submatrix, wherein the second intermediate variable submatrix is ​​the last intermediate variable submatrix in the current intermediate variable submatrix to be determined; The second calculator is used to determine the sub-check bit codeword corresponding to each of the sub-information codewords based on the second target expression.

8. The apparatus according to claim 5, characterized in that, The first calculator is used to perform cyclic shifting on each of the sub-information codewords according to the row check sub-matrix, so as to obtain the cyclic shifting result corresponding to each of the sub-information codewords; The first calculator is used to perform bitwise XOR on the cyclic shift results corresponding to each of the sub-information codewords to determine the intermediate variable submatrix corresponding to the row check submatrix.

9. The apparatus according to claim 5, characterized in that, The device further includes an intermediate variable register and a controller, wherein the intermediate variable register is connected to the first calculator, the second calculator, and the controller; The intermediate variable register is used to receive a first instruction sent by the controller, obtain the intermediate variable sub-matrix in the first calculator according to the first instruction, and store the intermediate variable sub-matrix. The second calculator is used to obtain the intermediate variable submatrix in the intermediate variable register.

10. The apparatus according to claim 9, characterized in that, The device further includes a check bit codeword register, a row check sub-matrix register, and a sub-information codeword register. The check bit codeword register is connected to the second calculator, the output device, and the controller. The row check sub-matrix register is connected to the first calculator and the controller. The sub-information codeword register is connected to the controller, the first calculator, and the output device. The check bit codeword register is used to receive a second instruction sent by the controller, obtain the sub-check bit codeword in the second calculator according to the second instruction, and send the sub-check bit codeword to the output device. The row check submatrix register is used to receive a third instruction sent by the controller and send the row check submatrix to the first calculator according to the third instruction; The sub-information codeword register is used to receive the fourth instruction sent by the controller, receive the information codeword to be encoded according to the fourth instruction, split the information codeword to be encoded into each of the sub-information codewords, and send each of the sub-information codewords to the output device and the first calculator.

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