Dual path signal interconnect on printed circuit board

Abstract

A dual path high speed interconnect PCB layout solution is provided. A dual path signal interconnect can include a first signal trace, a first pad and a second pad located above and connected to the first signal trace, and a third pad. The second pad is separated from the first pad. The third pad is separated from the second pad and connected to a second signal trace. The first and second pads are used to allow pins of a connector to be soldered to the first and second pads such that when the pins of an external connector are soldered, high speed electrical signals from the first signal trace are routed to the connector. The second and third pads are used to allow a conductor to be soldered to the second and third pads such that when the conductor is soldered, the high speed electrical signals are routed to the second signal trace.

Description

Technical Field

[0001] This disclosure generally relates to two-path signal interconnects on printed circuit boards. Background Technology

[0002] This disclosure generally relates to the design of printed circuit boards (PCBs). More specifically, this disclosure relates to dual-path high-speed signal interconnects on PCBs that allow high-speed signal traces to be connected to two different types of device interfaces while preserving the signal integrity of the high-speed path. Summary of the Invention

[0003] According to one aspect of this disclosure, a dual-path signal interconnect on a printed circuit board (PCB) is provided, the dual-path signal interconnect comprising: a first signal trace for carrying a high-speed electrical signal; a first pad having a first size, the first pad being located above and connected to the first signal trace; a second pad having a second size, the second pad being located above and connected to the first signal trace, wherein the second pad is spaced apart from the first pad by a first gap; and a third pad having a third size, wherein the third pad is spaced apart from the second pad by a second gap and is connected to the second signal trace; wherein the first pad and the second pad are arranged such that pins of an external connector can be simultaneously soldered to the first pad and the second pad, and the high-speed electrical signal is routed to the external connector when the pins of the external connector are soldered; and wherein the second pad and the third pad are arranged such that conductors can be simultaneously soldered to the second pad and the third pad, and the high-speed electrical signal is routed to the second signal trace when the conductors are soldered.

[0004] According to another aspect of this disclosure, a printed circuit board (PCB) is provided, comprising: a plurality of signal traces; and a connector package connected to the plurality of signal traces; wherein one or more signal traces and a portion of the connector package form a dual-path signal interconnect; and wherein the dual-path signal interconnect comprises: a first signal trace for carrying a high-speed electrical signal; a first pad having a first size, the first pad being located above and connected to the first signal trace; and a second pad having a second size, the second pad being located above and connected to the first signal trace, wherein the second pad... A pad is separated from the first pad by a first gap; and a third pad having a third size, wherein the third pad is separated from the second pad by a second gap, and the third pad is electrically connected to a second signal trace; wherein the first pad and the second pad are arranged such that pins of an external connector can be soldered to both the first pad and the second pad simultaneously, and when pins of the external connector are soldered, the high-speed electrical signal is routed to the external connector; and wherein the second pad and the third pad are arranged such that a conductor can be soldered to both the second pad and the third pad simultaneously, and when the conductor is soldered, the high-speed electrical signal is routed to the second signal trace.

[0005] According to another aspect of this disclosure, a connector package for mounting an external connector on a printed circuit board (PCB) is provided, the connector package comprising: a first set of connector pads; a second set of connector pads; and a set of resistor pads; wherein the first connector pad in the first set of connector pads is a standard pad, the standard pad being used to connect a first pin of the external connector to a signal trace on the printed circuit board; wherein the second connector pad in the second set of connector pads and a corresponding pair of resistor pads positioned adjacent to the second connector pad form a dual-path signal interconnect, the dual-path signal interconnect being capable of routing a signal from a first signal trace connected to the second connector pad to a second pin of the external connector. Alternatively, the signal can be routed to a second signal trace connected to the far-end resistor pad in the corresponding pair of resistor pads; wherein the second connector pad and the near-end resistor pad in the corresponding pair of resistor pads are arranged such that the second pin can be soldered to both the second connector pad and the near-end resistor pad simultaneously, and when the external connector is soldered, the signal from the first signal trace is routed to the second pin of the external connector; and wherein the near-end resistor pad and the far-end resistor pad are arranged such that the conductor can be soldered to both the near-end resistor pad and the far-end resistor pad simultaneously, and when the conductor is soldered, the signal from the first signal trace is routed to the second signal trace. Attached Figure Description

[0006] Figure 1 The diagram illustrates a scenario where two routing channels are needed for the same high-speed interface.

[0007] Figure 2A illustrates a standard package of cable connector pins on a PCB according to the prior art.

[0008] Figure 2B The illustration shows a modified package of cable connector pins according to one aspect of this disclosure.

[0009] Figure 3A The illustration depicts a first signal routing scenario according to one aspect of this disclosure.

[0010] Figure 3B The illustration depicts a second signal routing scenario according to one aspect of this disclosure.

[0011] Figure 4 The figure shows a side view of a soldered connector pin according to one aspect of this disclosure.

[0012] Figure 5A The illustration shows a dual-path interconnect for differential signals according to one aspect of this disclosure.

[0013] Figure 5B An enlarged view of connector pads and resistor pads for providing dual-path routing of differential signals, according to one aspect of this disclosure, is provided.

[0014] Figure 6A The illustration shows a connector package for implementing dual-path signal routing according to one aspect of this disclosure.

[0015] Figure 6B The illustration shows a partial top view of a PCB according to one aspect of the present disclosure, including a connector package and conductive traces connected to the connector package.

[0016] Figure 7 A flowchart illustrating the process of designing a PCB with dual-path interconnect according to one aspect of this disclosure is presented.

[0017] In these accompanying figures, the same reference numerals refer to the same figures. Detailed Implementation

[0018] The following description is presented to enable any person skilled in the art to make and use these examples, and the description is provided in the context of a particular application and its requirements. Various modifications to the disclosed examples will be apparent to those skilled in the art, and the general principles defined herein can be applied to other examples and applications without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure is not limited to the examples shown, but is intended to be consistent with the maximum scope of the principles and features disclosed herein.

[0019] This disclosure provides a solution for providing routing paths for high-speed buses (such as Fast Peripheral Component Interconnect (PCIe) buses) on a PCB. More specifically, the proposed solution allows routing paths to two different types of destinations (e.g., cable connectors and conductive traces) to coexist on a common PCB without adding any trace stubs, thereby significantly reducing PCB development / manufacturing costs without compromising signal integrity. The dual-path high-speed interconnect includes connector pads for connection to a cable connector and a pair of resistor pads for connection to a zero-ohm resistor. The connector pad and one resistor pad are located above and connected to a first high-speed signal trace, with a gap between the connector pad and the resistor pad to prevent stub formation. Another resistor pad may be located above and connected to a second high-speed signal trace, such that when a zero-ohm resistor is soldered to this pair of resistor pads, a high-speed signal from the first high-speed signal trace can be routed to the second high-speed signal trace. Conversely, if a cable connector is soldered to the connector pad and the adjacent resistor pad, a high-speed signal from the first high-speed signal trace can be routed to the cable connector.

[0020] Hardware engineers often face the task of designing PCBs that can be used for multiple purposes. For example, equipment vendors may manufacture servers with similar specifications but intended for use in different environments (e.g., mounted in different types of chassis). Because different chassis have different interface requirements, specific signal traces on the server motherboard may need to be routed to different destinations. For instance, a server used in one type of chassis might have a PCIe bus routing from the chassis's CPU to embedded devices on the chassis (e.g., an embedded memory controller), while a server used in a different type of chassis might have the same PCIe bus routing to cable connectors on a different type of chassis (e.g., connectors for interfacing with external storage devices). To reduce costs, it's desirable to share the same PCB design for the motherboards of both types of servers and use Bill of Materials (BOM) filling options to choose between two printed circuit assemblies (PCAs) or two signal routing options. A simple approach is to include two circuits (e.g., two routing channels) for two different purposes at different locations on the same PCB and add zero-ohm resistors as BOM options to choose between the two routing channels. However, such an approach not only consumes valuable board space but can also cause problems for high-speed signals. More specifically, simply using a zero-ohm resistor to select between two different routing paths can add a large number of stubs to the PCIe interface, which can negatively impact signal integrity, especially for high-speed (e.g., >5Gbps) signals. Note that a stub refers to a transmission line where one end is connected to other circuitry while the other end remains open. In the above scenario, unfilled routing paths can generate unwanted stubs that can lead to signal degradation.

[0021] Figure 1 The diagram illustrates a scenario where two routing channels are needed for the same high-speed interface. Figure 1 In this configuration, PCB 100 may include CPU 102, cable connector 104, and embedded device 106. CPU 102 may include PCIe interface 108, which can be routed to cable connector 104 or embedded device 106. Figure 1 It is also shown that traces 110, 112 and 114 are connected to PCIe interface 108, cable connector 104 and embedded device 106 respectively, and each trace includes a pad at its end.

[0022] Figure 1A zero-ohm resistor 116 is also shown, which can be used to couple traces 110 and 112 together, or to couple traces 110 and 114 together. When the zero-ohm resistor 116 is coupled to traces 110 and 112, signals from the PCIe interface 108 can be routed to cable connector 104, and then to an external device (e.g., an external storage device) inserted into cable connector 104. Similarly, when the zero-ohm resistor 116 is coupled to traces 110 and 114, signals from the PCIe interface 108 can be routed to an embedded device (e.g., an embedded memory controller) 106. The zero-ohm resistor 116 essentially acts as a switch to determine which circuitry will be activated in the final PCA. This approach is simple and easy to implement for low-speed signals. However, the pads and / or traces forming the two routing paths typically add stubs, which can lead to signal quality degradation. Furthermore, this method requires multiple pads, which increases the footprint of the signal interconnects, making it less practical for high-density PCBs. Considering that multiple traces from the PCIe interface 108 may need to be routed to the cable connector 104 and the embedded device 106, the increased number of pads could significantly increase the overall footprint of the signal interconnects.

[0023] To provide high-speed interconnects with dual-path options without the aforementioned problems, according to one aspect of this disclosure, dual-path interconnects can be achieved by modifying the standard package of the cable connector to integrate the pads for zero-ohm resistors as part of the cable connector package. This method does not add any stubs.

[0024] Figure 2A illustrates a standard package of cable connector pins on a PCB according to the prior art. Figure 2A shows a conductive trace 202 located on the top surface of PCB 200. More specifically, the conductive trace 202 may be a microstrip transmission line. In one example, the conductive trace 202 may be used to connect pins of the CPU's PCIe interface to pins of a cable connector. Because Figure 2A shows only a partial view of PCB 200, the PCIe interface and the portion of the conductive trace 202 extending to the PCIe interface are not shown.

[0025] Figure 2A also shows a connector pad 204 located on top of the conductive trace 202. The connector pad 204 can be a surface mount pad used to allow surface mount components (e.g., cable connectors) to be electrically connected (e.g., via soldering) to the conductive trace on the PCB. For example, a pin of a cable connector (not shown in Figure 2A) can be soldered to the connector pad 204, thereby establishing an electrical connection between the connector pin and the conductive trace 202. The connector pad 204 can also be referred to as a package for the connector pin. To show the portion of the conductive trace 202 below the connector pad 204, the connector pad 204 is shown as transparent, although it is actually opaque. In the example shown in Figure 2A, only a portion of the connector pad 204 is on top of the conductive trace 202 along its length, while the rest of the connector pad 204 is on the bare PCB. If conductive trace 202 is electrically connected to a pin of the PCIe interface, signals from that pin can be routed to the cable connector pin soldered to connector pad 204. This is a standard signal interconnect with single-path signal routing.

[0026] Figure 2B The illustration shows a modified package of cable connector pins according to one aspect of this disclosure. Figure 2B In this configuration, conductive trace 212 is located on the top surface of PCB 210. Like conductive trace 202, conductive trace 212 can be a microstrip used to connect pins of the CPU's PCIe interface to pins of a cable connector. Conductive trace 212 extends further than conductive trace 202.

[0027] Figure 2B A connector pad 214 located at the top of the conductive trace 212 is also shown. The connector pad 214 is smaller in size compared to the connector pad 204 shown in FIG. 2A. More specifically, the length of the connector pad 214 is reduced. The entire length of the connector pad 214 lies at the top of the conductive trace 212 as the conductive trace 212 extends. Furthermore, the conductive trace 212 extends beyond the edge of the connector pad 214 to allow a first resistor pad 216 to be formed at the top of the end of the conductive trace 212. According to one aspect, the first resistor pad 216 may be a standard pad for soldering surface mount resistors, and the size of the first resistor pad 216 may be significantly smaller than the size of the connector pad 204. Note that a gap exists between the first resistor pad 216 and the connector pad 214, preventing these pads from contacting each other.

[0028] In addition to the first resistor pad 216, the modified package of the connector pins also includes a second resistor pad 218 corresponding to the first resistor pad 216. The size of the second resistor pad 218 can be similar to that of the first resistor pad 216. The first resistor pad 216 and the second resistor pad 218 form a resistor pad pair to allow surface mount resistors to be mounted onto the PCB 210. Furthermore, the second resistor pad 218 is positioned at the top of the end of the conductive trace 220. The conductive trace 220 can be similar to the conductive trace 212 and can be a microstrip transmission line. According to one aspect, the conductive trace 220 can be connected to different devices (e.g., surface mount devices) on the PCB 210. Different devices are not on... Figure 2B As shown in the image.

[0029] The sizes of various components on PCB 210 (including conductive traces 212 and 220, and pads 214, 216, and 218) can be determined based on actual needs (e.g., PCB space constraints, transmission losses, surface mount resistor dimensions, etc.). The scope of this disclosure is not limited to the actual sizes of the conductive traces and pads. The accompanying drawings (including Figure 2A and...) Figure 2B (This is for illustrative purposes only and is not drawn to actual component scale.) In one example, the width of conductive traces 212 and 220 may be approximately 5 mil (or 0.13 mm). The gap between pads 214 and 216 may be comparable to the width of the conductive traces (e.g., between 5 mil and 10 mil). The distance between the end of pad 214 and the end of conductive trace 212 may be approximately 0.3 mm. The dimensions of resistor pads 216 and 218 and the gap between them may be determined based on the size of the resistor to be soldered. In one example, the surface mount resistor may be 0.6 mm × 0.3 mm.

[0030] according to Figure 2B As can be seen, when the first resistor pad 216 and the second resistor pad 218 are isolated from each other (e.g., when no resistors are soldered to these pads), conductive trace 220 is isolated from conductive trace 212. In this case, signals from conductive trace 212 can be routed to the cable connector by soldering cable connector pins to connector pad 214. On the other hand, if the cable connector is not filled on PCB 210 (or not soldered to connector pad 214) and if a low-resistance resistor (e.g., a zero-ohm resistor) is soldered to the first resistor pad 216 and the second resistor pad 218, conductive trace 220 will be electrically connected to conductive trace 212 to allow signals from conductive trace 212 to be routed to conductive trace 220. Through conductive trace 220, signals can then be routed to devices connected to conductive trace 220.

[0031] Figure 3A The illustration depicts a first signal routing scenario according to one aspect of this disclosure. Figure 3A In the PCB 300, there are first conductive traces 302 and second conductive traces 310, which can interact with... Figure 2B The conductive traces 212 and 220 shown are similar. PCB 300 also includes connector pads 304 and resistor pads 306 and 308, which are similar to connector pad 214 and resistor pads 216 and 218, respectively. Figure 3A In the example shown, connector pin 312 is soldered to connector pad 304 and resistor pad 306 to provide enhanced bonding between connector pin 312 and PCB 300. Figure 3A As can be seen, the signal from conductive trace 302 will be routed to connector pin 312. According to one aspect, connector pin 312 can be part of a cable connector to allow the signal from conductive trace 302 to be routed to a pluggable device connected to the cable connector. Note that in Figure 3A In the example shown, no resistor is soldered between resistor pads 306 and 308, keeping these resistor pads isolated from each other. Therefore, no signal is routed to conductive trace 310.

[0032] Figure 3B The illustration depicts a second signal routing scenario according to one aspect of this disclosure. Note that... Figure 3A The PCB300 shown and Figure 3B The PCB 320 shown can have the same board design, but can be filled with different components. Like PCB 300, PCB 320 can include a first conductive trace 322 and a second conductive trace 330, which can be connected to… Figure 3A The conductive traces 302 and 310 shown are similar. PCB 320 may also include connector pads 324 and resistor pads 326 and 328, which are respectively connected to... Figure 3A The connector pad 304 and resistor pads 306 and 308 shown are similar. Figure 3A The examples shown are different, in Figure 3B In this configuration, no connector pins are soldered to connector pad 324 because the corresponding cable connector is not filled on PCB 320. Instead, a zero-ohm resistor 332 is soldered to both resistor pads 326 and 328, thereby establishing an electrical connection between conductive traces 322 and 330. Therefore, signals from conductive trace 322 will be routed to conductive trace 330. According to one aspect, connection trace 330 can be connected to embedded devices on PCB 320. Figure 3B(Not shown in the image). Note that the embedded device may be located on the same side of the PCB 320 as the conductive trace 322 or on the opposite side. Alternatively, the conductive trace 330 may be connected to a connector at a different location on the PCB 320 to allow signals from the conductive trace 322 to be routed to that connector.

[0033] according to Figures 3A to 3B As can be seen, the signal interconnects on the PCB (including connector pads and this pair of resistor pads) can provide two distinct routing paths, and the choice between these two paths can be achieved through BOM fill options. When a cable connector is filled, the routing path from the first conductive trace leads to the cable connector; when a zero-ohm resistor is filled, the routing path from the first conductive trace leads to the second conductive trace. This approach is compact (e.g., it requires relatively minor modifications to the cable connector package) and does not add stubs to the circuit, thus preserving signal integrity.

[0034] Figure 4 The illustration shows a side view of a soldered connector pin according to one aspect of this disclosure. More specifically, Figure 4 The diagram shows connector pin 400 being soldered to connector pad 402 and resistor pad 404. Although there is a gap between connector pad 402 and resistor pad 404, connector pin 400 can be soldered to both pads by applying a sufficient amount of solder. Note that the amount of solder should be carefully controlled to avoid excessive solder causing unnecessary contact. For example, solder should not create contact between resistor pads 404 and 406, such as... Figure 4 As shown in the diagram, the dome at the top of resistor pad 406 contains solder, which protects pad 406 from oxidation. Figure 4 This illustrates that no stub is formed when connector pin 400 is soldered. More specifically, the heel area of ​​connector pin 400 (indicated by dashed box 408) is filled with solder, thus eliminating stub formation. Similarly, it is conceivable that no stub will be formed when zero-ohm resistors are soldered to disks 404 and 406. Therefore, this solution for providing two-path interconnects can be a zero-stub solution, making it suitable for high-speed signals.

[0035] Figures 3A to 3B A single conductive trace for carrying a single-ended signal is shown. In many cases, differential signals may be required. This proposed two-path interconnect solution can also be applied to differential signals. Figure 5A The illustration depicts a dual-path interconnect for differential signals according to one aspect of this disclosure. Figure 5AIn this design, PCB 500 may include a pair of conductive traces 502 and 504 carrying differential signals. Conductive traces 502 and 504 can be connected to high-speed interfaces of devices on PCB 500. For example, conductive traces 502 and 504 can be connected to the PCIe interface of a CPU mounted on PCB 500. Figure 2B Similar to conductive trace 212 shown, conductive traces 502 and 504 can each be connected to connector pads and resistor pads. For example, connector pad 506 and resistor pad 508 are shown on top of conductive trace 502, thus electrically connected to conductive trace 502; conductive pad 510 and resistor pad 512 are shown on top of conductive trace 504, thus electrically connected to conductive trace 504. Figure 5A Another pair of conductive traces (e.g., traces 514 and 516) and pads 518 and 520 are also shown, which are located on top of conductive traces 514 and 516, respectively. Figure 3A and Figure 3B As shown, when a pair of connector pins are soldered to the connector pads and resistor pads on the conductive traces 502 and 504, respectively, the differential signal carried by conductive traces 502 and 504 can be routed to the connector. On the other hand, when a pair of zero-ohm resistors are soldered to resistor pads 508 and 518 and resistor pads 512 and 520, the differential signal carried by conductive traces 502 and 504 can be routed to conductive traces 514 and 516.

[0036] For comparison, Figure 5A Standard connector pads 522 and 524 are also shown. Connector pad 522 is located on top of conductive trace 526. In this example, it is not necessary to provide a dual-path for conductive trace 526 (e.g., conductive trace 526 carries a low-speed signal that can be routed using other mechanisms). Therefore, connector pad 522 can be a standard pad for soldering connector pins. On the other hand, connector pad 524 is a ground pad, which can also be a standard pad. Figure 5A As can be seen, when a conductive trace requires a dual-path connection, the connector pads connected to the conductive trace can be modified (e.g., reduced in length) to allow resistor pads to connect to the same conductive trace. The conductive trace itself may also need to be extended to ensure contact with the added resistor pads. This additional resistor pad provides a bridging point to different conductive traces.

[0037] Figure 5B An enlarged view of connector pads and resistor pads for providing dual-path routing of differential signals, according to one aspect of this disclosure, is provided. Figure 5B The documentation also provides exemplary sizes for various pads, including the dimensions of the gap between adjacent pads.

[0038] A typical connector may include many pins, and not all signals need to have a dual-path routing option. For example... Figure 5A As shown, low-speed (e.g., less than 1Gbps) signals and ground signals do not require this method. Therefore, not all pin pads of the connector are modified. Figure 6A The illustration depicts a connector package according to one aspect of this disclosure for implementing dual-path signal routing. Connector package 600 may include multiple connector pads for soldering a connector to a PCB and for establishing electrical connections between the connector and conductive traces leading to these connector pads. Some of these connector pads are standard-sized pads, such as pads 602 and 604. Note that all pads in conventional connector packages are standard pads of uniform size. In addition to standard connector pads, connector package 600 may include modified connector pads (e.g., pads 606 and 608) and corresponding resistor pads to provide dual-path signal routing.

[0039] The modified connector pads are shorter than standard connector pads, and each modified connector pad is accompanied by a pair of resistor pads. For example, modified connector pad 606 is accompanied by a pair of resistor pads 610, which are adjacent to connector pad 606 and positioned along the longitudinal axis of the connector pad. The placement of the accompanying resistor pad pair is to ensure that the resistor pads immediately adjacent to the modified connector pads can be electrically connected to the connection traces carrying the signals to be routed to the connector.

[0040] Figure 6B The illustration shows a partial top view of a PCB according to one aspect of this disclosure, including a connector package and conductive traces connected to the connector package. Modified connector packages (as indicated by the dashed box) can be used with... Figure 6AThe connector package 600 shown is similar and can include standard connector pads and modified connector pads. More specifically, the area with modified connector pads is marked using two solid-line rectangles. The left rectangle includes a pair of modified connector pads connected to a pair of differential conductive traces. In one example, these differential conductive traces can provide a PCIe clock signal, which can be routed to the connector or to an embedded device. The right rectangle includes four pairs of modified connector pads in its top area. In one example, the four pairs of differential conductive traces connected to these modified conductive pads (marked by the ellipse above the rectangle) carry high-speed signals transmitted by the PCIe interface. The right rectangle also includes four pairs of modified connector pads in its bottom area, which are connected to four pairs of differential conductive traces (marked by the ellipse below the rectangle). In one example, these differential conductive traces carry high-speed signals from the PCIe interface. Note that when the connector pads are modified and the corresponding resistor pads are included, high-speed signals to and from the PCIe interface can be routed to embedded devices (e.g., embedded memory devices) via the zero-ohm resistors when the connector is not filled on the PCB and a zero-ohm resistor is filled.

[0041] exist Figure 6A and Figure 6B In the example shown, the cable connector has 74 pins. In practice, the proposed solution can be implemented for any type of connector, regardless of the number of pins or the size of each connector pad. According to one aspect, the connector type can include, but is not limited to: PCIe connectors, Universal Serial Bus (USB) connectors (which may also include different types of USB connectors), Ethernet connectors, etc.

[0042] Figure 7 A flowchart illustrating the process of designing a PCB with dual-path interconnects according to one aspect of this disclosure is presented. During operation, an initial PCB design can be generated for a routing option (operation 702). For example, the initial PCB design may assume that external pluggable devices will be used and that the CPU's PCIe interface will be connected to a cable connector. The initial PCB design may include a standard cable connector package, wherein all connector pads have standard dimensions.

[0043] Subsequently, a set of pads connected to high-speed signal paths can be identified from all connector pads (operation 704). High-speed signal paths may include PCIe clock signals, PCIe transmit paths, and PCIe receive paths, etc. Each identified connector pad can then be modified (operation 706). More specifically, the modified connector pads can be shorter. In addition to modifying the connector pads, the high-speed conductive traces connected to the modified connector pads can be extended (operation 708). With the conductive traces extended and the connector pads shortened, corresponding resistor pads can be added to accompany each modified connector pad (operation 710).

[0044] Additional conductive traces can be added to connect the resistor pads to the embedded device (operation 712). The layout of the additional conductive traces can be determined based on the size of the embedded device and the available space on the board. The PCB can then be fabricated based on the design (operation 714). Once the PCB is fabricated, it can be used for different applications, whether using external pluggable components or embedded devices. When using a PCB in an application utilizing pluggable components, the PCB BOM can include the pluggable components and the cable connectors to be soldered to the connector pads. On the other hand, when using a PCB in an application utilizing embedded devices, the PCB BOM does not include the cable connectors, but includes the embedded device and an appropriate number of zero-ohm resistors to be soldered to the resistor pads.

[0045] In general, this disclosure provides a solution to the problem of implementing dual-path signal routing on a PCB without adding any stubs. More specifically, in cases where high-speed signals require the option to be routed to pluggable devices (e.g., via cable connectors) or embedded devices (e.g., via conductive traces), the cable connector package can be modified to achieve dual-path signal routing. According to one aspect, standard connector pads can be shortened to allow both the shortened connector pads and resistor pads to connect to the conductive traces carrying the high-speed signal. The shortened connector pads and resistor pads should be spaced apart, which is necessary when mounting resistors to prevent excessive solder and component lifting. A corresponding resistor pad and an additional conductive trace connected to that corresponding resistor pad may also be included as part of the dual-path high-speed signal interconnect. When the cable connector is soldered to the cable connector package, the shortened connector pads and the adjacent resistor pads are soldered to the connector pins, thereby allowing high-speed signals from the conductive traces to be routed to the cable connector. On the other hand, when a zero-ohm resistor is soldered to the resistor pads, high-speed signals from the conductive traces will be routed to additional conductive traces. This allows selection between the two routing paths to be achieved using the PCB's BOM fill options. This method does not add any stubs to the signal path, thus making it suitable for high-speed signals.

[0046] One aspect of this disclosure provides a dual-path signal interconnect on a printed circuit board (PCB). The interconnect may include: a first signal trace for carrying a high-speed electrical signal; a first pad having a first size, located above and electrically connected to the first signal trace; a second pad having a second size, located above and electrically connected to the first signal trace; and a third pad having a third size. The second pad is spaced apart from the first pad by a first gap. The third pad is spaced apart from the second pad by a second gap and is electrically connected to the second signal trace. The first and second pads are configured to allow pins of an external connector to be soldered to both pads simultaneously, such that when the pins of the external connector are soldered, a high-speed electrical signal is routed to the external connector. The second and third pads are configured to allow conductors to be soldered to both pads simultaneously, such that when the conductors are soldered, a high-speed electrical signal is routed to the second signal trace.

[0047] In a variation of this, the conductor includes a zero-ohm surface-mount resistor.

[0048] In this variant, the first dimension is larger than the second dimension.

[0049] In this variation, the second and third dimensions are essentially similar.

[0050] In a variant of this aspect, no stub is formed when the pins of the external connector are soldered to both the first and second pads, or when the conductor is soldered to both the second and third pads.

[0051] In a variant of this aspect, the first signal trace is connected to the processor's Fast Peripheral Component Interconnect (PCIe) interface.

[0052] In variations of this aspect, the external connector includes one of the following: a PCIe (High-Speed ​​Peripheral Component Interconnect) connector, a USB (Universal Serial Bus) connector, and an Ethernet connector.

[0053] In a variant of this aspect, the high-speed electrical signal is a differential signal, and the first signal trace comprises a pair of differential signal traces.

[0054] One aspect of this disclosure provides a printed circuit board (PCB). The PCB may include multiple signal traces and a connector package connected to the signal traces. One or more signal traces and a portion of the connector package form a two-path signal interconnect. The two-path signal interconnect may include: a first signal trace for carrying a high-speed electrical signal; a first pad having a first size, located above and connected to the first signal trace; a second pad having a second size, located above and connected to the first signal trace; and a third pad having a third size. The second pad is spaced apart from the first pad by a first gap. The third pad is spaced apart from the second pad by a second gap and is connected to the second signal trace. The first pad and the second pad are used to allow pins of an external connector to be soldered to both pads simultaneously, such that when the pins of the external connector are soldered, high-speed electrical signals are routed to the external connector; and the second pad and the third pad are used to allow conductors to be soldered to both pads simultaneously, such that when the conductors are soldered, high-speed electrical signals are routed to the second signal trace.

[0055] One aspect of this disclosure provides a connector package for mounting an external connector on a printed circuit board (PCB). The connector package may include a first set of connector pads, a second set of connector pads, and a set of resistor pads. The first connector pad in the first set is a standard pad used to couple a first pin of the external connector to a signal trace on the PCB. The second connector pad in the second set and a corresponding pair of resistor pads positioned adjacent to the second connector pad form a two-path signal interconnect capable of routing a signal from a first signal trace connected to the second connector pad to a second pin of the external connector, or to a second signal trace connected to the distal resistor pad of the corresponding pair of resistor pads. The near-end resistor pad in the second connector pad and the corresponding pair of resistor pads are used to allow the second pin to be soldered to both the second connector pad and the near-end resistor pad simultaneously, such that when the external connector is soldered, the signal from the first signal trace is routed to the second pin of the external connector; and the near-end resistor pad and the far-end resistor pad are used to allow the conductor to be soldered to both the near-end resistor pad and the far-end resistor pad simultaneously, such that when the conductor is soldered, the signal from the first signal trace is routed to the second signal trace.

[0056] The methods and processes described in the Detailed Description section may be embodied in code and / or data, which may be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and / or data stored on the computer-readable storage medium, the computer system executes the methods and processes embodied in data structures and code and stored within the computer-readable storage medium.

[0057] Furthermore, the methods and processes described above may be included in hardware modules or devices. Hardware modules or devices may include, but are not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), dedicated or shared processors that execute specific software modules or code at specific times, and other programmable logic devices now known or developed later. When a hardware module or device is activated, it executes the methods and processes included therein.

[0058] The foregoing description has been presented for purposes of illustration and description only. These descriptions are not intended to be exhaustive or to limit the scope of this disclosure to the disclosed form. Accordingly, many modifications and variations will be apparent to those skilled in the art.

Claims

1. A dual-path signal interconnect on a printed circuit board (PCB), the dual-path signal interconnect comprising: The first signal trace is used to carry high-speed electrical signals; A first pad having a first size, the first pad being located above and connected to the first signal trace; A second pad having a second size, the second pad being located above and connected to the first signal trace, wherein the second pad is separated from the first pad by a first gap, and the first size is larger than the second size; and A third pad having a third size, wherein the third pad is spaced apart from the second pad by a second gap, and the third pad is connected to a second signal trace; The first pad and the second pad are arranged such that the pins of the external connector can be soldered to both the first pad and the second pad simultaneously, and when the pins of the external connector are soldered, the high-speed electrical signal is routed to the external connector. The second and third pads are arranged such that a conductor can be simultaneously soldered to both pads, and when the conductor is soldered, the high-speed electrical signal is routed to the second signal trace; and Specifically, when the pins of the external connector are simultaneously soldered to the first pad and the second pad, or when the conductor is simultaneously soldered to the second pad and the third pad, no short circuit is formed.

2. The dual-path signal interconnection as described in claim 1, wherein, The conductor includes a zero-ohm surface mount resistor.

3. The dual-path signal interconnection as described in claim 1, wherein, The first signal trace is connected to the processor's PCIe (Packet Interconnect) interface.

4. The dual-path signal interconnection as described in claim 1, wherein, The external connector includes one of the following: PCIe (Peripheral Component Interconnect) connector; Universal Serial Bus (USB) connector; and Ethernet connector.

5. The dual-path signal interconnection as described in claim 1, wherein, The second signal trace is connected to a surface mount device.

6. The dual-path signal interconnection as described in claim 1, wherein, The high-speed electrical signal is a differential signal, and the first signal trace includes a pair of differential signal traces.

7. A printed circuit board (PCB), comprising: Multiple signal traces; as well as A connector package is connected to the plurality of signal traces, wherein the connector package includes a first pad having a first size, a second pad having a second size, and a third pad having a third size; The multiple signal traces, the first pad, the second pad, and the third pad form a dual-path signal interconnect; and The dual-path signal interconnection includes: The first signal trace is used to carry high-speed electrical signals; The first pad is located above and connected to the first signal trace; The second pad is located above and connected to the first signal trace, wherein the second pad is separated from the first pad by a first gap, and the first size is larger than the second size; and The third pad is separated from the second pad by a second gap, and the third pad is electrically connected to the second signal trace; The first pad and the second pad are arranged such that the pins of the external connector can be soldered to both the first pad and the second pad simultaneously, and when the pins of the external connector are soldered, the high-speed electrical signal is routed to the external connector. The second and third pads are arranged such that a conductor can be simultaneously soldered to both pads, and when the conductor is soldered, the high-speed electrical signal is routed to the second signal trace; and Specifically, when the pins of the external connector are simultaneously soldered to the first pad and the second pad, or when the conductor is simultaneously soldered to the second pad and the third pad, no short circuit is formed.

8. The printed circuit board as claimed in claim 7, wherein, The conductor includes a zero-ohm surface mount resistor.

9. The printed circuit board as claimed in claim 7, wherein, The first signal trace is connected to the processor's PCIe (Packet Interconnect) interface.

10. The printed circuit board of claim 7, wherein, The external connector includes one of the following: PCIe (Peripheral Component Interconnect) connector; Universal Serial Bus (USB) connector; and Ethernet connector.

11. The printed circuit board of claim 7, wherein, The second signal trace is connected to a surface mount device.

12. The printed circuit board of claim 7, wherein, The high-speed electrical signal is a differential signal, and the first signal trace includes a pair of differential signal traces.

13. A connector package for mounting an external connector on a printed circuit board (PCB), the connector package comprising: First set of connector pads; Second set of connector pads; as well as A set of resistor pads; Wherein, the first connector pad in the first group of connector pads is a standard pad, and the standard pad is used to connect the first pin of the external connector to the signal trace on the printed circuit board; Wherein, the second connector pad in the second set of connector pads and the corresponding pair of resistor pads positioned adjacent to the second connector pad form a dual-path signal interconnect. The dual-path signal interconnect can route a signal from a first signal trace connected to the second connector pad to the second pin of the external connector, or to a second signal trace, the second signal trace being connected to the far end resistor pad in the corresponding pair of resistor pads. The second connector pad and the near-end resistor pad of the corresponding pair of resistor pads are arranged such that the second pin can be soldered to both the second connector pad and the near-end resistor pad simultaneously, and when the external connector is soldered, the signal from the first signal trace is routed to the second pin of the external connector, wherein the size of the second connector pad is larger than the size of the near-end resistor pad. The near-end resistor pad and the far-end resistor pad are arranged such that a conductor can be simultaneously soldered to both the near-end resistor pad and the far-end resistor pad, and when the conductor is soldered, a signal from the first signal trace is routed to the second signal trace; and Specifically, when the second pin is simultaneously soldered to the second connector pad and the near-end resistor pad, or when the conductor is simultaneously soldered to the near-end resistor pad and the far-end resistor pad, a short stub is not formed.

14. The connector package as described in claim 13, wherein, The external connector includes one of the following: PCIe (High-Speed ​​Peripheral Component Interconnect) connector; Universal Serial Bus (USB) connector; and Ethernet connector.

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