A video decoding and display system based on a domestic platform core

Abstract

The application discloses a kind of based on localization platform core video decoding display system, including sequentially connected CPU, core graphics card and display, CPU includes several cores, core graphics card includes decoding unit, image processing unit and display unit, and decoding unit is equipped with API interface.This based on localization platform core video decoding display system uses localization processor platform to decode and display video using core graphics card, reduces the load of CPU, and compared with independent core graphics card, using core graphics card for decoding has the advantages of small size, low overall power consumption, cheap;CPU sends the video data supported by core graphics card to the video memory of core graphics card, and keeps the video data not supported by core graphics card in the memory of CPU, solves the problem that directly sending screen data to core graphics card for decoding in prior art will cause format not supported, resulting in black screen, and serious will cause core graphics card blocking exception.

Description

Technical Field

[0001] This invention belongs to the field of video decoding, specifically relating to a video decoding and display system based on a domestically developed platform with integrated graphics. Background Technology

[0002] In existing video decoding technologies, considering the high resolution and high bitrate of high-definition videos, traditional CPU decoding results in a heavy load, negatively impacting the user experience. Currently, domestically produced CPUs mainly consist of solutions from Shenwei, Phytium, and Loongson, and most chip solutions do not implement integrated graphics functionality within the CPU. On non-domestic platforms, Intel and AMD CPUs have integrated graphics functionality, including media acceleration capabilities; however, domestically produced CPU platforms, due to technological limitations and hardware manufacturing processes, do not yet possess integrated graphics functionality. To meet multimedia needs, one must either rely on the CPU's computing power for video processing, leading to high CPU utilization, or rely on an external discrete graphics card (such as the Jingjia Micro JM7200) or a dedicated IP core (such as the Phytium X100 chipset).

[0003] The Jingjia Micro JM7200 graphics card is a dedicated graphics card with integrated video encoding and decoding acceleration. It needs to connect to the CPU via a PCIe x4 slot and is relatively large. The Phytium X100 chipset, launched by Phytium in 2021, integrates integrated graphics, SATA, audio / video interfaces, etc. When paired with a Phytium CPU, it can achieve high-performance desktop applications. However, the X100 and Phytium CPU are two different chipsets. The common practice is to combine the X100 with other peripheral interfaces into a hardware module and use it with the Phytium CPU as a core board. Alternatively, the X100 chipset can be used to create a dedicated graphics card for discrete graphics applications.

[0004] On domestically produced platforms, implementing video decoding and display functions using either the Jingjia Micro JM7200 discrete graphics card or a similar Phytium X100 chipset results in disadvantages such as large size and high power consumption due to complex structural design. This makes them unsuitable for mobile light office applications, and laptops cannot meet the requirements for miniaturized devices. Furthermore, both the Jingjia Micro JM7200 graphics card and the Phytium X100 chipset have issues with not supporting or having limited decoding capabilities for the H.265 video format. Directly sending such videos to the graphics card for decoding will result in decoding failure, a black screen, and in severe cases, abnormal blocking of the integrated graphics. Summary of the Invention

[0005] The purpose of this invention is to address the problems mentioned in the background art by proposing a video decoding and display system based on a domestically developed platform.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] This invention proposes a video decoding and display system based on a domestically developed platform with integrated graphics, comprising a CPU, an integrated graphics card, and a monitor connected in sequence. The CPU includes several cores, and the integrated graphics card includes a decoding unit, an image processing unit, and a display unit. The decoding unit is equipped with an API interface.

[0008] One of the CPU's cores reads the video data into the CPU's memory, and the CPU analyzes and processes the video data to obtain relevant information.

[0009] The CPU calls the API interface to initialize resources and queries the set of video decoding capabilities of the integrated graphics card.

[0010] The CPU transmits relevant information about the video data to the video decoding capability set parameters of the integrated graphics card, sends the video data supported by the integrated graphics card to the integrated graphics card's video memory, and leaves the video data not supported by the integrated graphics card in the CPU's memory.

[0011] The CPU configures the scaling parameters and format conversion of the decoded video data, and configures the binding relationship between the video frame to be displayed and the display unit.

[0012] The CPU calls the API interface of the decoding unit, which reads the video data supported by the graphics card core and starts decoding the video data, storing the decoded data into the video memory.

[0013] The image processing unit reads the decoded data from the video memory, and performs corresponding processing on the decoded data according to the scaling parameters and format conversion to obtain the video image to be displayed, and sends it to the display unit.

[0014] Finally, the display unit outputs the video image directly as a signal, and displays the video image on the monitor.

[0015] Preferably, the CPU analyzes and processes the video data to obtain relevant information about the video data, including: the CPU removes the encapsulation information from the video data, retains the original encoded data, and analyzes the encoding format, resolution, frame rate, specifications, and grade-related information of the video data.

[0016] Preferably, the API interface is a public interface of the VAAPI or VDPAU architecture, or a non-public SDK interface.

[0017] Preferably, the CPU configures the scaling parameters and format conversion of the decoded video data, including:

[0018] The image processing unit performs proportional scaling on the decoded video data;

[0019] It then converts the decoded video data into RGB format (YV12 or NV12).

[0020] Preferably, the display unit is provided with a display port, and the display port is connected to the monitor via a video signal.

[0021] Preferably, configuring the binding relationship between the video image to be displayed and the display unit includes:

[0022] The binding relationship between the video image to be displayed and the display port, and the coordinate position relationship of the scaled image on the monitor surface.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] 1. This video decoding and display system based on a domestic platform uses a domestic processor platform to decode and display video using integrated graphics, which reduces the CPU load. Compared with a dedicated integrated graphics card, using integrated graphics for decoding has the advantages of small size, low overall power consumption, and low price.

[0025] 2. The CPU sends video data supported by the integrated graphics card to the integrated graphics card's video memory, while keeping video data not supported by the integrated graphics card in the CPU's memory. This solves the problem in existing technologies where directly sending video data to the integrated graphics card for decoding can cause format incompatibility issues leading to black screens, and in severe cases, can cause the integrated graphics card to become blocked or malfunction. Attached Figure Description

[0026] Figure 1 This is a block diagram of the video decoding and display system based on a domestically developed platform according to the present invention.

[0027] Figure 2 This is a flowchart of the video decoding and display system based on a domestically developed platform according to the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] It should be noted that when a component is referred to as being "connected" to another component, it can be directly connected to the other component or there may be an intervening component. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to limit the application.

[0030] like Figures 1-2 As shown, a video decoding and display system based on a domestically developed platform with integrated graphics includes a CPU, an integrated graphics card, and a monitor connected in sequence. The CPU includes several cores, and the integrated graphics card includes a decoding unit, an image processing unit, and a display unit. The decoding unit has an API interface. The CPU and the integrated graphics card communicate via a PCIe bus. In this embodiment, as shown... Figure 1 The CPU shown has a four-core architecture, but the specific data of the core architecture is not limited.

[0031] The entire video decoding and display process based on the domestically developed platform is as follows:

[0032] Step 1: One of the CPU cores reads the video data into the CPU's memory, and the CPU analyzes and processes the video data to obtain relevant information.

[0033] Specifically, video data can be a network stream or a file stream. When the CPU analyzes and processes the video data, it removes the encapsulation information, retains the original encoded data, and analyzes the encoding format, resolution, frame rate, specifications, and rating information of the video data. Video data encoding formats generally include H.264 and H.265, resolutions include CIF (352x288 pixels), D1 (704x576), HD (1920x1080), and 4K (3840x2160), and specifications include H.264 encoding specifications (Base Profile, Main Profile, High Profile, and External Profile) and H.265 encoding specifications (H.265 Main Profile 8-bit and 10-bit).

[0034] Step 2: The CPU calls the API interface to initialize resources and queries the set of video decoding capabilities of the integrated graphics card.

[0035] Specifically, the API interface is a public interface based on the VAAPI or VDPAU architecture, or a non-public SDK interface. The purpose of querying the integrated graphics card's video decoding capabilities is to understand the formats, resolutions, frame rates, specifications, or levels that the integrated graphics card can support for video decoding.

[0036] Step 3: The CPU transmits the relevant information of the video data to the video decoding capability set parameters of the integrated graphics card, and sends the video data supported by the integrated graphics card to the video memory of the integrated graphics card, while leaving the video data that is not supported by the integrated graphics card in the CPU's memory.

[0037] It should be noted that the CPU's memory and the integrated graphics card's video memory are shared (the CPU has already sent the video data to the video memory), resulting in fast interaction speed.

[0038] Specifically, the relevant information of the video data is compared with the video decoding capability set parameters of the integrated graphics card. SPS (Sequence Parameter Set) is used to perform software filtering on the relevant information of the video data. The CPU sends video data supported by the integrated graphics card to the integrated graphics card's video memory, while video data not supported by the integrated graphics card remains in the CPU's main memory. Video data not supported by the integrated graphics card is then decoded by the CPU using software decoding.

[0039] Step 4: Configure the scaling parameters and format conversion of the decoded video data in the CPU, and configure the binding relationship between the video frame to be displayed and the display unit.

[0040] Specifically, image scaling parameters: The image processing unit performs proportional scaling on the decoded video data. If the video resolution exceeds the display resolution range, the video needs to be scaled, such as scaling a video with a resolution exceeding 1920x1080 to 1920x1080. Using the image processing unit for this operation, instead of the CPU, aims to reduce the performance overhead of reading data from video memory to main memory.

[0041] Format conversion: The image processing unit converts the decoded video data in YV12 or NV12 format into RGB formats, such as RGGB, RGBA, etc., because the display unit outputs in RGB format.

[0042] The display unit is equipped with a display port (VideoPort), which is connected to the monitor via a video signal.

[0043] Configure the binding relationship between the video image to be displayed and the display unit: the binding relationship between the video image to be displayed and the display port (consistent format) and the coordinate position relationship of the scaled image on the display surface (physical coordinate position).

[0044] Step 5: The CPU calls the API interface of the decoding unit. The decoding unit reads the video data supported by the graphics card core and starts decoding the video data through the decoding unit, and stores the decoded data into the video memory.

[0045] Step 6: The image processing unit reads the decoded data from the video memory, and performs corresponding processing on the decoded data according to the scaling parameters and format conversion to obtain the displayed video image, and sends it to the display unit.

[0046] Step 7: Finally, the display unit outputs the video image directly and displays the video image on the monitor. The coordinate position of the image on the monitor surface is consistent with that in Step 4.

[0047] This video decoding and display system based on a domestically developed platform utilizes a domestically produced processor platform and integrated graphics to decode and display video, reducing the CPU load. Compared to a dedicated integrated graphics card, using integrated graphics for decoding has advantages such as smaller size, lower overall power consumption, and lower price. The CPU sends video data supported by the integrated graphics card to the integrated graphics card's video memory, while keeping video data not supported by the integrated graphics card in the CPU's main memory. This solves the problem in existing technologies where directly sending video data to the integrated graphics card for decoding can cause format incompatibility issues leading to black screens, and in severe cases, can cause the integrated graphics card to become blocked or malfunction.

[0048] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The embodiments described above are merely specific and detailed examples of the embodiments described in this application, and should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this patent application should be determined by the appended claims.

Claims

1. A video decoding and display system based on a domestically developed platform, characterized in that: The domestically developed platform-based integrated graphics video decoding and display system includes a CPU, an integrated graphics card, and a monitor connected in sequence. The CPU includes several cores, and the integrated graphics card includes a decoding unit, an image processing unit, and a display unit. The decoding unit is equipped with an API interface, wherein: One of the CPU cores reads video data into the CPU's memory, and the CPU analyzes and processes the video data to obtain relevant information about the video data. The CPU calls the API interface to initialize resources and queries the set of video decoding capabilities of the integrated graphics card. The CPU transmits relevant information about the video data to the video decoding capability set parameters of the integrated graphics card, sends the video data supported by the integrated graphics card to the integrated graphics card's video memory, and leaves the video data not supported by the integrated graphics card in the CPU's memory. The CPU configures the scaling parameters and format conversion of the decoded video data, and configures the binding relationship between the video frame to be displayed and the display unit; The CPU calls the API interface of the decoding unit, the decoding unit reads the video data supported by the graphics card core, and starts decoding the video data through the decoding unit, and stores the decoded data into the video memory; The image processing unit reads the decoded data from the video memory, and performs corresponding processing on the decoded data according to the scaling parameters and format conversion to obtain the displayed video image, which is then sent to the display unit. Finally, the display unit directly outputs the video image to be displayed, and the video image is displayed on the monitor. Among them, the API interface is a public interface of VAAPI or VDPAU architecture, or a non-public SDK interface; The relevant information of the video data is compared with the video decoding capability set parameters of the integrated graphics card, and the relevant information of the video data is filtered by software using SPS. The CPU sends the video data supported by the integrated graphics card to the integrated graphics card's video memory, and keeps the video data that the integrated graphics card does not support in the CPU's memory.

2. The video decoding and display system based on a domestically developed platform as described in claim 1, characterized in that: The CPU analyzes and processes the video data to obtain relevant information, including: removing the encapsulation information from the video data, retaining the original encoded data, and analyzing the encoding format, resolution, frame rate, specifications, and rating of the video data.

3. The video decoding and display system based on a domestically developed platform as described in claim 1, characterized in that: The CPU configures the scaling parameters and format conversion of the decoded video data, including: The image processing unit performs proportional scaling on the decoded video data; It then converts the decoded video data into RGB format (YV12 or NV12).

4. The video decoding and display system based on a domestically developed platform as described in claim 1, characterized in that: The display unit is provided with a display port, and the display port is connected to the monitor via a video signal.

5. The video decoding and display system based on a domestically developed platform as described in claim 4, characterized in that: The configuration of the binding relationship between the video frame to be displayed and the display unit includes: The binding relationship between the video image to be displayed and the display port, and the coordinate position relationship of the scaled image on the monitor surface.

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