Display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device. The display panel comprises a pixel circuit and a light emitting element; in the pixel circuit, a driving module comprises a driving transistor, a gate of the driving transistor is connected to a first node; a reset module comprises a first sub-transistor and a second sub-transistor, a connection node between the first sub-transistor and the second sub-transistor is a second node; a compensation module comprises a third sub-transistor and a fourth sub-transistor, a connection node between the third sub-transistor and the fourth sub-transistor is a third node; in a first stage, both a first double-gate transistor and a second double-gate transistor are turned off, the first node, the second node and the third node satisfy (V2-V1) x (V1-V3) > 0. Embodiments of the present application solve the problem of the first node potential change caused by the transistor drain current, can ensure that the first node voltage is relatively stable, maintain the stability of the light emitting element brightness, and improve the display effect of the display panel.

Description

[0001] This application is a divisional application of the patent filed on May 17, 2021, with application number 202110536427.3 and invention title: Display Panel and Display Device. Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) have become a research hotspot in the display field due to their advantages such as low power consumption, low cost, self-emissive nature, wide viewing angle, and fast response speed. Electronic display products employ different refresh rates in different application scenarios. For example, a higher refresh rate is used to drive dynamic images to ensure smoothness, while a lower refresh rate is used to drive static images to reduce power consumption.

[0004] When electronic products using organic self-emissive technology are displayed at low refresh rates, the gate potential of the driving transistor in the existing pixel circuit will change due to leakage current from other switches. This causes the brightness of the driving light-emitting element to continuously decrease and then increase, resulting in unstable display brightness of the display panel, which affects the display effect and user experience. Summary of the Invention

[0005] The present invention provides a display panel and a display device to stabilize the potential of the gate of the driving transistor in the pixel circuit, maintain the stability of the brightness of the light-emitting element, and improve the display effect of the display panel.

[0006] In a first aspect, embodiments of the present invention provide a display panel, comprising:

[0007] Pixel circuits and light-emitting elements;

[0008] The pixel circuit includes a driving module, a reset module, and a compensation module;

[0009] The driving module is used to provide driving current to the light-emitting element. The driving module includes a driving transistor, and the gate of the driving transistor is connected to the first node.

[0010] The reset module is used to provide a reset signal for the gate of the driving transistor. The reset module includes a first dual-gate transistor, which includes a first sub-transistor and a second sub-transistor. The connection node between the first sub-transistor and the second sub-transistor is a second node.

[0011] The compensation module is used to compensate the threshold voltage of the driving transistor. The compensation module includes a second dual-gate transistor, which includes a third sub-transistor and a fourth sub-transistor. The connection node between the third and fourth sub-transistors is a third node.

[0012] The operation of the pixel circuit includes a first stage, in which the first dual-gate transistor and the second dual-gate transistor are both turned off, the voltage of the first node is V1, the voltage of the second node is V2, and the voltage of the third node is V3, wherein (V2-V1)×(V1-V3)>0.

[0013] Secondly, embodiments of the present invention also provide a display device, including the display device described in any of the first aspects.

[0014] In this embodiment, the voltage between the first node and the third node is set to satisfy (V2-V1)×(V1-V3)>0, which ensures that the voltage of the first node is between the voltages of the second node and the third node. At this time, even if there are voltage differences between the first node and both the second and third nodes, the two voltage differences have different signs, resulting in different directions of leakage current in the inter-node transistors. For the first node, the leakage current flows from the second node through the first node to the third node, or from the third node through the first node to the second node. Compared to the prior art where leakage current flows from both the second and third nodes to the first node, this embodiment ensures a relatively stable voltage for the first node. This embodiment solves the problem in the prior art where transistor leakage current caused by scanning signals and capacitance leads to changes in the first node's potential. By changing the node voltage difference, it reduces the impact of leakage current on the first node, ensuring a relatively stable voltage for the first node, thereby maintaining the stability of the light-emitting element's brightness and improving the display effect of the display panel, especially under low-frequency driving. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the pixel circuit structure in a conventional display panel provided by an embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram of the structure of a pixel circuit and a light-emitting element in a display panel provided by an embodiment of the present invention;

[0017] Figure 3 This is a timing diagram of the driving signals for the pixel circuit provided in an embodiment of the present invention;

[0018] Figure 4 This is a schematic diagram of the pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention;

[0019] Figure 5 This is a schematic diagram of the structure of pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention;

[0020] Figure 6 This is a schematic diagram of the structure of pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention;

[0021] Figure 7 This is a schematic diagram of the structure of pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention;

[0022] Figure 8 This is a schematic diagram of the structure of pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention;

[0023] Figure 9 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0025] Figure 1 This is a schematic diagram of the pixel circuit structure in a conventional display panel provided by an embodiment of the present invention, for reference. Figure 1 As described in the background section, in the existing pixel circuit 10, the first node N1 is connected to the gate of the driving transistor T3, one end of the first dual-gate transistor T1, and one end of the second dual-gate transistor T2. Those skilled in the art will understand that this pixel circuit may include a reset phase, a data writing phase, and a light-emitting phase. In the reset phase, the first dual-gate transistor T1 provides a reset signal Vref to reset the potential of the first node N1. In the data writing phase, the second dual-gate transistor T2 writes a data signal data to the first node N1 while simultaneously compensating the threshold voltage of the driving transistor T3 to the potential of the first node N1. In the light-emitting phase, the driving transistor T3 uses the threshold-compensated data signal stored at the gate (i.e., the first node N1) to drive the light-emitting element 20 to emit light.

[0026] It is important to note that the dual-gate transistor in this pixel circuit includes two sub-transistors, and a capacitor is connected in parallel between the node connecting the two sub-transistors and their gates. It can be understood that when the two sub-transistors are turned on or off by a scan signal, one plate of the capacitor also receives the scan signal. According to the charging and discharging principle of the capacitor plates, the charge on the two plates of the capacitor will affect each other; that is, when one plate receives the scan signal, it will affect the potential of the other plate, thus affecting the potential of the connection node between the two sub-transistors. Taking the first dual-gate transistor T1 in the figure as a P-type dual-gate transistor as an example, the connection node between the first sub-transistor T11 and the second sub-transistor T12 in the first dual-gate transistor T1 is the second node N2. During the light-emitting stage, the gate of the first dual-gate transistor T1 receives the first scan signal S1 (high-level signal) and is turned off. At this time, the second capacitor C2 will raise the potential of the second node N2 due to the high-level signal, causing the potential of the second node N2 to be greater than the potential of the first node N1. This causes leakage current to occur in the second sub-transistor T12 during this stage, and the potential of the first node N1 increases. Similarly, the second dual-gate transistor T2, also a P-type transistor, will have the same effect on the first node N1 during this light-emitting stage. Specifically, the potential of the third node N3 is raised due to the influence of the third capacitor C3 and the second scan signal S2 (high-level signal), causing the potential of the third node N3 to be greater than that of the first node N1. The third sub-transistor T23 in the second dual-gate transistor T2 also generates leakage current, causing the potential of the first node N1 to rise. Ultimately, the potential of the first node N1 will be affected by the potentials of the second node N2 and the third node N3, causing leakage current in the sub-transistors and thus affecting the potential of the first node N1. Experiments have shown that during this stage, when the driving transistor T3 drives the light-emitting element 20 to light up, the brightness of the light-emitting element 20 exhibits a phenomenon of continuous decrease followed by gradual recovery due to changes in the first node N1, resulting in unstable brightness of the light-emitting element 20.

[0027] To address the aforementioned problems, this invention provides a display panel. The display panel includes: a pixel circuit and a light-emitting element; the pixel circuit includes a driving module, a reset module, and a compensation module; the driving module provides driving current to the light-emitting element, and includes a driving transistor whose gate is connected to a first node; the reset module provides a reset signal to the gate of the driving transistor, and includes a first dual-gate transistor, which includes a first sub-transistor and a second sub-transistor, with the connection node between the first and second sub-transistors being a second node; the compensation module compensates for the threshold voltage of the driving transistor, and includes a second dual-gate transistor, which includes a third and a fourth sub-transistor, with the connection node between the third and fourth sub-transistors being a third node; wherein the operation of the pixel circuit includes a first stage, in which both the first and second dual-gate transistors are turned off, the voltage of the first node is V1, the voltage of the second node is V2, and the voltage of the third node is V3, wherein (V2-V1)×(V1-V3)>0.

[0028] In this embodiment, the voltage between the first and third nodes is set to satisfy (V2-V1)×(V1-V3)>0, which ensures that V2>V1 while V3<V1, or V3>V1 while V2<V1. In other words, this embodiment ensures that the voltage of the first node is between the voltage of the second and third nodes. At this time, even if there are voltage differences between the first node and both the second and third nodes, the two voltage differences have different signs, resulting in different directions of leakage current in the inter-node transistors. For the first node, the leakage current will flow from the second node through the first node to the third node, or from the third node through the first node to the second node. It can be understood that, compared to the prior art where leakage current flows from both the second and third nodes to the first node, this embodiment of the invention ensures that the voltage of the first node is relatively stable. Therefore, based on the relationship (V2-V1)×(V1-V3)>0, the pixel circuit provided in this embodiment of the invention ensures that even if the voltages of the second and third nodes change due to the scanning signal and capacitance, it will not have a significant impact on the voltage of the first node, thus guaranteeing the relative stability of the voltage of the first node.

[0029] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0030] Figure 2This is a schematic diagram of the pixel circuit and light-emitting element in a display panel according to an embodiment of the present invention. (Refer to...) Figure 2 The display panel includes a pixel circuit 10 and a light-emitting element 20. The pixel circuit 10 includes a driving module 11, a reset module 12, and a compensation module 13. The driving module 11 provides driving current to the light-emitting element 20 and includes a driving transistor T3, the gate of which is connected to a first node N1. The reset module 12 provides a reset signal to the gate of the driving transistor T3 and includes a first dual-gate transistor T1, which includes a first sub-transistor T11 and a second sub-transistor T12. The connection node between the first sub-transistor T11 and the second sub-transistor T12 is the second node N1. 2; The compensation module 13 is used to compensate the threshold voltage of the driving transistor T3. The compensation module 13 includes a second dual-gate transistor T2. The second dual-gate transistor T2 includes a third sub-transistor T23 and a fourth sub-transistor T24. The connection node between the third sub-transistor T23 and the fourth sub-transistor T24 is the third node N3. The operation process of the pixel circuit 10 includes a first stage. In the first stage, both the first dual-gate transistor T1 and the second dual-gate transistor T2 are turned off. The voltage of the first node N1 is V1, the voltage of the second node N2 is V2, and the voltage of the third node N3 is V3, where (V2-V1)×(V1-V3)>0.

[0031] Furthermore, in this pixel circuit, the reset module 12 is connected between the reset signal terminal Vref and the gate of the driving transistor T3, one end of the first dual-gate transistor T1 is connected to the reset signal terminal Vref, and the other end is connected to the gate of the driving transistor T3; the compensation module 13 is connected between the gate of the driving transistor T3 and the drain of the driving transistor T3, and one end of the second dual-gate transistor T2 is connected to the gate of the driving transistor T3, and the other end is connected to the drain of the driving transistor T3.

[0032] In this embodiment, the pixel circuit 10 is connected to the first power supply voltage signal terminal PVDD to receive the first power supply voltage signal, which is a constant high-level signal. The gate of the first dual-gate transistor T1 is connected to the first scan signal line S1 to receive the first scan signal; wherein, the pixel circuit 10 includes a second capacitor C2, the first plate of the second capacitor C2 is connected to the first scan signal line S1, and the second plate is connected to the second node N2. The gate of the second dual-gate transistor T2 is connected to the second scan signal line S2 to receive the second scan signal; wherein, the pixel circuit 10 includes a third capacitor C3, the first plate of the third capacitor C3 is connected to the second scan signal line S2, and the second plate is connected to the third node N3.

[0033] Figure 3This is a timing diagram of the driving signals for the pixel circuit provided in an embodiment of the present invention. First, refer to... Figure 2 and Figure 3 This document describes the functional modules and driving process of the pixel circuit in this embodiment of the invention. It should be noted that transistors T1-T7 in the pixel circuit of this embodiment are exemplary P-type transistors. When the control signal provided to their gates is high, the transistors are turned off; when the control signal is low, the transistors are turned on. In addition to the driving module 11, reset module 12, and compensation module 13, the pixel circuit also includes a light-emitting control module 14, an initialization module 15, and a data writing module 16. The light-emitting control module 14 includes a first light-emitting control module 141 and a second light-emitting control module 142. The first light-emitting control module 141 includes a fifth transistor T5, the second light-emitting control module 142 includes a sixth transistor T6, the initialization module 15 includes a seventh transistor T7, and the data writing module 16 includes a fourth transistor T4. The gates of the fifth transistor T5 and the sixth transistor T6 are both connected to the light-emitting control signal terminal EM; one end of the seventh transistor T7 is connected to the initialization signal terminal Vini, and the other end is connected to the anode of the light-emitting element 20; one end of the fourth transistor T4 is connected to the data signal terminal Vdata, and the other end is connected to the first terminal of the driving module 11, i.e., the driving transistor T3. In addition, other connections between functional modules or transistors, such as Figure 2 As shown, it will not be elaborated further here.

[0034] Those skilled in the art will understand that the driving process of this pixel circuit includes an initialization (reset) phase ta, a data writing phase tb, and a light emission phase tc. During the initialization (reset) phase ta, the first scan signal S1 transitions from high to low, at which point the first dual-gate transistor T1 is turned on, and the reset signal Vref is written to the first node N1. Simultaneously, the fourth scan signal S4 transitions from high to low, at which point the seventh transistor T7 is turned on, and the initialization signal Vini is written to the anode of the light-emitting element 20. This initialization (reset) phase is used to reset or initialize the first node N1 and the anode of the light-emitting element 20 to avoid the influence of the voltage signal written in the previous frame.

[0035] During the data writing (threshold capture) phase tb: the third scan signal S3 transitions from high to low, at which point the fourth transistor T4 turns on. Simultaneously, the second scan signal S2 transitions from high to low, at which point the second dual-gate transistor T2 turns on. The data signal Vdata flows into the first node N1 sequentially through the fourth transistor T4, the driving transistor T3, and the second dual-gate transistor T2. Furthermore, since the voltage of the fourth node N4 is Vdata, when the voltage of the first node N1 reaches Vdata-Vth (Vth is the threshold voltage of the driving transistor T3), the driving transistor T3 will turn off. That is, in this phase, the first node N1 writes the threshold-compensated data voltage signal Vdata-Vth.

[0036] During the light-emitting stage tc: the light-emitting control signal EM transitions from high to low. At this time, the fifth transistor T5 and the sixth transistor T6 are turned on, forming a path between the first power supply voltage signal terminal PVDD and the second power supply voltage signal terminal PVEE. The light-emitting element 20 emits light, and the magnitude of the emitting current is controlled by the gate potential of the driving transistor T3. Since the voltage stored at the first node N1 in the previous stage is Vdata-Vth, and the voltage at the third node N3 is slightly higher than the voltage at the second power supply voltage signal terminal PVEE, the current through the driving transistor T3 is I = K(N2-N1-Vth) = K(PVDD-Vdata). It can be understood that the larger the voltage stored at the first node N1, the larger the emitting current, and the greater the brightness of the light-emitting element 20. The voltage at the first node N1 affects the brightness of the light-emitting element 20.

[0037] Based on the above-described pixel circuit driving process, it should be noted that in this embodiment of the invention, in the first stage, the voltages of the first node N1 to the third node N3 satisfy (V2-V1)×(V1-V3)>0, where the first stage is the time period during which the first dual-gate transistor T1 and the second dual-gate transistor T2 are turned off. As can be seen from the above pixel circuit driving process, there is at least a light-emitting stage where the first dual-gate transistor T1 and the second dual-gate transistor T2 need to be turned off. In this embodiment, the voltages of the first node N1 to the third node N3 satisfy (V2-V1)×(V1-V3)>0 to avoid the turn-off signal affecting the second node N2 and the third node N3 when the first dual-gate transistor T1 and the second dual-gate transistor T2 are turned off, thereby affecting the voltage of the first node N1.

[0038] Specifically, when V2 > V1 and V3 < V1, since V2 > V1, there is a voltage difference across the second sub-transistor T12 between the second node N2 and the first node N1. If leakage current occurs in the second sub-transistor T12, the leakage current will flow from the second node N2 to the first node N1. Simultaneously, since V3 < V1, there is a voltage difference across the third sub-transistor T23 between the third node N3 and the first node N1. If leakage current occurs in the third sub-transistor T23, the leakage current will flow from the first node N1 to the third node N3. In this case, the voltage of the first node N1 is less affected by the transistor leakage current, and the voltage remains relatively stable. When V2 < V1 and V3 > V1, since V2 < V1, there is a voltage difference across the second sub-transistor T12 between the second node N2 and the first node N1. If leakage current occurs in the second sub-transistor T12, the leakage current will flow from the first node N1 to the second node N2. Meanwhile, since V3 > V1, there is a voltage difference across the third sub-transistor T23 between the third node N3 and the first node N1. If leakage current occurs in the third sub-transistor T23, the leakage current will flow from the third node N3 to the first node N1. At this time, the voltage of the first node N1 is less affected by the transistor leakage current, and the voltage can remain basically stable.

[0039] Based on the same principle, it can be understood that when both the first dual-gate transistor T1 and the second dual-gate transistor T2 are N-type transistors, the voltage of the first node N1 will also be affected by the second node N2 and the third node N3. Specifically, since the gates of the first dual-gate transistor T1 and the second dual-gate transistor T2 are at a low level when they are turned off, the potentials of the second node N2 and the third node N3 will be lower than the potential of the first node N1 due to the influence of the capacitor. This causes leakage current to be generated in the second sub-transistor T12 and the third sub-transistor T23, and the direction of the leakage current is from the first node N1 to the second node N2 and from the first node N1 to the third node N3, respectively, resulting in a decrease in the potential of the first node N1. In this case, the voltage between the first node N1 and the third node N3 in this embodiment is set to satisfy (V2-V1)×(V1-V3)>0. This also ensures that V2>V1 and V3<V1, or V2<V1 and V3>V1. At this time, the leakage current flow between the first node N1, the second node N2, and the third node N3 is from the second node N2 through the first node N1 to the third node N3, or from the third node N3 through the first node N1 to the second node N2. Obviously, the first node N1 is less affected by the transistor leakage current, and its voltage can remain basically stable.

[0040] To ensure that the voltage from the first node N1 to the third node N3 satisfies (V2-V1)×(V1-V3)>0, continue referring to... Figure 1 In one embodiment of the present invention, the voltages of the first node N1 to the third node N3 may be configured to satisfy V2 < V1 < V3. Specifically, the pixel circuit 10 may include a first capacitor C1, the first plate of the first capacitor C1 being connected to the first power supply voltage signal terminal PVDD, and the second plate being connected to the second node N2.

[0041] It is understandable that, since the second node N2 in the pixel circuit of this embodiment is electrically connected to the first power supply voltage signal terminal PVDD through the first capacitor C1, and the first power supply voltage signal terminal PVDD is a constant high-level signal, the potential of the second node N2 in the first stage will be affected by the charging and discharging of the capacitor plates of the first capacitor C1 and the second capacitor C2. Specifically, in this first stage, the first scan signal S1 jumps from the low level VGL to the high level VGH, and the first dual-gate transistor T1 is turned off; at the same time, the first capacitor C1 and the second capacitor C2 are connected in series, and since the first capacitor C1 is connected to the constant high-level signal, it can be known that the potential of the second node N2 is V2 = (VGH-VGL)×C2 / (C1+C2)+Vref1. As can be seen from the formula, compared to when the first capacitor C1 is not set, the potential of the second node N2 will be appropriately reduced, so that the potential of the first node N1 is between the potentials of the second node N2 and the third node N3, that is, V2 < V1 < V3. This can prevent leakage current from flowing from the second node N2 to the first node N1, affecting the potential of the first node N1 and thus ensuring the relative stability of the brightness of the light-emitting element 20.

[0042] Further optionally, in this embodiment of the invention, the first capacitor C1 and the second capacitor C2 may be configured to satisfy: C1 > C2. According to the above-mentioned potential formula for the second potential N2, the larger the first capacitor C1, the smaller the potential V2 of the second node N2. This allows the potential of the second node N2 to be reduced as much as possible, causing the leakage current of the second sub-transistor T12 to flow towards the second node N2, thus avoiding potential changes in the first node N1.

[0043] Further optionally, in this embodiment of the invention, the second capacitor C2 and the third capacitor C3 may be configured to satisfy: C2 ≤ C3. For example... Figure 2 As shown, exemplarily, since the second dual-gate transistor T2 is a P-type transistor, in the first stage, the second scan signal S2 changes from low to high, and the second dual-gate transistor T2 is turned off. At this time, under the action of the third capacitor C3, the second scan signal S2 will raise the potential of the third node N3. Since the relationship between voltage U, capacitance C, and charge Q is: U = Q / C, the larger the capacitance C, the smaller the voltage U. Therefore, in this embodiment, setting C2 ≤ C3 ensures that the potential of the third node N3 is raised higher, thereby ensuring that the first node N1 and the third node N3 satisfy V1 < V3.

[0044] In summary, in such Figure 2 In the illustrated embodiment, a first capacitor C1 may be set between the first power supply voltage signal terminal PVDD and the second node N2, and the first capacitor C1 is set to be greater than the second capacitor C2. At the same time, the second capacitor C2 is set to be greater than or equal to the third capacitor C3, so that the voltage between the first node N1 and the third node N3 satisfies V2 < V1 < V3. This allows the leakage current between the first node N1 and the third node N3 to flow from the third node N3 through the first node N1 to the second node N2, thus avoiding the first node N1 from receiving too much leakage current and causing its potential to rise, which would affect the stability of the light emission brightness of the light-emitting element.

[0045] In another embodiment of the present invention, the voltages of the first node N1 to the third node N3 may also be optionally set to satisfy V2 < V1 < V3. Figure 4 This is a schematic diagram of the pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention, for reference. Figure 4 In this embodiment, one end of the first sub-transistor T11 is optionally connected to the reset signal terminal Vref, and the other end is connected to the second node N2. In the first stage, the first sub-transistor T11 remains in the on state, and the second sub-transistor T12 remains in the off state.

[0046] It is understandable that if the first sub-transistor T11 is kept on in the first stage, then in this stage, the second node N2 always receives the reset signal Vref, and the potential of the second node N2 is a low-level reset signal. At this time, the potential V2 of the second node N2 is less than the potential V1 of the first node N1.

[0047] Specifically, to ensure that the first sub-transistor T11 remains in the on state during the first stage, as follows: Figure 4 As shown, in this embodiment, the gate of the first sub-transistor T11 can be connected to the reset signal line Vref to receive the reset signal. It can be understood that since the first sub-transistor T11 is a P-type transistor, and the reset signal line Vref is a low-level signal, when the gate of the first sub-transistor T11 is connected to the reset signal line Vref, the first sub-transistor T11 remains in the on state under the control of this effective reset signal. This means that the second node N2 receives the reset signal in the first stage, and the potential of the second node N2 is lower than that of the first node N1.

[0048] Figure 5 This is a schematic diagram of the pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention, based on the same concept, such as... Figure 5The pixel circuit shown also includes an initialization module 15, which is connected between the initialization signal terminal Vini and the light-emitting element 20 to provide an initialization signal to the light-emitting element 20; wherein, the gate of the first sub-transistor T11 can be connected to the initialization signal line Vini to receive the initialization signal.

[0049] Similarly, the effective signals of the initialization signal line Vini and the reset signal Vref are both low-level signals. In order to ensure that the first sub-transistor T11 is in the on state in the first stage and that the second node N2 receives the reset signal Vref, the first sub-transistor T11 can also be kept in the on state by using the low-level initialization signal. That is, as mentioned above, the gate of the first sub-transistor T11 can be connected to the initialization signal terminal Vini.

[0050] In addition to changing the pixel circuit structure in the above embodiments to make the potentials of the first node N1 to the third node N3 satisfy V2 < V1 < V3, in other embodiments of the present invention, the potentials of the first node N1 to the third node N3 can also be set to satisfy V2 > V1 > V3.

[0051] Figure 6 This is a schematic diagram of the pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention, for reference. Figure 6 First, in this pixel circuit, the gate of the first dual-gate transistor T1 is connected to the first scan signal line S1 to receive the first scan signal. The pixel circuit 10 includes a second capacitor C2, whose first plate is connected to the first scan signal line S1 and its second plate is connected to the second node N2. The gate of the second dual-gate transistor T2 is connected to the second scan signal line S2 to receive the second scan signal. The pixel circuit 10 also includes a third capacitor C3, whose first plate is connected to the second scan line S2 and its second plate is connected to the third node N3. The pixel circuit 10 can be configured to connect to a first power supply voltage signal terminal PVDD to receive the first power supply voltage signal, which is a constant high-level signal. The pixel circuit 10 also includes a first capacitor C1, whose first plate is connected to the first power supply voltage signal terminal PVDD and its second plate is connected to the third node N3.

[0052] Similarly, the two substrates of the first capacitor C1 are connected to the first power supply voltage signal and the third node N3 respectively, so that the first capacitor C1 and the third capacitor C3 form a series structure. Since one end of the first capacitor C1 is connected to the first power supply voltage signal terminal PVDD (constant high level signal), the potential of the third node N3 will be appropriately reduced compared to when the first capacitor C1 is not set. This makes the potential of the first node N1 located between the potentials of the third node N3 and the second node N2, that is, V2 > V1 > V3. This avoids leakage current flowing from the third node N3 to the first node N1, affecting the potential of the first node N1 and causing changes, thereby ensuring the relative stability of the brightness of the light-emitting element 20.

[0053] Similarly, based on the principle that the larger the first capacitor C1 is, the smaller the potential V3 of the third node N3, in this embodiment, the first capacitor C1 and the third capacitor C3 can be set to satisfy: C1 > C3. At this time, the potential of the third node N3 can be reduced as much as possible, so that the leakage current of the third sub-transistor T23 flows towards the third node N3, avoiding potential changes in the first node N1.

[0054] Furthermore, according to U = Q / C, the larger the capacitance C, the smaller the voltage U. Therefore, the second capacitor C2 and the third capacitor C3 can be set to satisfy: C2 ≥ C3. This ensures that the potential of the second node N2 is raised higher, thus ensuring that the first node N1 and the second node N2 satisfy V1 < V2.

[0055] In another embodiment of the present invention, the voltages of the first node N1 to the third node N3 may also be optionally set to satisfy V2 > V1 > V3. Figure 7 This is a schematic diagram of the pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention, for reference. Figure 7 In this embodiment, one end of the fourth sub-transistor T24 is optionally connected to the third node N3, and the other end is connected to the drain of the driving transistor T3. In the first stage, the fourth sub-transistor T24 remains in the on state, and the third sub-transistor T23 remains in the off state.

[0056] Similarly, if the fourth sub-transistor T24 is kept on in the first stage, then the third node N3 will always be equal to the drain potential of the driving transistor T3 in this stage. When the first dual-gate transistor T1 and the second dual-gate transistor T2 are both off, that is, when the reset module 12 and the compensation module 13 are both off, the pixel circuit 10 is in the light-emitting stage, and the driving transistor T3 is in a non-saturated state in the light-emitting stage, so that the drain potential of the driving transistor T3 is generally a low potential (the driving transistor is a P-type transistor). At this time, the third node N3 is a low potential, which realizes that the potential of the third node N3 is lower than the potential of the first node N1.

[0057] Specifically, to ensure that the fourth sub-transistor T24 remains on in the first stage, as follows: Figure 7 As shown, in this embodiment, the gate of the fourth sub-transistor T24 can be connected to the reset signal line Vref to receive the reset signal. It can be understood that since the fourth sub-transistor T24 is a P-type transistor, and the reset signal line Vref is a low-level signal, when the gate of the fourth sub-transistor T24 is connected to the reset signal line Vref, the fourth sub-transistor T24 remains in the on state under the control of this effective reset signal. This means that the third node N3 is always kept consistent with the drain potential of the driving transistor T3 in the first stage, and the potential of the third node N3 is lower than the potential of the first node N1.

[0058] Figure 8 This is a schematic diagram of the pixel circuit and light-emitting element in another display panel provided by an embodiment of the present invention, based on the same concept, such as... Figure 8 The pixel circuit shown also includes an initialization module 15, which is connected between the initialization signal terminal Vini and the light-emitting element 20, and is used to provide an initialization signal to the light-emitting element 20; wherein, the gate of the fourth sub-transistor T24 is connected to the initialization signal line Vini and receives the initialization signal.

[0059] Similarly, the effective signals of the initialization signal line Vini and the reset signal Vref are both low-level signals. In order to ensure that the fourth sub-transistor T24 is in the on state in the first stage and to keep the potential of the third node N3 consistent with the drain potential of the driving transistor T3, the low-level initialization signal Vini can also be used to control the fourth sub-transistor T24 to remain in the on state. That is, as mentioned above, the gate of the fourth sub-transistor T24 can be connected to the initialization signal terminal Vini.

[0060] Based on the various embodiments described above, the present invention further limits the transmission time of leakage current flowing from the second node N2 and the third node N3 to the first node N1. Specifically, in the first stage, the leakage current transmission time between the second node N2 and the first node N1 can be set to t1, and the leakage current transmission time between the third node N3 and the first node N1 can be set to t2; wherein the smaller of t1 and t2 is t0, the frame refresh rate of the display panel is MHz, and t0 ≥ 1 / M.

[0061] It can be understood that if the frame refresh rate of the display panel is MHz, then the time of one frame is 1 / M. In this embodiment, the smaller of the leakage current transmission time from the second node N2 to the first node N1 and the leakage current transmission time from the third node N3 to the first node N1 is set to be greater than or equal to the time of one frame of the display panel, that is, t0≥1 / M. Therefore, during the light-emitting phase of one frame, the first node N1 always participates in the leakage current processes of the second node N2 and the third node N3. That is, the leakage current flows from the second node N2 through the first node N1 and then into the third node N3, or the leakage current flows from the third node N3 through the first node N1 and then into the second node N2. At this time, the first node N1 is always in a state of leakage current equilibrium, and the potential of the first node N1 changes relatively little or even remains unchanged, thereby ensuring the stability of the light-emitting element's brightness.

[0062] Furthermore, in this embodiment of the invention, 0 ≤ |t1-t2| ≤ t0 × 1 / 5 can be set. In this case, the difference between t1 and t2 is small, which ensures that t0 is relatively large throughout the entire pixel driving process. This results in a longer leakage current balancing time for the first node N1, and correspondingly, a smaller frame refresh rate (MHz) for the display panel, which is beneficial for the display panel to achieve low-frequency driving display.

[0063] This invention also provides a display device. Figure 9 The diagram shown is a schematic representation of a display device according to an embodiment of the present invention. The display device 2 may include any of the display panels 1 provided in the above embodiments. Furthermore, since the display device is made using the aforementioned display panel, it possesses the same or corresponding technical effects as the aforementioned display panel. It should be noted that the display device also includes other devices for supporting the normal operation of the display device. Specifically, the display device may be a mobile phone, tablet, computer, television, wearable smart device, etc., and the embodiments of the present invention do not impose any limitations.

[0064] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a pixel circuit and a light emitting element; the pixel circuit comprises a driving module, a reset module and a compensation module; the driving module comprises a driving transistor; the reset module is connected between a reset signal end and a gate of the driving transistor, and the reset module comprises a first double-gate transistor, the first double-gate transistor comprises a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node; the compensation module is connected between the gate of the driving transistor and a drain of the driving transistor, and the compensation module comprises a second double-gate transistor, the second double-gate transistor comprises a third sub-transistor and a fourth sub-transistor, and a connection node between the third sub-transistor and the fourth sub-transistor is a third node; wherein the pixel circuit is connected to a first power voltage signal end for receiving a first power voltage signal, the first power voltage signal is a constant high level signal, the pixel circuit comprises a first capacitor, a first plate of the first capacitor is connected to the first power voltage signal end, and a second plate is connected to the second node; a gate of the first double-gate transistor is connected to a first scan signal line for receiving a first scan signal, the pixel circuit comprises a second capacitor, a first plate of the second capacitor is connected to the first scan signal line, and a second plate of the second capacitor is connected to the second node; a gate of the second double-gate transistor is connected to a second scan signal line for receiving a second scan signal, the pixel circuit comprises a third capacitor, a first plate of the third capacitor is connected to the second scan signal line, and a second plate of the third capacitor is connected to the third node; wherein the second capacitor C2 and the third capacitor C3 satisfy: C2≤C3.

2. The display panel of claim 1, wherein one end of the first sub-transistor is connected to a reset signal end, and the other end is connected to the second node; a working process of the pixel circuit comprises a first stage, in the first stage, the first sub-transistor remains in an open state, and the second sub-transistor remains in a closed state.

3. The display panel of claim 2, wherein the pixel circuit further comprises an initialization module, the initialization module is connected between an initialization signal end and the light emitting element, and is configured to provide an initialization signal for the light emitting element; wherein the gate of the first sub-transistor is connected to a reset signal line to receive the reset signal; or the gate of the first sub-transistor is connected to an initialization signal line to receive the initialization signal.

4. The display panel of claim 1, wherein one end of the fourth sub-transistor is connected to the third node, and the other end is connected to the drain of the driving transistor; a working process of the pixel circuit comprises a first stage, in the first stage, the fourth sub-transistor remains in an open state, and the third sub-transistor remains in a closed state.

5. The display panel of claim 4, wherein The pixel circuit further comprises an initialization module connected between an initialization signal terminal and the light-emitting element, configured to provide an initialization signal for the light-emitting element; wherein The gate of the fourth sub-transistor is connected to a reset signal line and receives the reset signal; or The gate of the fourth sub-transistor is connected to an initialization signal line and receives the initialization signal.

6. A display device, characterized by comprising: The display panel comprises the pixel circuit according to any one of claims 1-5.

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