Physical layer and data processing method

Abstract

The present application discloses a physical layer and a signal processing method for clock domain transfer of quarter-rate data. In the embodiment of the present application, a plurality of sampling circuits process quarter-rate data by means of a first clock signal, a second clock signal and a third clock signal, and a training mechanism is used to align the phases of the clock signals so that the clock signals have better timing margins.

Description

Technical Field

[0001] The present invention relates to a method for clock-domain transfer of quarter-rate data, and more particularly to a physical interface with good timing margin for data transfer. Background Technology

[0002] In a physical interface of double data rate synchronous dynamic random access memory (DDR SDRAM), the clock domain transfer of data from an internal clock to a write clock is crucial at high frequencies. Furthermore, due to on-chip variation (OCV), the circuitry used for clock domain transfer presents numerous design challenges, such as the synchronization of different data and static skew within the clock. Therefore, designing a physical interface with good timing performance is an important issue. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a physical interface with good timing margin for data transmission, thereby solving the above-mentioned problems.

[0004] According to an embodiment of the present invention, a physical layer is provided. The physical layer may include a first set of sampling circuits, a second set of sampling circuits, a first multiplexer, a second multiplexer, a third set of sampling circuits, and a third multiplexer. The first set of sampling circuits can be used to sample multiple data using a first clock signal to generate multiple first sampled data. The second set of sampling circuits can be used to sample the multiple first sampled data using a second clock signal to generate multiple second sampled data. The first multiplexer can be used to select one of a first signal and a second signal to generate a first multiplexer output signal, wherein the first signal and the second signal are obtained from a portion of the multiple second sampled data. The second multiplexer can be used to select one of a third signal and a fourth signal to generate a second multiplexer output signal, wherein the third signal and the fourth signal are obtained from another portion of the multiple second sampled data. The third set of sampling circuits can be used to sample the first multiplexer output signal and the second multiplexer output signal using a third clock signal to generate multiple third sampled data. The third multiplexer can be used to alternately select one of the multiple third sampled data to generate an output signal.

[0005] According to an embodiment of the present invention, a data processing method is provided. The data processing method may include: sampling a plurality of data using a first clock signal to generate a plurality of first sampled data; sampling the plurality of first sampled data using a second clock signal to generate a plurality of second sampled data; selecting one of a first signal and a second signal to generate a first multiplexer output signal, wherein the first signal and the second signal are obtained from a portion of the plurality of second sampled data; selecting one of a third signal and a fourth signal to generate a second multiplexer output signal, wherein the third signal and the fourth signal are obtained from another portion of the plurality of second sampled data; sampling the first multiplexer output signal and the second multiplexer output signal using a third clock signal to generate a plurality of third sampled data; and alternately selecting one of the plurality of third sampled data to generate an output signal.

[0006] One advantage of this invention is that by designing a physical layer with multiple sampling circuits and multiplexers to process quarter-rate data using a first clock signal, a second clock signal, and a third clock signal corresponding to different clock domains, and by designing a training mechanism to align the phases of the first clock signal, the second clock signal, and the third clock signal, these clock signals will have better timing margins to reduce static skew. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the physical interface of a double data rate synchronous dynamic random access memory according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram of a clock signal generator according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram of a circuit for generating a clock signal according to an embodiment of the present invention.

[0010] Figures 4-6 This is a signal timing diagram within a physical interface according to an embodiment of the present invention.

[0011] Figure 7 This is a schematic diagram illustrating the phase difference between clock signals CKCDC and CKW2 for different cases.

[0012] Figure 8 This is a flowchart of a training method for a clock signal generator according to an embodiment of the present invention.

[0013] Figure 9 This is a schematic diagram showing the phase difference between clock signals CKW1 and CKW2.

[0014] Figure 10 This is a flowchart of a training method for a clock signal generator according to an embodiment of the present invention.

[0015] [Symbol Explanation]

[0016] 100: Physical Interface

[0017] 110: Numerical part

[0018] 120: Simulation Section

[0019] 112_1~112_4, 121_1~121_4, 122_1~122_4, 123_1, 123_2, 125_1~125_3, 310, 320: D-type flip-flops

[0020] 124_1, 124_2, 127, 128: Multiplexers

[0021] DE0, DE1, DO0, DO1: Digital data

[0022] E0, E1, O0, O1, E0A, E1A, O0A, O1A: Sampled data

[0023] V1, V2, V3, V4, V7, V8: Sampled signals

[0024] V5, V6: Multiplexer output signals

[0025] Vout: Output signal

[0026] CKCDC, CKW2, CKW1, CK: Clock signal

[0027] CKW2', CKW1': Delayed clock signals

[0028] 200: Clock signal generator

[0029] 112, 136: Duty Cycle Corrector

[0030] 114, 124: Frequency dividers

[0031] 116, 126, 134: Digitally controlled delay lines

[0032] 118, 129, 138: Buffer

[0033] 130: Inverter

[0034] 132: Delay element

[0035] 330: Control Circuit

[0036] FLAG1, FLAG2: Sampling results

[0037] Vc1, Vc2, Vc3: Control signals

[0038] 800~832, 1000~1020: Steps Detailed Implementation

[0039] In the following embodiments and claims, certain terms are used to refer to specific system components. As those skilled in the art will understand, manufacturers may use different names to refer to a component. This document is not intended to distinguish between components with different names but the same function. In the following embodiments and claims, the term "comprising" is used in an open-ended manner and should therefore be interpreted as "comprising but not limited to...". The term "coupled" is intended to indicate an indirect or direct electrical connection. Thus, if a first device is coupled to a second device, the connection may be through a direct electrical connection or through an indirect electrical connection via other devices and connections.

[0040] Figure 1 This is a schematic diagram of the physical interface 100 of a double data rate synchronous dynamic random access memory (DDR SDRAM) according to an embodiment of the present invention. Figure 1 As shown, the physical interface 100 may include a digital section 110 and an analog section 120. The digital section 110 may include four sampling circuits (e.g., four D-type flip-flops (DFFs) 112_1 to 112_4), and the analog section 120 may include a first set of sampling circuits (containing four D-type flip-flops 121_1 to 121_4), a second set of sampling circuits (containing four D-type flip-flops 122_1 to 122_4), two sampling circuits (containing two D-type flip-flops 123_1 and 123_2), two multiplexers 124_1 and 124_2, a third set of sampling circuits (containing three D-type flip-flops 125_1, 125_2, and 125_3), and a multiplexer 127. Figure 1 In the physical interface 100 shown, the physical interface 100 can be used to receive multiple digital data DE0, DE1, DO0 and DO1 with a quarter data rate according to multiple clock signals CKCDC, CKW2 and CKW1 to generate an output signal Vout, wherein the frequency of clock signal CKCDC is substantially the same as the frequency of clock signal CKW2, and the frequency of clock signal CKW1 is twice the frequency of clock signal CKW2.

[0041] Figure 2This is a schematic diagram of a clock signal generator 200 according to an embodiment of the present invention, wherein the clock signal generator 200 can be located within the physical interface 100. For example... Figure 2 As shown, the clock signal generator 200 may include a first path for generating clock signal CKCDC, a second path for generating clock signal CKW2, and a third path for generating clock signal CKW1. The first path may include a duty-cycle corrector (DCC); for simplicity, in Figure 2 112 (marked as "DCC"), 114 (frequency divider), and 115 (digitally controlled delay line, DCDL). For simplicity, these are referred to as DCC. Figure 2 The first path may include a frequency divider 124, a digitally controlled delay line 126, an inverter 130, a multiplexer 128, and a buffer 129. The second path may include a delay element 132, a digitally controlled delay line 134, a duty cycle corrector 136, and a buffer 138.

[0042] In the operation of the first path of the clock signal generator 200, the duty cycle corrector 112 can receive a clock signal CK from a phase-locked loop and adjust the duty cycle of the clock signal CK so that the duty cycle of the adjusted clock signal is equal to 50%. Then, the frequency divider 114 can use the divisor "2" to divide the adjusted clock signal to generate a frequency-divided clock signal. The frequency-divided clock signal can pass through the digital control delay line 116 and the buffer 118 to generate a clock signal CKCDC, wherein the frequency of the clock signal CKCDC is half the frequency of the clock signal CK.

[0043] In the operation of the second path of the clock signal generator 200, the frequency divider 124 can use a divisor "2" to divide the adjusted clock signal output by the duty cycle corrector 112 according to a triggering of a falling edge of one of the adjusted clock signals, so as to generate a divided clock signal. Then, the digital control delay line 126 can delay the divided clock signal to generate a delayed clock signal. The inverter 127 can receive the delayed clock signal to generate an inverted delayed clock signal. The multiplexer 128 can select one of the delayed clock signal and the inverted delayed clock signal to generate an output clock signal. The output clock signal can pass through the buffer 129 to generate a clock signal CKW2, wherein the frequency of the clock signal CKW2 is half the frequency of the clock signal CK.

[0044] In the operation of the third path of the clock signal generator 200, the delay element 132 and the digital control delay line 134 can delay the clock signal CK to generate a delayed clock signal. The duty cycle corrector 136 can receive the delayed clock signal from the digital control delay line 134 and adjust the duty cycle of the delayed clock signal so that the duty cycle of the adjusted clock signal is equal to 50%. Then, the adjusted clock signal can pass through the buffer 138 to generate the clock signal CKW1, wherein the frequency of the clock signal CKW1 is substantially the same as the frequency of the clock signal CK.

[0045] In order for the physical interface 100 to output correct data, the phases of multiple clock signals CKCDC, CKW2, and CKW1 need to be precisely controlled to ensure good timing margin between clock signals CKCDC and CKW2, and good timing margin between clock signals CKW2 and CKW1. Therefore, this invention provides a training mechanism that can generate multiple control signals Vc1, Vc2, and Vc3 to control the digital control delay line 126, the multiplexer 128, and the digital control delay line 134 respectively, so as to align the phases of multiple clock signals CKCDC, CKW2, and CKW1. Figure 3 This is a schematic diagram of a control circuit 330 for generating multiple control signals Vc1, Vc2, and Vc3 according to an embodiment of the present invention. Figure 3 In this circuit, D-type flip-flop 310 can be used to sample clock signal CKW2 using clock signal CKCDC to generate a sampling result FLAG1. D-type flip-flop 320 can be used to sample clock signal CKW1 using clock signal CKW2 to generate a sampling result FLAG2. Control circuit 330 can receive sampling result FLAG1 and sampling result FLAG2 to determine appropriate control signals Vc1, Vc2, and Vc3. Detailed operation descriptions of D-type flip-flop 310, D-type flip-flop 320, and control circuit 330 are provided in [the relevant section]. Figure 8 as well as Figure 10 middle.

[0046] Please refer to the matching instructions. Figure 1 as well as Figures 4-6 , Figures 4-6This is a signal timing diagram within a physical interface 100 according to an embodiment of the present invention. In the operation of physical interface 100, multiple D-type flip-flops 112-1-112_4 respectively use the clock signal CKCDC to sample multiple digital data DE0, DE1, DO0, and DO1 to generate multiple sampled data E0, E1, O0, and O1. In this embodiment, the multiple D-type flip-flops 112-1-112_4 use a rising edge of the clock signal CKCDC to sample multiple digital data DE0, DE1, DO0, and DO1, but the present invention is not limited thereto. Then, multiple D-type flip-flops 121_1-121_4 respectively use the clock signal CKCDC to sample multiple sampled data E0, E1, O0, and O1 to generate multiple sampled data E0A, E1A, O0A, and O1A. In this embodiment, the multiple D-type flip-flops 121_1-121_4 use a falling edge of the clock signal CKCDC to sample multiple data E0, E1, O0, and O1, but the present invention is not limited thereto.

[0047] Next, D-type flip-flop 122_1 samples the data E0A using the falling edge of clock signal CKW2 to generate a sample signal V1. D-type flip-flop 122_2 samples the data E1A using the falling edge of clock signal CKW2 to generate a sample signal, and D-type flip-flop 123_1 samples the sample signal output by D-type flip-flop 122_2 using the rising edge of clock signal CKW2 to generate a sample signal V2. D-type flip-flop 122_3 samples the data O0A using the falling edge of clock signal CKW2 to generate a sample signal V3. D-type flip-flop 122_4 samples the data O1A using the falling edge of clock signal CKW2 to generate a sample signal, and D-type flip-flop 123_2 samples the sample signal output by D-type flip-flop 122_4 using the rising edge of clock signal CKW2 to generate a sample signal V4.

[0048] Next, the multiplexer 124_1 alternately selects one of the sampled signals V1 and V2 according to a delayed clock signal CKW2' to generate a multiplexer output signal V5, wherein the delayed clock signal CKW2' is generated by delaying the clock signal CKW2 using one or more delay elements. For example, refer to... Figure 5When the delayed clock signal CKW2' has a low voltage level, multiplexer 124_1 selects sampled signal V1 as the multiplexer output signal V5; and when the delayed clock signal CKW2' has a high voltage level, multiplexer 124_1 selects sampled signal V2 as the multiplexer output signal V5. Similarly, multiplexer 124_2 alternately selects one of sampled signals V3 and V4 according to the delayed clock signal CKW2' to generate a multiplexer output signal V6. For example, refer to... Figure 5 When the delayed clock signal CKW2' has a low voltage level, the multiplexer 124_2 selects the sampled signal V3 as the multiplexer output signal V6; and when the delayed clock signal CKW2' has a high voltage level, the multiplexer 124_2 selects the sampled signal V4 as the multiplexer output signal V6.

[0049] Next, D-type flip-flop 125_1 samples the sampling signal V5 using the rising edge of clock signal CKW1 to generate sampling signal V7. D-type flip-flop 125_2 samples the sampling signal V6 using the rising edge of clock signal CKW1, and D-type flip-flop 125_3 samples an output signal of D-type flip-flop 125_2 using the falling edge of clock signal CKW1 to generate sampling signal V8. Multiplexer 127 alternately selects one of sampling signal V7 and sampling signal V8 according to a delayed clock signal CKW1' to generate output signal Vout, wherein the delayed clock signal CKW1' is generated by delaying clock signal CKW1 using one or more delay elements. For example, refer to... Figure 6 When the delayed clock signal CKW1' has a high voltage level, the multiplexer 127 selects the sampled signal V7 as the output signal Vout; and when the delayed clock signal CKW1' has a low voltage level, the multiplexer 127 selects the sampled signal V8 as the output signal Vout.

[0050] Figures 4-6 The timing diagram shown represents an ideal case where the phases of multiple clock signals CKCDC, CKW1, and CKW2 are aligned. However, due to on-chip variation (OCV), the multiple clock signals CKCDC, CKW1, and CKW2 may not have proper phase, potentially causing errors in the output signal Vout. For example, refer to... Figure 7In an ideal scenario, the phase difference between clock signals CLCDC and CLW2 is 180 degrees of clock signal CK (i.e., 90 degrees of clock signal CKCDC / CKW2). However, the actual phase difference between CLCDC and CLW2 can fall into one of the following four categories (which may cause the physical interface 100 to output an incorrect output signal Vout): For category 1, the actual phase of clock signal CKW2 leads the ideal phase of CKW2, and this lead is between 0 and 180 degrees of clock signal CK (i.e., between 0 and 90 degrees of clock signal CKCDC / CKW2); for category 2, the actual phase of clock signal CKW2 lags. In the ideal case, the phase of clock signal CKW2 lags behind clock signal CK by 0 to -180 degrees (i.e., between 0 and -90 degrees) of clock signal CKCDC / CKW2. In case 3, the actual phase of clock signal CKW2 leads the ideal phase of clock signal CKW2 by more than 180 degrees (i.e., more than 90 degrees) of clock signal CKCDC / CKW2. In case 4, the actual phase of clock signal CKW2 lags behind the ideal phase of clock signal CKW2 by more than -180 degrees (i.e., more than -90 degrees) of clock signal CKCDC / CKW2. To address this issue, the present invention provides a training method to generate multiple control signals Vc1 and Vc2 to control the digital control delay line 126 and the multiplexer 128, respectively, to align the phases of clock signals CKCDC and CKW2.

[0051] Figure 8This is a flowchart of a training method for a clock signal generator 200 according to an embodiment of the present invention. In step 800, the process begins, and the control circuit 330 generates a control signal Vc1 to control the digital control delay line 126 to have an initial digital control code, wherein the initial digital control code can be 0 (i.e., the minimum delay of the digital control delay line 126). In step 802, the control circuit 330 determines whether the sampling result FLAG1 output by the D-type flip-flop 310 is equal to "1". If yes, the process proceeds to step 822; if no, the process proceeds to step 804. In step 804, the control circuit 330 generates a control signal Vc1 to increment the digital control code of the digital control delay line 126 by 1, thereby increasing the delay of the digital control delay line 126 to push the clock signal CKW2. In step 806, the control circuit 330 determines whether the sampling result FLAG1 output by the D-type flip-flop 310 is equal to "1". If yes, the process proceeds to step 808; if no, the process returns to step 804 to increment the digital control code of the digital control delay line 126 by 1, thereby further increasing the delay amount of the digital control delay line 126. In step 808, the control circuit 330 records the current digital control code as a first digital control code (i.e., Figure 8 (as shown in code1). In step 810, the control circuit 330 generates a control signal Vc1 to increment the digital control code of the digital control delay line 126 by 1, thereby increasing the delay of the digital control delay line 126. In step 812, the control circuit 330 determines whether the sampling result FLAG1 output by the D-type flip-flop 310 is equal to "0". If yes, the process proceeds to step 814; if no, the process returns to step 810 to increment the digital control code of the digital control delay line 126 by 1, thereby further increasing the delay of the digital control delay line 126. In step 814, the control circuit 330 records the current digital control code as a second digital control code (i.e., ...). Figure 8 As shown in code2), the control circuit 330 further calculates a one-cycle-code (i.e., one-cycle-code = code2 – code1) by subtracting the first digital control code from the second digital control code. In this embodiment, the one-cycle-code corresponds to 360 degrees of the clock signal CK or 180 degrees of the clock signal CKCDC / CKW2. At this time, the control circuit 330 can generate a control signal Vc1 to control the digital control delay line 126 to have the initial digital control code.

[0052] In step 816, the control circuit 330 determines whether the first digital control code is greater than half of the one-cycle code. If yes, the process proceeds to step 818; otherwise, the process proceeds to step 820. In step 818, the control circuit 330 determines whether the clock signal CKW2 belongs to... Figure 7 In Case 2 shown, the control circuit 330 can generate a control signal Vc1 to set the digital control delay line 126 using a final digital control code. This final digital control code is obtained by subtracting half of the one-cycle-code from the first digital control code (i.e., the final digital control code equals "code1 – one-cycle-code / 2"). Furthermore, the control circuit 330 generates a control signal Vc2 to control the multiplexer 128 to select the upper path (i.e., select the delayed clock signal output by the digital control delay line 126) to generate the clock signal CKW2. In step 820, the control circuit 330 determines that the clock signal CKW2 belongs to... Figure 7 As shown in Case 1, the control circuit 330 can generate a control signal Vc1 to set the digital control delay line 126 using a final digital control code, wherein the final digital control code is obtained by adding half of the one-cycle-code to the first digital control code (that is, the final digital control code is equal to "code1+one-cycle-code / 2"). In addition, the control circuit 330 generates a control signal Vc2 to control the multiplexer 128 to select the lower path (that is, select the inverted delayed clock signal output by the inverter 130) to generate the clock signal CKW2.

[0053] In step 822, the control circuit 330 generates a control signal Vc1 to increment the digital control code of the digital control delay line 126 by 1, thereby increasing the delay of the digital control delay line 126 to drive the clock signal CKW2. In step 824, the control circuit 330 determines whether the sampling result FLAG1 output by the D-type flip-flop 310 is equal to "0". If yes, the process proceeds to step 826; if no, the process returns to step 822 to increment the digital control code of the digital control delay line 126 by 1 again, thereby increasing the delay of the digital control delay line 126. In step 826, the control circuit 330 records the current digital control code as a first digital control code (i.e., Figure 8(as shown in code1). In step 828, the control circuit 330 generates a control signal Vc1 to increment the digital control code of the digital control delay line 126 by 1, thereby increasing the delay of the digital control delay line 126. In step 830, the control circuit 330 determines whether the sampling result FLAG1 output by the D-type flip-flop 310 is equal to "1". If yes, the process proceeds to step 832; if no, the process returns to step 828 to increment the digital control code of the digital control delay line 126 by 1 again, thereby increasing the delay of the digital control delay line 126. In step 832, the control circuit 330 records the current digital control code as a second digital control code (i.e., ...). Figure 8 As shown in code2), the control circuit 330 further calculates a one-cycle-code (i.e., one-cycle-code = code2 – code1) by subtracting the first digital control code from the second digital control code. In this embodiment, the one-cycle-code corresponds to 360 degrees of the clock signal CK or 180 degrees of the clock signal CKCDC / CKW2. At this time, the control circuit 330 can generate a control signal Vc1 to control the digital control delay line 126 to have the initial digital control code.

[0054] In step 834, the control circuit 330 determines whether the first digital control code is greater than half of the one-cycle code. If yes, the process proceeds to step 836; otherwise, the process proceeds to step 838. In step 836, the control circuit 330 determines whether the clock signal CKW2 belongs to... Figure 7 As shown in Case 3, the control circuit 330 can generate a control signal Vc1 to set the digital control delay line 126 using a final digital control code. This final digital control code is obtained by subtracting half of the one-cycle-code from the first digital control code (i.e., the final digital control code equals "code1 – one-cycle-code / 2"). Furthermore, the control circuit 330 generates a control signal Vc2 to control the multiplexer 128 to select the lower path (i.e., select the inverted delayed clock signal output by the inverter 130) to generate the clock signal CKW2. In step 838, the control circuit 330 determines that the clock signal CKW2 belongs to... Figure 7As shown in Case 4, the control circuit 330 can generate a control signal Vc1 to set the digital control delay line 126 using a final digital control code, wherein the final digital control code is obtained by adding half of the one-cycle-code to the first digital control code (that is, the final digital control code is equal to "code1+one-cycle-code / 2"). In addition, the control circuit 330 generates a control signal Vc2 to control the multiplexer 128 to select the upper path (that is, select the delayed clock signal output by the digital control delay line 126) to generate the clock signal CKW2.

[0055] By utilizing Figure 8 The training method flowchart shown can control the phase of clock signal CKW2 to approximate the phase of clock signal CKW2 in the ideal case. Therefore, clock signals CKCDC and CKW2 can have good timing margins and reduce the static skew between clock signals CKCDC and CKW2.

[0056] It should be noted that, Figure 8 The detailed operations shown are for illustrative purposes only, and the invention is not limited thereto. Specifically, as long as the control circuit 330 can generate a control signal Vc1 to control the second path with different delay amounts, such that multiple sampling results FLAG1 corresponding to the different delay amounts of the second path can be generated, and the control circuit 330 can refer to the multiple sampling results FLAG1 to determine a final digital control code (which is used to determine the most suitable delay amount for the second path), then the scope of the invention is not limited to this. Figure 8 The detailed calculations are shown below.

[0057] In addition, regarding the phases of clock signals CKW2 and CKW1, refer to Figure 9 In an ideal scenario, the falling edge of clock signal CKW1 is aligned with the falling edge of clock signal CKW2. In practice, the phase difference between clock signals CKW1 and CKW2 can fall into two categories: in case 5, clock signal CKW1 lags behind clock signal CKW2; and in case 6, clock signal CKW1 leads clock signal CKW2. These two cases may cause the physical interface 100 to generate an incorrect output signal Vout. To address this issue, the present invention provides another training method to generate a control signal Vc3 to control the digital control delay line 134 to align the phases of clock signals CKW2 and CKW1.

[0058] Figure 10 This is a flowchart illustrating a training method for a clock signal generator 200 according to an embodiment of the present invention. It should be noted that... Figure 10 The training method shown is in Figure 8 The training method shown is then performed, that is, the phase alignment of clock signals CKW2 and CKW1 is performed after the phase alignment of clock signals CKW2 and CKCDC. In step 1000, the process begins, and control circuit 330 generates control signal Vc3 to control digital control delay line 134 to have an initial digital control code, wherein the initial digital control code can be 0 (i.e., the minimum delay of digital control delay line 134). In step 1002, control circuit 330 records the sampling result FLAG2 output by D-type flip-flop 320. In step 1004, control circuit 330 generates control signal Vc3 to increment the digital control code of digital control delay line 134 by 1 to increase the delay of digital control delay line 134, thereby driving clock signal CKW1. In step 1006, the control circuit 330 determines whether the sampling result FLAG2 output by the D-type flip-flop 320 has changed from "1" to "0". If yes, the process proceeds to step 1008; if no, the process returns to step 1004 to increment the digital control code of the digital control delay line 134 by 1, thereby further increasing the delay of the digital control delay line 134. In step 1008, the control circuit 330 records the current digital control code as a first digital control code (i.e., Figure 10 (Code 1 shown). In step 1010, the control circuit 330 generates a control signal Vc3 to increment the digital control code of the digital control delay line 134 by 1, thereby increasing the delay of the digital control delay line 134. In step 1012, the control circuit 330 determines whether the sampling result FLAG2 output by the D-type flip-flop 320 has changed from "1" to "0". If yes, the process proceeds to step 1014; if no, the process returns to step 1010 to increment the digital control code of the digital control delay line 134 by 1 again, thereby increasing the delay of the digital control delay line 134. In step 1014, the control circuit 330 records the current digital control code as a second digital control code (i.e., ...). Figure 10 As shown in code2), the control circuit 330 further calculates a one-cycle-code (i.e., one-cycle-code = code2 – code1) by subtracting the first digital control code from the second digital control code. In this embodiment, the one-cycle-code corresponds to 360 degrees of the clock signal CK / CKW1. At this time, the control circuit 330 can generate a control signal Vc3 to control the digital control delay line 134 to have the initial digital control code.

[0059] In step 1016, the control circuit 330 determines whether the first digital control code is greater than half of the one-cycle code. If yes, the process proceeds to step 1018; otherwise, the process proceeds to step 1020. In step 1018, the control circuit 330 determines whether the clock signal CKW1 belongs to... Figure 9 As shown in Case 6, the control circuit 330 can generate a control signal Vc3 to set the digital control delay line 134 using a final digital control code, wherein the final digital control code is obtained by subtracting half of the one-cycle-code from the first digital control code (i.e., the final digital control code equals "code1 – one-cycle-code / 2"). In step 1020, the control circuit 330 determines that the clock signal CKW1 belongs to... Figure 9 As shown in Case 5, the control circuit 330 can generate a control signal Vc3 to set the digital control delay line 134 using a final digital control code, wherein the final digital control code is obtained by adding half of the one-cycle-code to the first digital control code (that is, the final digital control code is equal to "code1+one-cycle-code / 2").

[0060] By utilizing Figure 10 The training method flowchart shown can control the phase of clock signal CKW1 to be close to the phase of clock signal CKW1 in the ideal case. Therefore, clock signals CKW2 and CKW1 can have good timing margin and reduce the static skew between clock signals CKW2 and CKW1.

[0061] It should be noted that, Figure 10 The detailed operations shown are for illustrative purposes only, and the present invention is not limited thereto. Specifically, as long as the control circuit 330 can generate a control signal Vc3 to control the third path to have different delay amounts, such that multiple sampling results FLAG2 corresponding to the different delay amounts of the third path can be generated, and the control circuit 330 can refer to the multiple sampling results FLAG2 to determine a final digital control code (which is used to determine the most suitable delay amount for the third path), then the scope of the present invention is not limited to... Figure 10 The detailed calculations are shown below.

[0062] In the above embodiments, the timing margin between multiple clock signals CKCDC, CKW2 and CKW1 can be improved without shifting the clock signal CKCDC in the digital domain, thus maintaining synchronization across multiple data physical circuits and multiple address physical circuits.

[0063] In summary, this invention designs a physical layer with multiple sampling circuits and multiplexers to process quarter-rate data using a first clock signal, a second clock signal, and a third clock signal corresponding to different clock domains. Furthermore, a training mechanism is designed to align the phases of the first, second, and third clock signals, which will have better timing margins to reduce static skew.

[0064] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A physical interface comprising: The first set of sampling circuits is used to sample multiple data using the first clock signal to generate multiple first sampled data. The second set of sampling circuits is used to sample the multiple first sampled data using the second clock signal to generate multiple second sampled data. A first multiplexer is configured to select one of a first signal and a second signal to generate a first multiplexer output signal, wherein the first signal and the second signal are obtained from a portion of the plurality of second sampled data; A second multiplexer is used to select one of the third signal and the fourth signal to generate a second multiplexer output signal, wherein the third signal and the fourth signal are obtained from another portion of the plurality of second sampled data; The third set of sampling circuits is used to sample the output signal of the first multiplexer and the output signal of the second multiplexer using the third clock signal respectively, so as to generate multiple third sampling data. as well as A third multiplexer is used to alternately select one of the multiple third sampled data to generate an output signal; The frequency of the first clock signal is half the frequency of the clock signal, the frequency of the second clock signal is half the frequency of the clock signal, and the frequency of the third clock signal is equal to the frequency of the clock signal.

2. The physical interface as described in claim 1, wherein the first group of sampling circuits includes four sampling circuits, the second group of sampling circuits includes four sampling circuits, and the plurality of second sampling data packets contain four sampling data entries; The first sampled data of the four sampled data is used as the first signal; The sampling circuit uses the second clock signal to sample the second sampled data of the four sampled data to generate the second signal; the third sampled data of the four sampled data serves as the third signal. And the fourth sample data is generated by sampling the four sample data using the second clock signal through another sampling circuit.

3. The physical interface as claimed in claim 1, wherein the third set of sampling circuits includes a first sampling circuit, a second sampling circuit, and a third sampling circuit; the first sampling circuit is used to sample the first multiplexer output signal using the third clock signal to generate one of the plurality of third sampling data; The second sampling circuit is used to sample the output signal of the second multiplexer using the third clock signal to generate a sampling result; The third sampling circuit is used to sample the sampling result using the third clock signal to generate another of the plurality of third sampled data.

4. The physical interface as described in claim 1, further comprising: A clock generator is used to receive the clock signal to generate the first clock signal, the second clock signal, and the third clock signal; The clock signal generator has a first path, a second path, and a third path; The first path is used to generate the first clock signal, the second path is used to generate the second clock signal, and the third path is used to generate the third clock signal.

5. The physical interface as described in claim 4, further comprising: A control circuit is used to generate a first control signal based on the phase information of the first clock signal and the second clock signal, so as to control the delay of the second path.

6. The physical interface as described in claim 5, further comprising: The first sampling circuit is used to sample the second clock signal using the first clock signal to generate a first sampling result; The control circuit generates the first control signal based on the first sampling result to control the delay amount of the second path.

7. The physical interface of claim 6, wherein the control circuit generates the first control signal to control the second path to have a plurality of different delays, such that the first sampling circuit generates a plurality of first sampling results corresponding to the plurality of different delays of the second path; and the control circuit refers to the plurality of first sampling results to determine a final digital control code for determining the delay of the second path.

8. The physical interface as claimed in claim 6, wherein the second path comprises: The delay line is controlled by the first control signal to generate a delayed clock signal; An inverter is used to receive the delayed clock signal and generate an inverted delayed clock signal; The fourth multiplexer is used to select one of the delayed clock signal and the inverted delayed clock signal to generate the second clock signal; The control circuit further generates a second control signal to control the fourth multiplexer, so as to select one of the delayed clock signal and the inverted delayed clock signal to generate the second clock signal.

9. The physical interface of claim 5, wherein the control circuit is further configured to generate a third control signal based on the phase information of the second clock signal and the third clock signal, so as to control the delay of the third path.

10. The physical interface as described in claim 9, further comprising: The second sampling circuit is used to sample the third clock signal using the second clock signal to generate a second sampling result; The control circuit generates the third control signal based on the second sampling result to control the delay amount of the third path.

11. The physical interface of claim 10, wherein the control circuit generates the third control signal to control the third path to have a plurality of different delays, such that the second sampling circuit generates a plurality of second sampling results corresponding to the plurality of different delays of the third path; and the control circuit refers to the plurality of second sampling results to determine a final digital control code for determining the delay of the third path.

12. The physical interface as claimed in claim 1, wherein the physical interface is applied to a double data rate synchronous dynamic random access memory.

13. A data processing method, comprising: Multiple data points are sampled using a first clock signal to generate multiple first sampled data points; The multiple first sampled data are sampled using a second clock signal to generate multiple second sampled data. One of a first signal and a second signal is selected to generate a first multiplexer output signal, wherein the first signal and the second signal are obtained from a portion of the plurality of second sampled data; One of the third signal and the fourth signal is selected to generate a second multiplexer output signal, wherein the third signal and the fourth signal are obtained from another portion of the plurality of second sampled data; The output signals of the first multiplexer and the second multiplexer are sampled using a third clock signal respectively to generate multiple third sampled data. as well as Alternately select one of the multiple third sampled data to generate the output signal; The frequency of the first clock signal is half the frequency of the clock signal, the frequency of the second clock signal is half the frequency of the clock signal, and the frequency of the third clock signal is equal to the frequency of the clock signal.

14. The data processing method as described in claim 13, further comprising: The clock signal is received using the first path of the clock generator in order to generate the first clock signal; The clock signal is received using the second path of the clock generator in order to generate the second clock signal; as well as The clock signal is received using the third path of the clock generator in order to generate the third clock signal.

15. The data processing method as described in claim 14, further comprising: A first control signal is generated based on the phase information between the first clock signal and the second clock signal to control the delay of the second path.

16. The data processing method as described in claim 15, further comprising: The first clock signal is used to sample the second clock signal to generate a first sampling result; The step of generating the first control signal based on the phase information between the first clock signal and the second clock signal to control the delay amount of the second path includes: The first control signal is generated based on the first sampling result to control the delay amount of the second path.

17. The data processing method of claim 16, wherein the step of generating the first control signal based on the first sampling result to control the delay amount of the second path comprises: The first control signal is generated to control the second path to have multiple different delay amounts; The first clock signal is used to sample the second clock signal to generate multiple first sampling results corresponding to the multiple different delay amounts of the second path; as well as The final digital control code used to determine the delay amount for the second path is determined by referring to the multiple first sampling results.

18. The data processing method of claim 16, wherein the step of receiving the clock signal using the second path of the clock generator to generate the second clock signal comprises: A delayed clock signal is generated using a delay line controlled by the first control signal; An inverter is used to receive the delayed clock signal in order to generate an inverted delayed clock signal; as well as A second control signal is generated to select one of the delayed clock signal and the inverted delayed clock signal to generate the second clock signal.

19. The data processing method as described in claim 15, further comprising: A third control signal is generated based on the phase information of the second clock signal and the third clock signal to control the delay of the third path.

20. The data processing method as described in claim 19, further comprising: The second clock signal is used to sample the third clock signal to generate a second sampling result; The step of generating the third control signal based on the phase information of the second clock signal and the third clock signal to control the delay amount of the third path includes: The third control signal is generated based on the second sampling result to control the delay amount of the third path.

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