Conversions between signal constellations

Abstract

Accordingly, disclosed herein are receivers and receiving methods that provide superior conversion from PAM2 to PAM4 signaling. One illustrative method includes negotiating a link speed with PAM4 signaling, performing adaptation of at least one of a gain or a filter coefficient during PAM2 signaling, switching to PAM4 detection prior to receiving PAM4 signaling, disabling the adaptation prior to the switching to PAM4 detection, detecting PAM4 signaling using at least one statistic of detected PAM4 symbols, and enabling the adaptation after detecting PAM4 signaling. Another illustrative method includes negotiating a link speed with PAM4 signaling, adapting at least one of a gain and a filter coefficient during PAM2 signaling, monitoring for a change in at least one signal characteristic while performing PAM2 detection, and transitioning to PAM4 detection after detecting the change.

Description

Technical Field

[0001] This disclosure relates to digital communication receivers, and more particularly, to a channel symbol detection method that facilitates the transition between 2-level and 4-level pulse amplitude modulation. Background Technology

[0002] Various standards have been developed to support the need for faster and larger data transfers between devices. Fibre Channel, a standard established by the International Council for Information Technology Standards (INCITS) for use in Storage Area Networks (SANs), provides data transfer rates that have roughly doubled every three years since 1993. One consequence of this evolution is that various devices in a given network may adopt multiple generations of standards. To enable incremental upgrades to network hardware, the Fibre Channel standard recommends that each device should provide backward compatibility with up to three generations of standards and specifies a mechanism for Link Speed ​​Negotiation (LSN) methods that linked devices can use to determine the highest speed supported by two devices on the link.

[0003] The Link Training (LT) phase, following the LSN phase, enables the transmitter and receiver to optimize their equalization filters, decision thresholds, and clock timing for the negotiated signaling rate and constellation. For Fibre Channel standards supporting 4-level Pulse Amplitude Modulation (PAM4), the LT phase involves a conversion from 2-level Pulse Amplitude Modulation (PAM2, also known as NRZ modulation) to PAM4. This conversion can amplify timing jitter, impair adaptation, and excessively delay or prevent the completion of the LT phase for various reasons, including adaptation gain control located early in the receiver chain. Summary of the Invention

[0004] Therefore, this document discloses a receiver and receiving method that provide excellent conversion from PAM2 to PAM4 signaling. An illustrative method includes: negotiating a link speed with PAM4 signaling; performing an adaptation of at least one gain or filter coefficient during PAM2 signaling; switching to PAM4 detection before receiving PAM4 signaling; disabling the adaptation before saying the switch to PAM4 detection; detecting PAM4 signaling using at least one statistic of detected PAM4 symbols; and enabling the adaptation after detecting PAM4 signaling.

[0005] Another illustrative method includes: negotiating a link speed with PAM4 signaling; adapting at least one of gain and filter coefficients during PAM2 signaling; monitoring for changes in at least one signal characteristic while performing PAM2 detection; and switching to PAM4 detection after detecting said change.

[0006] An illustrative receiver for performing the above methods is also disclosed. Each of the foregoing implementations may be combined with any one or more of the following optional features: 1. Switching to PAM4 detection includes using an adjusted PAM4 detection value that causes PAM2 symbols to be detected only as external PAM4 symbols. 2. The adjusted PAM4 detection value is scaled from a nominal PAM4 detection value by a factor of approximately 0.8. 3. The at least one statistic is the rate or count of detected internal PAM4 symbols. 4. The detection includes determining when the rate or count exceeds a predetermined value. 5. Before switching to PAM4 detection, the bandwidth of the clock recovery loop is reduced. 6. After PAM4 signaling is detected, the bandwidth of the clock recovery loop is restored. 7. The detected PAM4 symbols are retransmitted as PAM2 symbols until PAM4 signaling is detected. 8. The at least one signal characteristic is a probability distribution of equalization error. 9. The at least one signal characteristic is a range of equalization error. 10. The at least one signal characteristic is the probability distribution of the equalization signal. 11. The at least one signal characteristic is the range of the equalization signal. Attached Figure Description

[0007] Figure 1A This is a block diagram illustrating a switch.

[0008] Figure 1B This is a block diagram illustrating the ports of a switch.

[0009] Figure 1C This is a block diagram of an illustrative decision feedback equalizer (DFE).

[0010] Figure 1D This is a block diagram illustrating the clock recovery module.

[0011] Figure 2 This is a diagram illustrating the "expanded" DFE.

[0012] Figure 3 (A) is an illustrative PAM2 (aka NRZ module) eye diagram with optimized PAM2 detection values.

[0013] Figure 3 (B) is an illustrative PAM4 eye diagram with optimized PAM4 detection values.

[0014] Figure 3 (C) is an illustrative PAM4 eye diagram with PAM2 detection values.

[0015] Figure 3 (D) is an illustrative PAM2 eye diagram with optimized PAM4 detection values.

[0016] Figure 3(E) is an illustrative PAM2 eye diagram with adjusted PAM4 detection values.

[0017] Figure 3 (F) is an illustrative PAM4 eye diagram with adjusted PAM4 detection values.

[0018] Figure 4 This is an illustrative probability distribution diagram of the PAM2 equalization error.

[0019] Figure 5 This is a flowchart of the first illustrative signal constellation conversion method.

[0020] Figure 6 This is a flowchart of the second illustrative signal constellation conversion method. Detailed Implementation

[0021] Although specific embodiments are given in the accompanying drawings and the following description, please remember that they do not limit this disclosure. Rather, they provide a basis for those skilled in the art to identify alternatives, equivalents, and modifications that fall within the scope of the appended claims.

[0022] For background purposes, Figure 1A An illustrative switch 102 is shown. (As used herein, the term "switch" includes not only conventional network switches but also routers, bridges, hubs, and other devices that forward network communication packets between ports.) The illustrative switch 102 includes an application-specific integrated circuit (ASIC) 104 that implements packet switching functionality. The ASIC 104 receives and transmits network communication packets via port connectors 105. Port connectors 105 are directly or indirectly coupled to cable connectors 108.

[0023] Pluggable module 106 is typically used to couple between port connector 105 and cable connector 108 to improve communication performance through equalization and optional format conversion (e.g., conversion between electrical and optical signals). Pluggable module 106 may conform to any of the various pluggable module standards including SFP, SFP-DD, QSFP, QSFP-DD, and OSFP.

[0024] Each of the pluggable modules 106 may include a data recovery and remodulation (DRR) chip 110 and a microcontroller chip 112, the microcontroller chip 112 controlling the operation of the DRR chip 110 according to firmware and parameters stored in non-volatile memory 114. The operating modes and parameters of the pluggable module 106 can be set via a two-wire bus (such as I2C or MDIO) connecting the microcontroller chip 112 to a host device (e.g., a switch 102). The microcontroller chip 112 responds to queries and commands received via the two-wire bus, and accordingly retrieves information from and saves the information to the control register 116 of the DRR chip 110.

[0025] DRR chip 110 includes host-side transceiver 120 coupled to line-side transceiver 122 via first-in-first-out (FIFO) buffer 124. Figure 1A Optional photoelectric emitter (PE) and photodetector (PD) elements are shown for switching between optical line-side and electrical line-side signals. Although the figures show only a single channel for the DRR chip transceiver, the transceiver can support multiple channels transmitted via multiple corresponding optical fibers or electrical conductors. Controller 118 coordinates the operation of the transceiver according to the contents of the control register and can provide multiple communication phases according to communication standards such as the Fibre Channel standard published by the National Institute of Information Technology Standards Certification Standards (INCITS), providing phases for Link Speed ​​Negotiation (LSN), Link Training (LT), and Normal Operation.

[0026] Figure 1B An example of a component comprising a transmit (outgoing) and receive (ingoing) chain of a switch port, including pluggable module 106, is shown. While function blocks are used herein to illustrate and describe components, it should be understood that these blocks represent integrated circuit modules that are found in academic literature and are commercially available in component libraries of various ASIC design software packages and / or can be implemented as firmware executable by a programmable controller or processing unit.

[0027] For each channel, the switch ASIC provides a transmit buffer 130 to buffer digital transmit data, which is typically received in the form of bit blocks or multi-bit symbols. In this example, a parallel-to-serial converter 132 accesses the buffer to generate a serialized stream of NRZ (Non-Return-to-Zero) or PAM4 (4-Level Pulse Amplitude Modulation) symbols. Other example implementations may generate channel-coded bit streams or other symbol streams. The symbol streams preferably conform to standard protocols, such as the Fibre Channel standard transmission protocol, which includes transmit words and ordered sets (modes for special functions such as delimited frames and aligned channels).

[0028] An optional finite impulse response (FIR) filter 134 can be used to provide pre-emphasis on high-frequency components to counteract attenuation from the short-range link 138. A digital-to-analog converter (DAC) converts the filtered signal into analog form, and a driver 136 provides sufficient current to transmit the transmitted signal across the short-range link 138 to the pluggable module 106. The short-range link 138 primarily comprises conductive printed circuit board traces coupling the switch ASIC to the DRR chip 110 via port connector 105. Although these traces may be limited, for example, to less than 500 mm, they can still cause significant frequency-dependent attenuation and dispersion within the upper limit of the signal frequencies conceived herein.

[0029] In the pluggable module 106, a continuous-time linear equalizer (CTLE) filter 140 cooperates with an optional FIR filter 134 to compensate for the effects of the short-distance link 138. A clock and data recovery (CDR) module 141 operates on the filtered signal to derive a clock signal for sampling and re-digitizing the digital symbol stream. An optional FIFO buffer 142 receives the digital symbol stream from the CDR module. An optional pre-equalizer 143 operates on the digital symbol stream to at least partially compensate for line-side channel effects. A DAC 144 converts the pre-equalized signal into an analog signal, which is amplified by a driver 145 for the photoelectric transmitter to drive the photoelectric transmitter 146. An optical fiber connector 148 couples the optical signal from the photoelectric transmitter into an optical fiber for transmission to a remote photodetector and receiver.

[0030] Here we note that, in addition to the necessary power consumption of the pre-equalizer 143 itself, pre-equalization typically increases signal energy in the frequency ranges where channel signal attenuation is highest, thereby increasing signal energy dissipation within the channel. However, for the envisioned channel, this increased power consumption is small compared to the achievable power savings resulting from the reduction in receiver complexity, especially compared to the power savings achievable through equalizer design.

[0031] In the pluggable module 106, fiber optic connector 148 further couples the optical fiber to an associated photodetector 150, which converts the received optical signal into an electrical form, typically a received signal current that can be converted into a received signal voltage by a transimpedance amplifier (TIA). Gain control amplifier 151 applies adjustable gain to optimize the received signal range for processing by subsequent components in the receiver chain. CTLE filter 152 provides anti-aliasing and optional spectral shaping before signal digitization via analog-to-digital converter 153. Digital equalizer 154 provides adaptive equalization, thus cooperating with a remote pre-equalizer to compensate for channel effects. CDR module 155 derives the sampling clock signal and recovers the received symbol stream from the equalized signal. Optional FIFO buffer 156 receives the digital received symbol stream from CDR module 155.

[0032] The pluggable module 106 further includes an optional FIR filter 157 to provide pre-emphasis on high-frequency components to counteract attenuation from the short-range link 160. A digital-to-analog converter (DAC) converts the filtered signal into analog form, and a driver 158 provides sufficient current to transmit the transmitted signal to the ASIC 104 across the short-range link 160, wherein a CTLE filter 162 cooperates with the optional FIR filter 157 to compensate for the effects of the short-range link 160. A clock and data recovery (CDR) module 164 operates on the filtered signal to derive a sampling clock signal for recovering the received symbol stream. A serial-to-parallel converter 166 stores blocks of the received symbol stream in a receive buffer 168, allowing the core circuitry of the ASIC 104 to use a lower clock rate.

[0033] The pluggable module 106 further includes a training control module 159 to accommodate the coefficients of the pre-equalizer module 143 and the equalizer 154. The training control module 159 can generate a sequence of training frames replacing the transmitted data stream during the duration of the link speed negotiation and link speed training phases, and can detect equalization errors associated with the training frame symbols in the received data stream. By combining the equalization errors with the training frame symbols, the training controller 159 can adapt the coefficients of the remote pre-equalizer and the local equalizer 154 to optimize their combined compensation for the combined receive channel effects. The training controller 159 can communicate remote pre-equalizer coefficient updates via various reverse channel options that include, for example, dedicated fields in the training frames of the transmitted symbol stream. Accordingly, the training controller 159 can extract updates for the local pre-equalizer 143 from dedicated fields in the frames of the received symbol stream. For further details on an illustrative example, see, for example, commonly owned U.S. Patent 10,212,260, “SerDes Architecture with a Hidden Backchannel Protocol,” which is incorporated herein by reference.

[0034] To gain a better understanding of the situation, Figure 1C and Figure 1D Additional details regarding the illustrative implementation of equalizer 154 and CDR module 155 are provided. Figure 1C In this configuration, a digital feedforward equalizer (FFE) filter 170 (shown as "front-end filter 170") filters the digitized received signal to reduce leading intersymbol interference. Adder 172 combines the filtered received signal with the feedback signal to provide an equalization signal to decision element 174. Decision element 174 uses an array of comparators 176 to determine which channel symbol the equalization signal is most likely to represent. The comparator outputs can optionally be converted into binary symbol decisions by digitizer 178. Alternatively, the comparator outputs can be used as a thermometer-coded representation of the symbol decisions.

[0035] Feedback filter (FBF) 180 uses a chain of delay elements 182 with corresponding multipliers 184 and adders 186 to convert the symbol decision from decision element 174 into a feedback signal that corrects trailing intersymbol interference in the filtered received signal. This equalization and detection arrangement is called decision feedback equalization (DFE), and it produces the symbol decision stream. Some receiver variants employ oversampling in both FFE 170 and FBF 180.

[0036] Figure 1D An illustrative implementation of the timing recovery loop is shown. ADC 153 samples the analog received signal 188 using sampling clock 195 and provides the digital received signal to equalizer 170 (which may be a DFE, FFE filter, or some other form of equalizer as described above). Decision element 174 converts the equalized signal into a digital received symbol stream 189.

[0037] Timing error unit 190 uses any suitable design for a timing error estimator, including, for example, a “bang-bang” or proportional phase detector, to derive the timing error signal 191. A suitable timing error estimator is described in co-owned patent US10,447,509, “Precompensator-based quantization for clock recovery,” which is incorporated herein by reference in its entirety. Other potentially suitable timing error estimators can be found in published literature, including, for example, Mueller’s “Timing Recovery in Digital Synchronous Data Receivers” (IEEE Communications Journal, May 1976, Vol. 24, No. 5) and Musa’s “High-speed Baud-Rate Clock Recovery” (University of Toronto paper, 2008).

[0038] The sampling clock signal can optionally be derived from a reference clock signal provided by a reference oscillator 192 using a phase-locked loop (PLL) 193. A phase interpolator 194 operates on the PLL clock signal to correct phase and frequency offsets in the sampled "clock" signal 195. A timing error signal 191 is used to control the phase interpolator 194 in a manner that statistically minimizes the energy of the timing error signal. In the first feedback path, the timing error signal is expressed with a phase coefficient (K... P The timing error signal is scaled and integrated by the phase error accumulator 196 to obtain a phase error signal, which is provided as a control signal to the phase interpolator 194. In the second feedback path, the timing error signal is expressed with a frequency coefficient (K). F The frequency offset signal is scaled and integrated by the frequency error accumulator 197. The adder 198 adds the frequency offset signal to the scaled timing error signal and provides the sum to the phase error accumulator 196 to correct the offset.

[0039] Figure 2An alternative receiver implementation with additional implementation details is shown. In this alternative implementation, the decision element 174 is replaced by a pre-compensation unit 202, which employs a threshold S0-S L-1 Additional comparator 176, the threshold S0-S L-1 The circuit has been adjusted to presuppose each possible feedback signal value. The digitizer 178 optionally converts the comparator output into a set of provisional symbol decisions 208. The multiplexer 210 selects the appropriate one of the provisional decisions based on previous symbol decisions stored in delay elements 212, 213. As described in commonly owned patent US11,018,656 (“Multi-function level finder for SerDes”, published 2021-05-25, and incorporated herein by reference), this arrangement eliminates the feedback filter, thereby enabling operation at higher baud rates.

[0040] Multi-functional level detection is enhanced Figure 2 The operation of DFE in the code, and will also be applicable to DFE operations in the code. Figure 1C This implementation is used in conjunction with other equalizer types. The multi-function level detector shown is a dual-level detector 216 with an input multiplexer 218 and an output demultiplexer 222. Based on the mode selection signal, the input multiplexer 218 selects one of multiple signals from different levels of the equalizer. Figure 2 In this context, these signals are the received signal, the limiter input signal, and the error signal, but may further or alternatively include signals from other stages of the equalizer. The received signal is the output of the FFE filter 170, the limiter input signal is the received signal modified by the FFE filter 170 (and by the output of the feedback filter, if present), and the error signal is the difference between the limiter input signal and the corresponding output symbol decision. The adder 220 may include an appropriate delay of the limiter input signal to ensure that the error is correctly determined.

[0041] As will become clear from U.S. Patent 11,018,656 (“Multi-function level finder for SerDes”), a level detector employs an asymmetric step size adapter controller to find a threshold at which the cumulative probability distribution function (CDF) of a selected signal reaches a given value. A dual-level detector enables the simultaneous determination of two such thresholds. Dual-level detector 216 operates on a selected signal using input parameters (step size, eye edge and / or ISI selection, accumulator initialization, and symbol decision) to measure the correspondingly adjusted signal level. Among other things, the dual-level detector output can represent the range of received signals, the size of a selected eye opening, or an error distribution measurement. These levels can be determined conditionally (e.g., measured only for a specific symbol decision value or pattern) or unconditionally (i.e., measured without considering symbol decision or pattern).

[0042] As an example, a dual-level detector can determine the range of equalization errors for any given symbol decision value. To determine the range of equalization errors, a mode selection signal causes multiplexer 218 to forward an error signal to dual-level detector 216. The dual-level detector is programmed to find a first threshold and a second threshold, at which the signal CDF is, for example, 1 / 128 (meaning the received signal exhibits only about a 0.78% probability of falling below that threshold), and at the second threshold, the signal CDF is, for example, 127 / 128 (meaning the signal exceeds the threshold only about 0.78% of the time). These two thresholds then represent the range of signals where the signal can be found 98% of the time. The thresholds are forwarded by demultiplexer 222 to appropriate registers and can be used by controller 118 or training controller 159 to perform adaptation gain control and / or detection of signal constellation transitions, as will be further described below.

[0043] Building upon the preceding illustrative implementation, we now turn to the Link Speed ​​Negotiation (LSN) phase for establishing Fibre Channel links between link partners, such as switches or other host devices, that conform to different generations of Fibre Channel standards. According to this standard, the LSN phase involves each link partner's transmitter sending a training signal at a progressively decreasing baud rate until the receiver determines that the signal can be satisfactorily received and notifies the transmitter accordingly. In itself, the receiver iterates between its supported baud rates to test if any baud rate matches the currently transmitted training signal. PAM2 (NRZ) signaling is used during the LSN phase, but link partners may agree to use PAM4 signaling for subsequent communications.

[0044] Once both ends of the link agree on the baud rate and signal constellation (PAM2, PAM4), the LSN phase ends. Afterward, the Fibre Channel standard provides a Link Training (LT) phase, during which training patterns are transmitted to allow the link partner to adaptively optimize its gain settings and filter coefficients. For Fibre Channel standards that support PAM4, the LT phase includes a conversion from PAM2 to PAM4. If this conversion is not handled properly, the receiver may not be able to complete the LT phase in PAM4 and will therefore be forced to use the Fibre Channel standard with a reduced data transmission rate.

[0045] Figure 3 (A) is an illustrative PAM2 eye diagram with optimized PAM2 detection values. The right side of each eye diagram represents the potential equalization signal value at the current decision time Y(i), while the left side represents the potential signal value at the previous decision time Y(i-1). The eye diagram is generated by superimposing many symbol intervals to observe the changes associated with all possible transitions between adjacent symbols. Thicker areas generally represent larger changes typically attributed to nonlinearity, noise, and / or jitter. Adaptation of filter coefficients and gain optimizes the alignment of the equalization signal with the target value at the decision time. (For consistency with PAM4, the outermost target value is shown here as T.) -3 (T3.) To minimize the error probability, the optimal limiter threshold S0 is located in the middle between the inner edges of the eye opening.

[0046] Figure 3 (B)B (on the right side of the page) is an illustrative PAM4 eye diagram with optimized PAM4 detection values. Typically, the receiver amplifier (e.g., a photodetector with transimpedance amplifiers) will automatically adjust its gain to maintain the average signal power at a constant level. This gain control strategy results in the amplitude of the outermost PAM4 signal being approximately 34% larger than the PAM2 signal amplitude. Accordingly, the associated receiver will need to quickly adapt the receiver gain, or equivalently, adjust the outermost PAM4 target value T. -3 T3 is adjusted to 1.34 times the PAM2 signal amplitude. For this example, the receiver gain remains constant. The innermost target value T... -1 T1 is the outermost target value T -3 One-third of the amplitude of T3. Limiter threshold S -2 S2 is nominally 2 / 3 of the outermost target value, while the limiter threshold is nominally 0. In practice, the limiter threshold is adjusted to a midpoint between the eye edges to minimize the probability of error.

[0047] During the LT phase, a receiver expecting to transition from PAM2 signaling to PAM4 signaling can (1) continue operating in PAM2 detection mode until PAM4 signaling is detected, or (2) begin operating in PAM4 detection mode while still receiving PAM2 signaling. In either case, there will be a period of mismatch between the eye diagram and the threshold and target value of the limiter used.

[0048] Figure 3 (C) illustrates the mismatch that occurs in the first option scenario, where an illustrative PAM4 eye diagram is received when the receiver is operating in PAM2 detection mode. The signal value at the current decision time differs from the target value T. -3 The T3 and T3 are fundamentally different. This is for reference only. Figure 4 The equalization error (the difference between the equalization signal and the target value) of T3 changes from a unimodal distribution 402 to a bimodal distribution 404. Note that the median equalization error is no longer zero, thus posing a potential problem for time-limited recovery.

[0049] However, the dual-level detector described above can be used to detect changes in the equalization error distribution or, alternatively, changes in the signal range. For example, when PAM4 signaling begins, the T3 equalization error range detected using the 1 / 128 and 127 / 128 CDF levels distributed in the attached figure will rapidly increase from ~20% to approximately ~110%. The receiver can use this change to detect the arrival of PAM4 signaling, thereby triggering a signal with... Figure 3 (B) shows the appropriate limiter threshold and target value changes in the PAM4 detection mode. To accelerate subsequent training, level detector measurements can be used to set the initial values ​​for the limiter threshold and target.

[0050] Figure 3 (D) illustrates the mismatch that occurs in the second option scenario, where illustrative PAM4 detection values ​​are applied to the PAM2 eye diagram. Unfortunately, the expected limiter threshold S... -2 S2 is almost aligned with the amplitudes of the upper and lower PAM2 signals, indicating the equilibrium position of these thresholds. This limiter position will cause erroneous detection of PAM4 symbols from the PAM2 eye diagram, even with a more unbalanced equilibrium error distribution than before, potentially amplifying timing jitter to levels that could force decision timing into the transition region and prolong or prevent successful training. Therefore, this approach is undesirable if attempted with ideal or expected PAM4 detection values.

[0051] A better approach is to use adjusted PAM4 detection values, such as Figure 3Those shown in (E). In this example, the expected PAM4 detection value has been scaled by 0.8. Taking the nominal value of the PAM2 target value as A, the scaled PAM4 detection value in this example is T. -3 =-1.07A,S -2 =-0.72A,T -1 = -0.36A, S0 = 0, T1 = 0.36A, S2 = 0.72A, and T3 = 1.07A. Although the scaling factor can vary, the selected value preferably balances the uniform error distribution of PAM2 and PAM4 signaling, and sets the limiter threshold S at the beginning of PAM4 signaling. -2 S2 remains comfortably positioned within the correct eye. During PAM2 signaling, the receiver using the adjusted PAM4 detection value detects only the channel symbols. + 3. For example Figure 3 As shown in (F), once the PAM4 signaling begins with the adjusted PAM4 detection value, the receiver correctly detects all four channel symbols. + 1. + 3. This allows for rapid conversion detection and facilitates successful training of PAM4 signals. From Figure 3 The detection level in (F) to Figure 3 The level transition in (B) can be achieved through simple adjustments, or it can be accelerated using an initial value determined based on the level detector measurements.

[0052] Figure 5 This is a flowchart of a first illustrative signal constellation conversion method that can be implemented by a host, chip controller 118, training controller 159, or any combination thereof. The method begins at block 502, where the LSN phase is performed when a link connection is initiated. As part of the LSN phase, the controller determines the highest baud rate and maximum signal constellation supported by the link partner and coordinates with the remote controller in block 504 to begin operation at that baud rate. In block 506, the LT phase begins by exchanging PAM2 training patterns at both ends of the link and adapting their filter coefficients and gain settings to optimize performance.

[0053] In block 508, the controller checks whether the PAM4 signal constellation was determined to be mutually supportive in block 504, and if not, ends the LT phase. Otherwise, the controller determines that the signal constellation transition is expected and proceeds to block 510.

[0054] In block 510, the controller configures the transmitter to begin transmitting the PAM4 training pattern, but retains the PAM2 detection values ​​for reception. The level detector is configured to monitor received signal statistics, such as signal range (conditional or unconditional), equalization error range (conditional or unconditional), or other signal characteristics such as the peak value of the probability distribution. In block 512, the controller periodically determines whether the signal statistics exhibit some change indicating that PAM4 signaling is being received. Control returns to block 510 until such a change is detected.

[0055] Once a PAM4 signaling is received, in block 514, the controller preferably determines an initial PAM4 detection value based on level detector measurements. As an example, the controller determines the entire signal range and sets an initial target value T at the upper and lower limits of the entire signal range. -3 T3, where S0 is set at the midpoint, S -2 S2 is set between S0 and T -3 At 2 / 3 of the distance between T1 and T2, and T -1 T1 is set at S0 and T -3 At the 1 / 3 mark between T3 and T4. In box 516, the receiver then uses the PAM4 detection value as the starting point for PAM4 link training. As an alternative to using a preset ratio, the controller averages the filtered signal values ​​associated with the selected signal pattern to eliminate the post-ISI effect.

[0056] In the filter coefficient f1 (see...) Figure 1C When ) is non-zero, the decision is made by comparing it with the code element [A]. k A k-1 The correlated filtered signal values ​​are averaged to eliminate the associated post-ISI effect, where A k-1 The values ​​are 3 and -3. The target value T3 is then the average of the filtered signal values ​​associated with [3,3] and [3,-3]. (Many such values ​​can be included in the average to combat noise.) The target value T1 is the average of the filtered signal values ​​associated with [1.3]. Target value T -1 T -3 It can be similarly determined or taken as a negative of the T1 and T3 values. The limiter value can initially be located in the middle between the appropriate target values.

[0057] The above method is expected to be robust, but unavoidable delays may occur due to the statistics of the measured signal. In contrast, Figure 6 The method shown, while potentially more complex, may facilitate faster detection of PAM4 signals. (Boxes 502-508) Figure 5The method is the same. Once the controller determines that the signal constellation transition is expected, the adaptation of gain and filter coefficients is disabled in block 610 to prevent misfit due to the unbalanced distribution of equalization errors.

[0058] In block 612, the receiver can optionally add clock recovery robustness to enhance its resistance to increased equalization error energy, when... Figure 3 When PAM4 detection is used for a PAM2 signal, as shown in (E), the increased equalization error may lead to potential synchronization loss. Robustness can be increased, for example, by reducing the bandwidth of the timing recovery loop. Alternatively, the receiver can be configured to use a different timing error estimation strategy, which is expected to perform better during this transition phase.

[0059] In box 614, the controller configures the decision element to use an adjusted PAM4 detection threshold, as previously combined. Figure 3 As discussed in (E). In block 616, the line-side transmitter is configured to begin transmitting a PAM4 training pattern, while an adjusted PAM4 detection threshold is used for reception. Although the DRR chip employs PAM4 detection for the line-side receiver, the channel symbols retransmitted by the host-side transmitter are preferably limited to PAM2 symbols until PAM4 signaling is detected.

[0060] Due to the limiter threshold S -2 S2 is comfortably positioned within the amplitude of the external PAM2 signal, therefore the receiver is expected to detect only... + 3-channel symbols, until PAM4 signal is received ( Figure 3 (F)), at this time half of the detected channel symbols are expected to be + 3, while the remaining half is expected to be + Channel 1 symbol. Therefore, the receiver can detect the signal in box 616. + One symbol is used for counting to detect the start of PAM4 signaling. Once a predetermined number (e.g., 16) are received... + If 1 symbol is received, the receiver can determine in box 618 that the PAM4 signal is being received and proceed to box 620. Otherwise, control returns to box 616.

[0061] As an alternative to simple counting, the receiver can take a moving average of the absolute values ​​of the channel symbols. While PAM2 signaling continues, the moving average is expected to be 3 or very close to 3. Once PAM4 signaling begins, the moving average is expected to converge rapidly to 2. The window length of the moving average filter could be approximately 32, although other lengths are also suitable.

[0062] In box 620, the unadjusted PAM4 detection value is set to a predetermined value or a value determined using a level detector to determine the appropriate location. Figure 3 (B)). Alternatively, the adjusted detection values ​​are used as initial values ​​for adaptation. In block 622, the controller enables gain and filter coefficient adaptation and optionally reverts to the default clock recovery configuration in block 624. Thereafter, the receiver performs link training using PAM4 signaling and detection in block 516.

[0063] Once fully aware of the above disclosure, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. For example, the aforementioned disabling of adaptation, tuning, or optimization can be achieved in various ways by setting the error scaling factor to zero, by zeroing the update step size, by "freezing" (multiple) related integrators, or by storing and restoring to the accumulated error value. The claims are intended to be interpreted as covering all such alternatives, equivalents, and modifications contained within the scope of the appended claims.

Claims

1. A receiving method, characterized in that, The receiving method includes: Negotiate the link speed with PAM4 signaling; During PAM2 signaling, at least one gain or filter coefficient adaptation is performed; Switch to PAM4 detection before receiving PAM4 signaling; Disable the adaptation before switching to PAM4 detection; PAM4 signaling is detected using at least one statistic of the detected PAM4 symbols; and After detecting PAM4 signaling, the adaptation is enabled; and The detected PAM4 symbols are retransmitted as PAM2 symbols until PAM4 signaling is detected.

2. A receiving method, characterized in that, The receiving method includes: Negotiate the link speed with PAM4 signaling; During PAM2 signaling, at least one gain or filter coefficient adaptation is performed; Switching to PAM4 detection before receiving PAM4 signaling includes using an adjusted PAM4 detection value, which causes PAM2 symbols to be detected only as external PAM4 symbols. Disable the adaptation before switching to PAM4 detection; PAM4 signaling is detected using at least one statistic of the detected PAM4 symbols; and The adaptation is enabled after PAM4 signaling is detected.

3. The method as described in claim 2, characterized in that, The adjusted PAM4 detection value was obtained by scaling the nominal PAM4 detection value by a factor of 0.

8.

4. The method as described in claim 2, characterized in that, The at least one statistic is the rate or count of detected internal PAM4 symbols.

5. The method as described in claim 4, characterized in that, The PAM4 detection includes determining when the rate or count exceeds a predetermined value.

6. A receiving method, characterized in that, The receiving method includes: Negotiate the link speed with PAM4 signaling; During PAM2 signaling, at least one gain or filter coefficient adaptation is performed; Switch to PAM4 detection before receiving PAM4 signaling; Disable the adaptation before switching to PAM4 detection; PAM4 signaling is detected using at least one statistic of the detected PAM4 symbols; and After detecting PAM4 signaling, the adaptation is enabled; and Before switching to PAM4 detection, reduce the bandwidth of the clock recovery loop.

7. The method as described in claim 6, characterized in that, The receiving method further includes: after detecting PAM4 signaling, restoring the bandwidth of the clock recovery loop.

8. A receiver, characterized in that, The receiver includes: A controller that coordinates with remote nodes to negotiate link speeds with PAM4 signaling; An equalizer having at least one filter coefficient, wherein the controller performs adaptation of the at least one filter coefficient during PAM2 signaling; and A decision element that switches from PAM2 detection to PAM4 detection before receiving PAM4 signaling. The decision element initially uses an adjusted PAM4 detection value that causes PAM2 symbols to be detected only as external PAM4 symbols. The controller monitors at least one statistic of the symbols detected by the decision element to detect when PAM4 signaling is received, and The controller disables the adaptation before switching to PAM4 detection and enables the adaptation after PAM4 signaling is detected.

9. The receiver as claimed in claim 8, characterized in that, The adjusted PAM4 detection value was obtained by scaling the nominal PAM4 detection value by a factor of 0.

8.

10. The receiver as claimed in claim 8, characterized in that, The at least one statistic is the rate or count of detected internal PAM4 symbols, and the PAM4 detection includes determining when the rate or count exceeds a predetermined value.

11. The receiver as claimed in claim 8, characterized in that, Before switching to PAM4 detection, reduce the bandwidth of the clock recovery loop.

12. A method for receiving a data stream, characterized in that, The method includes: Negotiate the link speed with PAM4 signaling; During PAM2 signaling, at least one of the gain and filter coefficients is adapted; During PAM2 detection, changes in at least one signal characteristic are monitored; and After detecting the change, switch to PAM4 detection.

13. The method as described in claim 12, characterized in that, The at least one signal characteristic is the probability distribution of the equalization error.

14. The method as described in claim 12, characterized in that, The at least one signal characteristic is the range of equalization error.

15. The method as described in claim 12, characterized in that, The at least one signal characteristic is the probability distribution of the equalization signal.

16. The method as described in claim 12, characterized in that, The at least one signal characteristic is the range of the equalization signal.

17. A receiver, characterized in that, The receiver includes: A controller that coordinates with remote nodes to negotiate link speeds with PAM4 signaling; An equalizer having at least one filter coefficient, wherein the controller performs adaptation of the at least one filter coefficient during PAM2 signaling; and Decision element, configured to switch from PAM2 detection to PAM4 detection. When the decision element is configured for PAM2 detection, the controller monitors for changes in at least one signal characteristic and, upon detecting such changes, configures the decision element for PAM4 detection.

18. The receiver as claimed in claim 17, characterized in that, The at least one signal characteristic is the probability distribution of the equalization error.

19. The receiver as claimed in claim 17, characterized in that, The at least one signal characteristic is the range of equalization error.

20. The receiver as claimed in claim 17, characterized in that, The at least one signal characteristic is the probability distribution or range of the equalization signal.

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