Programmable multi-core photonic integrated circuit and related methods of operation

Abstract

The present invention relates to a programmable multi-core photonic integrated circuit comprising at least one programmable photonic module or core, and / or other photonic units, such as specific high performance blocks, capable of implementing multi-purpose signal processing by appropriately programming its resources, routing within the circuit and blocks to enable multi-functional operation and selecting its input and output ports. The present invention also relates to scalable programmable photonic integrated circuits arranged in a modular multi-core approach to increase the processing power of the overall system and / or to increase the amount of functionalities enabled by complex photonic circuitry and parallelization and related operation methods. The present invention also relates to scalable programmable photonic integrated circuits arranged in a modular multi-core approach to increase the processing power of the overall system and / or to increase the amount of functionalities enabled by complex photonic circuitry and parallelization and related operation methods.

Description

Technical Field

[0001] This invention relates to a programmable multi-core photonic integrated circuit, comprising at least one programmable photonic module or core, and / or other photonic units, such as specific high-performance blocks, capable of multi-purpose signal processing by appropriately programming their resources, routing within circuits and blocks to achieve multifunctional operation, and selecting their input and output ports. The invention also relates to scalable programmable photonic integrated circuits arranged in a modular multi-core manner to increase the overall system processing power and / or increase the number of functions and associated operating methods implemented by complex photonic circuitry and parallelization. Background Technology

[0002] Programmable multifunctional photonics (PMP) seeks to design general-purpose, multi-purpose configurations of integrated optical hardware that can achieve various functions through the appropriate programming of a large number of reconfigurable basic processing elements or units. Different authors have covered theoretical work proposing different configurations and design principles for programmable circuits based on cascaded beamsplitters or Mach-Zehnder interferometers (MZIs). These suggestions provide multifunctional hardware solutions for realizing programmable circuits, but none of them address the scalability challenges that limit their development and practical use.

[0003] The performance of programmable multifunctional photonics and its ability to perform complex operations are directly proportional to the number of integrable tunable units and basic processing elements. These architectures are plagued by similar limitations faced by integrated electronics in terms of the number of transistors per chip.

[0004] In the case of programmable, multi-purpose integrated photonic circuits, the experimental demonstrations reported to date have primarily been proof-of-concept for small-scale integration of tunable elements. Scalability limitations stem from: the maximum number of basic units, which is in turn limited by the space available in the lithography process and the mask size; the cumulative losses within the circuit and optical interfaces; the ability to interface and package a large number of electronic ports; and finally, the ability to interface a large number of optical ports.

[0005] Regarding cumulative losses, even considering an infinite number of programmable unit cells, the maximum size of the circuit is limited by optical power losses propagating through waveguides and components within the processor chip.

[0006] Regarding electrical interfaces, the electrical routing of control signals imposes system overhead that consumes a valuable portion of the design footprint. In some cases, the distribution of routing tracks necessitates a redistribution of optical components across the circuitry to ensure matching between on-chip electrical and optical layers. This creates space constraints and limits the final integration density.

[0007] Inefficient programming can be found in large-scale single-core programmable photonic processors when high-performance peripheral building blocks are required. This problem arises when the location of the high-performance building blocks is not optimal for the required functionality, and signals are forced to travel relatively long distances through the core. This introduces additional losses into the circuitry and increases the demand on processor resources that are only used for internal interconnect purposes.

[0008] To alleviate the above limitations, a solution is needed to scale the number of programmable units in a circuit.

[0009] Multi-core processors are well-known in the electronics field, where these architectures revolve around the utilization of placing two or more computing units or cores within a single processor. This architecture is based on a "divide and conquer" strategy within a given clock cycle, thereby employing a "scaling-out" approach when physical constraints pose scaling challenges [Add ref.,10.1.1.687.5977,(Venu,2011)].

[0010] In photonic integrated circuits (PICs), several multi-chip architectures have been proposed, primarily for implementing interconnect networks on a single chip, which are then used in data centers and transceivers. These architectures employ different types of chips: photonic crosspoint matrix switches, photonic broadcasting and selection, and wavelength division multiplexing (WDM) circuit routers and electronic processors.

[0011] 1. Crosspoint switch [(A. Shacham, 2007), (Luca Ramini, 2012)]:

[0012] This approach relies on the interconnection of the cores that implement the crosspoint exchange matrix. Each "basic unit" in this approach typically consists of ring resonators arranged in a matrix layout, with basic units at each node. Some implementations also include a multi-channel waveguide bus using integrated wavelength division multiplexing operation.

[0013] 2. Broadcasting and Selection, WDM Circuit Routing [(T. Alexoudi, 2019), (Martijn Heck, 2014)]:

[0014] This approach relies on the use of MUX-DEMUX devices, such as arrayed waveguide gratings and / or directional couplers or trees of MMIs, as well as selective units, which can be in the form of semiconductor optical amplifiers or ring resonators.

[0015] 3. Photon-assisted electronic multi-core processor.

[0016] This approach relies on electronic processors interconnected via photonic links. To achieve this, the architecture requires photonic components to transition from the electronic domain to the optical domain (modulator), and photodetectors to transition signals from the optical domain back to the electronic domain within each core. Interconnection between the electronic cores is achieved via photonic networks using different technologies.

[0017] These methods have several things in common, namely:

[0018] a. Photon core:

[0019] 1. Based on fixed application-specific blocks (switching matrices and / or demultiplexers) typically used in network routing or optical interconnects (i.e., without carrying any optical signal processing tasks).

[0020] 2. Relying on a switch instead of a tunable coupler, both cores operate in a 1 or 0 on / off digital state, with the switch on or off, instead of using intermediate states in the coupler.

[0021] 3. They are fixed and rigid in their layout. While both can be used to selectively route channels to various outputs, they cannot be used to perform any other functions or to replicate any other circuitry as needed.

[0022] b. Electronic chip:

[0023] 1. Photonics is only used to facilitate interconnection between electronic chips.

[0024] 2. Each interface with the electronic chip requires electro-optical and opto-photonic components. Invention Overview

[0026] The present invention described herein aims to address the scalability and performance issues of the aforementioned programmable photonic integrated circuits (IPCs) and allows for the design and implementation of scalable IPCs via a multi-core architecture, wherein two or more programmable photonic cores and / or additional high-performance blocks are interconnected. This provides significant technical advantages over existing methods in terms of large-scale circuit fabrication, performance, electrical / optical interfaces, and scalability. Furthermore, the multi-core modular approach enables the rapid and efficient setup of parallel and multi-task computing and / or processing operations, leveraging their inherent advantages.

[0027] The objective of this invention is the interconnection of chips based on a multipurpose programmable photonic processor. Each chip comprises a reconfigurable optical waveguide grid arrangement of photonic gates that performs basic optical simulation operations (reconfigurable optical power and energy distribution, and independent phase shifts). Furthermore, each chip may include a set of high-performance photonic blocks specifically designed to perform complex photonic and electro-optic operations. Previous combinations and interconnections of components / resources defined a single module or chip. Therefore, in view of the foregoing, it can be observed that the present objective of this invention allows for one or more simultaneous photonic circuits and / or linear multiport transformations, achieved by appropriately programming their resources, i.e., the corresponding programmable photonic circuits and input and output ports for each chip.

[0028] This invention relates to a programmable multi-core photonic integrated circuit, comprising:

[0029] - At least two photonic blocks, wherein at least one of the at least two photonic blocks is a programmable photonic core, comprising:

[0030] i. The reconfigurable optical waveguide grid arrangement of photonic gates is configured to perform optical simulation operations;

[0031] The at least one programmable photonic core is configured to be programmed and reconfigured to provide signal processing tasks via non-recursive, recursive, or a combination of recursive and non-recursive signal propagation.

[0032] Optionally, each of the at least one programmable photonic core further includes a set of internal high-performance photonic blocks configured to perform photonic and electro-optical operations.

[0033] Optionally, each of the at least one programmable photonic core further includes an optical I / O port, wherein each of the at least one programmable photonic core is connected to the at least one programmable photonic core via the optical I / O port.

[0034] Optionally, each of the at least one programmable photonic core further includes a set of transitional high-performance photonic blocks configured to perform photonic and electro-optical operations and additionally connected to the optical I / O port.

[0035] Optionally, each of the at least one programmable photonic core is combined with a communication network configured to route optical signals from each of the at least one programmable photonic core.

[0036] Optionally, each of the at least one programmable photonic core is connected to an adjacent programmable photonic core.

[0037] Optionally, each of the at least one programmable photonic core further includes an auxiliary switching or routing layer.

[0038] Optionally, each of the at least one programmable photonic core is connected to a non-adjacent programmable photonic core.

[0039] Optionally, each of the at least one programmable photonic core is directly connected to the distribution network via at least one optical I / O port.

[0040] Optionally, the distribution network connecting the at least one programmable photonic core is configured to allocate a dedicated routing block on each programmable photonic core.

[0041] Optionally, the distribution network connecting the at least one programmable photonic core is configured to distribute dedicated routing blocks on a centralized subsystem.

[0042] Optionally, the at least one programmable photonic core is distributed on a two-dimensional layer.

[0043] Optionally, the at least one programmable photonic core is distributed on a three-dimensional stacked layer, with each layer including one programmable photonic core.

[0044] Optionally, the at least one programmable photonic core is distributed on a three-dimensional stacked layer, with each layer including at least one programmable photonic core.

[0045] Optionally, the programmable multi-core photonic integrated circuit also includes an optical connector or coupler configured to enable interconnection between the at least one programmable photonic core of the layer.

[0046] Optionally, the programmable multi-core photonic integrated circuit also includes an integration platform, wherein the at least two photonic blocks are physically interconnected.

[0047] Optionally, the at least two photonic blocks are optically and electrically connected.

[0048] Optionally, the programmable multi-core photonic integrated circuit also includes at least one optical power monitor, wherein the at least one programmable photonic core is connected.

[0049] Optionally, the programmable multi-core photonic integrated circuit also includes application-oriented blocks such as sensors, detectors, antennas, measurement, transmission blocks, electronic ICs selected from DACs or ADCs, drivers, monitors, and / or amplifiers, wherein at least one programmable photonic core is connected.

[0050] Optionally, the programmable multi-core photonic integrated circuit also includes an electrical subsystem for driving actuators or on-chip actuators / receivers, an electrical subsystem for monitoring photoelectric readouts, and an electronic processor or microprocessor for running optimization and configuration programs.

[0051] Optionally, the programmable multi-core photonic integrated circuit also includes control planes and / or software layers distributed across different subsystems, configured to control the at least one programmable photonic core.

[0052] Optionally, the programmable multi-core photonic integrated circuit also includes a control plane and / or software layer aggregated on a single system configured to control the at least one programmable photonic core.

[0053] Optionally, each of the at least one programmable photonic core is connected to a plurality of adjacent programmable photonic cores.

[0054] Optionally, the communication network is a dedicated communication network configured to route optical signals from each of the at least one programmable photonic core.

[0055] Optionally, the communication network is a dedicated communication network configured to allow programmable photonic cores to interconnect with other non-adjacent programmable photonic cores via an auxiliary switching or routing layer.

[0056] Optionally, programmable multi-core photonic integrated circuits are implemented and integrated on a chip.

[0057] Optionally, the chip follows a uniform PIC integration, wherein at least one programmable photonic core is integrated on the same substrate.

[0058] Optionally, the chip follows heterogeneous PIC integration, wherein at least one programmable photonic core is integrated on the same substrate.

[0059] Optionally, the chip follows an on-board integration (chip-like) approach, wherein a common substrate or common platform is used to apply plug-and-play connectivity to arrange the at least one programmable photonic chip based on the processor's desired performance.

[0060] The present invention also relates to a method of operating the above-described programmable multi-core photonic integrated circuit, wherein the method includes connecting and utilizing the at least one programmable photonic core such that a signal from one programmable photonic core enters at least other programmable photonic cores in a specific order in which the programmable photonic integrated circuits are cascaded.

[0061] Optionally, the method includes connecting and utilizing the at least one programmable photonic core such that signals from one programmable photonic core enter at least other programmable photonic cores in a specific order, wherein the programmable photonic integrated circuit separates and processes the signals on at least one programmable photonic core before combining the signals on different programmable photonic cores.

[0062] Optionally, the method includes programming the at least one programmable photonic core to simultaneously execute independent tasks running in parallel.

[0063] The proposed photonic architecture of the programmable multi-core photonic integrated circuit based on this invention significantly enhances a range of advantages inherent in field-programmable photonic hardware methods, extended through the circuit topology introduced in this invention. These include:

[0064] Scalability of multi-purpose programmable photonic circuits.

[0065] Shorten production and time to market.

[0066] Reduce prototyping and non-recurring engineering costs.

[0067] Reduce the financial risk of developing ideas and turning them into ASPICs.

[0068] Multifunctional and multitasking operation.

[0069] Circuit optimization.

[0070] Standard layout and reduced space requirements.

[0071] Programmable photonic analog blocks offer better yield and reproducibility.

[0072] A large number of alternative circuit topologies that are not constrained by geometric factors.

[0073] Programming more complex and multifunctional circuits. More ports, i.e., inputs and outputs.

[0074] Enhanced functionality.

[0075] The optical and electrical interfaces have been improved.

[0076] It performs better when programming larger and more complex circuits.

[0077] Reduce and mitigate optical crosstalk and tuning crosstalk.

[0078] Future scalability with lower design and verification costs.

[0079] The proposed programmable multi-core photonic integrated circuit based on this invention is suitable for the following applications:

[0080] Aerospace and defense (avionics, communications, security solutions, space).

[0081] Automotive (high-resolution video, image processing, vehicle networking and connectivity, automotive infotainment).

[0082] Data center (servers, routers, switches, gateways).

[0083] High-performance computing (servers, supercomputers, SIGINT systems, radar, beamforming systems, quantum computing, neural networks).

[0084] Integrated circuit design (ASPIC prototyping, hardware simulation).

[0085] Wired and wireless communications (optical transmission networks, network processing 5G connectivity interfaces, mobile backhaul).

[0086] Hardware accelerators.

[0087] Machine and deep learning applications.

[0088] AI.

[0089] Intelligent transceiver.

[0090] Quantum photonic processor.

[0091] Therefore, the technological innovations proposed in this invention present an architecture, workflow, and control protocol for a multi-core programmable photonic integrated processor, which enables large-scale integration of programmable processing units and leverages the parallelization of multiple tasks. Compared to current architectures, it also delivers significant performance improvements. It achieves functional improvements in several aspects, including but not limited to scalability, performance, and multitasking efficiency.

[0092] The photonic chips of this invention are not merely programmable interconnect subsystems that cannot be programmed and reconfigured to provide signal processing tasks via non-recursive or recursive signal propagation. Therefore, these chips influence application-independent additional degrees of freedom. The entire device here can be defined as a reconfigurable network of reconfigurable signal processing chips. Brief description of the attached diagram

[0094] To supplement the ongoing description and to aid in a better understanding of the features of the invention, the description, as an integral part of the preferred embodiments thereof, is accompanied by a set of drawings, in which the following are illustrated in an illustrative and non-limiting manner:

[0095] Figure 1 The illustration shows a non-limiting example of a schematic diagram of the photonic architecture proposed in this invention, wherein the illustration shows an example of a multi-core implementation with seamless interconnections.

[0096] Figure 2 A non-limiting example showing a schematic diagram of the photonic architecture proposed in this invention is provided.

[0097] Figure 3 A non-limiting example showing a schematic diagram of the photonic structure proposed in this invention is provided.

[0098] Figure 4 A non-limiting example showing a schematic diagram of the photonic architecture proposed in this invention is provided.

[0099] Figure 5A non-limiting example showing a schematic diagram of the photonic architecture proposed in this invention is provided.

[0100] Figure 6 A non-limiting example showing a schematic diagram of the photonic architecture proposed in this invention is provided.

[0101] Figure 7 (Left) shows a non-limiting example of a schematic diagram of the photonic architecture proposed in this invention. Figure 7 (Right) shows a non-limiting example of a schematic diagram of the photonic architecture proposed in this invention.

[0102] Figure 8 A non-limiting example showing a schematic diagram of the photonic architecture proposed in this invention is provided. Invention Details

[0104] In a preferred embodiment for the purpose of this invention, as follows is provided Figure 1 The illustrated apparatus, wherein at least two, but preferably a large number, of versatile programmable photonic circuits are aggregated and connected in a module or chip, wherein each module or chip of the programmable photonic integrated circuit is used in conjunction with other programmable photonic circuits or additional functional blocks (which may be high-performance blocks, specific functional blocks, or other such units). These modules are programmable and perform optical signal processing on the photonic chip. Considering Figure 1 The design does not assume any specific interconnect geometry or topology for the multipurpose programmable photonic circuitry present in each core or module, and the final design shown here is for illustrative purposes only. While various sub-core architectures can be considered, we will illustrate the design here with a very basic hexagonal waveguide mesh connected to a set of eight high-performance building blocks and a transitional high-performance building block. Figure 1-3 Examples of possible interconnect and architectural options are shown, but not limited to these examples. In particular, for a specific multi-core with a seamless interconnect architecture, the scheme for the multi-core programmable photonic processor is as follows: Figure 1 As shown in the diagram. In this architecture, each processing core is connected to up to four adjacent cores via its optical I / O ports. The replication and interconnection of this module with its adjacent cores results in a simple, scalable, cost-effective, and versatile direct processing network. Some design variations may include high-performance building blocks placed within the optical interface to perform specific functions, including but not limited to optical signal amplification and nonlinear operations.

[0105] In some cases, it is beneficial to access the core without needing direct access to its internal resources, or to have hardware that can support both as needed through software control. Figure 2A non-limiting example of a schematic diagram of the photonic architecture proposed in this invention is shown, illustrating an implementation example of a multi-core implementation with distributed interconnections. In this architecture, each processing core is coupled with a communication network that routes optical signals from each modular core. The replication and interconnection of this module with its neighboring cores results in an on-chip communication and processing network characterized by its efficiency, scalability, design cost, and versatility. This architecture is similar to a field-programmable photonic gate array architecture, where the user has access to a large number of general-purpose processing resources. As with the previous methods, the design does not have centralized resources, which become larger and more complex as the number of cores increases. Therefore, the design complexity and verification complexity are independent of the core count.

[0106] The first two methods do not allow direct interconnection of non-adjacent cores. Figure 3 The illustration shows a non-limiting example of a schematic diagram of the photonic architecture proposed in this invention, illustrating an example of a multi-core implementation with centralized interconnects. This scheme allows a given core to interconnect with other non-adjacent cores employing an auxiliary switching / routing layer. This design is interesting in multi-core systems with a reduced number of cores, but it comes at the cost of scalability issues and requires additional validation and customization for each hardware upgrade.

[0107] By appropriately programming each core or module, a multi-purpose, multi-core programmable photonic processor can achieve complex autonomous and / or parallel photonic circuitry and signal processing conversions by discretizing complex optical processing circuitry into different interconnected modules for programmable photonic processing. The goal is then to realize the functional advantages offered by the modular approach, improving performance, scalability, versatility, and adding new, higher processing capabilities.

[0108] In particular, Figure 4-6 The present invention is illustrated in the figure, which shows how complex optical signal processing circuitry can be configured by programming the proposed device. In particular, we demonstrate how a multi-core architecture with a seamless interconnect architecture can program complex circuitry distributed across four cores, adding circuitry sections that operate in parallel, and performing independent multitasking operations.

[0109] The multi-purpose, multi-core programmable photonic processor combines the programmability of a basic programmable photonic processor in a scalable interconnect architecture, allowing programmable circuits to have scalable processing capabilities and additional features such as enhanced circuit parallelization. Therefore, processing complexity arises from the interconnectivity within and between cores. Furthermore, it addresses key issues related to the scalability of programmable photonic circuits, where increasing the density of their programmable units comes at the cost of adversarial effects such as optical crosstalk, tuning crosstalk, non-scalable optical and electrical interfaces, and limited space in manufacturing processes. The multi-core programmable photonic processor architecture comprises the interconnection of multiple general-purpose cores and emerges as an elegant solution to extend the performance of traditional photonic processors. Since the scalability limitations of single-core processors are exacerbated when a large number of programmable units are integrated into a circuit, a simple approach is to use an architecture that integrates and interconnects several smaller cores.

[0110] Control of the entire device, including all interconnect blocks, can be performed using separate software to drive each chip, or it can be added to a software interface, forming a common means of driving, programming, controlling, and reconfiguring the entire hardware. Universal software enables intelligent programming and management of resources to achieve optimal configuration in terms of the number of components used, power consumption, programming efficiency, and mitigation of side effects (optical and tuning crosstalk).

[0111] Operation Example

[0112] The decomposition characteristics of multi-core photonic processors enable a wide range of operating modes. In this section, we will illustrate some non-limiting examples:

[0113] Figure 4 A programming schematic of a progressive distributed circuit (serialized) is shown, illustrating an example of a multi-core configuration with seamless interconnections, where complex circuitry is programmed on four cores following the serialized circuitry. This circuitry includes a ring resonator (first core), a dispersion delay in a high-performance building block, an optical amplifier in a transitional HPB, a beam splitter (second core), a beamforming network, a sixth-order finite impulse response filter (third core), and a branch (fourth core) with an optical attenuator implemented by the high-performance building block and a branch with a high-q filter and a polarization filter. The configuration of complex photonic circuitry on a single-core processor is limited by the number of available optical ports, programmable cell units, and high-performance blocks in the circuitry. Furthermore, the accumulation of non-ideal effects (optics and crosstalk during phase tuning), and the large number of programmable cells required to perform complex operations, rapidly limit the circuitry that can be implemented on the core. Figure 4This illustrates how a multi-core architecture partitions and assigns circuitry to cores. The programming circuitry is not targeted at any application but is simply set to highlight the primary function of this operating mode. In this case, the first core (top left) configures an optical ring resonator within its inner core, accesses the dispersion delay provided by the HPB 7, and amplifies the optical signal before connecting to the next core. The next core (top right) splits the optical signal into two paths. The first path feeds the programmed beamformer, demonstrating the benefits of the multi-core approach for circuits requiring multiple optical paths and ports. The other path points to the interconnected outputs to access the third core. The third core (bottom right) implements an optical lattice filter based on three unbalanced MZIs within its core and directs the two outputs of the filter to the next and last cores. The last core (bottom left) assigns one optical interconnect to an optical attenuator and another optical connection to the cascaded HPB filter and polarization filter, respectively.

[0114] Figure 5 A schematic diagram of parallel distributed circuitry (parallelization) is shown, illustrating an example of a multi-core configuration with seamless interconnections, where complex circuitry is programmed on four cores following parallel circuitry. This circuitry includes (top left core) a Mach-Zehnder modulator, beam splitter, and optical amplifier; (top right core) an optical filter with two outputs; (bottom left core) an optical filter based on MZI and four ring resonators; and (bottom right core) programming of a combiner and photodetector. Some circuits divide the circuitry into blocks that operate in parallel. While possible in a single-core processor, programming these circuits can be limited when programmed individually within a single core. In such cases, interference between parallel-running circuit branches can degrade overall processing performance. To mitigate this effect, multi-core architectures can distribute portions of the same circuitry operating in parallel across different processing cores. Figure 5 The programming of the circuit distributed across four cores is illustrated. The first core (top left) receives the input signal and accesses the MZI modulator before separating and routing it to the second core (top right) and the third core (bottom left). Each core contains a different filter. In the first case, it is a third-order ring resonator structure that extracts the passband and feeds it to the fourth core (bottom right), while feeding the stopband or reflection response to the external port. The second case (bottom left) is an optical filter that combines a lattice filter and an optical ring resonator before guiding the two output ports to the fourth core. The last core (bottom right) receives signals from two different cores. A high-speed photodiode block is used to detect the signal from the bottom left core. The second signal from the bottom left core is combined with the optical signal from the top right core before accessing the optical output port.

[0115] Figure 6A schematic diagram of a programmable independent circuit (multitasking) is shown, illustrating an example of a multi-core configuration with seamless interconnections, where two independent, complex circuits are programmed on four cores after multitasking operation. The circuit comprises a cascade of two unit blocks with intermediate nonlinear sections (top cores) and another cascade of a filtering section consisting of four rings, followed by a 4x4 multiport interferometer. A final key advantage of multi-core photonic processors lies in their ability to execute independent tasks simultaneously. This capability can also be used in single-core processors, but requires the application of additional optimization techniques to mitigate crosstalk between the two circuits. In short, the processor programs two or more circuits that operate in parallel and perform independent tasks. The circuits can be identical or completely different designs. Furthermore, the circuits can be distributed across different cores or can be programmed to share some available resources on the same core for situations including, but not limited to, emergency applications. Figure 6 This illustrates an example of programming two independent circuits using a multi-core architecture. The upper core is configured with a two-layer neural network consisting of six modes. The lower core, located in the processor, configures the initial filtering stage before accessing the 4x4 interferometer, followed by the nonlinear array.

[0116] Physical implementation

[0117] The physical realization of a multi-purpose, multi-core programmable optical processor requires an integrated optical approach based on silicon photonics platforms and / or hybrid / heterogeneous III-V and / or III-V group and / or barium titanate and / or any other chalcogenide and / or II-VI platforms. It is not limited to the integration of programmable photonics ICs with other photonics ICs and / or blocks, but also to the integration with electronic ICs and subsequent blocks of this nature.

[0118] As for programmable photonic blocks, currently available photonic technology options are based on any phase or amplitude tuning effect, such as: MEMS, thermo-optical effect, electro-optical effect, optomechanical, capacitive effect, or non-volatile phase actuator. The phase shifter and actuator are integrated into any interference structure with two or more ports.

[0119] Physical implementations include different architectures and integration levels, which can be categorized as follows:

[0120] Architecture:

[0121] Heterogeneous architecture: While a key advantage of multi-core architecture is the replication of the same unit core, the range of applications can be expanded if each core uses a different HPB and internal core topology. As an illustrative example, Figure 7(Left) shows an example of a configuration of a seamlessly interconnected multi-core with a heterogeneous architecture, where the four cores have different internal compositions. Specifically, each core includes a set of high-performance processing blocks and different waveguide mesh arrangements (hexagonal, triangular, square, and feedforward). That is, it is a 4-core architecture, with each module having a different inner core: a hexagonal mesh architecture, a triangular mesh architecture, a square mesh architecture, and a rectangular multiport interferometer. It is also noteworthy that each can integrate a different HPB. A key advantage of this implementation is the availability of specific resources required for certain applications. For example, the feedforward mesh shown in the lower right core could be implemented using a hexagonal mesh, but with lower efficiency.

[0122] 2D Architecture: A 2D architecture can be implemented by considering the current standards and status of PICs and their integration. A 2D architecture is generally considered to be connecting one core to another, which is equivalent to creating a "short circuit" by connecting optical fibers or waveguides from different cores. This can be achieved through a single package of different photonics cores on the same or different integration platforms.

[0123] 3D architecture (single-core and multi-core): Figure 7 (Right) shows a 3D architecture with four cores, each connected to its neighbor via vertical interconnects. That is, it is multi-core, with four cascaded circuits seamlessly interconnected in a 3D integrated shape. The connections between the cores are accomplished by waveguide couplers designed to couple vertical light to the upper / lower waveguide layers.

[0124] 3D stacking architecture relies on placing multiple cores in a 3D layout (such as...) Figure 7 As shown, performance enhancements are related to processing power. The scalability of single-core designs is limited by the mask size of the manufacturing tooling. These core-pillar assemblies can be stacked individually to form multiple cores to overcome these limitations, but the form factor is affected. One solution that can significantly reduce the form factor is 3D stacking, which offers multifaceted performance improvements. In this solution, such cores are placed in stacks of one on top of another, with interconnects on each stack, forming a larger, more powerful unit. Stacks can be configured in parallel to facilitate parallel processing, allowing functions to be executed in parallel.

[0125] It can also realize a hybrid architecture of 2D and 3D multi-core.

[0126] Integration level:

[0127] On-chip integration: On-chip integration means that a photonic core is connected to an adjacent core or additional functional block, with all cores and components located on the same substrate. On-chip integration can be achieved using various methods, the most common of which are as follows:

[0128] Homogeneous PIC Integration: In this approach, all cores are implemented in the same manufacturing process on a single die of the PIC. This approach allows for the implementation of multiple cores, and the key advantage of homogeneous integration comes from the very small form factor that can be achieved. Single-core implementation in a programmable PIC is limited by the purely geometric constraints imposed by the mask size. In the approach proposed in this invention, a non-limiting example is a multi-core processor formed by manufacturing identical cores on a single wafer, where one or more cores are defined as cells manufactured in a single mask. Then, all or some different segments of the wafer are interconnected with the cores defined in the mask; that is, the different dies are not cut but rather act as aggregate interconnects of multiple dies and cores, resulting in a multi-core processor where all cores are defined and set during the manufacturing process, thus eliminating the need for interconnects of different cores during the packaging process. This approach then relaxes the requirements for PIC packaging, increases throughput, and facilitates hardware implementation through a simpler process flow.

[0129] Heterogeneous PIC Integration: Heterogeneous PICs are the integration of two or more different materials on the same chip substrate. The most common implementation of this approach can be seen in the integration of active devices in InP with small form factor SOI circuitry or low-loss SiN platforms, but it can even be extended to other materials such as barium titanate (BTO), graphene, chalcogenides, etc. Since there is no photonic gain medium in pure SOI or SiN circuitry, this adds a significant amount of functionality, integrating on-chip lasers and gain elements, thus facilitating multi-core architectures. This implementation itself relies on a thin layer of InP or other III-V material “attached” to specific portions on top of the SOI or SiN chip. Light at these portions is evanescently coupled from the SOI or SiN waveguide into the InP portion to induce gain or as an effective phase modulation component. The “attachment” process is then performed via wafer bonding techniques such as BCB or other polymers, or other methods such as micro-transfer printing can be used.

[0130] On-board integration (similar to chiplets): This implementation is based on dividing chip design (co-design) and manufacturing according to the chip's basic functions. For example, it can take the form of functional subsystem blocks (such as chips), active blocks (such as lasers and gain media), nonlinear blocks, etc. After manufacturing these blocks and completing the sub-components (single chip packages), they are placed on a platform that serves as an interconnect substrate and then packaged into a single unit. Chips address the fact that there is no single method that works for everyone to meet current needs. This implementation is not limited to the aggregation of photonic multi-purpose photonic blocks and / or other high-performance photonic blocks, but can also include purely electronic blocks, including but not limited to drivers, monitors, ADCs, DACs, amplifiers, sensors, and antennas.

[0131] Figure 8The diagram illustrates a non-limiting example of the photonic structure proposed in this invention, showing an example of an implementation of the versatile programmable photonic processor in a multi-core layout, where each core can be connected in a plug-and-play or similar chip-like manner, thereby interconnecting two or more programmable photonic blocks with other programmable photonic blocks or functional units using a common platform shown in green. All these units are represented as black boxes in the diagram because they can comprise two or more programmable PICs and / or high-performance photonic building blocks, which can be further extended to include purely electronic ICs such as drivers, monitors, ADCs, DACs, sensors, antennas, etc.

[0132] Furthermore, all previous implementations can employ a control and drive subsystem to control and drive the multi-purpose, multi-core programmable photonic processor. The control and drive circuitry enables the extraction and readout of optical signals as well as the driving of the photonic actuators.

Claims

1. A programmable multi-core photonic integrated circuit, comprising: At least two photonic blocks, wherein at least one of the at least two photonic blocks is a programmable photonic core, comprising: i. The reconfigurable optical waveguide grid arrangement of photonic gates is configured to perform optical simulation operations; The at least one programmable photonic core is configured to be programmed and reconfigured to provide signal processing tasks via non-recursive, recursive, or combined recursive and non-recursive signal propagation; and The programmable multi-core photonic integrated circuit is configured to be programmed to share available resources on the programmable photonic cores of the at least two photonic blocks.

2. The programmable multi-core photonic integrated circuit of claim 1, wherein each of the at least one programmable photonic core further comprises a set of internal high-performance photonic blocks configured to perform photonic and electro-optical operations.

3. The programmable multi-core photonic integrated circuit according to claim 1, wherein each of the at least one programmable photonic core further includes an optical I / O port, wherein each of the at least one programmable photonic core is connected to the at least one programmable photonic core via the optical I / O port.

4. The programmable multi-core photonic integrated circuit of claim 3, wherein each of the at least one programmable photonic core further comprises a set of transition high-performance photonic blocks configured to perform photonic and electro-optical operations and additionally connected to the optical I / O port.

5. The programmable multi-core photonic integrated circuit of claim 1, wherein each of the at least one programmable photonic core is integrated with a communication network configured to route optical signals from each of the at least one programmable photonic core.

6. The programmable multi-core photonic integrated circuit according to any one of claims 4 or 5, wherein each of the at least one programmable photonic core is connected to an adjacent programmable photonic core.

7. The programmable multi-core photonic integrated circuit of claim 5, wherein each of the at least one programmable photonic core further comprises an auxiliary switching or routing layer.

8. The programmable multi-core photonic integrated circuit of claim 7, wherein each of the at least one programmable photonic core is connected to a non-adjacent programmable photonic core.

9. The programmable multi-core photonic integrated circuit according to any one of claims 3 or 4, wherein each of the at least one programmable photonic core is directly connected to a distribution network via at least one optical I / O port.

10. The programmable multi-core photonic integrated circuit of claim 9, wherein the allocation network connecting the at least one programmable photonic core is configured to allocate a dedicated routing block on each programmable photonic core.

11. The programmable multi-core photonic integrated circuit of claim 9, wherein the distribution network connecting the at least one programmable photonic core is configured to distribute dedicated routing blocks on a centralized subsystem.

12. The programmable multi-core photonic integrated circuit according to claim 1, wherein at least one programmable photonic core is distributed on a two-dimensional layer.

13. The programmable multi-core photonic integrated circuit according to claim 1, wherein the at least one programmable photonic core is distributed on a three-dimensional stacked layer, each layer comprising one programmable photonic core.

14. The programmable multi-core photonic integrated circuit according to claim 1, wherein the at least one programmable photonic core is distributed on a three-dimensional stacked layer, and each layer includes at least one programmable photonic core.

15. The programmable multi-core photonic integrated circuit according to any one of claims 12 to 14, further comprising an optical connector or coupler configured to realize interconnection between the at least one programmable photonic core of the layer.

16. The programmable multi-core photonic integrated circuit of claim 1, further comprising an integration platform, wherein the at least two photonic blocks are physically interconnected.

17. The programmable multi-core photonic integrated circuit of claim 1, wherein the at least two photonic blocks are optically and electrically connected.

18. The programmable multi-core photonic integrated circuit of claim 1, further comprising at least one optical power monitor, wherein the at least one programmable photonic core is connected.

19. The programmable multi-core photonic integrated circuit of claim 1, further comprising an application-oriented block, wherein the at least one programmable photonic core is connected.

20. The programmable multi-core photonic integrated circuit according to claim 1 further includes an electrical subsystem for driving actuators or on-chip actuators / receivers, an electrical subsystem for monitoring photoelectric readouts, and an electronic processor or microprocessor for running optimization and configuration programs.

21. The programmable multi-core photonic integrated circuit according to claim 1, further comprising a control plane and / or software layer distributed on different subsystems, configured to control the at least one programmable photonic core.

22. The programmable multi-core photonic integrated circuit of claim 1, further comprising a control plane and / or software layer aggregated on a single system, the single system being configured to control the at least one programmable photonic core.

23. The programmable multi-core photonic integrated circuit of claim 1, wherein each of the at least one programmable photonic core is connected to a plurality of adjacent programmable photonic cores.

24. The programmable multi-core photonic integrated circuit of claim 5, wherein the communication network is a dedicated communication network configured to route optical signals from each of the at least one programmable photonic core.

25. The programmable multi-core photonic integrated circuit of claim 7, wherein the communication network is a dedicated communication network configured to allow programmable photonic cores to interconnect with other non-adjacent programmable photonic cores via an auxiliary switching or routing layer.

26. The programmable multi-core photonic integrated circuit of claim 1, wherein it is implemented and integrated on a chip.

27. The programmable multi-core photonic integrated circuit of claim 26, wherein the chip follows uniform PIC integration, wherein at least one programmable photonic core is integrated on the same substrate.

28. The programmable multi-core photonic integrated circuit of claim 26, wherein the chip follows heterogeneous PIC integration, wherein at least one programmable photonic core is integrated on the same substrate.

29. The programmable multi-core photonic integrated circuit of claim 26, wherein the chip follows an on-board integration (chip-like) approach, wherein a common substrate or common platform is used to apply plug-and-play connectivity to arrange the at least one programmable photonic core based on the processor's desired performance.

30. A method of operating a programmable multi-core photonic integrated circuit according to any one of the preceding claims, wherein the method includes connecting and utilizing the at least one programmable photonic core such that a signal from one programmable photonic core enters at least other programmable photonic cores in a specific order in which the programmable photonic integrated circuit is cascaded.

31. A method of operating a programmable multi-core photonic integrated circuit according to any one of claims 1 to 29, wherein the method includes connecting and utilizing the at least one programmable photonic core such that signals from one programmable photonic core enter at least other programmable photonic cores in a specific order, wherein the programmable photonic integrated circuits are connected in series.

32. A method of operating a programmable multi-core photonic integrated circuit according to any one of claims 1 to 29, wherein the method comprises programming the at least one programmable photonic core to simultaneously perform independent tasks running in parallel.

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