A method for predicting gate switch oscillations in GaN-HEMT

Abstract

This invention discloses a method for predicting gate switch oscillation in GaN-HEMT devices, belonging to the field of semiconductors and power devices. The invention trains a BPNN network model to obtain a preliminary mapping relationship between parasitic capacitance and gate-source voltage based on the BPNN algorithm model. Then, a Cascode-based two-port network function for GaN HEMT is established. The parasitic capacitance value of the GaN HEMT device under all S-parameters is obtained experimentally. This extracted parasitic capacitance value is then input into the BPNN network model as a dataset to obtain Vo. GS_m V under all S parameters DS C GS C GD The relationship between the surface and the curve is shown. Simulation results show that the standard error of the prediction method of the present invention is smaller than that of ANN and PSO, proving that the detection method for GaN-HEMT gate switch oscillation based on the BPNN algorithm model of the present invention has high prediction accuracy.

Description

Technical Field

[0001] This invention relates to a method for predicting gate switch oscillations in GaN-HEMT devices, belonging to the field of semiconductors and power devices. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) are a new type of wide bandgap semiconductor devices. Their advantages include lower on-resistance and junction capacitance, higher switching speed, efficiency, and power density, making them widely used in power supply systems, power conversion systems, and drive circuits of control systems.

[0003] The high switching speed of GaN devices results in large dv / dt and di / dt, leading to spikes and oscillations in the switching waveform, even when the gate-source voltage V... GS When the fluctuation deviates from the safe range, it can also cause false turn-on of the switching transistor, which makes the driving voltage range of GaN devices very narrow. Existing literature has conducted segmented analysis of this oscillation process, but only provides a qualitative analysis of the impact of parasitic parameters on the gate voltage fluctuation range. To accurately grasp the influence of parasitic parameters on gate-source voltage fluctuation, it is necessary to establish an accurate device model to guide the design of the driving circuit and the selection of device parameters. Existing methods use physical basis equivalent circuit model parameter extraction. Although this method can accurately understand the device structure, for users of device models, the physical basis model is highly dependent on specific material, device and process parameters, and the number of parameters in its equivalent circuit model is very large, making the parameter extraction and partial differential equation solution process very complex (Wang Jiajia. Establishment and Verification of AlGaN / GaN HEMT Device Model [D]. Xi'an University of Electronic Science and Technology, 2017.).

[0004] Large-signal equivalent circuit models offer fast simulation speeds and do not require in-depth research into the relationship between the internal structure and external behavior of devices. They have been widely validated in practice and represent the simplest and most direct engineering approach. The core of this method lies in establishing an input-output correspondence within a certain data range, i.e., obtaining the output from the mapping relationship.

[0005] In recent years, with the widespread application of neural networks in industry, applying artificial neural networks to establish nonlinear parametric models of large-signal devices has advantages in terms of time cost and efficiency. Existing literature has studied the establishment of drain-source current Id under large-signal conditions of GaN HEMT devices based on artificial neural network (ANN) methods. DS Gate-drain capacitance C GD and gate-source capacitance C GSThe nonlinear parametric model (W.Hu,H.Luo,X.Yan and Y.-X.Guo, et al.An Accurate NeuralNetwork-Based Consistent Gate Charge Model for GaN HEMTs by RefiningIntrinsic Capacitances[J].IEEE Transactions on Microwave Theory and Techniques,2021,69(7):3208-3218;

[0006] D. Maafri, A.A. Saadi, M.A. Sabbagh and M.C. Yagoub, et al. A New High-Frequency HEMT GaN Extrinsic Capacitance Extraction Technique [J]. IEEE Microwave and Wireless Components Letters, 2022, 32(4): 305-307.). While these methods can solve the problem of fitting a large number of model parameters, they still require extracting parameters from small-signal equivalent circuit models, and do not clearly define the significance of parasitic parameters in the device switching process. Furthermore, existing GaN HEMT internal parasitic capacitance models characterize the dependence of the switching transistor on nonlinear voltage under bias conditions. Therefore, modeling the inherent nonlinear capacitance under large-signal excitation results in low simulation accuracy of the GaN HEMT gate-source voltage. In actual operation, the gate-source voltage V... GS Parasitic capacitance may exceed its threshold voltage, leading to false turn-on of the switching transistor, increasing switching losses, causing continuous voltage oscillations in bridge circuit structures, and even reducing converter reliability. Therefore, simulating and predicting the impact of parasitic capacitance on the oscillating voltage of the switching transistor during operation is crucial. Summary of the Invention

[0007] To address the problem of low accuracy in simulating and predicting gate-source voltage in GaN HEMTs, this invention provides a method for predicting gate switch oscillations in GaN-HEMTs, the technical solution of which is as follows:

[0008] Step 1: Establish a large-signal equivalent circuit model containing GaN HEMT switching oscillation parameters;

[0009] Step 2: Design a half-bridge dual-pulse test circuit based on the large-signal equivalent circuit model. Use an adjustable capacitor to change the external capacitor value, and obtain the partial drain-source voltage V through actual measurement.DS The gate-source voltage waveform is obtained, and the extreme values ​​of the gate-source voltage V are obtained. GS_m ;

[0010] Step 3: Based on the external capacitance value and drain-source voltage V obtained in Step 2 DS and gate-source voltage extreme value V GS_m Construct a dataset, build an error function and training set based on the BPNN network model, and obtain the preliminary mapping relationship between parasitic capacitance and gate-source voltage based on the BPNN model by training neurons;

[0011] Step 4: Establish the GaN HEMT two-port network function. First, use ADS software to simulate the S-parameters of the network function model. Then, obtain the parasitic capacitance value of the GaN HEMT device under the full S-parameters through experiments. Input the extracted parasitic capacitance value as a dataset into the BPNN network model in Step 3 to obtain the gate-source voltage extreme value V. GS_m With drain-source voltage V under all S parameters DS The relationship between the surface and curve of parasitic capacitance.

[0012] Optionally, step one employs a large-signal equivalent circuit model of a Cascode-type GaN HEMT device, including:

[0013] (1) Establish a Cascode-type GaN HEMT half-bridge dual-pulse test circuit;

[0014] The Cascode-type GaN HEMT half-bridge dual-pulse test circuit diagram includes: V DC V is the total voltage applied across the drain and source terminals of the switching transistor. GL This is the driving voltage for the lower transistor;

[0015] Q1 is the upper tube, Q2 is the lower tube, R G_H R G_L R represents the external parasitic resistance of the upper and lower transistors, respectively. in_H R in_L The internal parasitic resistances of the upper and lower transistors are L and L, respectively. G_H and L G_L These are the parasitic inductances in the drive circuits of the upper and lower transistors, respectively, L. S_H L is the parasitic inductance between the two switching transistors. S_L L is the parasitic inductance between the lower tube and ground. D_H C is the parasitic inductance of the drain of the upper transistor. GS_H C GD_H C DS_H It is the inherent internal parasitic capacitance of the upper transistor Q1, C GS_L C GD_L C DS_L It is the inherent internal parasitic capacitance of the lower transistor Q2;

[0016] The lower transistor Q2 is used as the test transistor, L and C are the load inductance and load capacitance, respectively, and I... L This is the load current flowing through Q2;

[0017] (2) Establish an equivalent model of the half-bridge drive circuit in the Cascode type GaN HEMT with the lower transistor turned on;

[0018] The drive circuit model is derived from parameter analysis and circuit equivalence of an actual half-bridge dual-pulse test circuit. The simplified drive circuit model includes: the drive voltage V of the lower transistor. GL Parasitic resistance R inside the lower tube in_L External parasitic resistance R G Parasitic inductance L in the drive circuit S and L G GaN HEMT's inherent internal parasitic capacitance C GS V GS The parasitic capacitance C in the drive circuit GS Voltage at both ends;

[0019] Among them, the driving voltage V of the lower transistor GL One end is connected in series with the parasitic resistance R inside the lower tube. in_L External parasitic resistance R G Gate parasitic inductance L G and the parasitic capacitance C between the internal gate and source. GS The charging terminal is connected to the internal gate-source parasitic capacitance C. GS The discharge terminal and source parasitic inductance L S Connected, the driving voltage V GL The other end is grounded, and the voltage and current formulas of the simplified drive circuit model in the lower transistor's on state are as follows:

[0020]

[0021]

[0022] V GD =V GS -V DS (3)

[0023]

[0024] Optionally, in step two, the extreme value V of the gate-source voltage is obtained. GS_m The process includes:

[0025] A double-pulse experiment was performed on the Cascode-type GaN HEMT. Based on the simplified driving circuit model, multiple sets of different drain-source voltages V were set.DS Use an oscilloscope to test the gate-source voltage V when the lower transistor is turned on. GS Partial oscillation waveforms were obtained at different drain-source voltages V. DS Lower gate-source voltage V GS The waveform test diagram of (t) is then used to determine the maximum gate-source voltage V under various conditions. GS_m As the true value of the output layer of the BP neural network.

[0026] Optionally, the BP neural network includes: an input layer, a first hidden layer, a second hidden layer, and an output layer;

[0027] The parasitic capacitance C between the gate and source in the BP neural network model GS Parasitic capacitance C between the gate and drain GD With gate-source voltage extreme value V GS_m The mapping expression is:

[0028]

[0029]

[0030]

[0031] Where N is the number of neurons in the first hidden layer, M is the number of neurons in the second hidden layer, b3 is the output deviation, and b 1j It is the bias of the first hidden layer, b 2i It is the bias of the second hidden layer, ω 1ij and ω 2ij These are the weights of the j-th and i-th neurons in the inputs of the first and second hidden layers, respectively, where i = 1, 2, ..., M, j = 1, 2, ..., N;

[0032] Output of a single neuron For weight ω i And a linear combination of input variables, This is the output of the first hidden layer neural network. This is the output of the second hidden layer neural network.

[0033] Optionally, the BP neural network constructs the backpropagation process by building a mean squared error loss function, solving for the backpropagation error along the gradient descent direction, and solving for the error of each hidden layer, including:

[0034]

[0035] δ k =(o k -t k )o k (1-ok (9)

[0036]

[0037]

[0038]

[0039] Equation (8) is the mean squared error loss function MSE, where k represents the number of data in the output layer and xij represents the input. The MSE is used to set the integer weight ω to reduce the gap between the predicted value o and the true value t.

[0040] Equation (9) represents the transmission error of the output layer, δ k The meaning is to connect ω ij The contribution value to the error function;

[0041] Equation (10) represents the gradient descent formula, where η represents the learning rate;

[0042] Equations (11) and (12) represent the transmission error expressions for the first hidden layer and the second hidden layer, respectively, δ k δ j δ i These represent the transmission error functions of each node's network layer.

[0043] Optionally, the process of establishing the GaN HEMT two-port network function in step four includes:

[0044] Based on the structure of the Cascode GaN HEMT, the static large-signal parasitic parameter model circuit is established. The Z-impedance network is then established through this static large-signal parasitic parameter model to perform an equivalent RF S-parameter model.

[0045] The entire two-port network transformation process is shown in equations (15)-(31):

[0046]

[0047]

[0048]

[0049]

[0050]

[0051]

[0052] Z AB =Z 2Y +sL int1+Z 4Y (twenty one)

[0053] Z AC =Z 3Y +sL int3 +R int3 (twenty two)

[0054] Z BC =Z 6Y +sL int2 +R int2 (twenty three)

[0055]

[0056]

[0057]

[0058] Z P =Z A / / Z B / / Z C (27)

[0059]

[0060]

[0061]

[0062]

[0063] Among them, C GS_Si C is the Si parasitic capacitance between the gate and source. GD_Si C is the parasitic capacitance of Si between the gate and drain. DS_Si C is the parasitic capacitance of Si between the drain and source. GS_GaN C is the GaN parasitic capacitance between the gate and source. GD_GaN C is the GaN parasitic capacitance between the gate and drain. DS_GaN L is the GaN parasitic capacitance between the drain and source. int1 L is the parasitic inductance between drain and source. int2 For the parasitic inductance between the gate and source, L int3 R is the parasitic inductance between the gate and drain. int1 R is the parasitic resistance between source and drain. int2 L is the parasitic resistance between the gate and source. Gi L Si L Di These are the parasitic inductances of the gate, source, and drain terminals inside the device, respectively. G L S L DThese are the parasitic inductances of the gate, source, and drain terminals outside the device, respectively, V DS Bias voltage; Z 1Y -Z 6Y Z represents the equivalent impedance parameters of each port after the Laplace transform. AB Z AC Z BC Z A Z B Z C Z P For impedance transformation operator, Z 11 Z 12 Z 21 Z 22 These are the equivalent impedances after transformation by the two-port network;

[0064] This completes the process of establishing the Z-impedance network for the port network based on the static large-signal parasitic parameter model. Finally, the Z-impedance network is transformed into an S-parameter model, and the functional relationship between the S-parameters and the Z-impedance is shown in equations (32)-(35):

[0065]

[0066]

[0067]

[0068]

[0069] The S-parameter model of the two-port network function was simulated, and under thermal bias, GaN HEMT transistors were selected under different gate-source and drain-source voltages, with a frequency range f of 0.5-40GHz, and the S-parameter model of the two-port network was measured.

[0070] Optionally, in step four, obtaining the parasitic capacitance value of the GaN HEMT device under all S-parameters through experiments includes:

[0071] (1) By changing the external capacitor and drain-source voltage, the input dataset C of the initial BPNN model is obtained. GS C GD and V DS ;

[0072] Set the gate adjustable input capacitor C iss The output capacitor C is 14-100pF with adjustable gate-drain capacitance. OSS The value is 0-12pF; the external C is discretized using the parametric method. GS C GD V DSThe extracted data is read into the input layer of the BP neural network model, where: the input capacitance C iss Output capacitor C oss The relationship between the parasitic capacitance of GaN HEMT and the capacitance of GaN HEMT is shown in equations (36)-(38):

[0073] C iss =C GD +C GS (36)

[0074] C oss =C DS +C GD (37)

[0075] C rss =C GD (38)

[0076]

[0077]

[0078] (2) Extracting the parasitic capacitance parameter C of GaN-HEMT power devices under full S-parameters. GS C GD ;

[0079] After the back propagation process, the parasitic capacitance under full S-parameters is obtained through the S-parameter model of the two-port network function. The S-parameter model of the two-port network function is shown in equation (32-35). The S-parameter model of the two-port network is measured under RF conditions through experiments and compared with the simulation results obtained by ADS software. According to equation (15-31), the measured S-parameter relationship is converted into the impedance Z-parameter relationship in MathCAD, and then the Z-network function relationship is converted into the quantitative relationship of parasitic capacitance.

[0080] Optionally, the training process of the BP neural network includes:

[0081] (1) Construct the dataset;

[0082] A half-bridge dual-pulse test circuit was designed based on a large-signal circuit model, and the partial drain-source voltage V was obtained through actual measurement. DS The gate-source voltage waveform is obtained, and the extreme values ​​of the gate-source voltage V are obtained. GS_m Numerical value;

[0083] By using an adjustable capacitor to change the external capacitance value, the external capacitance parameter of the GaN HEMT switching oscillator circuit and the measured gate-source voltage extreme value V are compared. GS_m The data is input as a dataset into the BPNN algorithm model;

[0084] (2) Solve for the hidden layer and output layer of the BP neural network.

[0085] Use the extracted external capacitance value as a reference for V GS_m The dataset is used to pass the signal result to the output layer by multiplying the value of each layer by the corresponding weight and activation function in the hidden layer, thus obtaining the gate-source voltage V. GS And for the gate-source voltage V GS Perform the inverse Laplace transform, as shown in equation (13), to obtain the corresponding time-domain expression for the gate-source voltage V. GS (t), perform a partial differential operation with respect to t before the output layer node to obtain the extreme value V of the gate-source voltage. GS_m Parasitic capacitance C between gate and source GS Drain-source voltage V DS Parasitic capacitance C between the gate and drain GD The functional relationship;

[0086] (3) Solve for the deviation between the output layer and the expected output;

[0087] The extreme values ​​of the gate-source voltage V obtained by sampling are obtained through the backpropagation process. GS_m The true value is input into the BPNN network, the deviation between the expected output and the obtained output value is calculated, and the integer weights ω are set by the deviation value MSE to obtain the transmission error function of each network layer. The hidden layer error of each node in each layer is calculated iteratively, and then the gradient of the weight matrix ω of each layer is calculated. The network parameters are iteratively optimized using the gradient descent algorithm.

[0088] (4) Backpropagation, sample training;

[0089] Adjusting the corresponding weights ω according to the desired result completes one backpropagation and enters the next iteration until the convergence condition is met and the loop is exited.

[0090] The S-parameter model was improved by embedding a two-port network function during backpropagation. Data was repeatedly recorded and trained, with experimentally collected data points transferred to the training set. Training stopped after reaching a preset maximum number of iterations. Measured data was imported into MATLAB for backpropagation calculations, where the gate-source voltage extreme value V... GS_m As the true value of the output layer, it is used to solve the deviation between the output layer and the expected output, and then the weights and biases of the neurons are adjusted according to the hidden layer error formulas (11) and (12).

[0091] Optionally, the preset maximum number of iterations is 500.

[0092] Optionally, during the training process, the ratio of the training set, validation set, and test set is set to 70%, 15%, and 15%, respectively.

[0093] The beneficial effects of this invention are:

[0094] The switching oscillation prediction method of this invention designs a half-bridge dual-pulse test circuit based on a large-signal circuit model, uses an adjustable capacitor to change the external capacitance value, and compares the external capacitance value parameter of the GaN HEMT switching oscillation circuit with the measured V. GS_m Data was input as a dataset into the BPNN algorithm model, and the preliminary mapping relationship between parasitic capacitance and gate-source voltage was obtained by training neurons based on the BPNN model. A Cascode-based GaN HEMT two-port network function was established, and the parasitic capacitance values ​​of the GaN HEMT device under full S-parameters were obtained experimentally. These extracted parasitic capacitance values ​​were then input as a dataset into the trained BPNN network model to obtain the S-parameters under full bias and predict V. GS_m With C GS C GD This invention addresses the complex problem of nonlinear parameter fitting in the physical modeling of GaN-based wide-bandgap semiconductor devices, simulates the quantitative relationship of parasitic parameters under nonlinear bias conditions during device switching, and simplifies the experimental steps for extracting parasitic parameters during prediction. Compared with existing large-signal analysis methods, this method has smaller prediction errors and higher reliability for the extreme values ​​of gate-source voltage oscillations during switching. Attached Figure Description

[0095] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0096] Figure 1 This is a flowchart of the BP neural network algorithm of the present invention.

[0097] Figure 2 For different V of the present invention DS C GS C GD With V GS_m The fitted curve.

[0098] Figure 3 This is an equivalent model circuit diagram of the half-bridge drive circuit in the GaN-HEMT with the lower transistor on, according to an embodiment of the present invention.

[0099] Figure 4 This is a flowchart of the BP neural network model of the present invention.

[0100] Figure 5 V of the present invention GS_mWith parasitic capacitance C GS C GD and V DS The three-dimensional relational surface diagram.

[0101] Figure 6 This is the static large-signal parasitic parameter model of GaN HEMT under the ADS software of the present invention.

[0102] Figure 7 This is a diagram of a GaN HEMT half-bridge dual-pulse test circuit according to an embodiment of the present invention.

[0103] Figure 8 This is a block diagram of the experimental platform for extracting parasitic parameters from GaN chips according to an embodiment of the present invention.

[0104] Figure 9 This is a line graph showing the extraction of parasitic capacitance parameters based on the INN650D02 GaN chip according to the present invention.

[0105] Figure 10 For different V of the embodiments of the present invention DS Lower V GS Waveform test diagram of (t).

[0106] Figure 11 The Smith chart shows the comparison between the simulated S-parameters and measured parameters of GaN HEMT in an embodiment of the present invention.

[0107] Figure 12 This is a comparison chart of the prediction errors of BPNN, ANN, and PSO in an embodiment of the present invention. Detailed Implementation

[0108] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0109] Example 1:

[0110] This embodiment provides a method for detecting GaN-HEMT gate switch oscillations, see [link to relevant documentation]. Figure 1 The method includes:

[0111] Step 1: Establish a large-signal equivalent circuit model containing GaN HEMT switching oscillation parameters;

[0112] Step 2: Design a half-bridge dual-pulse test circuit based on the large-signal equivalent circuit model. Use an adjustable capacitor to change the external capacitor value, and obtain the partial drain-source voltage V through actual measurement. DS The gate-source voltage waveform is obtained, and the extreme values ​​of the gate-source voltage V are obtained. GS_m ;

[0113] Step 3: Based on the external capacitance value and drain-source voltage V obtained in Step 2 DS and gate-source voltage extreme value V GS_m Construct a dataset, build an error function and training set based on the BPNN network model, and obtain the preliminary mapping relationship between parasitic capacitance and gate-source voltage based on the BPNN model by training neurons;

[0114] Step 4: Establish the GaN HEMT two-port network function. First, use ADS software to simulate the S-parameters of the network function model. Then, obtain the parasitic capacitance value of the GaN HEMT device under the full S-parameters through experiments. Input the extracted parasitic capacitance value as a dataset into the BPNN network model in Step 3 to obtain the gate-source voltage extreme value V. GS_m With drain-source voltage V under all S parameters DS The relationship between the surface and curve of parasitic capacitance.

[0115] Example 2:

[0116] This embodiment provides a training method based on a BP neural network, which is used to predict gate switch oscillations in GaN-HEMT systems. The method includes the following steps:

[0117] Step 1: Construct the dataset (C GS C GD V DS )

[0118] A half-bridge dual-pulse test circuit was designed based on a large-signal circuit model, and the partial drain-source bias voltage V was obtained through actual measurement. DS The gate-source voltage waveform is obtained, and the extreme values ​​of the gate-source voltage V are obtained. GS_m Numerical values. The external capacitance value is changed using an adjustable capacitor; this external capacitor in the large-signal circuit model is used to simulate the equivalent parasitic capacitance value of the GaN HEMT port. Recording is performed at different drain-source bias voltages V. DS Below, the equivalent parasitic capacitance C at the gate-source port of a GaN HEMT GS The equivalent parasitic capacitance C of the gate-drain port GD The values ​​are the external capacitance parameters of the GaN HEMT switching oscillator circuit and the measured V. GS_m The data is input as a dataset into the BPNN algorithm model.

[0119] Step 2: Solve for the hidden and output layers of the BP neural network.

[0120] Using the extracted parasitic capacitance C between the gate and source GS Parasitic capacitance C between the gate and drain GD As for V GS_mThe dataset is used to pass the signal result to the output layer by multiplying the value of each layer by the corresponding weight and activation function in the hidden layer, thus obtaining V. GS and V GS Perform the inverse Laplace transform, as shown in equation (4), to obtain the corresponding time-domain expression V. GS (t), perform a partial differential operation on t before the output layer node to obtain V. GS( The maximum value of t) and C GS V DS and C GD V DS The functional relationship. In actual propagation, the extracted C is used. GS and C GD As for V GS_m The training data, Equation (5) represents the neuron output after the activation function operation.

[0121] V GS (t)=L -1 [V GS (s)] (4)

[0122]

[0123] Step 3: Solve for the deviation between the output layer and the expected output.

[0124] In this embodiment, the maximum value V of the gate-source voltage obtained by sampling is obtained through a backpropagation process. GS_m The true values ​​are input into the BPNN network, the deviation between the expected output and the calculated output value is calculated, and the integer weights ω are set using the deviation value MSE. The learning rate is set to 0.6, and the transmission error function of each network layer is obtained. The hidden layer error of each node in each layer is iteratively calculated, and then the gradient of the weight matrix ω of each layer is calculated. The gradient descent algorithm is then used to iteratively optimize the network parameters. Figure 1 The flowchart of the BP neural network algorithm of the present invention is shown. The above backpropagation algorithm is implemented by programming in MATLAB software.

[0125] Step 4: Backpropagation, Sample Training

[0126] In this embodiment, adjusting the weights ω according to the desired result completes one backpropagation iteration and proceeds to the next iteration until the convergence condition is met, at which point the loop exits. The S-parameter model is improved by embedding a two-port network function during backpropagation. Data is repeatedly recorded and trained, experimentally collected data points are transferred to the training set, and a maximum of 500 iterations is set, stopping training after 500 iterations. The measured data is imported into MATLAB for backpropagation calculations, where V... GS_mThe true values ​​of the output layer are used to calculate the deviation between the output layer and the expected output. Then, the weights and biases of the neurons are adjusted according to the hidden layer error formulas (16) and (17), and the ratios of the training set, validation set, and test set are adjusted to 70%, 15%, and 15%, respectively. Figure 2 For different V of the present invention DS C GS C GD With V GS_m The fitted curve is the output result obtained in MATLAB. The results show that V GS_m The changes are always related to V DS Maintaining a positive correlation, C GS With V GS_m First increase, then decrease; C GD With V GS_m The fitting results are consistent with the actual data collection and analysis results.

[0127] The large-signal equivalent circuit model in step 1 is the equivalent model of the GaN HEMT half-bridge drive circuit in the on state. Figure 3 This is an equivalent model circuit diagram of the half-bridge drive circuit in the GaN HEMT with the lower transistor in the on state, according to this embodiment. Its simplified drive circuit model includes: the drive voltage V of the lower transistor. GL Parasitic resistance R inside the lower tube in_L External parasitic resistance R G Parasitic inductance L in the drive circuit S and L G GaN HEMT's inherent internal parasitic capacitance C GS V GS The parasitic capacitance C in the drive circuit GS Voltage at both ends.

[0128] Among them, the driving voltage V GL One end is connected in series with the internal parasitic resistance R of the lower tube. in_L External parasitic resistance R G Parasitic inductance L G and with internal parasitic capacitance C GS Connect to the charging port, C GS The discharge terminal and parasitic inductance L S Connected, driving voltage V GL The other end is grounded.

[0129] The gate driver sends a pulse signal to drive the voltage signal V. GL Set to high level to enable the conduction process of the lower transistor Q2. After the turn-on delay phase, the drive current is the gate-source capacitance C. GS_L Charging, current flows through R G_L L S LG Upon reaching ground, the switching transistor gradually turns on, causing V to... DS Gradually decreasing, V GS After passing the Miller plateau, the voltage continues to rise to the gate drive voltage, ending the transistor's turn-on process. During this stage, V... GS Oscillations will occur due to the influence of high dv / dt.

[0130] The simplified driving circuit model in step 1 provides the following voltage and current formulas for the lower transistor in the on state:

[0131]

[0132]

[0133] V GD =V GS -V DS (8)

[0134]

[0135] Figure 4 This is a flowchart of the BP neural network model in step 2 of this embodiment, including: N is the number of neurons in the first hidden layer, M is the number of neurons in the second hidden layer, b3 is the output bias, and ω... 3i It is the weight of the output of the i-th neuron in the second hidden layer, b 1j It is the bias of the first hidden layer, b 2i It is the bias of the second hidden layer, ω 1ij and ω 2ij The weights of the first and second hidden layers are ω, respectively. 1ij and ω 2ij These are the weights of the j-th and i-th neurons in the inputs of the first and second hidden layers, respectively (i = 1, 2, ..., M and j = 1, 2, ..., N). The output of a single neuron... For weight ω i And a linear combination of input variables, This is the output of the first hidden layer neural network. This is the output of the second hidden layer neural network. Equation (10-12) is the expression for the mapping relationship between parasitic capacitance and gate-source voltage based on this BPNN model:

[0136]

[0137]

[0138]

[0139] The backpropagation process of the BP neural network model in step 3 includes: constructing the mean squared error loss function, solving for the backpropagation error along the gradient descent direction, and solving for the error of each hidden layer, as shown in equations (13-17).

[0140]

[0141] δ k =(o k -t k )o k (1-o k (14)

[0142]

[0143]

[0144]

[0145] Equation (13) is the mean squared error loss function (MSE), where k represents the number of data points in the output layer, and xij represents the input. The MSE is used to set the integer weight ω, reducing the gap between the predicted value o and the true value t. Equation (14) represents the transmission error of the output layer, where δk represents the contribution of connection ωij to the error function. Equation (15) represents the gradient descent formula of the algorithm, where η represents the learning rate, set to 0.6. Equations (16) and (17) represent the transmission error expressions for hidden layer 1 and hidden layer 2, respectively. δk, δj, and δi represent the transmission error functions of each node's network layer, and the final measured V... GS_m After importing the data into MATLAB and performing backpropagation, the fitting results are obtained. Figure 5 This indicates that after backpropagation, V GS_m With parasitic capacitance C respectively GS C GD and V DS A three-dimensional relational surface plot. (From...) Figure 5 (a) We can obtain V GS_m The changes are always related to V DS Maintain a positive correlation, and when C GS Below 80 pF, V GS_m Follow C GS It first increases slowly, then levels off, and then increases rapidly; from Figure 5 (b) It can be obtained that in C GD Within the interval less than 10pF, when C GD When it is small, V GS_m Basically unchanged, when C GD As it gradually increases, V GS_m Slight increase. Figure 5(c) shows the input parasitic capacitance and V after backpropagation following coordinate transformation. GS_m The three-dimensional surface result, which is consistent with the above V GS_m With C GS and C GD The trends are basically consistent, indicating that the data in the training set correctly realized the mapping relationship between input and output during backpropagation.

[0146] The two-port network function in step 4 is a Z-impedance network established based on the GaN HEMT static large-signal parasitic parameter model, thereby equivalently representing the RF S-parameter model. The GaN HEMT static large-signal parasitic parameter model is as follows: Figure 6 As shown, where C GS_Si C is the Si parasitic capacitance between the gate and source. GD_Si C is the parasitic capacitance of Si between the gate and drain. DS_Si C is the parasitic capacitance of Si between the drain and source. GS_GaN C is the GaN parasitic capacitance between the gate and source. GD_GaN C is the GaN parasitic capacitance between the gate and drain. DS_GaN L is the GaN parasitic capacitance between the drain and source. int1 L is the parasitic inductance between drain and source. int2 For the parasitic inductance between the gate and source, L int3 R is the parasitic inductance between the gate and drain. int1 R is the parasitic resistance between source and drain. int2 L is the parasitic resistance between the gate and source. Gi L Si L Di These are the parasitic inductances of the gate, source, and drain terminals inside the device, respectively. G L S L D These are the parasitic inductances of the gate, source, and drain terminals outside the device, respectively, V DS Bias voltage, Z 1Y -Z 6Y Z represents the equivalent impedance parameters of each port after the Laplace transform. AB Z AC Z BC Z A Z B Z C Z P For impedance transformation operator, Z 11 Z 12 Z 21 Z 22The equivalent impedances after transformation by the two-port network are shown in equations (18)-(34). This completes the process of establishing the Z-impedance network of the port network based on the static large-signal parasitic parameter model. Finally, the Z-impedance network is transformed into an S-parameter model, and the functional relationship between the S-parameters and the Z-impedance is shown in equations (35)-(38). The model embedding process of this two-port network function is performed in the RF simulation software ADS, and the simulation sweep frequency range is set to 300KHz-18GHz.

[0147]

[0148]

[0149]

[0150]

[0151]

[0152]

[0153] Z AB =Z 2Y +sL int1 +Z 4Y (twenty four)

[0154] Z AC =Z 3Y +sL int3 +R int3 (25)

[0155] Z BC =Z 6Y +sL int2 +R int2 (26)

[0156]

[0157]

[0158]

[0159] Z P =Z A / / Z B / / Z C (30)

[0160]

[0161]

[0162]

[0163]

[0164]

[0165]

[0166]

[0167]

[0168] Example 3:

[0169] The detection method for GaN-HEMT gate switch oscillation in this embodiment uses the large-signal equivalent circuit model of Cascode-type GaN HEMT devices.

[0170] The GaN HEMT half-bridge dual-pulse test circuit diagram in this embodiment (dual-pulse testing is a widely used test method for evaluating the characteristics of power switching components such as MOSFETs and IGBTs; this test can evaluate the switching characteristics of the target component) is shown below. Figure 7 As shown: V DC V is the total voltage applied across the drain and source terminals of the switching transistor. GL This is the drive voltage for the lower transistor. Q1 is the upper transistor, Q2 is the lower transistor, and R... G_H R G_L R represents the external parasitic resistance of the upper and lower transistors, respectively. in_H R in_L The internal parasitic resistances of the upper and lower transistors are L and L, respectively. G_H and L G_L These are the parasitic inductances in the drive circuits of the upper and lower transistors, respectively, L. S_H L is the parasitic inductance between the two switching transistors. S_L L is the parasitic inductance between the lower tube and ground. D_H C is the parasitic inductance of the drain of the upper transistor. GS_H C GD_H C DS_H It is the inherent internal parasitic capacitance of the upper transistor Q1, C GS_L C GD_L C DS_L This is the inherent internal parasitic capacitance of the lower transistor Q2. When the lower transistor Q2 is used as the test transistor, L and C represent the load inductance and load capacitance, respectively, and I... L This is the load current flowing through Q2. The gate adjustable input capacitor C is also set. iss The output capacitor C is 14-100pF with adjustable gate-drain capacitance. OSS The value is 0-12 pF. The external C is then processed using the parametric discretization method (a data sampling and processing method). GS CGD V DS The extracted data is read into the input layer of the BP neural network model.

[0171] C iss =C GD +C GS (39)

[0172] C oss =C DS +C GD (40)

[0173] C rss =C GD (41)

[0174]

[0175]

[0176] Step 1: Obtain the C of the GaN-HEMT device under test GS C GD and V DS This includes the following steps:

[0177] (1) By changing the external capacitor and drain-source voltage, the values ​​of different C values ​​can be extracted. GS C GD 、 and V DS Maximum gate-source voltage V of GaN-HEMT power device under certain conditions GS_m The true value;

[0178] A double-pulse experiment was performed on GaN HEMT. Figure 8 For this embodiment, in different V DS Lower V GS Waveform test diagram (t): The GaN power transistor used is Innoscience model INN650D02, the GaN HEMT gate driver chip is model SI8271GB-IS, the load capacitance is 10μF, the load inductance is 40μH, the gate adjustable input capacitance is 14-100pf, and the gate-drain adjustable capacitance is 0-12pF. V DS By changing the DC bias voltage V DC The connection method between devices is obtained according to the driving circuit model described in claim 2. In the gate driving resistor R... G Under the condition of 5Ω, set V DS The voltage levels are 40V, 60V, 80V, 100V, and 120V respectively. Use an oscilloscope to test the portion of the gate-source voltage V when the lower transistor is turned on. GS The oscillation waveform, and then the maximum gate-source voltage V under various conditions. GS_mAs the true value of the output layer of the BP neural network.

[0179] (2) Extracting the parasitic capacitance parameter C of GaN-HEMT power devices GS C GD and V DS (C GS The parasitic capacitance between the gate and source, C GD Parasitic capacitance between the gate and drain, V DS (The bias voltage applied between the source and drain);

[0180] Where: input capacitance C iss Output capacitor C oss The relationship between the parasitic capacitance of GaN HEMT and the capacitance of GaN HEMT is shown in equations (39)-(41):

[0181] After the backpropagation process, the parasitic capacitance under full S-parameter conditions is obtained through the S-parameter model of the two-port network function. The S-parameter model of the two-port network function is shown in equation (18-38). The S-parameter model of the two-port network is measured under RF conditions through experiments and compared with the simulation results obtained from ADS software. According to equation (18-38), the measured S-parameter relationship is converted into the impedance Z-parameter relationship in MathCAD, and then the Z-network function relationship is converted into the quantitative relationship of parasitic capacitance. C is extracted using an AM3200 RF device. GS and C GD About V DS The varying parameter sampling points are used to extract experimental setup platform block diagrams for GaN and other RF devices, as shown in the figure. Figure 9 As shown, the test platform mainly includes: an amplifier, two sets of isolators, two sets of T-biasers, two sets of couplers, a source regulator, a load tuner, and a 50-ohm load resistor. Figure 10 To finally obtain the parasitic capacitance C under all S-parameters GS and C GD .

[0182] Step 2: Take the C obtained in Step 1 GS C GD V DS The BP neural network is used for input training. The BP neural network responds to the input C. GS C GD and V DS We perform data training and ultimately obtain V under this method. GS_m Predictive models.

[0183] (1) Transfer data C GS C GD V DSThe input layer of the neural network model is read in, and MATLAB automatically constructs the dataset based on the desired model.

[0184] (2) The system initializes the weight matrix and assigns values ​​to the network weights and biases based on the preset conditions of the input dataset. It then runs the algorithm forward to calculate the output values ​​of each hidden layer and the output layer. In the hidden layers, the signal result is passed to the output layer by multiplying the value of each layer by the corresponding weight and activation function, resulting in V. GS_m The forward propagation output results.

[0185] (3) The backpropagation process of the BPNN model includes: constructing the mean squared error loss function, solving the backpropagation error along the gradient descent direction, solving the error of each hidden layer, and solving the deviation between the output layer and the expected output as shown in equations (13-17). The system, trained using the BP neural network method, can obtain a relatively accurate V. GS_m After determining the value, a cyclic simulation is implemented during the training of the neural network to organize the errors generated by the system. The error values ​​are then fed back to the output to adjust the weights of the neurons, thereby generating a neural network training set that can fit the system's mapping relationship.

[0186] (4) Adjust the weights ω of the obtained results to complete one backpropagation and proceed to the next iteration until the convergence condition is met and the loop is exited. This model continuously adjusts the neuron biases, repeatedly records and trains data, transmits experimentally collected data points to the training set, and sets a maximum of 500 iterations, stopping training after 500 iterations. The measured data is imported into MATLAB for backpropagation calculation, where V... GS_m The true values ​​of the output layer are used to calculate the deviation between the output layer and the expected output. Then, the weights and biases of the neurons are adjusted according to the hidden layer error formulas (16) and (17), and the ratios of the training set, validation set, and test set are adjusted to 70%, 15%, and 15%, respectively.

[0187] The measured S-parameter model in step one is: under thermal bias, selecting GaN HEMT transistors at gate voltage V... GS = -1.0V, V DS =20V; V GS = -1.75V, V DS =16V; V GS = -1.8V, V DS =15V; V GS =-1.2, V DS=20V; and with a bias state where the frequency range f is 0.5-40GHz, the S-parameter model of the two-port network proposed in this invention is simulated to obtain its simulated S-parameters. These simulated S-parameters are then compared with the measured parameters of the GaN HEMT transistor, as shown in the comparison curves. Figure 11 As shown (solid lines represent measured S-parameter data, circles represent simulation parameter data). Figure 10 The simulated S-parameters and the measured S-parameters show good consistency in the Smith chart.

[0188] Step two involves extracting, verifying, and predicting the data collected in the experiment. This includes verifying whether the output results converge and predicting the extreme values ​​of the gate-source voltage oscillations. During the BPNN propagation process, a Bayesian function-based neural network fitting toolbox is used to change the number of hidden neurons to improve accuracy and convergence, obtaining the same V... DS C GS With C GD The parameter values ​​are fitted to the curve. During sample training, the Dropout regularization method is used to discard some neurons whose predicted values ​​exceed the threshold to prevent overfitting of the parameters. The Dropout rate is set to (0.01, 0.25, 0.5).

[0189] To verify the reliability of the relationship between the device parasitic parameters extracted in the above steps and the gate-source voltage, and to accurately predict the misleading gate on-voltage extreme value, this step compares the relative errors of some predicted values ​​with the true values ​​using BPNN, ANN, and PSO algorithms. Figure 12 It can be seen that the standard error of BPNN prediction is smaller than that of ANN and PSO, which proves that the BPNN algorithm model used in this invention has high prediction accuracy.

[0190] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0191] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for predicting GaN-HEMT gate switch oscillation, characterized in that, The method includes: Step 1: Establish a large-signal equivalent circuit model containing GaN HEMT switching oscillation parameters; Step 2: Design a half-bridge dual-pulse test circuit based on the large-signal equivalent circuit model. Use an adjustable capacitor to change the external capacitor value, and obtain the partial drain-source voltage V through actual measurement. DS The gate-source voltage waveform is obtained, and the extreme values ​​of the gate-source voltage V are obtained. GS_m ; Step 3: Based on the external capacitance value and drain-source voltage V obtained in Step 2 DS and gate-source voltage extreme value V GS_m Construct a dataset, build an error function and training set based on the BPNN network model, and obtain the preliminary mapping relationship between parasitic capacitance and gate-source voltage based on the BPNN model by training neurons; Step 4: Establish the GaN HEMT two-port network function. First, use ADS software to simulate the S-parameters of the network function model. Then, obtain the parasitic capacitance value of the GaN HEMT device under the full S-parameters through experiments. Input the extracted parasitic capacitance value as a dataset into the BPNN network model in Step 3 to obtain the gate-source voltage extreme value V. GS_m With drain-source voltage V under all S parameters DS The relationship between the surface and curve of parasitic capacitance; The BPNN network includes: an input layer, a first hidden layer, a second hidden layer, and an output layer; The parasitic capacitance between the gate and source in the BPNN network model Parasitic capacitance between gate and drain With gate-source voltage extreme values The mapping expression is: (5) (6) (7) in, N It is the number of neurons in the first hidden layer. M It is the number of neurons in the second hidden layer. b 3 represents the output deviation. b 1j It is the bias of the first hidden layer. b 2i It is the bias of the second hidden layer. ω 1ij and ω 2ij These are the weights of the neurons in the inputs of the first and second hidden layers, respectively. i =1.2,…, M , j =1.2,.., N ; Output of a single neuron φ i For weight ω i And a linear combination of input variables, φ 1j This is the output of the first hidden layer neural network. φ 2i This is the output of the second hidden layer neural network.

2. The method for predicting GaN-HEMT gate switch oscillation according to claim 1, characterized in that, Step one employs a large-signal equivalent circuit model of a Cascode-type GaN HEMT device, including: (1) Establish a Cascode-type GaN HEMT half-bridge dual-pulse test circuit; The Cascode-type GaN HEMT half-bridge dual-pulse test circuit diagram includes: V DC V is the total voltage applied across the drain and source terminals of the switching transistor. GL This is the driving voltage for the lower transistor; Q1 is the upper tube, Q2 is the lower tube, R G_H R G_L R represents the external parasitic resistance of the upper and lower transistors, respectively. in_H R in_L The internal parasitic resistances of the upper and lower transistors are L and L, respectively. G_H and L G_L These are the parasitic inductances in the drive circuits of the upper and lower transistors, respectively, L. S_H L is the parasitic inductance between the two switching transistors. S_L L is the parasitic inductance between the lower tube and ground. D_H C is the parasitic inductance of the drain of the upper transistor. GS_H C GD_H C DS_H It is the inherent internal parasitic capacitance of the upper transistor Q1, C GS_L C GD_L C DS_L It is the inherent internal parasitic capacitance of the lower transistor Q2; The lower transistor Q2 is used as the test transistor, L and C are the load inductance and load capacitance, respectively, and I... L This is the load current flowing through Q2; (2) Establish an equivalent model of the half-bridge drive circuit in the Cascode type GaN HEMT with the lower transistor turned on; The drive circuit model is derived from parameter analysis and circuit equivalence of an actual half-bridge dual-pulse test circuit. The simplified drive circuit model includes: the drive voltage V of the lower transistor. GL Parasitic resistance R inside the lower tube in_L External parasitic resistance R G Parasitic inductance L in the drive circuit S and L G The inherent internal parasitic capacitance C of GaN HEMT GS V GS The parasitic capacitance C in the drive circuit GS Voltage at both ends; Among them, the driving voltage V of the lower transistor GL One end is connected in series with the parasitic resistance R inside the lower tube. in_L External parasitic resistance R G Gate parasitic inductance L G and the parasitic capacitance C between the internal gate and source. GS The charging terminal is connected to the internal gate-source parasitic capacitance C. GS The discharge terminal and source parasitic inductance L S Connected, the driving voltage V GL The other end is grounded, and the voltage and current formulas of the simplified drive circuit model in the lower transistor's on state are as follows: (1) (2) (3) (4) 3. The method for predicting GaN-HEMT gate switch oscillation according to claim 2, characterized in that, In step two, the extreme value V of the gate-source voltage is obtained. GS_m The process includes: A double-pulse experiment was performed on the Cascode-type GaN HEMT. Based on the simplified driving circuit model, multiple sets of different drain-source voltages V were set. DS Use an oscilloscope to test the gate-source voltage V when the lower transistor is turned on. GS Partial oscillation waveforms were obtained at different drain-source voltages V. DS Lower gate-source voltage V GS The waveform test diagram of (t) is then used to determine the maximum gate-source voltage V under various conditions. GS_m As the true value of the output layer of the BP neural network.

4. The method for predicting GaN-HEMT gate switch oscillation according to claim 3, characterized in that, The BP neural network constructs a backpropagation process by building a mean squared error loss function, solving for the backpropagation error along the gradient descent direction, and solving for the error of each hidden layer, including: (8) (9) (10) (11) (12) Equation (8) is the mean square error loss function MSE. k Represents the number of data items in the output layer. xij The input is represented by the MSE, which is used to set the integer weights. ω Narrowing the predicted value o Compared with the true value t The gap; Equation (9) represents the transmission error of the output layer. δ k The meaning is connection ω ij The contribution value to the error function; Equation (10) represents the gradient descent formula, where η Represents the learning rate; Equations (11) and (12) represent the transmission error expressions for the first hidden layer and the second hidden layer, respectively. δ k , δ j , δ i These represent the transmission error functions of each node's network layer.

5. The method for predicting GaN-HEMT gate switch oscillation according to claim 1, characterized in that, The process of establishing the GaN HEMT two-port network function in step four includes: Based on the structure of the Cascode GaN HEMT, the static large-signal parasitic parameter model circuit is established. The Z-impedance network is then established through this static large-signal parasitic parameter model to perform an equivalent RF S-parameter model. The entire two-port network transformation process is shown in equations (15)-(31): (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) in, C GS_Si This is the Si parasitic capacitance between the gate and source. C GD_Si This is the Si parasitic capacitance between the gate and drain. C DS_Si This is the Si parasitic capacitance between the drain and source. C GS_GaN This represents the GaN parasitic capacitance between the gate and source. C GD_GaN This represents the GaN parasitic capacitance between the gate and drain. C DS_GaN This is the GaN parasitic capacitance between the drain and source. L int1 The parasitic inductance between drain and source, L int2 For the parasitic inductance between the gate and source, L int3 The parasitic inductance between the gate and drain, R int1 For source-drain parasitic resistance, R int2 This refers to the parasitic resistance between the gate and source. L Gi , L Si , L Di These are the parasitic inductances of the gate, source, and drain electrodes inside the device, respectively. L G , L S , L D These are the parasitic inductances of the gate, source, and drain terminals outside the device, respectively. V DS Bias voltage; Z 1Y -Z 6Y These are the equivalent impedance parameters of each port after the Laplace transform. Z AB 、Z AC 、Z BC 、Z A 、Z B 、Z C 、Z P For impedance transformation operators, Z 11 、Z 12 、Z 21 、Z 22 These are the equivalent impedances after transformation by the two-port network; This completes the process of establishing the Z-impedance network for the port network based on the static large-signal parasitic parameter model. Finally, the Z-impedance network is transformed into an S-parameter model, and the functional relationship between the S-parameters and the Z-impedance is shown in equations (32)-(35): (32) (33) (34) (35) The S-parameter model of the network function at this port was simulated, and under thermal bias, the GaN HEMT transistor was tested at different gate-source voltages V. GS and drain-source voltage V DS Under the conditions, and frequency range f The S-parameter model of the two-port network was measured under bias conditions of 0.5-40 GHz.

6. The method for predicting GaN-HEMT gate switch oscillation according to claim 5, characterized in that, Step four involves obtaining the parasitic capacitance value of the GaN HEMT device under all S-parameters through experiments, including: (1) By changing the external capacitor and drain-source voltage, the input dataset of the initial BPNN model is obtained. C GS , C GD and V DS ; Set adjustable gate input capacitor C iss 14-100 pF, gate-drain adjustable output capacitor C OSS The value is 0-12 pF; the external parameter discretization method is used to determine the value. C GS , C GD , V DS The extracted data is read into the input layer of the BP neural network model, where: input capacitance C iss Output capacitor C oss The relationship between the parasitic capacitance of GaN HEMT and the capacitance of GaN HEMT is shown in equations (36)-(38): (36) (37) (38) (39) (40) (2) Extracting the parasitic capacitance parameters of GaN-HEMT power devices under full S-parameters C GS , C GD ; After the back propagation process, the parasitic capacitance under full S-parameters is obtained through the S-parameter model of the two-port network function. The S-parameter model of the two-port network function is shown in equation (32-35). The S-parameter model of the two-port network is measured under RF conditions through experiments and compared with the simulation results obtained by ADS software. According to equation (15-31), the measured S-parameter relationship is converted into the impedance Z-parameter relationship in MathCAD, and then the Z-network function relationship is converted into the quantitative relationship of parasitic capacitance.

7. The method for predicting GaN-HEMT gate switch oscillation according to claim 1, characterized in that, The training process of the BP neural network includes: (1) Construct the dataset; A half-bridge dual-pulse test circuit was designed based on a large-signal circuit model, and the partial drain-source voltage V was obtained through actual measurement. DS The gate-source voltage waveform is obtained, and the extreme values ​​of the gate-source voltage V are obtained. GS_m Numerical value; By using an adjustable capacitor to change the external capacitance value, the external capacitance parameter of the GaN HEMT switching oscillator circuit and the measured gate-source voltage extreme value V are compared. GS_m The data is input as a dataset into the BPNN algorithm model; (2) Solve for the hidden layer and output layer of the BP neural network. Use the extracted external capacitance value as a reference for V GS_m The dataset is used to pass the signal result to the output layer by multiplying the value of each layer by the corresponding weight and activation function in the hidden layer, thus obtaining the gate-source voltage V. GS and the gate-source voltage V GS Perform the inverse Laplace transform, as shown in equation (13), to obtain the corresponding time-domain expression for the gate-source voltage V. GS (t), perform a partial differential operation with respect to t before the output layer node to obtain the extreme value V of the gate-source voltage. GS_m Parasitic capacitance C between gate and source GS Drain-source voltage V DS Parasitic capacitance C between the gate and drain GD The functional relationship; (3) Solve for the deviation between the output layer and the expected output; The extreme values ​​of the gate-source voltage V obtained by sampling are obtained through the backpropagation process. GS_m The true value is input into the BPNN network, the deviation between the expected output and the obtained output value is calculated, and the integer weights ω are set by the deviation value MSE to obtain the transmission error function of each network layer. The hidden layer error of each node in each layer is calculated iteratively, and then the gradient of the weight matrix ω of each layer is calculated. The network parameters are iteratively optimized using the gradient descent algorithm. (4) Backpropagation, sample training; Adjusting the corresponding weights ω according to the desired result completes one backpropagation and enters the next iteration until the convergence condition is met and the loop is exited. The S-parameter model was improved by embedding a two-port network function during backpropagation. Data was repeatedly recorded and trained, with experimentally collected data points transferred to the training set. Training stopped after reaching a preset maximum number of iterations. Measured data was imported into MATLAB for backpropagation calculations, where the gate-source voltage extreme value V... GS_m As the true value of the output layer, it is used to solve the deviation between the output layer and the expected output, and then the weights and biases of the neurons are adjusted according to the hidden layer error formulas (11) and (12).

8. The method for predicting GaN-HEMT gate switch oscillation according to claim 7, characterized in that, The preset maximum number of iterations is 500.

9. The method for predicting GaN-HEMT gate switch oscillation according to claim 7, characterized in that, During the training process, the ratio of training set, validation set, and test set is set to 70%, 15%, and 15%, respectively.

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