Ion trap chips and quantum computing devices

Abstract

The present invention discloses an ion trap chip and a quantum computing device, wherein the ion trap chip comprises: a non-conductive substrate; a radio frequency electrode, arranged on the upper surface of the non-conductive substrate; two groups of direct current electrodes, arranged on the upper surface of the non-conductive substrate and symmetrically distributed on both sides of two parallel wirings of the radio frequency electrode; and a first grounding electrode and a second grounding electrode, respectively arranged on the upper surface of the non-conductive substrate and the lower surface of the non-conductive substrate, the first grounding electrode being electrically connected to the second grounding electrode via a metal via hole provided in the first electrode and penetrating the non-conductive substrate. The ion trap chip proposed in the embodiment of the present invention can reduce the use of chip surface connection lines and improve the incident intensity of laser into the ion confinement region.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing, and in particular to an ion trap chip for trapping ions and a quantum computing device comprising the ion trap chip. Background Art

[0002] In the field of quantum computing, ion trap technology based on trapped ions is one of the mainstream technical paths to achieve quantum computing. It uses ions cooled to the ground state as quantum bits, and uses lasers to manipulate and read quantum bits. As an application form of linear ion trap structure, ion trap chips are the core device for precisely manipulating ions to achieve quantum computing. The setting of each electrical component on the chip will directly affect the performance of the chip, and then affect the core performance of quantum computing. Therefore, it is particularly important to reasonably design the connection method of each electrical component on the chip.

[0003] However, due to the complexity of connecting various electrical components on the ion trap chip, it is often necessary to set up multiple electrical connection lines. The use of connection lines often produces some defects such as solder chips and burrs on the chip surface, which not only affects the quality of the chip, but also blocks the laser directed to the ion trapping area, making the intensity of the laser entering the ion trapping area lower than the intensity of the laser directed to the chip surface, affecting the ion trapping effect. Summary of the invention

[0004] In view of the technical problems existing in the prior art, the present invention proposes an ion trap chip and a quantum computing device, which can reduce the use of connecting lines and improve the irradiation intensity of the laser irradiating the ion trapped area.

[0005] An embodiment of the present invention provides an ion trap chip, comprising: a non-conductive substrate; a radio frequency electrode, arranged on the upper surface of the non-conductive substrate; two groups of direct current electrodes, arranged on the upper surface of the non-conductive substrate and symmetrically distributed on both sides of two parallel wirings of the radio frequency electrode; and a first grounding electrode and a second grounding electrode, respectively arranged on the upper surface of the non-conductive substrate and the lower surface of the non-conductive substrate, the first grounding electrode being electrically connected to the second grounding electrode via a metal via provided in the first electrode and penetrating the non-conductive substrate, wherein the wiring of the first grounding electrode comprises two parts, the first part surrounding the first parallel wiring of the two parallel wirings of the radio frequency electrode and the first group of direct current electrodes distributed on one side of the first parallel wirings of the two groups of direct current electrodes, and the second part surrounding the second parallel wiring of the two parallel wirings of the radio frequency electrode and the second group of direct current electrodes distributed on one side of the second parallel wirings of the two groups of direct current electrodes, so that ions in the ion trap are confined within a predetermined distance above the interval between the two parallel wirings of the radio frequency electrode under the action of the electromagnetic field generated by the radio frequency electrode and the direct current electrode.

[0006] Optionally, the predetermined distance is between 60 μm and 100 μm.

[0007] Optionally, the non-conductive substrate is made of one of ceramics, silicon material, plastic and glass.

[0008] Optionally, the wiring of the first ground electrode passes through a gap between two parallel wirings of the radio frequency electrode.

[0009] Optionally, spacing grooves are provided between the first group of DC electrodes and the first parallel wirings, between the first parallel wirings and the wirings of the first grounding electrodes passing through the spacings, between the wirings of the first grounding electrodes passing through the spacings and the second parallel wirings, and between the second parallel wirings and the second group of DC electrodes, and the spacing grooves are formed in the non-conductive substrate.

[0010] Optionally, a radio frequency electrode feeding pad is provided on the lower surface of the non-conductive substrate, and the radio frequency electrode is electrically connected to the radio frequency electrode feeding pad via a metal via hole provided in the radio frequency electrode and penetrating the non-conductive substrate.

[0011] Optionally, a DC electrode feeding pad is provided on the lower surface of the non-conductive substrate, and the DC electrode is electrically connected to the DC electrode feeding pad via a metal via hole provided in the DC electrode and penetrating the non-conductive substrate.

[0012] Optionally, the first group of DC electrodes includes one or more DC electrodes, and the distances from the metal vias penetrating the non-conductive substrate in each DC electrode to the first parallel wiring are not equal.

[0013] Optionally, the second group of DC electrodes includes one or more DC electrodes, and the distances from the metal vias penetrating the non-conductive substrate in each DC electrode to the second parallel wiring are not equal.

[0014] Optionally, the RF electrode feeding pad is connected to a signal source via a coaxial line, and the impedance of the coaxial line is 45-55Ω.

[0015] The present invention also provides a quantum computing device, comprising the ion trap chip described above.

[0016] The ion trap chip proposed in the embodiment of the present invention is provided with a metal via that penetrates the non-conductive substrate. The metal via can electrically connect the electrical components located on the upper surface and the lower surface of the non-conductive substrate. This can avoid setting connecting lines on the upper surface of the ion trap chip, thereby reducing the welding shavings, burrs and other materials that affect the chip quality caused by setting the connecting circuits, thereby improving the process and quality of the ion trap chip. Furthermore, reducing the connecting lines on the upper surface of the chip can also reduce the shielding of the laser in the ion trap area by the electrical components, thereby improving the intensity of the laser entering the ion trap area. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0018] Figure 1 A schematic diagram of the three-dimensional structure of an ion trap chip according to an embodiment of the present invention is shown;

[0019] Figure 2 yes Figure 1 A view of the structure shown;

[0020] Figure 3 is a schematic diagram of the three-dimensional structure of an ion trap chip according to another embodiment of the present invention;

[0021] Figure 4 yes Figure 3 B-direction view (top view) of the structure shown;

[0022] Figure 5 yes Figure 3 A C-direction view (bottom view) of the structure shown;

[0023] Figure 6 yes Figure 3 D-direction view (side view) of the structure shown;

[0024] Figure 7 The main process flow chart of the ion trap chip of the present invention is schematically shown;

[0025] Figure 8 The diagram schematically shows the electric field intensity distribution of the confinement field along the X-axis direction;

[0026] Fig. 9 The magnetic field intensity distribution diagram of the confinement field along the X-axis direction is schematically shown;

[0027] Fig.10 The pseudopotential distribution diagram of the ion trap chip of the present invention at different frequencies is schematically shown;

[0028] Fig.11a The planar electric field distribution diagram when the ion height Z = 0.06 mm is shown;

[0029] Fig.11b shows the planar magnetic field distribution diagram when the ion height Z = 0.06 mm;

[0030] Fig.11c A schematic diagram of the magnetic field distribution when the ion height Z=0.06 mm is shown. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] In the following detailed description, reference may be made to the various drawings of the specification which are part of the present invention and which illustrate specific embodiments of the present invention. In the drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present invention are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present invention. It should be understood that other embodiments may also be utilized or structural, logical or electrical changes may be made to the embodiments of the present invention.

[0033] An embodiment of the present invention provides an ion trap chip, comprising: a non-conductive substrate; a radio frequency electrode, arranged on the upper surface of the non-conductive substrate; two groups of direct current electrodes, arranged on the upper surface of the non-conductive substrate and symmetrically distributed on both sides of two parallel wirings of the radio frequency electrode; and a first grounding electrode and a second grounding electrode, respectively arranged on the upper surface of the non-conductive substrate and the lower surface of the non-conductive substrate, the first grounding electrode being electrically connected to the second grounding electrode via a metal via provided in the first electrode and penetrating the non-conductive substrate, wherein the wiring of the first grounding electrode comprises two parts, the first part surrounding the first parallel wiring of the two parallel wirings of the radio frequency electrode and the first group of direct current electrodes distributed on one side of the first parallel wirings of the two groups of direct current electrodes, and the second part surrounding the second parallel wiring of the two parallel wirings of the radio frequency electrode and the second group of direct current electrodes distributed on one side of the second parallel wirings of the two groups of direct current electrodes, so that ions in the ion trap are confined within a predetermined distance above the interval between the two parallel wirings of the radio frequency electrode under the action of the electromagnetic field generated by the radio frequency electrode and the direct current electrode.

[0034] The ion trap chip proposed in the embodiment of the present invention is provided with a first grounding electrode and a second grounding electrode, and is also provided with a metal via penetrating the non-conductive substrate on the ion trap chip, the metal via being able to electrically connect the electrical components located on the upper surface and the lower surface of the non-conductive substrate, thereby avoiding the need to set connection lines on the upper surface of the ion trap chip, thereby reducing the welding shavings, burrs and other materials that affect the chip quality caused by setting the connection circuits, thereby improving the production quality of the ion trap chip, and reducing the number of connection lines on the upper surface of the chip, thereby reducing the shielding of the laser in the ion trap region by the electrical components, thereby improving the intensity of the laser entering the ion trap region.

[0035] In some embodiments of the present invention, optionally, the predetermined distance is between 60 μm and 100 μm. The distance between the ions in the ion trap and the upper surface of the ion trap chip above the interval between the first parallel wiring and the second parallel wiring is between 60 μm and 100 μm.

[0036] In some embodiments of the present invention, optionally, the non-conductive substrate is made of one of ceramic, silicon material, plastic and glass. The substrate is the bottom material of the ion trap chip, which mainly plays the role of physical support and heat conduction. The non-conductive substrate can better meet the application requirements of the ion trap chip of the present invention. Since the substrate of the ion trap chip is an insulating material, the RF voltage on the RF electrode will have a large loss on the substrate material, and the loss will increase as the RF voltage increases. Most of the RF loss will accumulate in the form of heat on the substrate material, thereby causing the surface electrode ion trap temperature to increase and affect the stability of the trapped ions. Preferably, in some embodiments, optionally, the non-conductive substrate is made of ceramic, and the loss angle of the substrate made of ceramic is small, which can reduce the loss of the RF electrode on the substrate material on the RF electrode and improve the stability of the ion trap chip trapped ions. In addition, the non-conductive substrate made of glass has a low heat loss when the ion trap chip is working, and has a small effect on the ion heating rate; the silicon-based substrate made of silicon material has the advantages of high mechanical strength and high compatibility with existing processes as the ion trap chip substrate of the present invention.

[0037] In some embodiments of the present invention, optionally, the wiring of the first ground electrode passes through a gap between two parallel wirings of the radio frequency electrode.

[0038] In the embodiment of the present invention, the wiring of the first ground electrode passes through the interval between the two parallel wirings of the RF electrode, and cooperates with other wirings of the first ground electrode to surround the two groups of DC electrodes, so that the periphery of the DC electrode is surrounded by an electric potential field, thereby improving the isolation between the RF electrode and the DC electrode and reducing the electromagnetic coupling effect between them.

[0039] In some embodiments of the present invention, optionally, spacing grooves are provided between the first group of DC electrodes and the first parallel wirings, between the first parallel wirings and the wirings of the first grounding electrodes passing through the spacings, between the wirings of the first grounding electrodes passing through the spacings and the second parallel wirings, and between the second parallel wirings and the second group of DC electrodes, and the spacing grooves are formed in the non-conductive substrate.

[0040] The reason for such arrangement is that the potential loss of the non-conductive substrate in the ion trap chip will reduce the potential well depth, and the power loss will accelerate the ion heating rate, while the potential loss is positively correlated with the substrate coupling capacitance, and the power loss is positively correlated with the substrate equivalent conductivity. The present invention proposes that arranging multiple spacing grooves on the ion trap chip can effectively reduce the potential loss and power loss of the substrate, thereby reducing the influence of the substrate on the potential well depth and the ion heating rate.

[0041] In some embodiments of the present invention, optionally, a RF electrode feeding pad is provided on the lower surface of the non-conductive substrate, and the RF electrode is electrically connected to the RF electrode feeding pad via a metal via hole provided in the RF electrode and penetrating the non-conductive substrate.

[0042] The radio frequency electrode proposed in the present invention is electrically connected to the radio frequency electrode feeding pad located on the lower surface of the chip through a metal via, which can reduce the use of connecting circuits, make the distribution and connection of electrical components on the ion trap chip simpler and neater, reduce the obstruction to laser irradiation, and improve the injection intensity of laser into the ion trap area. In addition, it can also reduce the number of connection circuits set on the ion trap chip, reduce the generation of welding chips and burrs, etc., so that the production quality of the chip can be improved.

[0043] In some embodiments of the present invention, optionally, a DC electrode feed pad is provided on the lower surface of the non-conductive substrate, and the DC electrode is electrically connected to the DC electrode feed pad via a metal via provided in the DC electrode and penetrating the non-conductive substrate.

[0044] The advantage of this arrangement is that the metal vias on the DC electrode enable the DC electrode feed pad to be electrically connected to the DC electrode in a relatively simple and compact manner, further reducing the number of connection circuits on the ion trap chip, reducing the generation of solder scraps and burrs, etc., and improving the production quality of the chip.

[0045] In some embodiments of the present invention, optionally, the first group of DC electrodes includes one or more DC electrodes, and the distances from the metal vias penetrating the non-conductive substrate in each DC electrode to the first parallel wiring are not equal.

[0046] The advantage of such a setting is that the setting position of the metal via on the DC electrode affects the distribution of the electric potential field between the DC electrode and the RF electrode. The distances from the metal via penetrating the non-conductive substrate in each DC electrode proposed by the present invention to the first parallel wiring are not equal (the connection line between the metal vias on each two adjacent DC electrodes is not parallel to the first parallel wiring), so that the distribution of the electric potential field between the DC electrode and the RF electrode meets the requirements of the electromagnetic field of the ion trapping region in the chip.

[0047] On the other hand, the distances from the metal vias on the DC electrodes to the first parallel wiring are not equal, which can prevent the DC electrode feed pads on the lower surface of the ion trap chip from being connected due to limited distribution range, thereby preventing the chip circuit short circuit caused by the DC electrode feed pad connection.

[0048] In some embodiments of the present invention, optionally, the second group of DC electrodes includes one or more DC electrodes, and the distances from the metal vias penetrating the non-conductive substrate in each DC electrode to the second parallel wiring are not equal.

[0049] The second group of DC electrodes are close to the second parallel wiring, and the distances from the metal vias in each DC electrode that penetrate the non-conductive substrate to the second parallel wiring are not equal. The setting principle and beneficial effects are the same as those of the first group of DC electrodes mentioned above, that is, not only can the distribution of the electric potential field between the DC electrode and the RF electrode meet the requirements of the electromagnetic field in the ion trapping area of ​​the chip, but it can also prevent the DC electrode feeding pad from being connected, thereby reducing the occurrence of short circuit problems.

[0050] In some embodiments of the present invention, optionally, the RF electrode feeding pad is connected to the signal source via a coaxial line, and the impedance of the coaxial line is 45-55Ω. For example, the impedance of the coaxial line can be 50Ω, and the RF electrode can maintain good impedance matching with the signal source through the 50Ω coaxial line excitation, thereby improving the efficiency of the input RF signal.

[0051] The present invention also provides a quantum computing device, which includes the ion trap chip described above.

[0052] The above describes the implementation method and technical advantages of the ion trap chip of the present invention through multiple embodiments. (Take ceramic substrate as an example) Describe the structure and usage of the ion trap chip.

[0053] Embodiment 1

[0054] As an example, Figure 1 FIG. 1 is a schematic diagram showing a three-dimensional structure of an ion trap chip 100 according to an embodiment of the present invention. Figure 2 yes Figure 1A-axis view of the structure shown. Figure 1 and Figure 2 As shown, the ion trap chip 100 includes a ceramic substrate 101, a radio frequency electrode 102, a plurality of direct current electrodes 103, a first ground electrode 104, a second ground electrode 105 and a plurality of metal vias 109, wherein the radio frequency electrode 102, the plurality of direct current electrodes 103 and the first ground electrode 104 are located on the upper surface 107 of the ceramic substrate 101. The second ground electrode 105 is located on the lower surface 108 of the ceramic substrate 101. In some embodiments, optionally, the first ground electrode 104 is a metal wiring, and preferably, the electrode on the ion trap chip of the present invention uses metal gold as the electrode material, so that the electrode will have high electrical conductivity and strong anti-oxidation and anti-corrosion capabilities. The first ground electrode 104 is electrically connected to the second ground electrode 105 via a metal via 109 that is arranged in the first electrode and penetrates the ceramic substrate.

[0055] The wiring of the first ground electrode 104 includes two parts, the first part 1041 surrounds the first parallel wiring 1021 of the two parallel wirings of the RF electrode and the first group of DC electrodes 201 distributed on one side of the first parallel wiring 1021 of the two groups of DC electrodes, and the second part 1042 surrounds the second parallel wiring 1022 of the two parallel wirings of the RF electrode 102 and the second group of DC electrodes 202 distributed on one side of the second parallel wiring 1022 of the two groups of DC electrodes, so that the ions in the ion trap are confined within a predetermined distance above the interval between the two parallel wirings of the RF electrode 102 under the action of the electromagnetic field generated by the RF electrode 102 and the DC electrode 103. In some embodiments of the present invention, optionally, the predetermined distance is between 60 μm and 100 μm.

[0056] exist Figure 1 In the embodiment, the number of the first group of DC electrodes 201 is equal to the number of the second group of DC electrodes 202, both of which are five. In addition, a plurality of metal vias 109 are also provided on the ion trap chip 100, and the plurality of metal vias 109 penetrate the ceramic substrate 101 to electrically connect the structure located on the upper surface 107 of the ceramic substrate 101 with the structure located on the lower surface 108 of the ceramic substrate 101. The use of metal vias penetrating the ceramic substrate actually forms a special circuit, which can realize the electrical connection of the electrical components on the upper surface of the ceramic substrate and the lower surface of the ceramic substrate, and can also reduce the setting of the connection lines on the ion trap chip, so that the circuit connection on the upper surface and the lower surface of the ion trap chip is cleaner and neater, and the blocking of the laser beam injected into the ion trap region by the electrical components is reduced.

[0057] In some embodiments of the present invention, optionally, a metal via 109 is provided on the first ground electrode 104, so that the first ground electrode 104 is electrically connected to the second ground electrode 105. Further, a metal via 109 may also be provided on the DC electrode 103, and the metal via 109 may realize electrical connection between the DC electrode feeding pad 110 on the lower surface 108 of the ceramic substrate 101 and the DC electrode 103.

[0058] In some embodiments of the present invention, optionally, in order to prevent the DC electrode feeding pads 110 from being connected together, in the first group of DC electrodes or the second group of DC electrodes, a plurality of DC electrodes 103 are arranged adjacent to each other in sequence, wherein the connection line between the metal vias 109 on each two adjacent DC electrodes is not parallel to the extension direction of the two parallel wirings (the first parallel wiring 1021 and the second parallel wiring 1022) of the RF electrode. Optionally, among the plurality of metal vias in the first group of DC electrodes 201 or the second group of DC electrodes 202, the first metal via 1091 is located in the center, and the vertical distance from the first metal via 1091 to the first parallel wiring 1021 or the second parallel wiring 1022 is the farthest. In some embodiments, optionally, among the multiple metal vias 109 in the first group of DC electrodes 201, the vertical distance from the metal via 109 on the DC electrode 103 located in the middle position to the first parallel wiring 1021 is the largest, and, among the multiple metal vias in the second group of DC electrodes 202, the vertical distance from the metal via 109 on the DC electrode 103 located in the middle position to the second parallel wiring 1022 is also the largest.

[0059] In some embodiments of the present invention, optionally, an RF electrode feeding pad 112 is provided on the lower surface 108 of the ceramic substrate, and a metal via 109 is opened on the RF electrode 102 , and the metal via 109 penetrates the ceramic substrate 101 to electrically connect the RF electrode 102 with the RF electrode feeding pad 112 .

[0060] In some embodiments of the present invention, the RF electrode feeding pad 112 is optionally connected to the signal source via a coaxial line, and the impedance of the coaxial line is 40-60Ω. For example, the impedance of the coaxial line may be 45Ω, 47Ω, 50Ω, 52Ω or 55Ω, etc.

[0061] In some embodiments of the present invention, optionally, the wiring 113 of the first ground electrode passes through a gap between two parallel wirings (the first parallel wiring 1021 and the second parallel wiring 1022 ) of the RF electrode 102 .

[0062] In some embodiments of the present invention, optionally, spacing grooves 301 are provided between the first group of DC electrodes 201 and the first parallel wiring 1021, between the first parallel wiring 1021 and the wiring 113 of the first grounding electrode passing through the spacing, between the wiring 113 of the first grounding electrode passing through the spacing and the second parallel wiring 1022, and between the second parallel wiring 1022 and the second group of DC electrodes 202, and the spacing grooves 301 are formed in the ceramic substrate 101.

[0063] Embodiment 2

[0064] Figure 3 It is a schematic diagram of the three-dimensional structure of another ion trap chip according to an embodiment of the present invention. Figure 4 yes Figure 3 B-direction view (top view) of the structure shown. Figure 5 yes Figure 3 C-direction view (bottom view) of the structure shown. Figure 6 yes Figure 3 D-direction view (side view) of the structure shown. Figure 3-6 As shown, the ion trap chip 20 includes: a radio frequency electrode module 21, a direct current electrode module 22, a ground electrode module 23, a plurality of ground vias 32 and a ceramic substrate 25, wherein the radio frequency electrode module 21, the direct current electrode module 22 and the ground electrode module 23 are all arranged on the ceramic substrate 25, wherein:

[0065] The ground electrode module 23 is arranged on the upper surface 26 and the lower surface 27 of the ceramic substrate 25. In some embodiments of the present invention, optionally, the wiring of the ground electrode module 23 located on the upper surface 26 includes two parts, the first part 61 surrounds the first parallel wiring 210 of the two parallel wirings of the RF electrode module 21 and the first group of DC electrodes 221 distributed on one side of the first parallel wiring 210 in the DC electrode module 22, and the second part 62 surrounds the second parallel wiring 211 of the two parallel wirings of the RF electrode module and the second group of DC electrodes 222 distributed on one side of the second parallel wiring 211 in the DC electrode module 22, so that the ions in the ion trap are confined within a predetermined distance above the interval between the two parallel wirings of the RF electrode under the action of the electromagnetic field generated by the RF electrode and the DC electrode.

[0066] Specifically, see Figure 3 As shown, the grounding electrode module 23 is a square frame structure, the first side 231 of the square frame has an opening 232, and the third side 233 opposite to the first side 231 has a wiring 230 of the first grounding module, and the wiring 230 is located between the first parallel wiring 210 and the second parallel wiring 211 of the RF electrode module. The grounding electrode module 23 located on the lower surface 27 of the ceramic substrate 25 covers the remaining portion of the lower surface 27 of the ceramic substrate excluding the feeding pad.

[0067] In some embodiments of the present invention, the grounding vias 32 pass through the ceramic substrate 25, connecting the grounding electrode module 23 on the upper surface 26 of the ion trap chip and the grounding electrode module 23 on the lower surface 27. The grounding vias 32 are arranged on the grounding electrode module 23 on the upper surface of the ion trap chip, and the diameters of the grounding vias 32 on the same side are equal and connected in a straight line. It should be noted that the grounding vias 32 are only provided on the third side 233 of the grounding module 23 and the two sides connected to the third side, and no grounding vias 32 are provided on the first side 231.

[0068] The radio frequency ground (ground electrode module, in some embodiments, the material is a metal plate) on the front (upper surface) of the ion trap chip proposed in the embodiment of the present invention is connected to the radio frequency ground (ground electrode module) on the back (lower surface) of the ion trap chip through a metal via (ground through hole), so that the DC electrode module is surrounded by the ground potential field, and the magnetic field of the DC electrode module can only affect the part close to the direction of the radio frequency electrode module, thereby improving the isolation between the radio frequency electrode and the DC electrode and reducing the electromagnetic coupling effect between them. At the same time, the current flowing through the substrate between the radio frequency electrode and the ground module is greatly reduced, and the thermal power consumption of the substrate is reduced.

[0069] Continue to see Figure 4 As shown, the DC electrode module 22 includes a plurality of DC electrodes 221. In some embodiments, optionally, the number of DC electrodes 221 is ten and evenly distributed in two rows, each row being a group of DC electrodes. The two groups of DC electrodes are respectively distributed on both sides of the first parallel wiring 210 and the second parallel wiring 211 of the RF electrode module, and are located on the inner side of the square structure of the ground electrode module 23. The DC electrode module 22 is spaced apart from the RF electrode module 21, that is, the DC electrode module 22 is spaced apart from the RF electrode module 21 by a preset distance, so that the distribution of the electric potential field meets the optimal requirements for trapped ions. In addition, in the two rows of DC electrodes, the DC electrode in the middle position has the smallest upper surface area.

[0070] In some embodiments of the present invention, optionally, the ion trap chip 20 further includes a DC electrode grounding via 31, and the DC electrode grounding via 31 passes through the DC electrode module 22 and the ceramic substrate 25 to connect with the DC electrode feed pad 29 on the back (lower surface) of the ion trap chip. Each DC electrode 221 is provided with a DC electrode grounding via 31, and a DC electrode feed pad 29 is provided on the lower surface of the ceramic substrate opposite to each DC electrode. When the DC electrode feed pad 29 is connected to the power supply, the power is conducted to the DC electrode 221 through the DC electrode grounding via 31.

[0071] In some embodiments of the present invention, optionally, an RF electrode metal via 30 is provided on the RF electrode wiring 212 on the common side of the first parallel wiring and the second parallel wiring, and the RF electrode metal via 30 penetrates the ceramic substrate 25 to electrically connect the RF electrode module 21 with the RF electrode feeding pad 28. After the RF electrode feeding pad 28 is connected to the power supply, the power is conducted to the top edge 212 of the RF electrode module through the RF electrode metal via 30, and then the power is conducted to the two free ends of the RF electrode module, and the RF electrode module 21 cooperates with the DC electrode module 22 to generate an electric potential field to trap the ions in the electric potential field.

[0072] In some embodiments of the present invention, optionally, the shortest distances of the multiple DC electrode grounding vias 31 from the RF electrode module 21 are different. The DC electrode grounding via 31 is located in the center of the DC electrode 221, and the shortest distance from the DC electrode grounding via 31 to the RF electrode module 21 is positively correlated with the distance from the DC electrode 221 to the RF electrode module. The shortest distances of the multiple DC electrode grounding vias provided in the present invention to the RF electrode are different, so that the distances from the DC electrode to the RF electrode are also different, so that the electric potential field formed between the DC electrode and the RF electrode can meet the requirements of the electric potential field for trapping ions, thereby improving the ion trapping effect.

[0073] In addition, Figure 3 and Figure 6 In order to facilitate observation and explanation, the positions and structures of vias (ground vias, DC electrode ground vias and RF electrode metal vias) are schematically shown. It can be seen that the vias penetrate and connect the upper and lower surfaces of the ceramic substrate, and can electrically connect the electrodes on the upper and lower surfaces of the ceramic substrate. Figure 4 In the embodiment, the inner diameter of the DC electrode grounding through hole is smaller than the inner diameter of the grounding through hole, and the inner diameter of the grounding through hole is larger than the inner diameter of the grounding through hole.

[0074] Embodiment 3

[0075] See also Figure 3 , 4 As shown in FIG. 6 , the present invention further proposes an ion trap chip, comprising: a radio frequency electrode module 21, a direct current electrode module 22, a spacing groove 51 and a ceramic substrate 25, wherein the radio frequency electrode module 21, the direct current electrode module 22 and the spacing groove 51 are all arranged on the ceramic substrate 25, wherein the spacing groove 51 separates the radio frequency electrode module 21 and the direct current electrode module 22. Figure 3 and Figure 6 , the position and structure of the isolation groove 51 are schematically shown. The isolation groove 51 has a certain depth. In the illustrated embodiment, the depth of the isolation groove is greater than the width.

[0076] In some embodiments of the present invention, optionally, the DC electrode module 22 includes a plurality of DC electrodes 71, the plurality of DC electrodes 71 are evenly divided into two rows of DC electrodes, and the two rows of DC electrodes each form a group; the RF electrode module 21 includes an RF electrode wiring 212 and two first parallel wirings 210 and second parallel wirings 211 vertically connected to the RF electrode wiring 212 and parallel to each other. The two groups of DC electrodes are respectively distributed on both sides of the two parallel wirings of the RF electrode.

[0077] Further, in some embodiments of the present invention, optionally, the number of the spacing grooves 51 is four, namely, the first spacing groove 511, the second spacing groove 512, the third spacing groove 513 and the fourth spacing groove 514. The first spacing groove 511 is arranged between the first group of DC electrodes 221 and the first parallel wiring 210 of the RF electrode module, the second spacing groove 512 is arranged between the first parallel wiring 210 of the RF electrode module and the wiring 230 of the first ground electrode, the third spacing groove 513 is arranged between the wiring 230 of the first ground electrode and the second parallel wiring 211 of the RF electrode module, and the fourth spacing groove 514 is arranged between the second parallel wiring 211 of the RF electrode module and the second group of DC electrodes 222, wherein the first group of DC electrodes 221 is close to the first parallel wiring 210 of the RF electrode module, and the second group of DC electrodes 222 is close to the second parallel wiring 211 of the RF electrode module.

[0078] The potential loss of the ceramic substrate of the ion trap chip proposed by the present invention will reduce the potential well depth, and the power loss will accelerate the ion heating rate, while the potential loss is positively correlated with the substrate coupling capacitance, and the power loss is positively correlated with the substrate equivalent conductance. In order to reduce the power loss and potential loss of the ion trap substrate, a plurality of isolation grooves are etched between the radio frequency electrode and the ground electrode on the substrate surface of the ion trap chip to achieve the purpose of reducing the substrate equivalent conductance and coupling capacitance.

[0079] In combination with the structures of the ion trap chips shown in the above embodiments, Figure 7 The main process flow chart of the ion trap chip of the present invention is schematically shown. Figure 7 As shown, the process of the ion trap of the present invention includes the following steps:

[0080] Step 1: Wafer cleaning: The purpose of wafer cleaning is to eliminate the impact of impurities on the wafer surface on the process.

[0081] Step 2: Two layers of metal are thermally evaporated on the surface of the substrate as the connecting layer between the substrate and the electrode and the growth layer for electroplating, so that metal electrodes can be electroplated on the surface of the non-metallic substrate.

[0082] Step 3: Perform photolithography according to the layout to form a photoresist barrier layer.

[0083] Step 4: Electroplating is performed to form a thick electrode.

[0084] Step 5: Strip the barrier layer and etch away the chromium as the connecting layer and the single layer of gold as the growth layer.

[0085] Step 6: Finally, bond it together with the chip pins to complete the entire surface electrode ion trap manufacturing process.

[0086] Figure 8 The electric field intensity distribution diagram of the trapped field along the X-axis is schematically shown. Figure 8 As shown, the electric field strength in region 801 is the strongest, ranging from approximately 7910 V / m to 10000 V / m; the electric field strength in region 802 ranges from approximately 3350 V / m to 7340 V / m; and the electric field strength in region 803 ranges from approximately 600 V / m to 1640 V / m. Fig. 9 The magnetic field intensity distribution diagram of the confinement field along the X-axis is schematically shown. Fig. 9 As shown, the magnetic field strength range of region 901 is approximately 10938.8047 A / m-50000 A / m; the magnetic field strength range of region 902 is approximately 397.1641 A / m-4774.9614 A / m, and the magnetic field strength range of region 903 is approximately 173.3684 A / m-50.0000 A / m. Fig.10 The pseudopotential distribution diagram of the ion trap chip of the present invention at different frequencies is schematically shown. Fig.10 It can be known that the ion trapping height Z = 0.06mm. Correspondingly, Fig.11a The planar electric field distribution diagram when the ion height Z = 0.06 mm is shown. Fig.11b The planar magnetic field distribution when the ion height Z = 0.06 mm is shown; Fig.11c The schematic diagram of magnetic field distribution when the ion height Z = 0.06 mm is shown. Figure 8-11c From the simulation results shown, it can be seen that the field distribution conforms to the parabolic confinement field required for ion trap confinement. Under 10MHz RF excitation, the pseudopotential size is 0.22meV.

[0087] Based on at least one of the above embodiments of the present invention, the ion trap chip proposed in the embodiment of the present invention can perfectly integrate the radio frequency electrode and the direct current electrode on a chip, and the preparation and installation are very convenient, and the surface trap has good scalability. Specifically, the ion trap chip proposed in the present invention is to prepare the metal electrode on the surface of the semiconductor substrate. Thanks to the mature semiconductor lithography technology, electrodes of various shapes can be prepared on the substrate. In addition, it is also very convenient to prepare a large number of identical electrodes, that is, it is easy to achieve the expansion of the number of ion trapping areas.

[0088] In addition, since the ion trap chip proposed by the present invention uses metal vias instead of connecting lines, the wiring circuits on the surface of the ion trap are reduced, which can not only reduce the generation of undesirable substances such as welding chips and burrs, but also reduce the obstruction of laser irradiation such as ion trapping areas caused by electrical components. Because in the "five-line" surface electrode ion trap structure, the optical path of the ion manipulation laser must be flat on the surface of the trap. Therefore, the use of connecting lines is reduced, which can significantly improve the intensity of the laser injected into the ion trap area and improve the quality of the ion trap chip.

[0089] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.

Claims

1. An ion trap chip, characterized in that: include: Non-conductive substrate; A radio frequency electrode is arranged on the upper surface of the non-conductive substrate; Two groups of DC electrodes are arranged on the upper surface of the non-conductive substrate and symmetrically distributed on both sides of the two parallel wirings of the RF electrodes; as well as a first ground electrode and a second ground electrode; The first ground electrode is respectively arranged on the upper surface of the non-conductive substrate and the lower surface of the non-conductive substrate, and the first ground electrode is electrically connected to the second ground electrode via a metal via hole provided in the first ground electrode and penetrating the non-conductive substrate. The wiring of the first grounding electrode includes two parts, the first part surrounds the first parallel wiring of the two parallel wirings of the RF electrode and the first group of DC electrodes distributed on one side of the first parallel wiring of the two groups of DC electrodes, and the second part surrounds the second parallel wiring of the two parallel wirings of the RF electrode and the second group of DC electrodes distributed on one side of the second parallel wiring of the two groups of DC electrodes, so that the ions in the ion trap are confined within a predetermined distance above the interval between the two parallel wirings of the RF electrode under the action of the electromagnetic field generated by the RF electrode and the DC electrode.

2. The ion trap chip according to claim 1, characterized in that: The predetermined distance is between 60 μm and 100 μm.

3. The ion trap chip according to claim 1, characterized in that: The non-conductive substrate is made of one of ceramic, silicon material, plastic and glass.

4. The ion trap chip according to claim 1, characterized in that: The wiring of the first ground electrode passes through a space between two parallel wirings of the radio frequency electrode.

5. The ion trap chip according to claim 4, characterized in that: Spacing grooves are provided between the first group of DC electrodes and the first parallel wirings, between the first parallel wirings and the wirings of the first grounding electrodes passing through the spacings, between the wirings of the first grounding electrodes passing through the spacings and the second parallel wirings, and between the second parallel wirings and the second group of DC electrodes, and the spacing grooves are formed in the non-conductive substrate.

6. The ion trap chip according to claim 1, characterized in that: A radio frequency electrode feeding pad is disposed on the lower surface of the non-conductive substrate, and the radio frequency electrode is electrically connected to the radio frequency electrode feeding pad via a metal via hole disposed in the radio frequency electrode and penetrating the non-conductive substrate.

7. The ion trap chip according to claim 1, characterized in that: A DC electrode feeding pad is disposed on the lower surface of the non-conductive substrate, and the DC electrode is electrically connected to the DC electrode feeding pad via a metal via hole disposed in the DC electrode and penetrating the non-conductive substrate.

8. The ion trap chip according to claim 1, characterized in that: The first group of DC electrodes includes one or more DC electrodes, and the distances from the metal vias penetrating the non-conductive substrate in each DC electrode to the first parallel wiring are not equal.

9. The ion trap chip according to claim 1, characterized in that: The second group of DC electrodes includes one or more DC electrodes, and the distances from the metal vias penetrating the non-conductive substrate in each DC electrode to the second parallel wiring are not equal.

10. The ion trap chip according to claim 6, characterized in that: The radio frequency electrode feeding pad is connected to a signal source via a coaxial line, and the impedance of the coaxial line is 45-55Ω.

11. A quantum computing device, characterized in that: An ion trap chip comprising any one of claims 1 to 10.

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