Pixel circuit and display panel

Abstract

A pixel circuit and a display panel are disclosed. The pixel circuit includes a light emitting element, a driving transistor, a first driving circuit and a second driving circuit. The light emitting element and the driving transistor are coupled in series between a power supply voltage and a reference ground voltage. The first driving circuit provides a driving current control signal to a control terminal of the driving transistor based on a first reference voltage and a second reference voltage. The second driving circuit is coupled to the first driving circuit. The second driving circuit provides a driving time control signal to the first driving circuit according to a modulation signal. The first driving circuit determines whether to enable the driving current control signal according to the driving time control signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a pixel circuit and a display panel, and in particular, to a pixel circuit and a display panel capable of reducing power consumption. BACKGROUND

[0002] Generally speaking, a display panel applying mini light emitting diodes (Mini LED) can control whether a driving current is output to a light emitting element by controlling whether a light emitting path is turned on or off through a switch and a driving transistor. However, since multiple electronic elements (including the switch, the driving transistor, and the light emitting element) are configured on the light emitting path, the power consumption of the driving current is increased, and the driving transistor can also operate in a linear region and is not easy to control the driving current.

[0003] In another aspect, some applications can control the size of the driving current by operating the driving transistor in a saturation region by increasing the voltage across the driving transistor. However, the aforementioned way of increasing the voltage increases the power consumption of the display panel. SUMMARY

[0004] Embodiments of the present application provide a pixel circuit capable of reducing the number of electronic elements on a light emitting path to reduce power consumption during operation.

[0005] The pixel circuit of embodiments of the present application includes a light emitting element, a driving transistor, a first driving circuit, and a second driving circuit. The light emitting element and the driving transistor are coupled in series between a power supply voltage and a reference ground voltage. The first driving circuit provides a driving current control signal to a control terminal of the driving transistor based on a first reference voltage and a second reference voltage. The second driving circuit is coupled to the first driving circuit. The second driving circuit provides a driving time control signal to the first driving circuit according to a modulation signal. The first driving circuit determines whether to enable the driving current control signal according to the driving time control signal.

[0006] Embodiments of the present application also provide a display panel. The display panel includes a pixel array and a control circuit. The pixel array includes a plurality of pixel circuits as described above. The control circuit is coupled to the pixel array. The control circuit provides a power supply voltage, a reference ground voltage, a first reference voltage, a second reference voltage, and a modulation signal to the pixel array.

[0007] Based on the above, the pixel circuit and the display panel of embodiments of the present application can reduce the number of electronic elements on the light emitting path by configuring only one driving transistor on the light emitting path, thereby reducing power consumption during operation. In addition, the pixel circuit can accurately control the size and output time of the driving current by providing a driving current control signal with a fixed current size through the first driving circuit and determining whether to enable the driving current control signal through the second driving circuit, thereby improving the consistency of the brightness of the display panel and reducing power consumption during operation.

[0008] In order to make the above features and advantages of the present application more apparent, the following detailed description is made with reference to the accompanying drawings, in which: BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a block diagram of a pixel circuit according to an embodiment of the present application.

[0010] Figure 2 is a circuit diagram of a pixel circuit according to an embodiment of the present application.

[0011] Figure 3 is a schematic diagram of an operation of a pixel circuit according to an embodiment of the present application. Figure 2

[0012] Figures 4A to 4E is a schematic diagram of an operation of a pixel circuit according to an embodiment of the present application. Figure 3

[0013] Figure 5 is a block diagram of a display panel according to an embodiment of the present application.

[0014] REFERENCE NUMERALS

[0015] 100, 200, 500: pixel circuit

[0016] 110, 210: light emitting element

[0017] 120, 230: drive transistor

[0018] 130, 230: first drive circuit

[0019] 140, 240: second drive circuit

[0020] 50: display panel

[0021] 510: pixel array

[0022] 520: control circuit

[0023] C1-C2: capacitor

[0024] EM[N]: light emission signal

[0025] F1-F2: image frame period

[0026] N1-N5: node

[0027] P_RT, P_CT, P_EM, P_TF: period

[0028] S1[N], S2[N]: control signal ​​

[0029] T1-T11: transistors

[0030] t1-t6: time

[0031] TD: drive transistor

[0032] VDATA: data signal

[0033] VDD: power supply voltage

[0034] VGH, VGL, VSWEEP H, VSWEEP M, VSWEEP L: voltage level

[0035] VREF, VREF2, VL, VLL: reference voltage

[0036] VSS: reference ground voltage

[0037] VSWEEP: modulation signal DETAILED DESCRIPTION

[0038] Embodiments of the present application will be described in detail below with reference to the attached drawings, which are incorporated in and constitute a part of this specification. The elements in the drawings that have the same function or are the same as those that have been described with reference to the previous drawings are denoted with the same reference numerals, and thus their repetitive description will be omitted. These embodiments are only a part of the embodiments of the present application, and do not disclose all the embodiments that can be implemented. Rather, these embodiments are only examples in the scope of the patent application of the present application.

[0039] Figure 1 is a block diagram of a pixel circuit according to an embodiment of the present application. Referring to Figure 1 , the pixel circuit 100 can be applied to a display device (e.g., a display panel) of a mini light emitting diode (Mini LED). The display device can include a plurality of pixel circuits 100 arranged in an array and a control circuit to drive the pixel circuits 100 according to a plurality of signals and / or voltages provided by the control circuit.

[0040] In the embodiment shown in Figure 1 , the pixel circuit 100 includes a light emitting element 110, a drive transistor 120, a first drive circuit 130, and a second drive circuit 140. The light emitting element 110 and the drive transistor 120 are coupled in series between a power supply voltage VDD and a reference ground voltage VSS.

[0041] It should be noted that only one driving transistor 120 is configured between the power supply voltage VDD and the reference ground voltage VSS to drive the light emitting element 110. That is, in the light emitting path, the driving current only flows through the one driving transistor 120 and the light emitting element 110, without flowing through other transistors. In this way, the required voltage across between the power supply voltage VDD and the reference ground voltage VSS can be reduced to reduce the power consumption of the pixel circuit 100.

[0042] In the present embodiment, a first driving circuit 130 is coupled to the driving transistor 120. The first driving circuit 130 can receive a reference voltage VREF, VREF2. The first driving circuit 130 can provide a driving current control signal (not shown) to the control terminal of the driving transistor 120 based on the reference voltage VREF and the reference voltage VREF2. That is, the first driving circuit 130 can generate the driving current control signal with a fixed current value to cause the driving transistor 120 to operate according to the driving current control signal. The aforementioned fixed current value is related to the reference voltage VREF and the reference voltage VREF2. In the present embodiment, the first driving circuit 150 can be, for example, a pulse-amplitude modulation (PAM) circuit to control the current size of the driving current.

[0043] In the present embodiment, a second driving circuit 140 is coupled to the first driving circuit 130. The second driving circuit 140 can receive a modulation signal VSWEEP. The second driving circuit 140 can provide a driving time control signal (not shown) to the first driving circuit 130 according to the modulation signal VSWEEP. In the present embodiment, the first driving circuit 130 can determine whether to enable the driving current control signal according to the driving time control signal to determine whether to turn on or turn off the light emitting path. That is, the second driving circuit 140 can control whether the first driving circuit 130 enables the driving current control signal according to the modulation signal VSWEEP to further control the length of time for which the light emitting path is enabled. The aforementioned length of time is related to the voltage variation amplitude of the modulation signal VSWEEP.

[0044] For example, when the voltage value of the modulation signal VSWEEP is in the first voltage range, the first driving circuit 130 can disable the driving current control signal to disable the light emitting path. When the voltage value of the modulation signal VSWEEP is in the second voltage range, the first driving circuit 130 can enable the driving current control signal to enable the light emitting path. When the voltage value of the modulation signal VSWEEP is switched between the first voltage range and the second voltage range, the first driving circuit 130 can switch between disabling and enabling to control the driving current control signal. In this embodiment, the second driving circuit 140 can be, for example, a pulse-width modulation (PWM) circuit to control the length of time that the driving current is allowed to flow to further control the gray scale value displayed.

[0045] It is worth mentioning that the pixel circuit 100 is coupled with the light emitting element 110 in series through the single driving transistor 120 on the light emitting path, which can reduce the number of electronic elements (e.g., transistors or switches) required on the light emitting path to simplify the transistors and the signal lines required and reduce the power consumption during operation. In addition, the pixel circuit 100 controls the current value of the driving current control signal through the first driving circuit 130 and controls the time when the driving current control signal is enabled through the second driving circuit 140, which can avoid the driving current from operating in the linear region due to the current value being too large and accurately control the size and output time (i.e., pulse width) of the driving current. In this way, the pixel circuit 100 can reduce the error of the driving current to improve the consistency of brightness, for example, to be able to display a full black screen, and reduce the power consumption during operation.

[0046] Figure 2 is a circuit diagram of a pixel circuit according to an embodiment of the present application. Please refer to Figure 2 The light emitting element 210, the driving transistor 220, the first driving circuit 230, and the second driving circuit 240 included in the pixel circuit 200 can be referred to the related descriptions of the pixel circuit 100 and be analogized, so they are not described again here.

[0047] The first end (i.e., anode end) of the light emitting element 210 is coupled with the driving transistor 220. The second end (i.e., cathode end) of the light emitting element 210 receives a reference ground voltage VSS. In this embodiment, the light emitting element 210 can be implemented, for example, with a sub-millimeter light emitting diode.

[0048] The driving transistor 220 may, for example, be implemented in a p-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET), and the following embodiments are described by way of example with the driving transistor TD. A control terminal (i.e., a gate terminal) of the driving transistor TD is coupled to the first driving circuit 230 at the first node N1. A first terminal (i.e., a source terminal / drain terminal) of the driving transistor TD receives a power supply voltage VDD. A second terminal (i.e., a source terminal / drain terminal) of the driving transistor TD is coupled to a first terminal (i.e., an anode terminal) of the light emitting element 210.

[0049] The first driving circuit 230 can include first to seventh transistors T1-T7 and a first capacitor C1. In the present embodiment, the first to fourth transistors T1-T4 and the sixth transistor T6 may, for example, be implemented in an n-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET). The fifth transistor T5 and the seventh transistor T7 may, for example, be implemented in a PMOSFET. A control terminal (i.e., a gate terminal) of the first transistor T1 is coupled to the third node N3. A first terminal (i.e., a source terminal / drain terminal) of the first transistor T1 is coupled to the control terminal (i.e., a source terminal / drain terminal) of the driving transistor TD at the first node N1. A second terminal (i.e., a source terminal / drain terminal) of the first transistor T1 is coupled to the second node N2. A control terminal (i.e., a gate terminal) of the second transistor T2 receives the light emission signal EM[N]. A first terminal (i.e., a source terminal / drain terminal) of the second transistor T2 is coupled to the second terminal (i.e., a source terminal / drain terminal) of the first transistor T1 at the second node N2. A second terminal (i.e., a source terminal / drain terminal) of the second transistor T2 receives a reference voltage VREF. A control terminal (i.e., a gate terminal) of the third transistor T3 receives the light emission signal EM[N]. A first terminal (i.e., a source terminal / drain terminal) of the third transistor T3 is coupled to the first node N1. A second terminal (i.e., a source terminal / drain terminal) of the third transistor T3 receives the reference voltage VREF. A control terminal (i.e., a gate terminal) of the fourth transistor T4 receives the light emission signal EM[N]. A first terminal (i.e., a source terminal / drain terminal) of the fourth transistor T4 is coupled to the control terminal (i.e., a gate terminal) of the first transistor T1 at the third node N3. A second terminal (i.e., a source terminal / drain terminal) of the fourth transistor T4 receives the reference voltage VLL.

[0050] Continuing the above description, the first end of the first capacitor C1 is coupled to the second node N2. The first end of the first capacitor C1 is coupled to the fourth node N4. The control end (i.e., the gate end) of the fifth transistor T5 receives the emission signal EM[N]. The first end (i.e., the source end / drain end) of the fifth transistor T5 is coupled to the second end of the first capacitor C1 on the fourth node N4. The second end (i.e., the source end / drain end) of the fifth transistor T5 is coupled to the first end (i.e., the source end / drain end) of the driving transistor TD. The control end (i.e., the gate end) of the sixth transistor T6 receives the emission signal EM[N]. The first end (i.e., the source end / drain end) of the sixth transistor T6 is coupled to the fourth node N4. The control end (i.e., the gate end) of the seventh transistor T7 receives the reference voltage VREF2. The first end (i.e., the source end / drain end) of the seventh transistor T7 is coupled to the second end (i.e., the source end / drain end) of the sixth transistor T6. The second end (i.e., the source end / drain end) of the seventh transistor T7 receives the first control signal S1[N].

[0051] In this embodiment, the first driving circuit 230 can provide a signal (i.e., a driving current control signal) on the first node N1 to control whether the driving transistor TD is turned on or not by the first transistor T1 in the emission stage. That is, in the emission stage, the voltage on the first node N1 can be, for example, the driving current control signal.

[0052] In this embodiment, the driving transistor TD and the seventh transistor T7 are matched with each other. Specifically, the driving transistor TD and the seventh transistor T7 have the same size, threshold voltage value, and other transistor-related parameters.

[0053] The second driving circuit 240 may include an eighth transistor T8 through an eleventh transistor T11 and a second capacitor C2. In this embodiment, the eighth transistor T8 through the eleventh transistor T11 may be implemented, for example, as a PMOSFET. The control terminal (i.e., the gate terminal) of the eighth transistor T8 is coupled to the fifth node N5. The first terminal (i.e., the source / drain terminal) of the eighth transistor T8 is coupled to the third node N3. The second terminal (i.e., the source / drain terminal) of the eighth transistor T8 receives a reference voltage VL. The first terminal of the second capacitor C2 is coupled to the control terminal (i.e., the gate terminal) of the eighth transistor T8 at the fifth node N5. The second terminal of the second capacitor C2 receives a modulation signal VSWEEP. The control terminal (i.e., the gate terminal) of the ninth transistor T9 receives a second control signal S2[N]. The first terminal (i.e., the source / drain terminal) of the ninth transistor T9 is coupled to the fifth node N5. The second terminal (i.e., the source / drain terminal) of the ninth transistor T9 receives a reference voltage VL. The control terminal (i.e., the gate terminal) of the tenth transistor T10 receives a first control signal S1[N]. The first terminal (i.e., source / drain terminal) of the tenth transistor T10 is coupled to the fifth node N5. The second terminal (i.e., source / drain terminal) of the tenth transistor T10 is coupled to the control terminal (i.e., gate terminal) and the first terminal (i.e., source / drain terminal) of the eleventh transistor T11. The second terminal (i.e., source / drain terminal) of the eleventh transistor T11 receives the data signal VDATA.

[0054] In this embodiment, the second driving circuit 240 can provide a signal (i.e., a driving time control signal) at the third node N3 via the eighth transistor T8 during the light-emitting phase to control whether the first transistor T1 is turned on or off. In other words, during the light-emitting phase, the voltage at the third node N3 can be, for example, the driving time control signal. In this embodiment, the eighth transistor T8 can serve as a control switch for the second driving circuit 240.

[0055] In this embodiment, the eighth transistor T8 and the eleventh transistor T11 are matched. Specifically, the eighth transistor T8 and the eleventh transistor T11 have the same size, threshold voltage value, and other transistor-related parameters.

[0056] Figure 3 Based on the present invention Figure 2 A schematic diagram of the operation of the pixel circuit shown in the embodiment. Figures 4A to 4E Based on the present invention Figure 3 A schematic diagram of the pixel circuit operation shown in the embodiment. Figure 3 In the diagram, the horizontal axis represents the operating time of the pixel circuit 200, and the vertical axis represents the voltage value.

[0057] In this embodiment, the reference voltages VREF and VREF2 can be, for example, high power supply signals different from the power supply voltage VDD. The reference voltages VLL and VL can be, for example, low voltage source signals different from the reference ground voltage VSS.

[0058] In this embodiment, the light-emitting signal EM[N], the first control signal S1[N], and the second control signal S2[N] can each be, for example, an independent control signal. The light-emitting signal EM[N], the first control signal S1[N], and the second control signal S2[N] can switch between a first voltage level VGH and a second voltage level VGL. The first voltage level VGH can be, for example, a logic high level, and the second voltage level VGL can be, for example, a logic low level. In this embodiment, the first control signal S1[N] can be, for example, a subsequent signal of the second control signal S2[N] (i.e., the subsequent second control signal S2[N+1]).

[0059] In this embodiment, the modulation signal VSWEEP may have a triangular pulse or other ramp wave. The voltage level VSWEEP_H may be the same as the first voltage level VGH. The voltage level VSWEEP_L may be the same as the second voltage level VGL. The voltage level VSWEEP_M is within the range between the first voltage level VGH and the second voltage level VGL.

[0060] For details regarding the operation of pixel circuit 200 during the reset phase P_RT, please refer to [the relevant documentation / reference]. Figure 3 as well as Figure 4A At time t1, during the first image frame period F1, the second control signal S2[N] generates a falling edge to be pulled from the first voltage level VGH to the second voltage level VGL, and the reset phase begins. At time t2, the reset phase ends.

[0061] Specifically, during the reset phase P_RT (i.e., time t1 to t2), the light-emitting signal has a first voltage level VGH to turn off the fifth transistor T5 and turn on the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6. The seventh transistor T7 is turned on by the reference voltage VREF2. At this time, the voltage on the first node N1 is pulled to the reference voltage VREF to turn off the driving transistor TD. The voltages on the second node N2 and the third node N3 are pulled to the reference voltage VREF and the reference voltage VLL, respectively, to turn off the first transistor T1. The voltage on the fourth node N4 is pulled to the first control signal S1[N] (i.e., the first voltage level VGH) minus the critical voltage value of the sixth transistor T6. The first control signal S1[N] has the first voltage level VGH to turn off the tenth transistor T10. The eleventh transistor T11 operates as a diode and is turned on by the data signal VDATA. The second control signal S2[N] has a second voltage level VGL to turn on the ninth transistor T9, causing the voltage at the fifth node N5 to be pulled up to the reference voltage VL. Because the voltage at the fifth node N5 is pulled up to the reference voltage VL, the eighth transistor is turned off. During this period P_RT, the voltages at the first node N1 through the fifth node N5 are reset respectively.

[0062] For details regarding the operation of pixel circuit 200 during the compensation phase and data writing period P_CT, please refer to [the relevant documentation / reference]. Figure 3 as well as Figure 4B At time t2, the second control signal S2[N] generates a rising edge to be pulled from the second voltage level VGL to the first voltage level VGH, and the first control signal S1[n] generates a falling edge, thus initiating the compensation phase. At time t3, the compensation phase ends.

[0063] Specifically, during the compensation phase and data writing period P_CT (i.e., time t2 to t3), the light-emitting signal has a first voltage level VGH to turn off the fifth transistor T5 and turn on the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6. The seventh transistor T7 is turned on by the reference voltage VREF2. At this time, the voltage on the first node N1 is maintained at the reference voltage VREF to turn off the driving transistor TD. The voltages on the second node N2 and the third node N3 are maintained at the reference voltage VREF and the reference voltage VLL, respectively, to turn off the first transistor T1. The voltage on the fourth node N4 can be implemented as shown in the following formula (1). In formula (1), VN4 is the voltage on the fourth node N4, VREF2 is the voltage value of the reference voltage VREF2, and VTH_T7 is the critical voltage value of the seventh transistor T7.

[0064] VN4=VREF2+|VTH_T7| Formula (1)

[0065] It should be noted that since the driving transistor TD and the seventh transistor T7 have the same critical voltage value, the critical voltage value of the driving transistor TD (i.e., VTH_T7 in formula (1)) is compensated to the fourth node N4 to compensate the driving transistor TD so that the current output of the driving current control signal to the driving transistor TD is consistent so that the light emission brightness is consistent, and the gray level value can be accurately controlled.

[0066] Continuing the above explanation, the second control signal S2[N] has a first voltage level VGH to turn off the ninth transistor T9. The first control signal S1[N] has a second voltage level VGL to turn on the tenth transistor T10, and the eleventh transistor T11 is turned on by the data signal VDATA, so that the voltage at the fifth node N5 can be realized as shown in the following formula (2). Since the voltage at the fifth node N5 is pulled to the voltage shown in formula (2), the eighth transistor is turned off. In formula (2), VN5 is the voltage at the fifth node N5, and VTH_T11 is the critical voltage value of the eleventh transistor T11.

[0067] VN5=VDATA-|VTH_T11| Formula (2)

[0068] It should be noted that since the eighth transistor T8 and the eleventh transistor T11 have the same critical voltage value, the critical voltage value of the eighth transistor T8 (i.e., VTH_T11 in formula (1)) is compensated to the fifth node N5 to compensate the control switch of the second driving circuit 240 (i.e., the eighth transistor T8) so as to ensure that the emission time is consistent under the same gray level so that the emission brightness is consistent, and the gray level value can be precisely controlled.

[0069] For details regarding the operation of pixel circuit 200 during the light-emitting phase (P_EM), please refer to [the relevant documentation / reference]. Figure 3 as well as Figure 4C , 4D At time t3, the first control signal S1[n] generates a rising edge, the light-emitting signal EM[n] generates a falling edge, and the modulation signal VSWEEP begins to generate a triangular pulse to be linearly pulled from the voltage level VSWEEP_H to the voltage level VSWEEP_L, thus initiating the light-emitting phase. At time t4, the light-emitting phase ends.

[0070] In this embodiment, the period P_EM of the light emission stage can be divided into a first period (time t3 to t3-1) and a second period (time t3-1 to t4). At time t3-1, the modulation signal VSWEEP has a voltage level VSWEEP_M to switch the conduction state of the eighth transistor T8 (e.g., from off to on), so as to further switch the conduction state of the driving transistor TD through the first transistor T1.

[0071] In detail, such as Figure 3 as well as Figure 4C As shown, during the first period of P_EM in the light-emitting phase (i.e., time t3 to t3-1), the light-emitting signal has a second voltage level VGL to turn on the fifth transistor T5 and turn off the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6. The seventh transistor T7 is turned on by the reference voltage VREF2. At this time, the voltage on the first node N1 (i.e., the drive current control signal) is maintained at the reference voltage VREF to turn off the drive transistor TD. The voltage on the third node N3 (i.e., the drive time control signal) is maintained at the reference voltage VLL to turn off the first transistor T1, further turning off the drive transistor TD. The voltage on the fourth node N4 is pulled up by the power supply voltage VDD. The voltage change on the fourth node N4 is coupled to the second node N2 through the first capacitor C1 so that the voltage on the second node N2 can be realized as shown in the following formula (3). In formula (3), VN2 is the voltage at the second node N2, VREF is the voltage value of the reference voltage VREF, VDD is the voltage value of the power supply voltage VDD, and VTH_T7 is the critical voltage value of the seventh transistor T7.

[0072] VN2=VREF+VDD-VREF2-|VTH-T7| Formula (3)

[0073] Continuing the above explanation, the eleventh transistor T11 is turned on by the data signal VDATA. The first control signal S1[N] has a first voltage level VGH to turn off the tenth transistor T10. The second control signal S2[N] has a first voltage level VGH to turn off the ninth transistor T9. The modulation signal VSWEEP has a partial triangular pulse, and the change in the modulation signal VSWEEP is coupled to the fifth node N5 through the second capacitor C2 to gradually turn on the eighth transistor T8. At this time, the change in the modulation signal VSWEEP is coupled to the fifth node N5 through the second capacitor C2 so that the voltage at the fifth node N5 can be realized as shown in the following formula (4). Formula (4) can be referred to the relevant explanation of formula (2), where ΔVSWEEP is the voltage change at the fifth node N5, which is the change in the modulation signal VSWEEP.

[0074] VN5 = VDATA - |VTH T11 |+ΔVSWEEP formula (4)

[0075] like Figure 3 as well as Figure 4D As shown, during the second period of P_EM in the light-emitting phase (i.e., time t3-1 to t4), the difference from the first period is that the modulation signal VSWEEP has another part of triangular pulses, and the change in the modulation signal VSWEEP is coupled to the fifth node N5 through the second capacitor C2 to fully turn on the eighth transistor T8. The aforementioned other part of the triangular pulses is a linear waveform between the voltage level VSWEEP_M and the enable voltage level VSWEEP_L. At this time, the voltage on the third node N3 (i.e., the drive time control signal) is pulled to the reference voltage VL to turn on the first transistor T1, so that the voltage on the first node N1 (i.e., the drive current control signal) is pulled to the voltage on the second node N2 (i.e., the voltage shown in formula (3)). Therefore, the drive transistor TD is turned on to output the drive current according to the voltage on the first node N1.

[0076] It should be noted that when the eighth transistor T8 is fully turned on, the reference voltage VL can be quickly written to the third node N3 to turn on the driving transistor TD through the first transistor T1, thus reducing the transition time of the drive current. On the other hand, the eighth transistor T8 is turned off first and then turned on, which can prevent the driving transistor TD from being mistakenly turned on and causing the light-emitting unit 210 to flicker.

[0077] In this embodiment, the difference between the power supply voltage VDD and the voltage difference of the light-emitting element 210 (i.e., the current-resistance voltage drop (IR Drop)) and the critical voltage value of the driving transistor TD (i.e., VTH_T7 as shown in formula (3)) are both compensated to the first node N1, which can reduce the error of the driving current and improve the uniformity of brightness. In addition, the driving current has a fixed current value, and the aforementioned current value is related to the difference between the reference voltage VREF and VREF2.

[0078] For details regarding the operation of pixel circuit 200 within P_TF during the turn-off phase, please refer to [link / reference needed]. Figure 3 as well as Figure 4E At time t4, the light emission signal EM[n] and the modulation signal VSWEEP generate rising edges and begin the turn-off phase. At time t5, the first image frame period F1 is switched to the second image frame period F2. At time t6, in the second image frame period F2, the second control signal S2[N] generates falling edges and ends the turn-off phase.

[0079] Specifically, during the turn-off phase P_TF (i.e., time t4 to t6), the light-emitting signal has a first voltage level VGH to turn off the fifth transistor T5 and turn on the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6. The seventh transistor T7 is turned on by the reference voltage VREF2. At this time, the voltage on the first node N1 is maintained at the reference voltage VREF to turn off the drive transistor TD. The voltages on the second node N2 and the third node N3 are maintained at the reference voltage VREF and the reference voltage VLL, respectively, to turn off the first transistor T1. The voltage on the fourth node N4 is pulled to the first control signal S1[N] (i.e., the first voltage level VGH). The first control signal S1[N] has the first voltage level VGH to turn off the tenth transistor T10. The eleventh transistor T11 is turned on by the data signal VDATA. The second control signal S2[N] has the first voltage level VGH to turn off the ninth transistor T9. The change in the modulation signal VSWEEP is coupled to the fifth node N5 through the second capacitor C2, so that the voltage on the fifth node N5 can be realized as shown in the following formula (5), and the eighth transistor T8 is turned off. Formula (5) can be referred to the relevant explanation of formula (4).

[0080] VN5 = VDATA - |VTH T11 | Formula (5)

[0081] Figure 5 This is a block diagram of a display panel according to an embodiment of the present invention. Please refer to... Figure 5 The display panel 50 includes a pixel array 510 and a control circuit 520. The control circuit 520 is coupled to the pixel array 510. The control circuit 520 can provide multiple reference voltages and control signals to the pixel array 510. The aforementioned voltages and signals may include power supply voltage VDD, reference voltages VSS, VREF, VREF2, VL and VLL, modulation signal VSWEEP, and signals S1[N], S2[N], EM[N] and VDATA.

[0082] In this embodiment, the pixel array 510 may include a plurality of pixel circuits 500 arranged in an array. Each pixel circuit 500 can be described by analogy with the relevant description of the pixel circuit 100, and therefore will not be repeated here.

[0083] In summary, the pixel circuit and display panel of this invention can be configured with a single driving transistor on the light-emitting path without the need for additional transistors or switches connected in series, thereby reducing the voltage across the light-emitting path and reducing power consumption. The pixel circuit and display panel can also control the magnitude and output time of the driving current through a PAM circuit (i.e., the first driving circuit) and a PWM circuit (i.e., the second driving circuit), respectively, which can improve the accuracy and consistency of the emitted light brightness and reduce power consumption. In some embodiments, compensation through mutually matched transistors (and driving transistors) in the PAM circuit and PWM circuit can improve compensation accuracy and increase the uniformity and consistency of brightness. In some embodiments, the operation of the switch (i.e., the eighth transistor) in the PWM circuit during the light-emitting phase can reduce the transition time of the driving current and avoid flickering.

[0084] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A pixel circuit, comprising: a light emitting element and a driving transistor coupled in series between a power supply voltage and a reference ground voltage; a first driving circuit providing a driving current control signal to a control terminal of the driving transistor based on a first reference voltage and a second reference voltage; and a second driving circuit coupled to the first driving circuit, providing a driving time control signal to the first driving circuit according to a modulation signal, wherein the first driving circuit determines whether to enable the driving current control signal according to the driving time control signal, wherein the first driving circuit comprises: a first transistor having a first terminal coupled to the control terminal of the driving transistor at a first node; a second transistor having a control terminal receiving a light emission signal, a first terminal of the second transistor coupled to a second terminal of the first transistor at a second node, and a second terminal of the second transistor receiving the first reference voltage; a third transistor having a control terminal receiving the light emission signal, a first terminal of the third transistor coupled to the first node, and a second terminal of the third transistor receiving the first reference voltage; a fourth transistor having a control terminal receiving the light emission signal, a first terminal of the fourth transistor coupled to a control terminal of the first transistor at a third node, and a second terminal of the fourth transistor receiving a third reference voltage; a first capacitor having a first terminal coupled to the second node; a fifth transistor having a control terminal receiving the light emission signal, a first terminal of the fifth transistor coupled to a second terminal of the first capacitor at a fourth node, and a second terminal of the fifth transistor coupled to a first terminal of the driving transistor; a sixth transistor having a control terminal receiving the light emission signal, a first terminal of the sixth transistor coupled to the fourth node; and a seventh transistor having a control terminal receiving the second reference voltage, a first terminal of the seventh transistor coupled to a second terminal of the sixth transistor, and a second terminal of the seventh transistor receiving a first control signal, wherein the second driving circuit comprises: an eighth transistor having a first terminal coupled to the third node, and a second terminal of the eighth transistor receiving a fourth reference voltage; a second capacitor having a first terminal coupled to a control terminal of the eighth transistor at a fifth node, and a second terminal of the second capacitor receiving the modulation signal; a ninth transistor having a control terminal receiving a second control signal, a first terminal of the ninth transistor coupled to the fifth node, and a second terminal of the ninth transistor receiving the fourth reference voltage; a tenth transistor having a control terminal receiving the first control signal, a first terminal of the tenth transistor coupled to the fifth node; and an eleventh transistor having a control terminal and a first terminal coupled to a second terminal of the tenth transistor, and a second terminal of the eleventh transistor receiving a data signal.

2. The pixel circuit of claim 1, wherein the driving transistor and the seventh transistor are matched with each other.

3. The pixel circuit of claim 1, wherein the eighth transistor and the eleventh transistor are matched with each other. ​ 4. The pixel circuit of claim 1, wherein the first terminal of the driving transistor receives the power voltage, the second terminal of the driving transistor is coupled to the first terminal of the light emitting element, and the second terminal of the light emitting element receives the reference ground voltage.

5. The pixel circuit of claim 1, wherein during a reset phase, the light emitting signal has a first voltage level to turn off the fifth transistor and turn on the second transistor, the third transistor, the fourth transistor, and the sixth transistor, the seventh transistor is turned on, the first control signal has the first voltage level to turn off the tenth transistor, the eleventh transistor is turned on, the second control signal has a second voltage level to turn on the ninth transistor, and the eighth transistor, the first transistor, and the driving transistor are turned off.

6. The pixel circuit of claim 5, wherein during a compensation phase and data write, the light emitting signal has the first voltage level to turn off the fifth transistor and turn on the second transistor, the third transistor, the fourth transistor, and the sixth transistor, the seventh transistor is turned on, the first control signal has the second voltage level to turn on the tenth transistor, the eleventh transistor is turned on, the second control signal has the first voltage level to turn off the ninth transistor, and the eighth transistor, the first transistor, and the driving transistor are turned off.

7. The pixel circuit of claim 5, wherein during a first period of a light emitting phase, the light emitting signal has the second voltage level to turn on the fifth transistor and turn off the second transistor, the third transistor, the fourth transistor, and the sixth transistor, the seventh transistor is turned on, the first control signal has the first voltage level to turn off the tenth transistor, the eleventh transistor is turned on, the second control signal has the first voltage level to turn off the ninth transistor, the modulation signal has a partial triangle pulse to gradually turn on the eighth transistor, and the first transistor is turned off to turn off the driving transistor.

8. The pixel circuit of claim 7, wherein during a second period of the light emitting phase, the light emitting signal has the second voltage level to turn on the fifth transistor and turn off the second transistor, the third transistor, the fourth transistor, and the sixth transistor, the seventh transistor is turned on, the first control signal has the first voltage level to turn off the tenth transistor, the eleventh transistor is turned on, the second control signal has the first voltage level to turn off the ninth transistor, the modulation signal has a partial triangle pulse to fully turn on the eighth transistor, and the first transistor is turned on to turn on the driving transistor.

9. The pixel circuit of claim 8, wherein during an off phase, the emission signal has the first voltage level to turn off the fifth transistor and turn on the second transistor, the third transistor, the fourth transistor, and the sixth transistor, the seventh transistor is turned on, the first control signal has the first voltage level to turn off the tenth transistor, the eleventh transistor is turned on, the second control signal has the first voltage level to turn off the ninth transistor, the eighth transistor, the first transistor, and the driving transistor are turned off.

10. A display panel, comprising: a pixel array comprising a plurality of pixel circuits as claimed in claim 1 ; and a control circuit coupled to the pixel array to provide the supply voltage, the reference ground voltage, the first reference voltage, the second reference voltage, and the modulation signal to the pixel array. ​

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