ESD protection structure under nanoscale process

Abstract

This application provides an ESD protection structure for nanoscale process technology, comprising an RC detection structure and a protective NPN transistor. A trigger source based on the P+ diffusion region in the protective NPN transistor is connected to the RC detection structure. Once static electricity is generated, the detection current generated by the RC detection circuit enters the protective NPN transistor through the trigger source, generating a current flowing from the trigger source to the P- epitaxial layer. When the voltage generated by the P- epitaxial resistor and this current reaches the NPN transistor's turn-on voltage, the protective NPN transistor conducts to discharge the ESD current. The protective NPN transistor in this application is triggered to conduct through the transistor's substrate. Because the protective NPN transistor lacks the lightly doped drain structure (LDD) produced by standard process technology, and the ESD current is discharged through the parasitic NPN transistor substrate rather than concentrated on the diffusion region channel surface, it can provide relatively high ESD protection capability with a relatively small layout area, making it more suitable for high-density chips and nanoscale process technology.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection technology for integrated circuits, specifically to an ESD protection structure fabricated using nanoscale processes. Background Technology

[0002] As integrated circuit manufacturing processes have evolved from the micrometer level to the nanometer level, the layout area of ​​effective ESD (Electro-Static Discharge) protection structures at the micrometer level is relatively large for nanometer-level processes. When the number of I / O ports on a chip is large, many large-area micrometer-level ESD protection structures will significantly increase the overall chip area.

[0003] Under current nanoscale process technology, the channel depth of an NMOS transistor in the on-state is typically around 300 Å, with the junction depth of N+ and P+ injections around 150 nm. When using an N-channel NMOS transistor to discharge ESD current, the current path is concentrated on the channel surface, and a lightly doped drain (LDD) structure also exists. Under these conditions, the NMOS transistor is very prone to overheating and breakdown, which is why the NMOS device design for ordinary ESD in micron-scale process technology is so large.

[0004] In subsequent micron-scale processes, engineers designed GGNMOS protection structures. These structures utilize a parasitic NPN transistor formed by the breakdown of the drain N+ and PSUB terminals to discharge ESD current. This structure represents a significant improvement over the previous channel-based ESD discharge method. However, because GGNMOS still exhibits an LDD (lightly doped drain) structure, and the collector and emitter regions of this parasitic NPN transistor are injected from ordinary N+ diffusion regions, the junction depth is relatively shallow (around 150nm). Large amounts of high-intensity ESD current still flow through the shallow N+ collector region to the shallow N+ emitter region. This presents a significant weakness for high-current ESD events, requiring a very large GGNMOS area, making it unsuitable for nanometer-scale process products. Summary of the Invention

[0005] To address the issue of excessively large area occupied by ESD structures in existing nanoscale chip manufacturing processes, this invention provides an ESD protection structure for nanoscale processes that can reduce the area occupied by the ESD structure itself while achieving effective electrostatic protection.

[0006] The technical solution of the present invention is as follows: an ESD protection structure fabricated using nanoscale processes, characterized in that it comprises: an RC detection structure and a protective NPN transistor; the RC detection structure identifies ESD events and activates the protective NPN transistor to conduct and discharge ESD current;

[0007] The protective NPN transistor is a deep N+ diffusion region NPN transistor formed by N-type ESD injection, which includes: a trigger source based on the P+ diffusion region generated on the P- epitaxial layer, and a collector region and emitter region based on the deep N+ diffusion region.

[0008] The trigger source is connected to the RC detection structure and is located at the very center of the entire device;

[0009] The collector area is closed and surrounds the outside of the trigger source, and the collector area is connected to the PAD;

[0010] The transmitting region is closed and surrounds the outside of the collector region, and the transmitting region is connected to GND;

[0011] The outer side of the emission region is a closed P+ protection ring, which is based on the P+ diffusion region and connected to GND.

[0012] The area between the collector region and the transmitter region constitutes the working base region.

[0013] Its further features are:

[0014] A hole-blocking protection ring is installed below the emission area; the hole-blocking protection ring is implemented based on NW or DNW.

[0015] The N-type ESD injection spacing between the collector region and the emitter region is greater than 3 micrometers;

[0016] The injection spacing between the collector region and the trigger source, and the injection spacing between the emitter region and the P+ guard ring are both greater than 2.5 micrometers;

[0017] The RC detection structure includes a resistor R, a capacitor C, a PMOS transistor P0, and an NMOS transistor N3;

[0018] The PMOS transistor P0 and the NMOS transistor N3 form an inverter. The gate of the PMOS transistor P0 and the gate of the NMOS transistor N3 are connected to form the inverter input terminal VA. The drain of the PMOS transistor P0 and the drain of the NMOS transistor N3 are connected to form the inverter output terminal VB.

[0019] One end of the resistor R is connected to the source of the PMOS transistor P0 and then to PAD. The other end of the resistor R is connected to one end of the capacitor C and then to the input terminal VA of the inverter. The other end of the capacitor C is grounded to the source of the NMOS transistor N3.

[0020] The output terminal VB of the inverter is connected to the trigger source of the protective NPN transistor;

[0021] The area of ​​the protective NPN transistor is 90um*60um; the effective design area of ​​the collector region is 1100um. 2 The effective design area of ​​the launch zone is 1600 μm. 2 The collector and emitter regions of the N-type ESD injection are designed to have a width of 8µm.

[0022] In the NPN transistor used for protection, the injection junction depth of the deep N+ diffusion region is controlled at 500 nm.

[0023] This application provides an ESD protection structure fabricated using a nanoscale process, comprising an RC detection structure and a protective NPN transistor. A trigger source based on the P+ diffusion region in the protective NPN transistor is connected to the RC detection structure. Once static electricity is generated, the detection current generated by the RC detection circuit enters the protective NPN transistor through the trigger source, generating a current flowing from the trigger source to the P-epitaxial layer. When the voltage generated by the P-epitaxial resistor and this current reaches the NPN transistor's turn-on voltage, the protective NPN transistor conducts to discharge the ESD current. Simultaneously, this application uses an NW hole-blocking protection ring under the emitter region to accelerate the flow of current from the base region to the emitter region, thereby accelerating the turn-on of the NPN transistor to discharge the ESD current. The protective NPN transistor in this application is triggered to conduct through the transistor substrate. Because the protective NPN transistor does not have the lightly doped drain structure produced by the standard process, and the ESD current is discharged through the parasitic NPN transistor substrate rather than concentrated on the diffusion channel surface, the protective NPN transistor in this application can provide a relatively high ESD protection capability with a relatively small layout area. Therefore, the protective NPN transistor in this application is more suitable for high-density chips and nanometer process technology. Attached Figure Description

[0024] Figure 1 This is a circuit schematic diagram of the ESD protection structure fabricated using nanoscale process technology in this application.

[0025] Figure 2 This is an example of the operation of the RC detection circuit during the normal power-on process of a PAD;

[0026] Figure 3 Example of how the RC detection circuit works when an ESD event occurs on the PAD;

[0027] Figure 4 A cross-sectional structural diagram of an NPN transistor used for protection;

[0028] Figure 5 This is a schematic diagram of the layout structure of the ESD protection structure under the nanoscale process of this application.

[0029] Figure 6A schematic diagram of the layout structure of an NPN transistor for protection;

[0030] Figure 7 Example of comparing test results for different ESD protection structures. Detailed Implementation

[0031] This application includes an ESD protection structure fabricated using a nanoscale process, comprising: an RC (Resistor-Capacitance) detection structure and a protective NPN transistor. The circuit schematic of the specific ESD protection structure is shown below. Figure 1 As shown, when an ESD occurs at the PAD port, the current is discharged by the protective NPN transistor.

[0032] The RC detection structure identifies ESD events and activates the protective NPN transistor;

[0033] The RC detection structure includes a resistor R, a capacitor C, a PMOS transistor P0, and an NMOS transistor N3;

[0034] PMOS transistor P0 and NMOS transistor N3 form an inverter. The gates of PMOS transistor P0 and NMOS transistor N3 are connected to form the inverter input terminal VA. The drains of PMOS transistor P0 and NMOS transistor N3 are connected to form the inverter output terminal VB.

[0035] One end of resistor R is connected to PAD, which is the source of PMOS transistor P0. The other end of resistor R is connected to one end of capacitor C and then connected to the input terminal VA of inverter. The other end of capacitor C is grounded, which is the source of NMOS transistor N3.

[0036] The output terminal VB of the inverter is connected to the trigger source of the protective NPN transistor.

[0037] The RC detection circuit controls the operation of the protective NPN transistor by identifying normal PAD power-up and ESD events. The RC time constant is designed to be around 0.5 microseconds. When the PAD powers on normally, the rise time is 1 millisecond, and the RC circuit can follow its power-up speed. (See reference for details.) Figure 2 The voltage at terminal VA is essentially synchronized with the voltage at terminal PAD. Through the inverter in the subsequent stage, the voltage at terminal VB is 0V, and the NPN transistor in the deep N+ diffused region remains off. When an ESD event occurs at terminal PAD, the rise time is 10ns. Since the RC detection time is approximately 0.5 microseconds, the voltage at terminal VA cannot keep pace with the ESD voltage rise rate. (See details...) Figure 3Therefore, the low voltage at the VA terminal is converted to a high voltage at the VB terminal by the inverter in the subsequent stage. This high voltage at the VB terminal causes the protective NPN transistor to activate, allowing the ESD current on the PAD to flow through the protective NPN transistor to GND. Because the ESD current is discharged through the substrate of the protective NPN transistor, it provides relatively high ESD protection capability within a relatively small layout area. This makes the structure of the protective NPN transistor suitable for high-density chips and nanometer process technology.

[0038] like Figure 4 and Figure 6 As shown, the protective NPN transistor is a deep N+ diffused region NPN transistor formed by N-type ESD injection. It includes a trigger source formed on the P-epitaxy layer based on the P+ diffused region, a collector region formed based on the deep N+ diffused region, and an emitter region formed based on the deep N+ diffused region. This application uses N-type ESD injection, which can form a deep N+ diffused region with a relatively deep junction depth of up to 500 nanometers. Under nanometer process technology, it can withstand higher ESD voltage per unit area, ensuring that the ESD protection structure can effectively improve the ESD protection level while saving design area.

[0039] The trigger source connected to the VB terminal is located in the center of the device. On either side of the trigger source are the collector regions of NPN transistors formed using N-type ESD injection. These N-type collector regions are connected to the PAD port requiring protection. On either side of these N-type regions are the emitter regions of NPN transistors, also formed using N-type ESD injection. Both of these N-type emitter regions are connected to GND. The outermost part of the device is a closed P+ diffusion ring that surrounds the entire device. This P+ protection ring is also connected to GND, providing bias voltage to the base region of the NPN transistor.

[0040] The trigger source is connected to the output terminal VB of the inverter in the RC detection structure and is positioned at the very center of the entire device. If the trigger source connected to VB is located around the NW or DNW, some of the holes injected from VB will flow to the nearby substrate, causing a substrate debiasing effect, which will lead to problems with the turn-on of the nearby NMOS transistor. Therefore, in this application, the trigger source connected to VB is located at the very center and surrounded by the NW or DNW to ensure uniform triggering of the NPN transistor to discharge ESD current. The collector region is closed around the outside of the trigger source and is connected to the PAD.

[0041] The emitter region is enclosed and surrounds the collector region, and is connected to GND. A ring-shaped hole-blocking wall is placed below the emitter region. Specifically, an NW (N-well) or DNW (deep N-well) hole-blocking protection ring (HBGR) is used below the emitter region. The use of NW or DNW, due to their deeper junction depth, effectively blocks and collects holes injected from the VB terminal. This causes a positive current to flow from the base to the emitter, thereby accelerating the NPN transistor's turn-on.

[0042] The emitter region is surrounded by a closed P+ guard ring, which is based on the P+ diffusion region and connected to GND. In this application, the fully closed P+ guard ring provides bias voltage to the parasitic resistance Rsub (substrate resistance). Furthermore, this closed P+ guard ring ensures that the substrate near the device has a 0 potential, preventing substrate debiasing effects. The outermost closed P+ guard ring effectively prevents holes injected from the VB terminal from flowing to the nearby substrate: HCGR hole collection guard ring.

[0043] The area between the collector region and the transmitter region constitutes the working base region.

[0044] When an ESD event occurs at the PAD port, a high potential is generated at the VB terminal of the inverter. At this time, the trigger source of the P+ diffusion region connected to the VB terminal generates a current flowing to the P- epitaxial region. This current and the P- epitaxial resistance generate a voltage. In this embodiment, when this voltage reaches 0.6V, the protective NPN transistor will conduct to discharge the ESD current. To enhance the triggering and conduction of the protective NPN transistor, an N-well (or DNW) is added under the deep N+ diffusion region of the emitter region. Due to the relatively deep junction depth of the N-well (or DNW) and the depletion region of the PN junction, holes flowing out from the P+ region at the VB terminal are blocked and collected by the N-well region, flowing into the emitter region of the deep N+ diffusion region. This causes a positive voltage to be generated between the base and emitter regions of the NPN transistor, enhancing the conduction triggering of the NPN transistor. Thus, ESD occurring on the PAD can quickly flow through the deep N+ collector region to the deep N+ emitter region.

[0045] The protective NPN transistor in this application is triggered to conduct by the transistor substrate, and the protective NPN transistor in this application does not have the LDD (lightly doped drain) structure produced by the standard process. At the same time, the ESD current is discharged through the parasitic NPN transistor substrate and is not concentrated on the surface of the diffusion channel. Therefore, the ESD protection structure based on the protective NPN transistor in this application has a higher ESD protection capability than the existing NMOS transistor ESD protection structure.

[0046] like Figure 5The diagram shows the layout of the ESD protection structure in this application. The front-end is an RC detection circuit layout, and the rear-end is a protective NPN transistor layout. The RC detection circuit is used to detect normal power-on of the PAD port and ESD events, and the rear-end protective NPN transistor is used to discharge the ESD current on the PAD. The rear-end protective NPN transistor has a design area of ​​90um * 60um.

[0047] like Figure 6 The diagram shows the layout of the NPN transistor used for protection in this application. The P+ diffused region trigger source connected to the VB terminal is located at the very center of the device. Outside the trigger source is a closed N-type ESD-injected collector region connected to the PAD. Further out is another closed N-type ESD-injected emitter region, surrounded by an N-well ring to block holes flowing out of the VB terminal, enhancing the NPN transistor's trigger conduction; the emitter region is connected to GND. The outermost ring is a closed P+ protection ring based on the P+ diffused region, also connected to GND for base bias. Each diffused region in the diagram has a chamfered corner, with a chamfer height of 0.5 micrometers.

[0048] The N-type ESD injection collector and emitter regions are designed to have a width of 8µm, with a 3µm spacing between them. The distance from the trigger source at the intermediate VB terminal to the deep N+ collector region is 2.5µm, and the distance from the outermost P+ diffusion region to the deep N+ emitter region is also 2.5µm. The effective design area of ​​the collector region is 1100µm. 2 The effective design area of ​​the launch zone is 1600 μm. 2 Because N-type ESD injection has a certain lateral diffusion, the effective area of ​​the collector and emitter regions will actually increase slightly, which is beneficial. At the same time, because N-type ESD injection has a certain lateral diffusion distance, to prevent punch-through breakdown caused by injection into the collector and emitter regions too close together, the injection spacing L between them must be greater than 3 micrometers; to prevent the collector region from forming a junction with a low breakdown voltage due to excessively close proximity to the trigger source, the spacing L2 between them must be greater than 2.5 micrometers.

[0049] To confirm the performance of the ESD protection structure provided in this application under nanoscale process technology, tests were conducted using different ESD protection structures on the same process platform. The specific protection structures involved in the tests are as follows:

[0050] (1) A GGNMOS with an area of ​​120um*60um is designed as an ESD protection structure;

[0051] (2) A channel-conducting NMOS with an area of ​​120um*60um is designed as an ESD protection structure;

[0052] (3) The NPN transistor for protection with a design area of ​​90um*60um in this application;

[0053] The ESD test results are shown in the attached manual. Figure 7 The table is shown below.

[0054] Based on the appendix Figure 7 As shown in the ESD test data in the table, the ESD protection capability of the NPN transistor provided in this application under HBM is approximately three times that of the other two protection structures. Therefore, the NPN transistor provided in this application can provide sufficient ESD protection capability to achieve full-chip ESD protection within a relatively small design area.

Claims

1. An ESD protection structure fabricated using nanoscale processes, characterized in that, It includes: an RC detection structure and a protective NPN transistor; the RC detection structure identifies ESD events and activates the protective NPN transistor to conduct and discharge ESD current; The protective NPN transistor is a deep N+ diffusion region NPN transistor formed by N-type ESD injection, which includes: a trigger source based on the P+ diffusion region generated on the P- epitaxial layer, and a collector region and emitter region based on the deep N+ diffusion region. The trigger source is connected to the RC detection structure and is located at the very center of the entire device; The collector area is closed and surrounds the outside of the trigger source, and the collector area is connected to the PAD; The transmitting region is closed and surrounds the outside of the collector region, and the transmitting region is connected to GND; The outer side of the emission region is a closed P+ protection ring, which is based on the P+ diffusion region and connected to GND. The area between the collector region and the transmitter region constitutes the working base region.

2. The ESD protection structure fabricated using nanoscale processes according to claim 1, characterized in that: A hole-blocking protection ring is installed below the launch area; the hole-blocking protection ring is implemented based on NW or DNW.

3. The ESD protection structure fabricated using nanoscale processes according to claim 1, characterized in that: The N-type ESD injection spacing between the collector region and the emitter region is greater than 3 micrometers.

4. The ESD protection structure fabricated using nanoscale processes according to claim 1, characterized in that: The injection spacing between the collector region and the trigger source, as well as the injection spacing between the emitter region and the P+ guard ring, are both greater than 2.5 micrometers.

5. The ESD protection structure fabricated using nanoscale processes according to claim 1, characterized in that: The RC detection structure includes a resistor R, a capacitor C, a PMOS transistor P0, and an NMOS transistor N3; The PMOS transistor P0 and the NMOS transistor N3 form an inverter. The gate of the PMOS transistor P0 and the gate of the NMOS transistor N3 are connected to form the inverter input terminal VA. The drain of the PMOS transistor P0 and the drain of the NMOS transistor N3 are connected to form the inverter output terminal VB. One end of the resistor R is connected to the source of the PMOS transistor P0 and then to PAD. The other end of the resistor R is connected to one end of the capacitor C and then to the input terminal VA of the inverter. The other end of the capacitor C is grounded to the source of the NMOS transistor N3. The output terminal VB of the inverter is connected to the trigger source of the protective NPN transistor.

6. The ESD protection structure fabricated using nanoscale processes according to claim 1, characterized in that: The area of ​​the protective NPN transistor is 90um*60um; the effective design area of ​​the collector region is 1100um. 2 The effective design area of ​​the launch zone is 1600 μm. 2 The collector and emitter regions of the N-type ESD injection are designed to have a width of 8µm.

7. The ESD protection structure fabricated using nanoscale processes according to claim 1, characterized in that: In the NPN transistor used for protection, the injection junction depth of the deep N+ diffusion region is controlled at 500 nm.

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