A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The method comprises the following steps: providing a substrate; forming at least one gate structure on the substrate; forming a source-drain structure on a top surface of the gate structure; forming an isolation structure, the isolation structure being used for isolating the at least one source-drain structure and isolating the at least one gate structure; and forming an electrode connection structure on the source-drain structure. In this way, the gate structure is arranged below the source-drain structure, so that the influence of the substrate on the source-drain structure can be effectively reduced, the parasitic capacitance between the electrode connection structure and the gate structure can be reduced, the process difficulty can be reduced, and the performance of the semiconductor structure can be finally improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. In IC material design, advancements in technology have led to several generations of integrated circuits. Each generation features smaller and more complex circuitry than its predecessor. With the development of large-scale integrated circuit technology, circuit feature sizes continue to shrink, and device interconnect density continues to increase, which in turn brings a series of challenges to integrated circuit fabrication processes and device performance. Summary of the Invention

[0003] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure.

[0004] In a first aspect, embodiments of this disclosure provide a method for fabricating a semiconductor structure, comprising:

[0005] Provide substrate;

[0006] At least one gate structure is formed on the substrate;

[0007] A source / drain structure is formed on the top plane of the gate structure;

[0008] An isolation structure is formed, the isolation structure being used to isolate at least one of the source / drain structures and at least one of the gate structures;

[0009] An electrode connection structure is formed on the source-drain structure.

[0010] In some embodiments, the substrate is an SOI substrate, and the substrate includes: a first substrate layer, a substrate isolation layer formed on the first substrate layer, and a second substrate layer formed on the substrate isolation layer.

[0011] In some embodiments, at least one gate structure is formed on the substrate, including:

[0012] An initial gate layer is formed on the substrate;

[0013] The initial gate layer is patterned to form at least one gate structure and an isolation trench;

[0014] A gate isolation structure is formed within the isolation trench.

[0015] In some embodiments, after forming at least one gate structure on the substrate, the method further includes:

[0016] A gate oxide layer is formed on the gate structure.

[0017] In some embodiments, a source / drain structure is formed on the top plane of the gate structure, including:

[0018] An active layer is formed on the gate structure and the gate isolation structure;

[0019] The active layer is doped to form a channel, source, and drain, respectively.

[0020] The channel, the source, and the drain constitute the source-drain structure, the channel is formed above the gate structure, and the source and drain are formed on both sides of the channel.

[0021] In some embodiments, forming the isolation structure includes:

[0022] The isolation structure is formed within the active layer, the gate isolation structure, and the second substrate layer, and the isolation structure is connected to the substrate isolation layer.

[0023] In some embodiments, an electrode connection structure is formed on the source / drain structure, including:

[0024] An electrode isolation structure, a source contact structure, and a drain contact structure are formed on the active layer and the isolation structure; wherein the source contact structure is connected to the source, and the drain contact structure is connected to the drain.

[0025] Metal wire isolation structures, source metal interconnects, and drain metal interconnects are formed on the electrode isolation structure, the source contact structure, and the drain contact structure; wherein the source metal interconnects are connected to the source contact structure, and the drain metal interconnects are connected to the drain contact structure.

[0026] The electrode connection structure includes a source connection structure and a drain connection structure. The source contact structure and the source metal connection line form the source connection structure, and the drain contact structure and the drain metal connection line form the drain connection structure.

[0027] Secondly, embodiments of this disclosure provide a semiconductor structure, including: a substrate;

[0028] At least one gate structure formed on the substrate;

[0029] Source and drain structures formed on the top plane of the gate structure;

[0030] An isolation structure, the isolation structure being used to isolate at least one of the source / drain structures and to isolate at least one of the gate structures;

[0031] An electrode connection structure formed on the source / drain structure.

[0032] In some embodiments, the substrate is an SOI substrate, and the substrate includes: a first substrate layer, a substrate isolation layer formed on the first substrate layer, and a second substrate layer formed on the substrate isolation layer.

[0033] In some embodiments, the semiconductor structure further includes a gate isolation structure, wherein:

[0034] The gate isolation structure is located on the same layer as at least one of the gate structures, and the gate isolation structure isolates at least one of the gate structures.

[0035] In some embodiments, the semiconductor structure further includes:

[0036] A gate oxide layer is formed on the gate structure.

[0037] In some embodiments, the semiconductor structure further includes an active layer, wherein:

[0038] The active layer is formed over the gate structure and the gate isolation structure; the isolation structure is formed within the active layer, the gate isolation structure and the second substrate layer, and the isolation structure and the substrate isolation layer are connected.

[0039] Above the gate structure, the active layer includes a channel, and on both sides of the channel, the active layer includes a source and a drain, respectively; wherein, the channel, the source, and the drain constitute the source-drain structure.

[0040] In some embodiments, the semiconductor structure further includes:

[0041] An electrode isolation structure is formed on the active layer and the isolation structure, and an active electrode contact structure and a drain electrode contact structure are formed within the electrode isolation structure; wherein the source electrode contact structure is connected to the source electrode, and the drain electrode contact structure is connected to the drain electrode;

[0042] A metal wire isolation structure is formed on the electrode isolation structure, and a source metal interconnect and a drain metal interconnect are formed within the metal wire isolation structure; wherein, the source metal interconnect is connected to the source contact structure, and the drain metal interconnect is connected to the drain contact structure.

[0043] The electrode connection structure includes a source connection structure and a drain connection structure. The source contact structure and the source metal connection line form the source connection structure, and the drain contact structure and the drain metal connection line form the drain connection structure.

[0044] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method includes: providing a substrate; forming at least one gate structure on the substrate; forming a source / drain structure on the top plane of the gate structure; forming an isolation structure to isolate the at least one source / drain structure and the at least one gate structure; and forming an electrode connection structure on the source / drain structure. This disclosure provides a bottom-gate process, where the gate structure is below and the source / drain structure is above, thereby effectively reducing the influence of the substrate on the channel, source, and drain, and reducing the parasitic capacitance between the electrode connection structure and the gate structure. Furthermore, since the gate structure is below and there is a gate isolation structure between the gate structures, an additional process for forming a gate protection layer is not required, simplifying the process. Simultaneously, since the source / drain structure is above, its thickness control is simpler, eliminating the need for additional epitaxial processes and reducing dependence on restrictive equipment. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of a semiconductor structure;

[0046] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0047] Figure 3 This is a schematic diagram of the structure of a substrate provided in an embodiment of the present disclosure;

[0048] Figure 4 This is a schematic diagram of a structure obtained after forming an initial gate layer, provided by an embodiment of the present disclosure;

[0049] Figure 5 This is a schematic diagram of a structure obtained after forming a gate structure, provided by an embodiment of the present disclosure;

[0050] Figure 6 This is a schematic diagram of a structure obtained after forming a gate isolation structure according to an embodiment of the present disclosure;

[0051] Figure 7 This invention provides a schematic diagram of the structure obtained after forming a gate oxide layer according to an embodiment of the present disclosure;

[0052] Figure 8 This is a schematic diagram of a structure obtained after forming an active layer, provided by an embodiment of the present disclosure;

[0053] Figure 9 A schematic diagram of the structure obtained after forming a channel, source, and drain, provided in an embodiment of this disclosure;

[0054] Figure 10 This is a schematic diagram of a structure obtained after forming an isolation structure, provided by an embodiment of the present disclosure;

[0055] Figure 11 This is a schematic diagram of a structure obtained after forming an electrode isolation structure, provided by an embodiment of the present disclosure;

[0056] Figure 12 This is a schematic diagram of the structure obtained after forming source contact holes and drain contact holes according to an embodiment of the present disclosure;

[0057] Figure 13 This is a schematic diagram of the structure obtained after forming a source contact structure and a drain contact structure according to an embodiment of the present disclosure;

[0058] Figure 14 A schematic diagram of a structure obtained after forming source metal interconnects and drain metal interconnects, provided in an embodiment of this disclosure;

[0059] Figure 15 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0060] Figure 16 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0061] Figure 17 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0062] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0064] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0065] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0066] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows:

[0067] Integrated Circuit (IC);

[0068] Shallow Trench Isolation (STI);

[0069] Silicon on Insulator (SOI);

[0070] Interlayer Dielectric (ILD);

[0071] Active Area (AA);

[0072] Top silicon (Tsi);

[0073] Fully Depleted SOI (FDSOI);

[0074] Contact plug (CT);

[0075] Gate (G);

[0076] Source (S);

[0077] Drain (D);

[0078] Low dielectric constant (Low k);

[0079] High dielectric constant (High k).

[0080] Figure 1 A schematic diagram of a semiconductor structure is shown. (Example) Figure 1As shown, the semiconductor structure includes: a back substrate 101, a buried oxide layer 102, a top silicon layer 103, an STI layer 104, a gate oxide layer 105, a gate 106, a gate protection layer 107, an ILD layer 108, an epitaxial layer 109, a contact plug 110, a metal layer separator 111, and a metal line 112. The back substrate 101, the buried oxide layer 102, and the top silicon layer 103 constitute an SOI substrate. The STI layer 104 divides the SOI substrate into multiple active regions. After doping the active regions, a source 1031, a drain 1032, and a channel 1033 are formed at the top silicon layer 103. A gate oxide layer 105 is formed between the channel 1033 and the gate 106. In addition to the gate oxide layer 105, an active function adjustment layer can also be formed. A gate protection layer 107 is also formed on the surface of the gate 106; an epitaxial layer 109, a contact plug 110, and a metal line 112 are sequentially formed above the source 1031 to electrically connect the source 1031 to other devices; an epitaxial layer 109, a contact plug 110, and a metal line 112 are sequentially formed above the drain 1032 to electrically connect the drain 1032 to other devices; an ILD 108 insulates the multiple contact plugs 110, and a metal layer separator 111 insulates the multiple metal lines 112. Additionally, as... Figure 1 As shown, in the current SOI process, a region 113 without the buried oxide layer 102 (also known as silicon oxide insulating layer, abbreviated as BOX) will also be formed. In this region 113, some devices and connecting substrates will also be formed to form the back gate.

[0081] It can be seen that, Figure 1 In the semiconductor structure shown, the gate 106 in the transistor is a "top gate" structure, that is, the gate 106 is located above the source 1031, drain 1032 and channel 1033, and the source 1031, drain 1032 and channel 1033 are formed directly in the top silicon 103.

[0082] In this traditional structure, since the source 1031 and drain 1032 are fabricated on the top silicon 103, silicon is consumed during the manufacturing process. For example, for devices such as FDSOI, the thickness of the top silicon is already very thin. The consumption during the process makes controlling the thickness of the top silicon difficult, posing a significant challenge to the manufacturing process. Moreover, the impact of thickness variations on device performance is amplified. Furthermore, a silicide (used to reduce contact resistance, not shown in the figure) is typically included between the contact plug 110 and the source 1031 and drain 1032. Figure 1In the conventional structure shown, the top silicon layer is relatively thin and subject to consumption, making it impossible to directly grow silicide on the top silicon to reduce contact resistance. Instead, an epitaxial layer 109 needs to be formed on the top silicon first, followed by silicide growth, which further increases the process complexity. Moreover, in this structure, the gate 106 and the contact plug 110 are very close, which can lead to the influence of parasitic capacitance.

[0083] In summary, for this traditional top-gate structure, the top-gate process has the following problems: controlling the thickness of the top silicon poses a significant challenge to the process; the process window for gate / CT is reduced under high device density; the limitations imposed by the limited equipment on special epitaxial processes; and the presence of parasitic capacitance between CT and Gate affects device speed.

[0084] Based on this, embodiments of this disclosure provide a method for fabricating a semiconductor structure, the method comprising: providing a substrate; forming at least one gate structure on the substrate; forming a source / drain structure on the top plane of the gate structure; forming an isolation structure for isolating at least one source / drain structure and at least one gate structure; and forming an electrode connection structure on the source / drain structure. Thus, embodiments of this disclosure provide a bottom-gate process, i.e., the gate structure is below and the source / drain structure is above, thereby effectively reducing the influence of the substrate on the channel and the source and drain electrodes, and reducing the parasitic capacitance between the electrode connection structure and the gate structure. Furthermore, since the gate structure is below, and there is a gate isolation structure between the gate structures, an additional process for forming a gate protection layer is not required, simplifying the process; simultaneously, since the source / drain structure is above, its thickness control is simpler, eliminating the need for additional epitaxial processes and reducing dependence on restrictive equipment.

[0085] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0086] In one embodiment of this disclosure, see [link to embodiment]. Figure 2 This illustrates a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 2 As shown, the method may include:

[0087] S201: Provides a substrate.

[0088] It should be noted that the method provided in this disclosure is used to prepare a semiconductor structure, which can be used to form electronic devices such as memory, and the semiconductor structure may include transistors.

[0089] More specifically, this method can be a method for fabricating a novel semiconductor structure based on an SOI substrate, that is, the substrate is preferably an SOI substrate. SOI stands for silicon on an insulating substrate, and SOI structures can significantly improve device performance.

[0090] In some embodiments, the substrate 30 includes: a first substrate layer 301, a substrate isolation layer 302 formed on the first substrate layer 301, and a second substrate layer 303 formed on the substrate isolation layer 302.

[0091] It should be noted that, see Figure 3 This illustrates a schematic diagram of the structure of a substrate 30 provided in an embodiment of this disclosure. For example... Figure 3 As shown, the substrate 30 is an SOI substrate, which may specifically include three layers: a first substrate layer 301 (i.e., the back substrate in the SOI structure), a substrate isolation layer 302 (i.e., the buried oxide layer in the SOI structure), and a second substrate layer 303 (i.e., the top silicon in the SOI structure, or the top silicon layer, etc.).

[0092] It should also be noted that the materials of the first substrate layer 301 and the second substrate layer 303 can be silicon (Si) substrates or other suitable substrate materials such as silicon, germanium (Ge), silicon-germanium compounds, etc., such as doped or undoped single-crystal silicon substrates, polycrystalline silicon substrates, etc. This embodiment does not specifically limit this; here, a single-crystal silicon substrate is used as an example for description. The material of the substrate isolation layer 302 can include insulating materials such as silicon oxide or silicon nitride. For example, the material of the substrate isolation layer 302 can be silicon oxide.

[0093] It should also be noted that the SOI substrate can be formed using methods such as Separation by Implanted Oxygen (SIMOX) and Smart Cut. SIMOX utilizes oxygen ion implantation followed by high-temperature heat treatment to restore the crystallinity of the silicon layer, resulting in a thinner silicon layer and buried oxide layer. Smart Cut involves generating a thermal oxide film on the silicon wafer, then implanting hydrogen ions to penetrate the oxide film to form the layer to be separated. After bonding another silicon wafer, the silicon substrate is separated at the ion-implanted portion, thus fabricating the SOI substrate. Alternatively, the SOI substrate can be prepared using other methods, which are not specifically limited here.

[0094] Thus, since the embodiments of this disclosure use SOI substrates, dielectric isolation of components in integrated circuits can be achieved, parasitic latch-up effects can be eliminated, and parasitic capacitance and leakage current can be reduced. It has advantages such as high integration density, fast speed, simple process, and small short-channel effect, and is compatible with existing silicon processes without bringing additional process burden.

[0095] S202: At least one gate structure is formed on the substrate.

[0096] S203: A source / drain structure is formed on the top plane of the gate structure.

[0097] It should be noted that when forming a transistor, a gate structure (in this embodiment, the gate structure is the gate itself) is first formed on the substrate, and then a source-drain structure is formed above the gate structure. The source-drain structure includes the source, drain, and channel of the transistor. That is, in the semiconductor structure prepared in the embodiments of this disclosure, the gate is located below, and the source, drain, and channel are located above the gate, forming a "bottom gate" structure with the gate at the bottom.

[0098] Understandably, in traditional structures, the source and drain are fabricated on the top silicon layer, leading to silicon consumption during the manufacturing process. For FDSOI devices, since the top silicon layer is already very thin, variations in its thickness have amplified the impact on device performance. Controlling the thickness of the top silicon layer is difficult and poses a significant challenge to the manufacturing process. The disclosed embodiments provide a "bottom-gate" structure where the source and drain are located above the gate, eliminating the need to form the source and drain on the top silicon layer. This makes the thickness of the top silicon layer easier to control and avoids adverse effects on device performance.

[0099] Regarding the formation of the gate, in some embodiments, forming at least one gate structure 31 on the substrate 30 may include:

[0100] An initial gate layer 31A is formed on the substrate 30;

[0101] The initial gate layer 31A is patterned to form at least one gate structure 31 and an isolation trench 32;

[0102] A gate isolation structure 33 is formed within the isolation trench 32.

[0103] It should be noted that, Figure 4 This is a schematic diagram of the structure obtained after forming the initial gate layer 31A, as provided in an embodiment of this disclosure. Figure 4 As shown, the initial gate layer 31A is formed above the second substrate layer 303. The initial gate layer 31A can be formed by deposition, and the material of the initial gate layer 31A can include polysilicon (for forming a polysilicon gate) or metal (for forming a metal gate), etc., depending on the actual needs, and is not specifically limited here.

[0104] The initial gate layer 31A is patterned, and a portion of the initial gate layer 31A is removed, leaving the remaining initial gate layer 31A to form multiple gate structures 31. The patterning of the initial gate layer 31A can be achieved by forming a gate mask layer on top of the initial gate layer 31A, the gate mask layer having an arrayed pattern. Specifically, the gate mask layer can include several sub-masks arranged in an array, for example, along mutually perpendicular first and second directions, or the first and second directions can be at other angles, without specific limitation. The initial gate layer 31A covered by the sub-masks is the area retained as the gate structure 31, while the area not covered by the sub-masks is removed to form isolation trenches 32. The gate mask layer can be formed by deposition, and the material of the gate mask layer can be a single layer or multiple layers of masks, photoresist, etc., without specific limitation.

[0105] During patterning, the initial gate layer 31A not covered by the gate mask layer can be removed by etching, and the gate mask layer can be removed, thereby processing the initial gate layer 31A into multiple gate structures 31, resulting in... Figure 5 The structure shown. As an example, in Figure 5 In the diagram, only one gate structure 31 is shown.

[0106] like Figure 5 As shown, after the initial gate layer 31A is partially removed, an isolation trench 32 is formed. Next, a gate isolation structure 33 is formed in the isolation trench 32, resulting in... Figure 6 The structure shown.

[0107] It should be noted that, as Figure 6 As shown, a gate isolation structure 33 is formed within and completely fills an isolation trench 32, with its top surface flush with the top surface of the gate structure 31. The gate isolation structure 33 serves to insulate and isolate multiple gate structures 31, and its formation can be by deposition. The gate isolation structure 33 can be made of a Lowk material, which not only provides insulation but also helps reduce parasitic capacitance.

[0108] In some embodiments, after forming at least one gate structure 31 on the substrate, the method may further include:

[0109] A gate oxide layer 34 is formed on the gate structure 31.

[0110] It should be noted that, Figure 7This diagram illustrates the structure obtained after forming the gate oxide layer 34, as provided in an embodiment of this disclosure. Typically, in mature processes, this portion located on the surface of the gate structure 31 is simply the gate oxide layer 34. However, at nodes of 28nm and below, a function modulation layer 35 can also be formed (in... Figure 7 (The gate oxide layer 34 and the work function adjustment layer 35 are not distinguished). The gate oxide layer 34 and the work function adjustment layer 35 can be formed by deposition or oxidation growth, etc. The material of the gate oxide layer 34 can include silicon oxide, and the material of the work function adjustment layer can include high k material and / or metal gate material, etc., to adjust the work function.

[0111] In some embodiments, forming a source / drain structure on the top plane of the gate structure 31 may include:

[0112] An active layer 36 is formed on the gate structure 31 and the gate isolation structure 33;

[0113] The active layer 36 is doped to form the channel 363, the source 361 and the drain 362, respectively.

[0114] The channel 363, source 361 and drain 362 form a source-drain structure. The channel 363 is formed above the gate structure 31, and the source 361 and drain 362 are formed on both sides of the channel 363.

[0115] It should be noted that, Figure 8 This is a schematic diagram of the structure obtained after forming an active layer 36, as provided in an embodiment of this disclosure. Figure 8 As shown, the active layer 36 is formed above the plane containing the top surface of the gate isolation structure 33. The active layer 36 can be formed by deposition or growth processes, and the material of the active layer 36 can be monocrystalline silicon or polycrystalline silicon, for example, polycrystalline silicon. Alternatively, the active layer 36 can have the same material as the first substrate layer 301 and / or the second substrate layer 303, without specific limitations.

[0116] It should also be noted that after forming the active layer 36, the active layer 36 is doped to form the channel, source, and drain of the transistor. It can be understood that for a junction transistor, the source and drain have the same type of doped ions, while the channel has a different type of doped ions than the source and drain. Specifically, the active layer 36 located above the gate structure 31 is doped with the first type of doping (e.g., ...). Figure 8 (The dashed arrow in the image) to form channel 363, and to perform a second type of doping (such as...) on the active layer 36 located above the gate isolation structure 33. Figure 8(Solid arrows in the diagram) to form source 361 and drain 362 on both sides of channel 363, respectively. The first type of doping can be N-type doping, and the second type of doping can be P-type doping; or, the first type of doping can be P-type doping, and the second type of doping can be N-type doping, without specific limitations. For junctionless transistors, the source, drain, and channel can all have the same doping type, for example, all N-type or all P-type.

[0117] See Figure 9 This illustration shows a schematic diagram of a structure obtained after forming a channel, source, and drain, according to an embodiment of this disclosure. Figure 9 As shown, channel 363 is formed directly above gate structure 31, and source 361 and drain 362 are formed on both sides of channel 363, respectively. Additionally, in Figure 9 In this design, the doped region located to the left of the channel 363 is designated as the source 361, and the doped region located to the right of the channel 363 is designated as the drain 362. However, the doped region located to the left of the channel 363 can also be designated as the drain 362, and the doped region located to the right of the channel 363 can be designated as the source 361. The specific designation depends on the connection method of the device and is not specifically limited here.

[0118] It is understood that an SOI wafer has a sandwich structure, with the top layer being top silicon (i.e., the second substrate layer 303). In traditional structures, the source, drain, and channel are formed directly on the top silicon. Due to the consumption of the process, the thickness of the top silicon is difficult to control, which has an adverse effect on the device. However, in the new structure provided in this embodiment, the channel 363 is in the middle and is grown by subsequent processes. Its thickness is controllable and the control method is simpler. At the same time, in the new structure, the top silicon is no longer used as a channel layer, but is used to connect the gate. In addition, forming the source and drain first in this embodiment can also protect the gate oxide layer and the work function adjustment layer.

[0119] S204: Form an isolation structure for isolating at least one source / drain structure and at least one gate structure.

[0120] It should be noted that, in Figure 9 Only one transistor is shown (including gate structure 31, gate oxide layer 34, work function adjustment layer 35, source 361, drain 362, and channel 363). It can be understood that multiple transistors can be fabricated in this embodiment. After doping, the sources and / or drains of adjacent transistors are connected together. Therefore, further isolation structures are needed to separate the sources and drains of different transistors.

[0121] In some embodiments, forming an isolation structure may include:

[0122] An isolation structure 37 is formed within the active layer 36, the gate isolation structure 33, and the second substrate layer 303, and the isolation structure 37 is connected to the substrate isolation layer 302.

[0123] It should be noted that, Figure 10 This is a schematic diagram of the structure obtained after forming the isolation structure 37, as provided in an embodiment of this disclosure. Figure 10 As shown, the isolation structure 37 divides the active layer 36 into multiple active regions. Each active region includes a source 361, a drain 362, and a channel 363 corresponding to a transistor. Alternatively, the region corresponding to the channel 363 can be referred to as the active region. The isolation structure 37 can be an STI (Single-Tunneling Isolation), and its formation method can refer to the existing STI formation method, which will not be described in detail here.

[0124] like Figure 10 As shown, the isolation structure 37 is formed not only within the active layer 36, but also within the gate isolation structure 33 and the second substrate layer 303, extending to connect with the substrate isolation layer 302. The isolation structure 37 may have the same material as the substrate isolation layer 302, or other types of insulating material. It can be understood that, viewed from a top view, the isolation structure 37 divides the active layer 36 into multiple active regions in a grid-like pattern.

[0125] and Figure 1 Compared to the conventional structure shown, the conventional structure requires a gate protection layer 107 on the surface of the gate 106. This layer serves as a cover layer to protect the gate 106 in subsequent processes and is typically composed of silicon dioxide (SiO2) and silicon nitride (SiN). In the new structure provided in this disclosure embodiment, as... Figure 10 As shown, since the gate structure is already protected by the gate isolation structure 33 below, there is no need to fabricate an additional gate protection layer. In addition, in the new structure, the gate is at the bottom, and in addition to the STI isolating the gate structure 31, there is also the aforementioned Low k material (i.e., the gate isolation structure 33) between the STI and the gate structure, resulting in better isolation.

[0126] Additionally, it's important to note that SOI devices are typically dual-gate devices due to the presence of the BOX, where the front gate is controlled by the gate and the bottom gate is controlled by the voltage connected to the substrate below the BOX. However, this embodiment uses single-gate control; that is, the gate's bottom-mounted structure relative to the source and drain in this embodiment differs from the bottom-gate structure in SOI devices.

[0127] S205: A connection structure is formed on at least one source / drain structure.

[0128] It should be noted that after the isolation structure 37 is formed, a connection structure is formed to make conductive connections between the source and drain and other devices.

[0129] In some embodiments, forming an electrode connection structure on the source / drain structure may include:

[0130] An electrode isolation structure 38, a source contact structure 3101, and a drain contact structure 3102 are formed on the active layer 36 and the isolation structure 37; wherein, the source contact structure 3101 is connected to the source 361, and the drain contact structure 3102 is connected to the drain 362.

[0131] Metal wire isolation structure 311, source metal interconnect 3121 and drain metal interconnect 3122 are formed on electrode isolation structure 38, source contact structure 3101 and drain contact structure 3102; wherein, source metal interconnect 3121 is connected to source contact structure 3101 and drain metal interconnect 3122 is connected to drain contact structure 3102.

[0132] The electrode connection structure includes a source connection structure and a drain connection structure. The source contact structure 3101 and the source metal connection line 3121 form the source connection structure, and the drain contact structure 3102 and the drain metal connection line 3122 form the drain connection structure.

[0133] It should be noted that after forming the source 361 and drain 362, an electrode connection structure needs to be formed to electrically connect the source 361 and drain 362 to other devices. For a transistor, which includes a source 361 and a drain 362, for ease of description, the electrode connection structure in this disclosure is divided into a source connection structure and a drain connection structure. The source connection structure is used to electrically connect the source 361 to other devices, and the drain connection structure is used to electrically connect the drain 362 to other devices. Additionally, the electrode isolation structure can be an ILD (Insulated Layer Disk).

[0134] It should also be noted that, in order to reduce contact resistance, embodiments of this disclosure also form silicide on the surfaces of the source 361 and drain 362. Therefore, in some embodiments, before forming the electrode isolation structure 38, the source contact structure 3101, and the drain contact structure 3102 on the active layer 36 and the isolation structure 37, the method may further include:

[0135] The source electrode 361 and the drain electrode 362 are subjected to silicide growth process to form source silicide on the surface of the source electrode 361 and drain silicide on the surface of the drain electrode 362.

[0136] It should be noted that in this embodiment, the source and drain are grown after the gate, and their thickness can be flexibly controlled according to the actual needs of the device. Compared with the traditional structure, the consumption is reduced, and silicide can be grown directly. In contrast, as in... Figure 1In the conventional structure shown, silicon or silicon compounds need to be epitaxially grown between the source / drain and the contact transformer (CT) to form an epitaxial layer, and then silicide is formed on this epitaxial layer to reduce the contact resistance of the CT. The new structure provided by the present disclosure can directly grow silicide, which simplifies the process steps and reduces the process difficulty.

[0137] In the silicide growth process, the source electrode 361 and drain electrode 362 can be metallized using a metallic material to grow metal silicides, which serve as the source silicide and drain silicide, respectively. The metallic material used can be titanium, zirconium, tantalum, tungsten, palladium, platinum, cobalt, etc. Furthermore, the source electrode 361 and drain electrode 362 can be metallized using the same metallic material, or different metallic materials can be used for separate metallization processes; no specific limitation is made here.

[0138] When forming the source contact structure 3101 and the drain contact structure 3102, the following methods may be used: first, form a complete electrode isolation structure 38, then form a source contact hole 391 and a drain contact hole 392 in the electrode isolation structure 38, and then form a source contact structure 3101 in the source contact hole 391 and a drain contact structure 3102 in the drain contact hole 392.

[0139] See Figure 11 This illustration shows a schematic diagram of the structure obtained after forming an electrode isolation structure 38, as provided in an embodiment of this disclosure. Figure 11 As shown, the electrode isolation structure 38 is formed above the active layer 36 and the isolation structure 37. It can be understood that... Figure 11 The electrode isolation structure 38 shown is the initial state, not the final state.

[0140] The electrode isolation structure 38 is processed to form a source contact hole 391 and a drain contact hole 392, resulting in the following: Figure 12 The structure shown. (As illustrated) Figure 12 As shown, source contact hole 391 is located above source 361, exposing source 361; drain contact hole 392 is located above drain 362, exposing drain 362. It can be understood that source silicide is formed on the surface of source 361 and drain silicide is formed on the surface of drain 362, but it is not shown in the figure.

[0141] The source contact hole 391 and the drain contact hole 392 can be formed by a self-aligned etching process or other conventional photolithography and etching processes, and there is no specific limitation on this.

[0142] A source contact structure 3101 is formed within the source contact hole 391, and a drain contact structure 3102 is formed within the drain contact hole 392, resulting in the following... Figure 13The structure shown is such that the source contact hole 391 and drain contact hole 392 can be filled by depositing metal material into them. The filling material can be a metal material such as tungsten or other types of conductive materials. The electrode isolation structure 38, i.e., ILD, is used to insulate and isolate the source contact structure 3101 and drain contact structure 3102, and protect the device below while isolating the upper metal connection layer from the device below. Its material can be an insulating material such as silicon dioxide.

[0143] Next, at least one metal interconnect layer can be formed above the source contact structure 3101 and the drain contact structure 3102. The metal interconnect layer contains metal interconnects for electrically connecting the source 361 and the drain 362 to devices at other levels. In this embodiment of the disclosure, the formation of one metal interconnect layer is used as an example for description, but more metal interconnect layers may also be included to interconnect, logic interconnect and wire the devices. No specific limitation is made here.

[0144] See Figure 14 This illustration shows a schematic diagram of the structure obtained after forming source metal interconnect 3121 and drain metal interconnect 3122, according to an embodiment of this disclosure. Figure 14 As shown, a metal line isolation structure 311 is formed above the top plane of the electrode isolation structure 38, and a source metal interconnect 3121 and a drain metal interconnect 3122 are formed within the metal line isolation structure 311. The method of forming the metal line isolation structure 311, the source metal interconnect 3121, and the drain metal interconnect 3122 can be similar to the method of forming the electrode isolation structure, the source contact structure 3101, and the drain contact structure 3102. In simple terms, a complete metal line isolation structure 311 is first formed above the top plane of the electrode isolation structure 38, for example, by deposition. Then, source metal holes and drain metal holes are formed within the metal line isolation structure 311 by self-aligned etching or photolithography and etching. The source metal holes are located above the source contact structure 3101, exposing the source contact structure 3101; the drain metal holes are located above the drain contact structure 3102, exposing the drain contact structure 3102.

[0145] Then, metal material is deposited in the source metal hole to form the source metal interconnect 3121, and metal material is deposited in the drain metal hole to form the drain metal interconnect 3122, resulting in... Figure 14 The structure shown is as follows. The source metal interconnect 3121 and the drain metal interconnect 3122 can be made of conductive materials such as metals, and the metal wire isolation structure 311 can be made of low k material to insulate and isolate each source metal interconnect 3121 and drain metal interconnect 3122.

[0146] contrast Figure 1 and Figure 14 ,exist Figure 1 In the middle, the gate oxide layer 105 is close to the contact plug 110, resulting in a large parasitic capacitance, while Figure 14 In this configuration, the gate structure 31 is located below, while the source contact structure 3101 and drain contact structure 3102 are located above, at a greater distance from the gate structure 31. This reduces parasitic capacitance, increases device speed, and ultimately improves performance. Furthermore, embodiments of this disclosure can also improve the process window for the gate / CT, which is beneficial for fabricating high device density structures.

[0147] It should also be noted that during the formation of the source connection structure (CT) and drain connection structure (CT), a gate contact structure (CT) can also be formed simultaneously. The gate contact structure extends to connect with the second substrate layer 303, and then connects to the gate structure 31, thereby enabling the gate structure 31 to be electrically connected to other devices. In some advanced processes, during fabrication, two masks can be formed for the CT, one mask for deeper extensions and another mask for shallower extensions, thus obtaining CTs connecting the source 361, drain 362, and gate structure 31 respectively. For the CT connecting the gate structure 31, the gate is connected through the top silicon layer (i.e., the second substrate layer), and the gate is led out from the CT through the top silicon and connected to the metal layer.

[0148] See Figure 15 This illustrates a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 15 As shown, multiple gate structures and corresponding multiple channels, multiple sources, multiple drains, etc. are illustrated. In other words, in... Figure 15 Three examples are shown in the text. Figure 14 The structure shown is denoted as structure 40. Meanwhile, in region 313, a simplified gate connection structure is also shown. This gate connection structure includes a gate contact structure 3131 and a gate metal interconnect 3132. The gate contact structure 3131 may have the same material as the aforementioned source contact structure 3101 and drain contact structure 3102. The gate metal interconnect 3132 has the same material as the aforementioned source metal interconnect 3121 and drain metal interconnect 3122. The gate contact structure 3131 extends to connect with the second substrate layer 303, thereby connecting with its corresponding gate structure 31 through the second substrate layer 303.

[0149] Combined with reference Figure 16 It shows a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 16 In this paper, the insulating and isolating components within the semiconductor structure are omitted; only the main parts of the semiconductor structure are shown. From Figure 16In the diagram, the connection relationship between the source 361, drain 362, and gate structure 31 and their corresponding contact structures can be clearly seen.

[0150] In short, to address the problems of traditional top-gate structures, such as top silicon thickness control, process miniaturization, reduced process windows for gate / CT, and the impact of parasitic capacitance between CT and gate on device speed, this disclosure provides a bottom-gate process. Because the gate is at the bottom and the source, drain, and channel are at the top, the bottom-gate process effectively reduces the influence of the substrate on the channel and source / drain. The parasitic capacitance between the CT (i.e., gate contact structure and source contact structure) and the gate is reduced, increasing the process window. With the gate at the bottom and an isolation layer (gate isolation structure and STI) present, no additional spacer process is required. Simultaneously, because the source / drain is at the top, its thickness is controllable, eliminating the need for epitaxial processes and reducing dependence on restrictive equipment.

[0151] This disclosure provides a method for fabricating a semiconductor structure, the process of which is briefly described as follows: providing a silicon wafer (i.e., the aforementioned substrate); forming a gate; forming a source, drain, and channel; forming an isolation structure; forming a CT; and forming metal interconnects. The gate can be formed by first growing an initial gate layer, then forming a gate pattern through photolithography and dry etching, followed by filling with a Low-k material and then smoothing it. The source, drain, and channel can be formed by first forming an active layer, then forming the channel and source / drain through doping. Here, forming the S / D layer first can protect the gate oxide layer and the work function adjustment layer. Ideally, the active layer should be monocrystalline silicon like the substrate, but due to process limitations, it is often polycrystalline silicon. The material of the metal layer filler (i.e., the metal line isolation structure) between the metal interconnects can also be a Low-k material to isolate the metal interconnects. Other metal layers not specifically described can also be filled with Low-k material for insulating isolation. Thus, this disclosure proposes a novel device structure and fabrication method based on an SOI substrate, which can effectively reduce process difficulty, improve device performance, and reduce dependence on limiting equipment.

[0152] In another embodiment of this disclosure, a semiconductor structure is provided, which can be prepared by the aforementioned method. Figure 14 As shown, the semiconductor structure may include:

[0153] Substrate 30;

[0154] At least one gate structure 31 is formed on the substrate 30;

[0155] Source and drain structures formed on the top plane of gate structure 31;

[0156] An isolation structure 37 is provided for isolating at least one source / drain structure and at least one gate structure 31.

[0157] Electrode connection structure formed on the source / drain structure.

[0158] In some embodiments, the substrate 30 is an SOI substrate, and the substrate 30 includes: a first substrate layer 301, a substrate isolation layer 302 formed on the first substrate layer 301, and a second substrate layer 303 formed on the substrate isolation layer 302.

[0159] In some embodiments, the semiconductor structure further includes a gate isolation structure 33, wherein:

[0160] The gate isolation structure 33 is located on the same layer as at least one gate structure 31, and the gate isolation structure 33 isolates at least one gate structure 31.

[0161] In some embodiments, the semiconductor structure further includes:

[0162] Gate oxide layer 34 formed on gate structure 31.

[0163] It should be noted that the semiconductor structure may also include a work function adjustment layer 35 formed on the gate structure 31.

[0164] In some embodiments, the semiconductor structure further includes an active layer 36, wherein:

[0165] An active layer 36 is formed above the gate structure 31 and the gate isolation structure 33; an isolation structure 37 is formed within the active layer 36, the gate isolation structure 33, and the second substrate layer 303, and the isolation structure 37 is connected to the substrate isolation layer 302.

[0166] Above the gate structure 31, the active layer 36 includes a channel 363. On both sides of the channel 363, the active layer 36 includes a source 361 and a drain 362, respectively. The channel 363, the source 361 and the drain 362 form a source-drain structure.

[0167] It should be noted that the semiconductor structure may also include a source silicide formed on the surface above the source electrode 361 and a drain silicide formed on the surface above the drain electrode 362.

[0168] In some embodiments, the semiconductor structure further includes:

[0169] An electrode isolation structure 38 is formed on the active layer 36 and the isolation structure 37, and an active electrode contact structure 3101 and a drain electrode contact structure 3102 are formed in the electrode isolation structure 38; wherein, the source electrode contact structure 3101 is connected to the source electrode 361, and the drain electrode contact structure 3102 is connected to the drain electrode 362.

[0170] A metal wire isolation structure 311 is formed on the electrode isolation structure 38, and a source metal connection 3121 and a drain metal connection 3122 are formed in the metal wire isolation structure 311; wherein, the source metal connection 3121 is connected to the source contact structure 3101, and the drain metal connection 3122 is connected to the drain contact structure 3102.

[0171] The electrode connection structure includes a source connection structure and a drain connection structure. The source contact structure 3101 and the source metal connection line 3121 form the source connection structure, and the drain contact structure 3102 and the drain metal connection line 3122 form the drain connection structure.

[0172] It should be noted that, as Figure 15 Alternatively, as shown in 16, the semiconductor structure may further include a gate connection structure, which includes a gate contact structure 3131 and a gate metal interconnect 3132, and the gate contact structure 3131 is connected to the second substrate layer 303.

[0173] The semiconductor structure provided in this disclosure is prepared according to the method provided in the foregoing embodiments. For details not disclosed in this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0174] In short, the purpose of this disclosure is to provide a novel device structure based on an SOI substrate, with the gate on the bottom and the source and drain on top, reducing process complexity while optimizing device performance. By placing the gate on the bottom and the source and drain on top, the influence of the substrate on the source, drain, and channel is reduced, thus reducing secondary effects. In addition, with the gate on the bottom, the parasitic capacitance between the CT and the gate is reduced, eliminating the need for a protective layer process for the gate, reducing the process complexity of the gate / CT, and improving the process window of the gate / CT. Since the source and drain are formed after the source and drain, the problem of controlling the top silicon thickness in traditional structures is avoided. In this new structure, the source and drain are on top, and their thickness is controllable, eliminating the need for epitaxial processes and reducing dependence on limiting equipment.

[0175] In another embodiment of this disclosure, see [reference needed]. Figure 17 This illustrates a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Figure 17 As shown, the memory 170 includes the semiconductor structure described in the foregoing embodiments. The memory 170 can be a semiconductor memory, such as a dynamic random access memory (DRAM). Based on its included semiconductor structure, parasitic capacitance can be reduced, and memory performance can be improved.

[0176] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0177] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0178] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0179] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0180] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0181] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0182] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises: providing a substrate; forming at least one gate structure on the substrate, comprising: forming an initial gate layer on the substrate; performing a patterning process on the initial gate layer to form at least one gate structure and an isolation trench; and forming a gate isolation structure in the isolation trench; forming a source-drain structure on a top surface plane of the gate structure, comprising: forming an active layer on the gate structure and the gate isolation structure; and performing a doping process on the active layer to form a channel, a source and a drain, respectively; wherein the source and / or the drain of adjacent transistors are connected to each other; and the channel, the source and the drain constitute the source-drain structure; forming an isolation structure, comprising: forming the isolation structure in the active layer and the gate isolation structure; the isolation structure is used to separate the source and the drain of different transistors; and the isolation structure is also used to isolate at least one source-drain structure and at least one gate structure; forming an electrode connection structure on the source-drain structure.

2. The method of claim 1, wherein, The substrate is an SOI substrate, and the substrate comprises: a first substrate layer, a substrate isolation layer formed on the first substrate layer, and a second substrate layer formed on the substrate isolation layer.

3. The method of claim 2, wherein, After forming at least one gate structure on the substrate, the method further comprises: forming a gate oxide layer on the gate structure.

4. The method of claim 2, wherein, The channel is formed above the gate structure, and the source and the drain are formed on both sides of the channel, respectively.

5. The method of claim 4, wherein, The forming of the isolation structure further comprises: forming the isolation structure in the second substrate layer, and the isolation structure is connected to the substrate isolation layer.

6. The method of claim 4, wherein, The forming of the electrode connection structure on the source-drain structure comprises: forming an electrode isolation structure, a source contact structure and a drain contact structure on the active layer and the isolation structure; wherein the source contact structure is connected to the source, and the drain contact structure is connected to the drain; forming a metal line isolation structure, a source metal wire and a drain metal wire on the electrode isolation structure, the source contact structure and the drain contact structure; wherein the source metal wire is connected to the source contact structure, and the drain metal wire is connected to the drain contact structure; wherein the electrode connection structure comprises a source connection structure and a drain connection structure, the source contact structure and the source metal wire constitute the source connection structure, and the drain contact structure and the drain metal wire constitute the drain connection structure.

7. A semiconductor structure, characterized by comprises: a substrate; at least one gate structure formed on the substrate; a gate isolation structure, which is located in the same layer as at least one gate structure, and separates at least one gate structure; a source-drain structure formed on a top surface plane of the gate structure; an active layer formed above the gate structure and the gate isolation structure; wherein the active layer comprises the source-drain structure; and the source-drain structure comprises: a channel, a source and a drain. An isolation structure is formed in the active layer and the gate isolation structure; the isolation structure is used to separate the source and the drain of different transistors; the isolation structure is also used to isolate at least one of the source-drain structures and at least one of the gate structures; An electrode connection structure is formed on the source-drain structure.

8. The semiconductor structure of claim 7, wherein, The substrate is an SOI substrate, and the substrate comprises a first substrate layer, a substrate isolation layer formed on the first substrate layer, and a second substrate layer formed on the substrate isolation layer.

9. The semiconductor structure of claim 8, wherein, The semiconductor structure further comprises: A gate oxide layer is formed on the gate structure.

10. The semiconductor structure of claim 8, wherein, The isolation structure is formed in the second substrate layer, and the isolation structure is connected with the substrate isolation layer.

11. The semiconductor structure of claim 10, wherein, The semiconductor structure further comprises: An electrode isolation structure is formed on the active layer and the isolation structure, and a source contact structure and a drain contact structure are formed in the electrode isolation structure; the source contact structure is connected with the source, and the drain contact structure is connected with the drain; A metal line isolation structure is formed on the electrode isolation structure, and a source metal line and a drain metal line are formed in the metal line isolation structure; the source metal line is connected with the source contact structure, and the drain metal line is connected with the drain contact structure; The electrode connection structure comprises a source connection structure and a drain connection structure; the source contact structure and the source metal line constitute the source connection structure, and the drain contact structure and the drain metal line constitute the drain connection structure.

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