Storage device and electronic device

Abstract

A memory device and an electronic device. In the memory device, a ferroelectric layer (113), a first conductor layer (112) in contact with the ferroelectric layer (113), and a conductor structure (116) in contact with the ferroelectric layer (113) can form a memory unit; the ferroelectric layer (113), a second conductor layer (114) in contact with the ferroelectric layer (113), and a conductor structure (116) in contact with the ferroelectric layer (113) can form a memory unit, thereby realizing three-dimensionalization of the ferroelectric memory. One ferroelectric layer (113) can be used to form two memory units, thereby further improving the storage capacity. The isolation structure (115) is relatively large in size and is less difficult to etch than a deep hole. When the deep hole where the conductor structure (116) is located is formed, the etching object is the isolation structure of the insulating material, avoiding the difficult-to-etch ferroelectric layer (116) and the conductor layer (112). Therefore, the etching accuracy is higher. The deep hole is set within the isolation structure (115), which saves device area while ensuring the function of the device, improves the device integration, and makes the three-dimensional ferroelectric memory have more excellent performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a storage device and an electronic device. Background Art

[0002] The 21st century is the information age. Massive amounts of data are being transmitted every moment, which brings convenience to social development. At the same time, it also puts forward higher requirements on the processing capabilities of each link of data. As a data carrier, the performance of memory has also developed by leaps and bounds. However, it is certain that human demand for memory is much higher than the performance that existing memory can provide. For example, memory with excellent indicators such as extremely high read and write speed, extremely large transmission bandwidth, and extremely large capacity is actually required, but it is difficult for existing memory to meet these requirements at the same time. For example, static random access memory (SRAM) provides extremely fast erase and write speed, but its capacity is difficult to increase. High bandwidth memory (HBM) solutions provide high transmission bandwidth, but its speed is not ideal. Three-dimensional flash memory (3D NAND FLASH) provides storage capacity that increases exponentially in three dimensions, with high capacity and space for further capacity improvement, but its speed is even limited to milliseconds, and its life is also greatly limited.

[0003] In addition, the memory made by using the principle that the polarization direction of ferroelectric materials changes under the action of an electric field is called ferroelectric random access memory (FRAM), or also called "ferroelectric memory", which has the advantages of fast read and write speed, low power consumption and small area. The storage unit in the ferroelectric memory may include a ferroelectric field effect transistor (FeFET) based on a metal-ferroelectric layer-insulator layer-semiconductor layer (MFIS) structure, and a ferroelectric diode (Fe-diode) based on a metal-ferroelectric layer-metal (MFM) structure. The storage unit of the MFM structure has better endurance than the storage unit of the MFIS structure, so it is widely used in the FRAM of one transistor-one capacitor (1T-1C) architecture.

[0004] However, ferroelectric memories are mostly two-dimensional structures. How to expand ferroelectric memories from two dimensions to three dimensions, thereby increasing the storage capacity of the memory device and further improving the performance of the memory device, is an important research in this field. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a memory device and an electronic device, which expand the ferroelectric memory to three dimensions, further improving the performance of the memory device while improving the device reliability and reducing the manufacturing cost.

[0006] In a first aspect of an embodiment of the present application, a storage device is provided, comprising a substrate, a multi-layer composite storage layer on the substrate, an isolation structure vertically penetrating the composite storage layer, and a conductor structure vertically penetrating the isolation structure, wherein different composite storage layers are separated by an insulating layer, the composite storage layer comprises a first conductor layer, a ferroelectric layer, and a second conductor layer stacked in sequence, the ferroelectric layer has a protruding portion protruding from the first conductor layer and the second conductor layer on a side wall of the composite storage layer facing the isolation structure, the isolation structure is an insulating material, the conductor structure is in contact with the protruding portion of the ferroelectric layer, and is isolated from the first conductor layer and the second conductor layer by the isolation structure, so that the ferroelectric layer and the first conductor layer in contact with the ferroelectric layer are A conductor layer and a conductor structure in contact with a ferroelectric layer can constitute a storage unit, in which a domain wall can be located on the side of the ferroelectric layer facing the first conductor layer, and the first conductor layer and the conductor structure that do not contact each other can serve as two electrodes. Meanwhile, a ferroelectric layer, a second conductor layer in contact with the ferroelectric layer, and a conductor structure in contact with the ferroelectric layer can constitute a storage unit, in which a domain wall can be located on the side of the ferroelectric layer facing the second conductor layer, and the second conductor layer and the conductor structure that do not contact each other can serve as two electrodes. Therefore, a portion of the same ferroelectric layer facing the first conductor layer and a portion facing the second conductor layer can be used to form two independent storage units.

[0007] That is to say, in the embodiment of the present application, the three-dimensionalization of the ferroelectric memory is achieved by stacking the ferroelectric layer, the first conductor layer and the second conductor layer. One ferroelectric layer can be used to form two storage units, thereby further improving the storage capacity, reducing the waste of longitudinal interlayer capacity during three-dimensional stacking, and improving the storage density of the device. At the same time, the isolation structure is larger in size, and the etching difficulty is smaller than that of the deep hole. When the deep hole where the conductor structure is located is formed, the etching object is the isolation structure of the insulating material, which avoids the difficult-to-etch ferroelectric layer and the conductor layer. Therefore, its etching accuracy is higher and the etching reliability is improved. In addition, the deep hole is set within the isolation structure, which saves the device area while ensuring the device function, improves the device integration, and combines the high speed and high bandwidth characteristics of the ferroelectric memory itself, so that the three-dimensional ferroelectric memory has more excellent performance.

[0008] In some possible implementations, the conductor structure has extensions on the top and bottom of the multi-layer composite storage layer, the isolation structure extends along a first direction parallel to the substrate surface, and the first conductor layer and the second conductor layer have extensions on the first side wall and the second side wall of the composite storage layer along a second direction, and the second direction is parallel to the substrate surface and perpendicular to the first direction;

[0009] Among them, the extension portion located on the side wall of the first side is used to connect to the first control end, and the extension portion of the conductor structure located on the top of the composite storage layer is also used to connect to the first control end; the extension portion located on the side wall of the second side is used to connect to the second control end, and the extension portion of the conductor structure located at the bottom of the composite storage layer is also used to connect to the second control end; the first control end and the second control end do not work at the same time.

[0010] In an embodiment of the present application, the conductor structure can extend to the top and bottom of the composite storage layer, and the first conductor layer and the second conductor layer can extend to the side walls of the composite storage layer, so that the same conductor structure can be connected to two control ends, and the same conductor layer can also be connected to two control ends, which is conducive to independent control of multiple storage units.

[0011] In some possible implementations, the first control end is connected to the first conductor layer, the second conductor layer, and the extended part of the conductor structure through a first switch, and the second control end is connected to the first conductor layer, the second conductor layer, and the extended part of the conductor structure through a second switch; the first switch is turned on when the first control end is working, and the second switch is turned on when the second control end is working.

[0012] In an embodiment of the present application, the first control end can be connected to a first switch, and the second control end can be connected to a second switch. The first switch and the second switch are used to regulate the control of the first control end and the second control end over each electrode, thereby strengthening the control over each electrode of the storage unit.

[0013] In some possible embodiments, the extending portions of the first conductor layer and the second conductor layer on the first side wall form a step structure, and the extending portions on the second side wall form a step structure, which are used to lead out the first conductor layer and the second conductor layer respectively in a direction away from the substrate.

[0014] In the embodiment of the present application, the extended parts of the first conductor layer and the second conductor layer can form a stepped structure, which improves the convenience of leading out the first conductor layer and the second conductor layer and simplifies the device manufacturing process.

[0015] In some possible implementations, the thickness of the ferroelectric layer is greater than or equal to 3 times the width of the insulating material between the first conductor layer and the conductor structure, and greater than or equal to 3 times the width of the insulating material between the second conductor layer and the conductor structure.

[0016] In an embodiment of the present application, the ferroelectric layer can have a relatively large thickness, so that the portion of the ferroelectric layer close to the first conductor layer is used to form a storage unit, and the portion of the ferroelectric layer close to the second conductor layer is used to form another storage unit. The two storage units do not affect each other, thereby improving device reliability.

[0017] In some possible embodiments, the width of the ferroelectric layer between adjacent isolation structures is greater than or equal to 3 times the width of the insulating material between the first conductor layer and the conductor structure, and greater than or equal to 3 times the width of the insulating material between the second conductor layer and the conductor structure.

[0018] In an embodiment of the present application, the ferroelectric layer can have a larger width, so that the portion of the ferroelectric layer close to the conductor structure on one side is used to form a storage unit, and the portion of the ferroelectric layer close to the conductor structure on the other side is used to form another storage unit. The two storage units do not affect each other, thereby improving device reliability.

[0019] In some possible implementations, the distance between adjacent conductor structures is greater than or equal to the width of the insulating material between the first conductor layer and the conductor structure, and greater than or equal to the width of the insulating material between the second conductor layer and the conductor structure.

[0020] In the embodiment of the present application, there can be a reliable distance between the conductor structures, so that the electrical signals in different conductor structures will not interfere with each other, thereby improving the reliability of the device.

[0021] In some possible implementations, the material of the isolation structure and / or the insulating layer includes at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

[0022] In the embodiments of the present application, the materials of the isolation structure and / or the insulating layer may be limited to ensure the insulation between the electrodes, thereby improving the reliability of the device.

[0023] In some possible implementations, the ferroelectric layer includes at least one of the following materials: lithium niobate, blackened lithium niobate, doped lithium niobate, lithium tantalate, blackened lithium tantalate, doped lithium tantalate, bismuth ferrite, barium titanate, barium strontium titanate, and strontium titanate.

[0024] In the embodiments of the present application, the material of the ferroelectric layer may be limited to ensure the performance of the ferroelectric layer, thereby ensuring the performance of the device.

[0025] In some possible embodiments, the material of the conductor layer and / or the conductor structure includes at least one of the following materials: titanium nitride, tungsten, nickel, platinum, titanium, tungsten nitride, ruthenium, ruthenium oxide, iridium, iridium oxide, tantalum nitride, cobalt, aluminum, copper, polysilicon, and metal silicide.

[0026] In the embodiments of the present application, the material of the conductor layer and / or the conductor structure may be limited to ensure good conductivity of the conductor layer and the conductor structure, thereby ensuring the performance of the device.

[0027] A second aspect of the embodiments of the present application provides an electronic device, including a circuit board, and a storage device as described in the first aspect of the embodiments of the present application and connected to the circuit board.

[0028] In some possible implementations, the electronic device further includes: a first control terminal and a second control terminal;

[0029] One of the first control end and the second control end is used to control the potential of the conductor structure and the first conductor layer and the second conductor layer on one side of the conductor structure, and the other is used to control the potential of the conductor structure and the first conductor layer and the second conductor layer on the other side of the conductor structure; the first control end and the second control end do not work at the same time.

[0030] In some possible implementations, the electronic device further includes:

[0031] a first switch, wherein the first control end is connected to the first conductor layer, the second conductor layer, and the extended portion of the conductor structure through the first switch; the first switch is turned on when the first control end is in operation;

[0032] The second switch, the second control end is connected to the first conductor layer, the second conductor layer, and the extended part of the conductor structure through the second switch; the second switch is turned on when the second control end is working.

[0033] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0034] The present application provides a storage device and an electronic device. The storage device includes a substrate, a multi-layer composite storage layer on the substrate, an isolation structure vertically penetrating the composite storage layer, and a conductor structure vertically penetrating the isolation structure. Different composite storage layers are separated by an insulating layer. The composite storage layer includes a first conductor layer, a ferroelectric layer, and a second conductor layer stacked in sequence. On the side wall of the composite storage layer facing the isolation structure, the ferroelectric layer has a protruding portion protruding from the first conductor layer and the second conductor layer. The isolation structure is an insulating material. The conductor structure contacts the protruding portion of the ferroelectric layer and is isolated from the first conductor layer and the second conductor layer by the isolation structure. In this way, the ferroelectric layer and the conductor structure in contact with the ferroelectric layer The first conductor layer and the conductor structure in contact with the ferroelectric layer can constitute a storage unit, the domain wall in the storage unit can be located on the side of the ferroelectric layer facing the first conductor layer, the first conductor layer and the conductor structure that do not contact each other can serve as two electrodes, and at the same time, the ferroelectric layer, the second conductor layer in contact with the ferroelectric layer, and the conductor structure in contact with the ferroelectric layer can constitute a storage unit, the domain wall in the storage unit can be located on the side of the ferroelectric layer facing the second conductor layer, the second conductor layer and the conductor structure that do not contact each other can serve as two electrodes, so the part of the same ferroelectric layer facing the first conductor layer and the part facing the second conductor layer can be used to form two independent storage units.

[0035] That is to say, in the embodiment of the present application, the three-dimensionalization of the ferroelectric memory is achieved by stacking the ferroelectric layer, the first conductor layer and the second conductor layer. One ferroelectric layer can be used to form two storage units, thereby further improving the storage capacity, reducing the waste of longitudinal interlayer capacity during three-dimensional stacking, and improving the storage density of the device. At the same time, the isolation structure is larger in size, and the etching difficulty is smaller than that of the deep hole. When the deep hole where the conductor structure is located is formed, the etching object is the isolation structure of the insulating material, which avoids the difficult-to-etch ferroelectric layer and the conductor layer. Therefore, its etching accuracy is higher and the etching reliability is improved. In addition, the deep hole is set within the isolation structure, which saves the device area while ensuring the device function, improves the device integration, and combines the high speed and high bandwidth characteristics of the ferroelectric memory itself, so that the three-dimensional ferroelectric memory has more excellent performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to clearly understand the specific implementation of the present application, the following is a brief description of the drawings used in describing the specific implementation of the present application. Obviously, these drawings are only partial embodiments of the present application.

[0037] Figure 1 A schematic diagram of a three-dimensional structure of a storage device provided in an embodiment of the present application;

[0038] Figure 2 for Figure 1 A cross-sectional view of the storage device along the AA direction;

[0039] Figure 3 A schematic diagram of the structure of another storage device provided in an embodiment of the present application;

[0040] Figure 4 A partial schematic diagram of a storage structure in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of an MFM structure provided in an embodiment of the present application;

[0042] Figure 6 A schematic diagram of another MFM structure provided in an embodiment of the present application;

[0043] Figure 7 A schematic diagram of another MFM structure provided in an embodiment of the present application;

[0044] Figure 8 A schematic diagram of the structure of another storage device provided in an embodiment of the present application;

[0045] Fig. 9 A schematic top view of a storage structure provided in an embodiment of the present application;

[0046] Fig.10 A bottom view schematic diagram of a storage structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The embodiments of the present application provide a memory device and an electronic device, which expand the ferroelectric memory into three dimensions, thereby increasing the storage capacity of the memory device while simplifying the device manufacturing process and reducing the manufacturing cost.

[0048] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] This application is described in detail with reference to schematic diagrams. When describing the embodiments of this application in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of this application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0050] In actual operation, the memory can be made by using the principle that the polarization direction of ferroelectric materials changes under the action of an electric field. Specifically, when the polarization direction of the ferroelectric material is reversed, there will be a potential domain wall area between the reversed and non-reversed areas. When the polarization directions between the two are opposite, the domain wall is open and it is in a conductive state, that is, a low-resistance state; when the polarization directions between the two are the same, the domain wall is closed and it is in an insulating state, that is, a high-resistance state. The high and low resistance states are used to represent the stored "0" and "1" states, for example, the high resistance state corresponds to "0" and the low resistance state corresponds to "1", or the high resistance state corresponds to "1" and the low resistance state corresponds to "0", thereby forming a new type of ferroelectric memory. This memory is called a ferroelectric memory, which has the advantages of fast read and write speed, low power consumption and small area.

[0051] However, ferroelectric memories are mostly two-dimensional structures. How to expand ferroelectric memories from two dimensions to three dimensions, thereby increasing the storage capacity of the memory device and further improving the performance of the memory device, is an important research in this field. In fact, by increasing the storage capacity of the memory device, combined with the nanosecond duration of the ferroelectric memory's own domain wall opening and closing and the parallel read-write characteristics brought by the structure, it is possible to achieve the advantages of large capacity, high speed and high bandwidth in a memory architecture, while taking into account the reduction in production costs brought by this method, so that ferroelectric memory can become a universal memory. Therefore, the research on ferroelectric memory is extremely valuable.

[0052] At present, a three-dimensional ferroelectric memory can be formed based on the layer-by-layer stacking of multiple ferroelectric films. Specifically, a single-layer ferroelectric film can be first arranged on a silicon-based substrate, and metal electrodes and leads are arranged at specific structures thereon by micromachining and other means to form a storage array based on a single-layer ferroelectric film. The storage array of the single-layer film is based on an MFM structure, for example, and then a second layer of ferroelectric film is arranged thereon, and the same processing method as the first layer of ferroelectric film is adopted, and the same metal electrode and leads as the first layer of ferroelectric film are arranged thereon, so that the ferroelectric film can be arranged layer by layer and metal electrodes and leads are arranged on each layer of the ferroelectric film respectively, and finally the leads of each layer are interconnected by a certain method to form a three-dimensional structure. However, this method requires layer-by-layer processing and layer-by-layer stacking, which increases the complexity and cost of the process, is not conducive to the increase of storage capacity, and when stacking between layers, the storage unit and the metal lead need to be aligned, and the alignment accuracy even needs to reach the nanometer level, which poses a huge challenge to advanced processes, especially when ferroelectric materials cannot be stacked by thin film deposition, the alignment accuracy is much higher than the nanometer level, making the preparation of multilayer structures very difficult.

[0053] With the help of the existing 3D NAND FLASH memory model, multiple layers of thin films can also be stacked first, including a sacrificial layer and a ferroelectric material layer, etc., the sacrificial layer and the ferroelectric material are etched to obtain a through hole, a metal electrode is formed in the through hole as a bit line (bit line, BL), the sacrificial layer and the ferroelectric material layer are etched to obtain a spacing groove, and the sacrificial layer is processed by special means using the spacing groove to not completely consume the sacrificial layer. The etching stop point is controlled by time, and then the etched part is filled with a metal electrode as a word line (word line, WL), thereby realizing a three-dimensional structure. In the three-dimensional structure, a ferroelectric material layer is formed between two metal electrodes to constitute an MFM structure. However, this method involves a one-time lithography-etch (LE) of the multilayer film, which requires deep hole etching with high steepness and high aspect ratio, but is not friendly to the etching performance of ferroelectric materials, resulting in poor device reliability in the final performance. At the same time, due to the presence of deep hole electrodes and deep trench isolation in the device, the storage density of the device is not high, which is not conducive to achieving large-capacity storage. In addition, the inventors have found through research that the working area of ​​each layer of ferroelectric material is very narrow, and the space occupied by the stacked structure is not fully utilized.

[0054] Based on the above technical problems, the embodiments of the present application provide a storage device and an electronic device, wherein the storage device includes a substrate, a multi-layer composite storage layer on the substrate, an isolation structure vertically penetrating the composite storage layer, and a conductor structure vertically penetrating the isolation structure, wherein different composite storage layers are separated by an insulating layer, and the composite storage layer includes a first conductor layer, a ferroelectric layer, and a second conductor layer stacked in sequence, and on a side wall of the composite storage layer facing the isolation structure, the ferroelectric layer has a protruding portion protruding from the first conductor layer and the second conductor layer, the isolation structure is an insulating material, the conductor structure is in contact with the protruding portion of the ferroelectric layer, and is isolated from the first conductor layer and the second conductor layer by the isolation structure, so that the ferroelectric layer and the ferroelectric layer are in contact with each other. A first conductor layer in contact with the ferroelectric layer and a conductor structure in contact with the ferroelectric layer can constitute a storage unit, the domain wall in the storage unit can be located on the side of the ferroelectric layer facing the first conductor layer, the first conductor layer and the conductor structure that do not contact each other can serve as two electrodes, and at the same time, the ferroelectric layer, the second conductor layer in contact with the ferroelectric layer, and the conductor structure in contact with the ferroelectric layer can constitute a storage unit, the domain wall in the storage unit can be located on the side of the ferroelectric layer facing the second conductor layer, the second conductor layer and the conductor structure that do not contact each other can serve as two electrodes, so the part of the same ferroelectric layer facing the first conductor layer and the part facing the second conductor layer can be used to form two independent storage units.

[0055] That is to say, in the embodiment of the present application, the three-dimensionalization of the ferroelectric memory is achieved by stacking the ferroelectric layer, the first conductor layer and the second conductor layer. One ferroelectric layer can be used to form two storage units, thereby further improving the storage capacity, reducing the waste of longitudinal interlayer capacity during three-dimensional stacking, and improving the storage density of the device. At the same time, the isolation structure is larger in size, and the etching difficulty is smaller than that of the deep hole. When the deep hole where the conductor structure is located is formed, the etching object is the isolation structure of the insulating material, which avoids the difficult-to-etch ferroelectric layer and the conductor layer. Therefore, its etching accuracy is higher and the etching reliability is improved. In addition, the deep hole is set within the isolation structure, which saves the device area while ensuring the device function, improves the device integration, and combines the high speed and high bandwidth characteristics of the ferroelectric memory itself, so that the three-dimensional ferroelectric memory has more excellent performance.

[0056] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0057] refer to Figure 1 FIG. 1 is a schematic diagram of a three-dimensional structure of a storage device provided in an embodiment of the present application, referring to FIG. Figure 2 As shown, Figure 1The memory device is a cross-sectional view along the AA direction in FIG. 1 , wherein the memory device includes a substrate 100 , a multi-layer composite memory layer 110 located on the substrate 100 , an isolation structure 115 penetrating the composite memory layer 110 , and a conductor structure 116 penetrating the isolation structure 115 .

[0058] In the embodiment of the present application, the substrate 100 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, a silicon germanium substrate, etc. In specific implementation, the substrate 100 may be a silicon wafer or a die with a logic circuit function. The surface of the substrate 100 extends in a plane formed by the x-direction and the y-direction, wherein the y-direction may be used as a first direction, and the x-direction may be used as a second direction, wherein the first direction and the second direction are perpendicular and both are parallel to the surface of the substrate 100, and the z-direction is defined as a third direction, which is perpendicular to the first direction and also perpendicular to the second direction. For ease of explanation, the direction parallel to the substrate surface may also be referred to as the horizontal direction, and the direction perpendicular to the substrate surface may be referred to as the vertical direction.

[0059] Different composite storage layers 110 can be separated by insulating layers 111, and multiple composite storage layers 110 are separated by multiple insulating layers 111. Multiple composite storage layers 110 and multiple insulating layers 111 are alternately stacked in the longitudinal direction (z direction) and extend in the transverse direction (x direction and y direction). The number of composite storage layers 110 and insulating layers 111 can be determined comprehensively according to actual storage requirements and preparation processes. The more composite storage layers 110 and insulating layers 111 there are, the greater the storage capacity will be. In the embodiment of the present application, three layers of composite storage layers 110 and three layers of insulating layers 111 are used as an example for explanation, wherein the bottom layer is the composite storage layer 110 and the top layer is the insulating layer 111. Of course, in other embodiments, by changing the stacking order of the two, the composite storage layer 110 can also be located at the top layer.

[0060] The composite storage layer 110 may include a first conductor layer 112, a ferroelectric layer 113, and a second conductor layer 114 stacked in sequence, that is, the ferroelectric layer 113 and the conductor layers located on both sides of the ferroelectric layer 113, so that the upper and lower parts of each ferroelectric layer 113 can be used to set up storage units. Compared with a device in which only the upper or lower part of a ferroelectric layer 113 is provided with storage units, its storage capacity is doubled. Under the same storage capacity requirement, the storage device in the embodiment of the present application has a smaller volume, and under the same device volume, the storage device provided in the embodiment of the present application has double storage capacity. The principle of the ferroelectric layer 113 and the conductor layers located on both sides of the ferroelectric layer 113 forming multiple storage units is described below.

[0061] The material of the ferroelectric layer 113 is a material having ferroelectric properties, for example, it can be at least one of the following materials: lithium niobate (LiNbO3, LN), blackened lithium niobate, doped lithium niobate, lead zirconium titanate (PbZrTiO3), lithium tantalate (LiTaO3), blackened lithium tantalate, doped lithium tantalate, bismuth ferrite (BiFeO3), barium titanate (BaTiO3), strontium barium titanate (SrBa2Ta2O9), strontium titanate (SrTiO), hafnium zirconate (HfZrO3), hafnium lanthanum zirconate (La-HfZrO3), etc. Among them, the above-mentioned dopant is at least one of the following: silicon (Si), zirconium (Zr), yttrium (Y), aluminum (Al), gadolinium (Gd), strontium (Sr), lanthanum (La), iron (Fe), thulium (Tm), erbium (Er), etc.

[0062] The materials of the first conductor layer 112 and the second conductor layer 114 are materials with conductive properties, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), iridium oxide (IrOx), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the first conductor layer 112 and the second conductor layer 114 can be the same or different.

[0063] The insulating layer 111 is used to isolate the first conductor layer 112 and the second conductor layer 114 in adjacent composite storage layers 110 to separate different composite storage layers 110, thereby separating different storage units and improving the control accuracy of the storage units. The material of the insulating layer 111 can be at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

[0064] The memory device further includes an isolation structure 115 that vertically penetrates the composite memory layer 110. The isolation structure 115 may extend along a first direction parallel to the substrate surface, and divide the composite memory layer 110 into multiple parts in the horizontal direction. Multiple isolation structures 115 may be arranged in parallel. An independent memory cell may be formed in each independent composite memory layer 110 separated by the isolation structure 115. The isolation structure 115 may isolate different memory cells, which is beneficial to the integration of the memory device. The isolation structure 115 extends along a third direction perpendicular to the substrate surface, and vertically penetrates the composite memory layer 110. The isolation structure 115 may vertically penetrate at least to the bottom composite memory layer 110, for example, only to the bottom composite memory layer 110 without penetrating the insulating layer 111 thereunder, or completely penetrate the composite memory layer 110 and the insulating layer 111 to the substrate 100. Reference Figure 1As shown, the isolation structures 115 extend along the y direction (ie, the first direction) and the z direction (ie, the third direction), and are arranged in the x direction (ie, the second direction).

[0065] On the side wall of the composite storage layer 110 facing the isolation structure 115, the ferroelectric layer 113 has a protruding portion protruding from the first conductor layer 112 and the second conductor layer 114. The first conductor layer 112 and the second conductor layer 114 are recessed relative to the ferroelectric layer 113. The recesses of the first conductor layer 112 and the second conductor layer 114 relative to the ferroelectric layer 113 may be consistent in size or inconsistent in size along the substrate surface direction. The isolation structure 115 may be made of insulating material. Of course, the recesses of the first conductor layer 112 and the second conductor layer 114 relative to the ferroelectric layer 113 also have insulating material, so as to improve the stability of the device structure while ensuring the isolation effect. The insulating material includes at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

[0066] Since the isolation structure 115 runs through the composite storage layer 110, the insulating material of the isolation structure 115 is actually filled between adjacent ferroelectric layers 113 (laterally adjacent ferroelectric layers 113 are the same ferroelectric layers 113 isolated by the isolation structure 115), and between laterally adjacent first conductor layers 112 (laterally adjacent first conductor layers 112 are the same first conductor layers 112 isolated by the isolation structure 115), and between laterally adjacent second conductor layers 114 (laterally adjacent second conductor layers 114 are the same second conductor layers 114 isolated by the isolation structure 115), thereby isolating the ferroelectric layer 113, the first conductor layer 112 and the second conductor layer 114 of the same layer.

[0067] On the side wall of the composite storage layer 110 facing the isolation structure 115, the insulating layer 111 may also have a protruding portion protruding from the first conductor layer 112 and the second conductor layer 114. Specifically, the side wall of the insulating layer 111 may be flush with the side wall of the ferroelectric layer 113. The isolation structure 115 contacts the side wall of the insulating layer 111 and separates the same insulating layer 111 into multiple parts, and the lateral size of each part is consistent with the lateral size of the ferroelectric layer 113 of the part.

[0068] The isolation structure 115 further includes a plurality of conductor structures 116 that vertically penetrate the isolation structure 115. A plurality of conductor structures 116 may be formed in the same isolation structure 115. The extension direction of the conductor structure 116 is the stacking direction of the composite storage layer 110 ( Figure 1 The arrangement direction thereof is along the first direction ( Figure 1The conductor structure 116 is in contact with the side wall of the protruding portion of the ferroelectric layer 113 in the isolation structure 115. The conductor structure 116 and the first conductor layer 112, as well as the conductor structure 116 and the second conductor layer 114 can be isolated by the insulating material of the isolation structure 115. The insulating material isolating the conductor structure 116 and the first conductor layer 112 can be formed in a depression of the first conductor layer 112 relative to the ferroelectric layer 113, and the insulating material isolating the conductor structure 116 and the second conductor layer 114 can be formed in a depression of the second conductor layer 114 relative to the ferroelectric layer 113.

[0069] Specifically, the conductor structure 116 may contact the ferroelectric layer 113 on at least one side of the sidewall of the isolation structure 115, Figure 1 In the direction shown, the conductor structure 116 may be in contact with the ferroelectric layer 113 only on the left side, or only on the right side, or in contact with both the left and right sides of the ferroelectric layer 113. In an ideal device, the conductor structure 116 is in contact with each ferroelectric layer 113 in the isolation structure 115, and is not in contact with the first conductor layer 112 and the second conductor layer 114 of each layer, so as to ensure the structural and functional integrity of each storage unit.

[0070] The shape of the transverse cross section of the conductor structure 116 can be determined according to actual conditions, and can be circular, elliptical, polygonal, wherein the polygonal can be rectangular, triangular, etc. The material of the conductor structure 116 is a material having conductive properties, for example, it can be at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuOx), iridium (Ir), iridium oxide (IrOx), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc.

[0071] refer to Figure 3As shown, it is a structural schematic diagram of another memory device provided by an embodiment of the present application, which is a cross-sectional view of a plane formed by the memory device in the y direction and the z direction, wherein the conductor structure 116 has an extension portion of a certain height at the top of the composite memory layer 110, which is recorded as X Line 2 here, so as to extend the conductor structure 116 in a direction away from the substrate 100, and the conductor structure 116 can also have an extension portion of a certain height at the bottom of the composite memory layer 110, which is recorded as X Line 5 here, so as to extend the conductor structure 116 in the direction of the substrate 100 side, and the extended conductor structure 116 can be led out of the device through the interconnection layer (not shown) between the substrate 100 and the composite memory layer 110. The same conductor structure 116 can extend to the top and the bottom at the same time, and the extension portion of the conductor structure 116 can be used to apply a voltage to the conductor structure 116, so as to write and read data to the memory cell. Wherein X means that the line can be a word line or a bit line, that is, X represents Word or Bit, and the bit line or word line is determined according to the voltage characteristics applied thereto.

[0072] refer to Figure 3 As shown, when the isolation structure extends along the first direction (y direction) parallel to the substrate surface, the first conductor layer 112 and the second conductor layer 114 may have an extension portion on the first side wall and the second side wall of the composite storage layer 110 along the second direction (x direction), and the second direction is parallel to the substrate surface and perpendicular to the first direction, that is, when the extension direction of the isolation structure 115 is the y direction, the extension portion is located on the side wall of the composite storage layer 110 in the x direction, and the extension direction of the extension portion is along the y direction. The extension portion may form a stepped structure, wherein the side close to the substrate 100 has a larger lateral dimension and extends outward for a longer distance, so as to extend the electrode to the side away from the substrate 100, and respectively lead out the first conductor layer 112 and the second conductor layer 114. Specifically, the same first conductor layer 112 extends outward from the first side wall and the second side wall of the composite storage layer 110; the same second conductor layer 114 extends outward from the first side wall and the second side wall of the composite storage layer 110. The extended portion of the sidewall on the second side of the composite memory layer 110 may be denoted as X Line 1 , and the extended portion of the sidewall on the first side of the composite memory layer 110 may be denoted as X Line 4 .

[0073] Based on the above discussion, reference Figure 4As shown, it is a partial schematic diagram of the storage structure in the embodiment of the present application. For the ferroelectric layer 113, it extends in the horizontal direction, and the side wall is connected to the longitudinal conductor structure 116. The conductor structure 116 can be formed on both sides of the ferroelectric layer 113, and the ferroelectric layer 113 can also be formed on both sides of the conductor structure 116. A first conductor layer 112 and a second conductor layer 114 extending laterally are formed below and above the ferroelectric layer 113. The first conductor layer 112 extending laterally and the conductor structure 116 extending longitudinally are isolated by the insulating material of the isolation structure 115. The second conductor layer 114 extending laterally and the conductor structure 116 extending longitudinally are isolated by the insulating material of the isolation structure 115. Therefore, the first conductor layer 112 in contact with the lower surface of the ferroelectric layer 113 and the conductor structure 116 in contact with the side wall of the ferroelectric layer 113 can serve as a pair of electrodes, and the second conductor layer 114 in contact with the upper surface of the ferroelectric layer 113 and the conductor structure 116 in contact with the side wall of the ferroelectric layer 113 can serve as a pair of electrodes. The isolation structure 115 can prevent short circuits between the electrodes.

[0074] In this way, the portion of the ferroelectric layer 113 facing the first conductor layer 112, and the first conductor layer 112 and the conductor structure 116 connected to the ferroelectric layer 113 constitute an MFM structure, which can be used as a storage unit. By applying a voltage to the first conductor layer 112 and the conductor structure 116, data writing and data reading of the storage unit can be controlled; the portion of the ferroelectric layer 113 facing the second conductor layer 114, and the second conductor layer 114 and the conductor structure 116 connected to the ferroelectric layer 113 constitute an MFM structure, which can be used as another storage unit. By applying a voltage to the second conductor layer 114 and the conductor structure 116, data writing and data reading of the storage unit can be controlled.

[0075] The width of the ferroelectric layer 113 between adjacent isolation structures 115 is denoted as d0, and the thickness in the direction perpendicular to the substrate 100 is denoted as d2. The first conductor layer 112 and the second conductor layer 114 have the same width. The width of the insulating material 115 between the first conductor layer 112 and the conductor structure 116 can be denoted as d1, and the width of the insulating material 115 between the second conductor layer 114 and the conductor structure 116 can also be denoted as d1.

[0076] exist Figure 4 In the storage structure shown in FIG. 1 , a storage structure consisting of a conductor structure 116 and a ferroelectric layer 113, a first conductor layer 112, and a second conductor layer 114 on the left side is used as an example for explanation. Figure 5 and Figure 6 FIG. 1 is a schematic diagram of the MFM structure provided in an embodiment of the present application, wherein: Figure 4The second conductor layer 114 is located above the ferroelectric layer 113 and serves as an upper electrode. The first conductor layer 112 is located below the ferroelectric layer 113 and serves as a lower electrode. The conductor structure 116 is located on the side wall of the ferroelectric layer 113 and serves as a vertical electrode. The upper electrode, the vertical electrode, and a portion of the ferroelectric layer between the upper electrode and the vertical electrode can constitute a first storage unit cell 1. At the same time, the lower electrode, the vertical electrode, and a portion of the ferroelectric layer between the lower electrode and the vertical electrode can constitute a second storage unit cell 2.

[0077] refer to Figure 5 As shown, "1" can be written into the first storage cell cell 1 at the upper right corner of the ferroelectric layer, and "0" can be written into the storage cell cell 2 at the lower right corner of the ferroelectric layer. Specifically, the polarization direction in the first storage cell cell 1 can be reversed, while the polarization direction in the second storage cell cell 2 remains unchanged, so that the first storage cell cell 1 and the second storage cell cell 2 represent different storage states. Figure 5 A is a schematic diagram of the voltage state of the electrode in the storage unit, Figure 5 B is a simulation schematic diagram of a storage unit.

[0078] In a specific implementation, taking the initial spontaneous electric polarization direction of the ferroelectric layer to the right as an example, a voltage can be applied to the two electrodes of the storage unit cell1 so that the direction of the electric field between the two electrodes is opposite to the initial spontaneous polarization direction of the ferroelectric layer, and the electric field between the two electrodes is greater than the coercive electric field of the ferroelectric layer. The coercive voltage of the ferroelectric layer refers to the critical voltage that reverses the polarization direction of the ferroelectric layer. The polarization direction of the ferroelectric layer is reversed under the action of the electric field, forming a polarization direction to the left.

[0079] For example, refer to Figure 5 As shown in A, the voltage of the upper electrode (ground, GND) can be made smaller than the voltage of the vertical electrode (VDD), and the electric field generated by VDD is larger than the coercive electric field of the ferroelectric layer. Then the polarization direction of the ferroelectric layer between the upper electrode and the vertical electrode is reversed, forming a working module, which is roughly the triangular prism area (the cross section is a triangle) in the upper right corner of the ferroelectric layer. The polarization direction after reversal is to the left, while the polarization direction of other positions of the ferroelectric layer has not been reversed, forming a reference module with a polarization direction to the right. At this time, there will be a potential domain wall area between the inversion area and the non-inversion area, which is roughly located at the position shown by the dotted line. When the polarization directions between the two areas are opposite, the domain wall opens, and the domain wall connects the upper electrode and the vertical electrode, and has conductive properties. The upper electrode and the vertical electrode are in a conductive state, that is, a low-resistance state, which can be equivalent to writing "1". The corresponding simulation schematic diagram refers to Figure 5 As shown in B, Figure 5 The ferroelectric layer in B is lithium niobate (LN), and it can be seen from the figure that cell 1 has a domain wall.

[0080] At the same time, a voltage can be applied to the two electrodes of the storage unit cell 2 so that the direction of the electric field between the two electrodes is opposite to the initial spontaneous polarization direction of the ferroelectric layer, and the electric field between the two electrodes is smaller than the coercive electric field of the ferroelectric layer. Then, the electric field between the two electrodes is not sufficient to reach the critical electric field for reversing the electric polarization direction of the ferroelectric layer. Therefore, the polarization direction of the ferroelectric layer remains unchanged and is still a rightward polarization direction.

[0081] For example, refer to Figure 5 As shown in A, the voltage of the lower electrode (1 / 2VDD) can be made smaller than the voltage of the vertical electrode (VDD). The electric field generated by 1 / 2VDD is smaller than the coercive electric field of the ferroelectric layer. Then the polarization direction in the ferroelectric layer will not be reversed, which is equivalent to the polarization direction of the working module and the reference module being the same. The domain wall is closed and in an insulating state, i.e., a high resistance state, which is equivalent to writing "0". The corresponding simulation schematic diagram is referenced in Figure 5 As shown in Figure B, it can be seen that there is no domain wall in cell 2.

[0082] refer to Figure 6 As shown, "1" can be written to both the first storage cell cell 1 and the second storage cell cell 2. Specifically, the polarization direction in the first storage cell cell 1 can be reversed, and the polarization direction in the second storage cell cell 2 can also be reversed, so that the first storage cell cell 1 and the second storage cell cell 2 represent the same storage state. Figure 6 A is a schematic diagram of the voltage state of the electrode in the storage unit, Figure 6 B is a simulation schematic diagram of a storage unit.

[0083] In a specific implementation, a voltage can be applied to the two electrodes of the storage unit cell 1, so that the direction of the electric field between the two electrodes is opposite to the initial spontaneous polarization direction of the ferroelectric layer, and the electric field between the two electrodes is greater than the coercive electric field of the ferroelectric layer, then the polarization direction of the ferroelectric layer is reversed under the action of the electric field, forming a leftward polarization direction. Figure 6 As shown in A, the voltage of the upper electrode (ground, GND) can be made smaller than the voltage of the vertical electrode (VDD), the domain wall in the ferroelectric layer is opened, and the upper electrode and the vertical electrode are in a conductive state, that is, a low resistance state, which can be equivalent to writing "1". The corresponding simulation schematic diagram refers to Figure 6 As shown in Figure B, it can be seen that there is a domain wall in cell 1.

[0084] At the same time, a voltage can be applied to the two electrodes of the storage unit cell 2, so that the direction of the electric field between the two electrodes is opposite to the initial spontaneous polarization direction of the ferroelectric layer, and the electric field between the two electrodes is greater than the coercive electric field of the ferroelectric layer, then the polarization direction of the ferroelectric layer is reversed under the action of the electric field, forming a left polarization direction. Figure 6 As shown in A, the voltage of the lower electrode (ground, GND) can be made smaller than the voltage of the vertical electrode (VDD), the domain wall in the ferroelectric layer is opened, and the lower electrode and the vertical electrode are in a conductive state, that is, a low resistance state, which can be equivalent to writing "1". The corresponding simulation schematic diagram refers to Figure 6 As shown in Figure B, it can be seen that there is a domain wall in cell 2.

[0085] It can be seen that when the thickness of the ferroelectric layer 113 is large enough, the written states between the cell 1 and the cell 2 arranged in the vertical direction based on the same ferroelectric layer do not interfere with each other. The thickness of the ferroelectric layer 113 is related to its material, for example, it is related to the coercive electric field of the ferroelectric layer 113. The larger the coercive electric field, the thicker it needs to be. As an example, the thickness d2 of the ferroelectric layer 113 can be greater than or equal to 3 times the width d1 of the insulating material between the ferroelectric layer 113 and the conductor structure 116, that is, d2≥3*d1.

[0086] Similarly, when the conductor structures 116 are disposed on both sides of the ferroelectric layer 113, the positions of the ferroelectric layer 113 facing the conductor structures 116 on both sides can constitute two storage units, as shown in FIG. Figure 4 As shown, the position of the ferroelectric layer 113 facing the left conductor structure 116 can form a storage unit, and the position of the conductor structure 116 facing the right side can form a storage unit. In order for the write states of the two storage units to not interfere with each other, the width of the ferroelectric layer 113 also needs to be large enough. The width of the ferroelectric layer 113 refers to the width of the ferroelectric layer 113 between adjacent isolation structures 115, that is, the distance between the isolation structures 115. The width of the ferroelectric layer 113 is related to its material, for example, it is related to the coercive electric field of the ferroelectric layer 113. The larger the coercive electric field, the larger its width needs to be. As an example, the width d0 of the ferroelectric layer 113 can be greater than or equal to 3 times the width d1 of the insulating material between the ferroelectric layer 113 and the conductor structure 116, that is, d0≥3*d1.

[0087] In addition, the insulating material 115 between the conductor structures 116 needs to ensure that the voltages between different conductor structures 116 do not affect each other. As an example, the distance d3 between adjacent conductor structures 116 is greater than or equal to the width d1 of the insulating material between the ferroelectric layer 113 and the conductor structure 116, that is, d3≥d1.

[0088] After storing data using the above method, the stored data can also be read. When reading the data stored in the storage unit, the voltage applied at both ends of the storage unit is opposite to the initial spontaneous electric polarization direction of the ferroelectric layer, and its value can be less than the coercive voltage of the ferroelectric layer and greater than the threshold voltage (Threshold Voltage, Vth). At this time, the current value of the storage unit is read to determine whether the storage unit is turned on. For example, if it is turned on, the data stored in the storage unit is determined to be "1", and if it is not turned on, the data stored in the storage unit is determined to be "0". No detailed description will be given.

[0089] exist Figure 4 In the storage structure shown in FIG. 1 , a storage structure consisting of a conductor structure 116 and ferroelectric layers 113 on both sides thereof, and a second conductor layer 114 on the ferroelectric layer 113 is used as an example for explanation. Figure 7 As shown, it is a schematic diagram of another MFM structure provided in an embodiment of the present application, the second conductor layer 114 is located above the ferroelectric layer 113, serving as an upper electrode, and the conductor structure 116 is located on the side wall of the ferroelectric layer 113, serving as a vertical electrode. The upper electrode and the vertical electrode on the left, and the portion of the ferroelectric layer between the upper electrode and the vertical electrode on the left can constitute a first storage unit cell 1. At the same time, the upper electrode and the vertical electrode on the right, and the portion of the ferroelectric layer between the upper electrode and the vertical electrode on the right can constitute a third storage unit cell 3.

[0090] Assuming that the initial polarization direction of the ferroelectric layer is rightward, the initial storage states of cell 1 and cell 3 are both "0", that is, their polarization directions are consistent with the polarization direction of the ferroelectric layer, both are rightward, the potential of the upper electrode on the left is V1, the potential of the upper electrode on the right is V1', and the potential of the vertical electrode is V2.

[0091] When writing "1" to cell 1, V2 needs to be set to VDD, V1 to zero, and an electric field is generated between the vertical electrode and the upper electrode on the left, from the vertical electrode to the upper electrode on the left, that is, a leftward electric field, so that the polarization direction in cell 1 is reversed, that is, when writing, the electric field direction is V2 pointing to V1, and there is a conductive domain wall between the upper electrode on the left and the vertical electrode, which is a low-resistance state. In the subsequent reading process, since the basic storage unit of the memory is unidirectional reading, the application of the reading voltage should be the same as the writing process, that is, V2 applies the reading voltage Vread, and V1 is grounded. Only at this time can the low-resistance conductive current between the vertical electrode and the upper electrode on the left be correctly read. Otherwise, if the potentials of V2 and V1 are opposite, the low-resistance state cannot be read (the reading result is a high-resistance state), that is, "1" cannot be read.

[0092] When writing "0" to cell 1, the potential of V1 is VDD and V2 is grounded. At this time, the conductive domain wall in the ferroelectric layer of cell 1 disappears, and the upper electrode layer on the left and the vertical electrode are in an insulating state (high resistance state). Whether reading from the upper electrode to the vertical electrode or from the vertical electrode to the upper electrode, the result is a high resistance state. Therefore, the reading direction (reading voltage direction) of the left cell 1 is permanently defined as the direction from the vertical electrode to the left upper electrode.

[0093] Similarly, the writing and reading of cell 3 have the same characteristics as cell 1: the direction of writing "1" and reading "1" is from the right upper electrode to the vertical electrode, the direction of writing "0" is from the vertical electrode to the right upper electrode, and the direction of reading "0" is from the right upper electrode to the vertical electrode.

[0094] It can be seen that during the reading process of cell 1, the vertical electrode provides a high potential V2, while during the reading process of cell 2, the vertical electrode provides a low potential (ground) V2. The operation of V2 providing both high and low potentials is not friendly to the control end of the circuit, which will significantly increase the complexity of the control end and reduce the parallelism of the memory.

[0095] In the present application examples, reference Figure 8 , which is a schematic diagram of the structure of another memory device in an embodiment of the present application, wherein the extension portion X Line 2 of the conductor structure 116 to the top of the composite memory layer 110, and the extension portion X Line 4 of the first conductor layer 112 and the second conductor layer 114 to the first side wall of the composite memory layer 110, can be connected to the first control terminal, so that the first control terminal can be used to control X Line 2 and X Line 4. Specifically, the first control terminal can be connected to X Line 2 and X Line 4 respectively through a first switch, and X Line 2 and X Line 4 are controlled by the first switch. One of X Line 2 and X Line 4 is used as a bit line and the other is used as a word line to form a system. That is, the extension portion of the conductor structure 116 to the top of the composite memory layer 110 can be used to connect to the first control terminal through the first switch, and the extension portion of the first conductor layer 112 and the second conductor layer 114 to the first side wall of the composite memory layer 110 can be used to connect to the first control terminal through the first switch.

[0096] At the same time, the second control terminal can be connected to the extension portion X Line 5 of the conductor structure 116 to the bottom of the composite storage layer 110, and the extension portion X Line 1 of the first conductor layer 112 and the second conductor layer 114 to the second side of the composite storage layer, so that the second control terminal can be used to control X Line 1 and X Line 5. Specifically, the second control terminal can be connected to X Line 1 and X Line 5 respectively through a second switch, and X Line 1 and X Line 5 are controlled through the second switch. One of X Line 1 and X Line 5 is used as a bit line and the other is used as a word line to form a system. That is, the extension portion of the conductor structure 116 to the bottom of the composite storage layer 110 can be used to connect to the second control terminal through the second switch, and the extension portion of the first conductor layer 112 and the second conductor layer 114 to the sidewall of the second side of the composite storage layer 110 can be used to connect to the second control terminal through the second switch.

[0097] The first control terminal and the second control terminal do not work at the same time, and when one of the first switch and the second switch is in an open state, the other switch must be in a closed state; conversely, when one of the switches is in a closed state, the other switch must be in an open state. The first switch is turned on when the first control terminal is working, and the second switch is turned on when the second control terminal is working.

[0098] Specifically, the working state of the storage unit on the right side of the vertical electrode (e.g., cell 3) can be controlled by setting the control strategy using X Line 1 and X Line 5, the corresponding vertical electrode X Line 5 is the word line of the second control end, i.e., Word Line 5, and X Line 1 is the bit line of the second control end, i.e., Bit Line 1; similarly, the working state of the storage unit on the left side of the vertical electrode (e.g., cell 1) can be controlled by X Line 2 and X Line 4 at the same time, X Line 4 is the word line of the first control end, i.e., Word Line 4, and the corresponding vertical electrode X Line 2 is the bit line of the first control end, i.e., Bit Line 2. As configured above, when the first control end is working, the first switch is in the open state, the second switch is in the closed state, and the voltage applied only exists between Bit Line 2 and Word Line 4; when the second control end is working, the second switch is in the open state, the first switch is in the closed state, and the voltage applied only exists between Bit Line 1 and Word Line 5; in the above configuration, the X Line at a high potential when reading information is called Bit Line, and the X Line at a low potential is called Word Line.

[0099] Through this read-write operation method, the reading and writing of cell 1 and cell 3 are performed separately, which helps to avoid the problem that V2 provides both high potential and low potential, thereby controlling the parallel operation of all storage cells and simplifying the circuit design, thereby improving the parallel high-bandwidth reading and writing.

[0100] refer to Fig. 9 As shown, it is a top view schematic diagram of a storage structure provided by an embodiment of the present application, wherein the first controller is working, the first switch is in the on state, and all the BitLines and Word Lines in the first column on the left side of Word Line 4 and Bit Line 2 are selected, so that read and write operations can be performed on each layer of devices at the same position on the left side of the Bit Line (as a selected unit); at this time, the second switch is in the off state, and the second control end does not work.

[0101] refer to Fig.10 As shown, it is a bottom view schematic diagram of a storage structure provided by an embodiment of the present application, wherein the second controller is working, the second switch is in the on state, and all the Word Lines and Bit Lines in the first column on the right side of Bit Line 1 and Word Line 5 are selected, so that read and write operations can be performed on each layer of devices at the same position on the right side of the Word Line (as a selected unit); at this time, the first switch is in the off state, and the first control end does not work.

[0102] The embodiment of the present application provides a storage device, including a substrate, a multi-layer composite storage layer on the substrate, an isolation structure vertically penetrating the composite storage layer, and a conductor structure vertically penetrating the isolation structure, wherein different composite storage layers are separated by an insulating layer, the composite storage layer includes a first conductor layer, a ferroelectric layer, and a second conductor layer stacked in sequence, and on a side wall of the composite storage layer facing the isolation structure, the ferroelectric layer has a protruding portion protruding from the first conductor layer and the second conductor layer, the isolation structure is an insulating material, the conductor structure is in contact with the protruding portion of the ferroelectric layer, and is isolated from the first conductor layer and the second conductor layer by the isolation structure, so that the ferroelectric layer and the first conductor layer in contact with the ferroelectric layer are The ferroelectric layer and the conductor structure in contact with the ferroelectric layer can constitute a storage unit, the domain wall in the storage unit can be located on the side of the ferroelectric layer facing the first conductor layer, the first conductor layer and the conductor structure which are not in contact with each other can serve as two electrodes, and at the same time, the ferroelectric layer, the second conductor layer in contact with the ferroelectric layer, and the conductor structure in contact with the ferroelectric layer can constitute a storage unit, the domain wall in the storage unit can be located on the side of the ferroelectric layer facing the second conductor layer, the second conductor layer and the conductor structure which are not in contact with each other can serve as two electrodes, so the part facing the first conductor layer and the part facing the second conductor layer in the same ferroelectric layer can be used to form two independent storage units.

[0103] That is to say, in the embodiment of the present application, the three-dimensionalization of the ferroelectric memory is achieved by stacking the ferroelectric layer, the first conductor layer and the second conductor layer. One ferroelectric layer can be used to form two storage units, thereby further improving the storage capacity, reducing the waste of longitudinal interlayer capacity during three-dimensional stacking, and improving the storage density of the device. At the same time, the isolation structure is larger in size, and the etching difficulty is smaller than that of the deep hole. When the deep hole where the conductor structure is located is formed, the etching object is the isolation structure of the insulating material, which avoids the difficult-to-etch ferroelectric layer and the conductor layer. Therefore, its etching accuracy is higher and the etching reliability is improved. In addition, the deep hole is set within the isolation structure, which saves the device area while ensuring the device function, improves the device integration, and combines the high speed and high bandwidth characteristics of the ferroelectric memory itself, so that the three-dimensional ferroelectric memory has more excellent performance.

[0104] Based on this, an embodiment of the present application also provides an electronic device, which includes a circuit board and a storage device connected to the circuit board, and the storage device can be any of the storage devices provided above. Among them, the circuit board can be a printed circuit board (PCB), and of course the circuit board can also be a flexible circuit board (FPC), etc. This embodiment does not limit the circuit board. Optionally, the electronic device is a different type of user device or terminal device such as a computer, a mobile phone, a tablet computer, a wearable device, and a vehicle-mounted device; the electronic device can also be a network device such as a base station.

[0105] Optionally, the electronic device further comprises a packaging substrate, wherein the packaging substrate is fixed on a printed circuit board PCB via solder balls, and the storage device is fixed on the packaging substrate via solder balls.

[0106] Optionally, the device further includes: a first control terminal and a second control terminal;

[0107] One of the first control end and the second control end is used to control the potential of the conductor structure and the first conductor layer and the second conductor layer on one side of the conductor structure, and the other is used to control the potential of the conductor structure and the first conductor layer and the second conductor layer on the other side of the conductor structure; the first control end and the second control end do not work at the same time.

[0108] Optionally, the device further comprises:

[0109] a first switch, wherein the first control end is connected to the first conductor layer, the second conductor layer, and the extended portion of the conductor structure through the first switch; the first switch is turned on when the first control end is in operation;

[0110] The second switch, the second control end is connected to the first conductor layer, the second conductor layer, and the extended part of the conductor structure through the second switch; the second switch is turned on when the second control end is working.

[0111] In another aspect of the present application, a non-transitory computer-readable storage medium is provided for use with a computer having software for creating an integrated circuit, and one or more computer-readable data structures are stored on the computer-readable storage medium, wherein the one or more computer-readable data structures have photomask data for manufacturing the integrated circuit provided by any of the diagrams provided above.

[0112] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the structural embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the structural embodiment.

[0113] The above is a specific implementation of the present application. It should be understood that the above embodiments are only used to illustrate the technical solution of the present application, rather than to limit it; although the present application is described in detail with reference to the above embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the above embodiments, or replace some of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A storage device, It is characterized in that include: substrate; A multi-layer composite storage layer located on the substrate, wherein different composite storage layers are separated by insulating layers; each of the composite storage layers comprises a first conductor layer, a ferroelectric layer, and a second conductor layer stacked in sequence; An isolation structure vertically penetrating the composite storage layer, the isolation structure being made of insulating material; on a side wall of the composite storage layer facing the isolation structure, the ferroelectric layer has a protruding portion protruding from the first conductor layer and the second conductor layer; a plurality of conductor structures extending longitudinally through the isolation structure; The conductor structure contacts the protruding portion of the ferroelectric layer and is isolated from the first conductor layer and the second conductor layer by the isolation structure.

2. The memory device according to claim 1, It is characterized in that The conductor structure has extensions on the top and bottom of the multi-layer composite storage layer, the isolation structure extends along a first direction parallel to the substrate surface, and the first conductor layer and the second conductor layer have extensions on the first side wall and the second side wall of the composite storage layer along a second direction, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction; Among them, the extension portion located on the side wall of the first side is used to connect to the first control end, and the extension portion of the conductor structure located on the top of the composite storage layer is also used to connect to the first control end; the extension portion located on the side wall of the second side is used to connect to the second control end, and the extension portion of the conductor structure located at the bottom of the composite storage layer is also used to connect to the second control end; the first control end and the second control end do not work at the same time.

3. The memory device according to claim 2, It is characterized in that The first control end is connected to the first conductor layer, the second conductor layer, and the extended part of the conductor structure through a first switch, and the second control end is connected to the first conductor layer, the second conductor layer, and the extended part of the conductor structure through a second switch; the first switch is turned on when the first control end is working, and the second switch is turned on when the second control end is working.

4. The storage device according to claim 2 or 3, It is characterized in that The extending parts of the first conductor layer and the second conductor layer on the first side wall form a step structure, and the extending parts on the second side wall form a step structure, which are used to lead out the first conductor layer and the second conductor layer respectively in a direction away from the substrate.

5. The memory device according to any one of claims 1 to 3, It is characterized in that The thickness of the ferroelectric layer is greater than or equal to 3 times the width of the insulating material between the first conductor layer and the conductor structure, and greater than or equal to 3 times the width of the insulating material between the second conductor layer and the conductor structure.

6. The memory device according to any one of claims 1 to 3, It is characterized in that The width of the ferroelectric layer between adjacent isolation structures is greater than or equal to 3 times the width of the insulating material between the first conductor layer and the conductor structure, and greater than or equal to 3 times the width of the insulating material between the second conductor layer and the conductor structure.

7. The memory device according to any one of claims 1 to 3, It is characterized in that The distance between adjacent conductor structures is greater than or equal to the width of the insulating material between the first conductor layer and the conductor structure, and greater than or equal to the width of the insulating material between the second conductor layer and the conductor structure.

8. The memory device according to any one of claims 1 to 3, It is characterized in that The material of the isolation structure and / or the insulating layer includes at least one of the following materials: silicon dioxide, silicon nitride, titanium dioxide, hafnium dioxide, aluminum nitride, and aluminum oxide.

9. The memory device according to any one of claims 1 to 3, It is characterized in that The ferroelectric layer includes at least one of the following materials: lithium niobate, blackened lithium niobate, doped lithium niobate, lithium tantalate, blackened lithium tantalate, doped lithium tantalate, bismuth ferrite, barium titanate, barium strontium titanate, and strontium titanate.

10. The memory device according to any one of claims 1 to 3, It is characterized in that The material of the conductor layer and / or the conductor structure includes at least one of the following materials: titanium nitride, tungsten, nickel, platinum, titanium, tungsten nitride, ruthenium, ruthenium oxide, iridium, iridium oxide, tantalum nitride, cobalt, aluminum, copper, polysilicon, and metal silicide.

11. An electronic device, It is characterized in that It comprises a circuit board, and a storage device according to any one of claims 1 to 10 connected to the circuit board.

12. The electronic device according to claim 11, It is characterized in that Also includes: A first control terminal and a second control terminal; One of the first control end and the second control end is used to control the potential of the conductor structure and the first conductor layer and the second conductor layer on one side of the conductor structure, and the other is used to control the potential of the conductor structure and the first conductor layer and the second conductor layer on the other side of the conductor structure; the first control end and the second control end do not work at the same time.

13. The electronic device according to claim 12, It is characterized in that Also includes: a first switch, wherein the first control end is connected to the first conductor layer, the second conductor layer, and an extension portion of the conductor structure through the first switch; The first switch is turned on when the first control end is in operation; The second switch, the second control end is connected to the first conductor layer, the second conductor layer, and the extended part of the conductor structure through the second switch; the second switch is turned on when the second control end is working.

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