Lidar vcsel laser module with low parasitic inductance

Abstract

The invention relates to an optical module with a VCSEL laser array for emitting laser pulses for LIDAR applications, in which special construction and connection techniques are employed, so that the parasitic inductance is low, so that a high switching speed is achieved. To this end, a VCSEL laser array die VCSEL A and a capacitor array CAP are mounted in a stacked die arrangement on a carrier.

Description

Technical Field

[0001] The present invention relates to optical modules LM, particularly laser modules, for optical detection and ranging (i.e., LIDAR) applications, having VCSEL lasers (i.e., vertical cavity surface-emitting lasers) in a VCSEL laser array. Background Technology

[0002] WO 2021 140 160A1 discloses an optical module and a LiDAR device for automotive applications. The technical message of WO 2021 140 160A1 describes a laser module with a capacitor array and an arrayable driver IC that drives multiple lasers in a LiDAR system. The lasers provided herein emit light in front of the crystal of a laser diode in the optical module. Therefore, the radiating area of ​​the proposed laser is on the same order of magnitude as the thickness of the PN blocking layer in the vertical direction, which causes the laser beam to broaden in the vertical direction and leads to various other drawbacks.

[0003] However, in the prior art, VCSEL lasers can emit light through the crystal surface of the VCSEL laser die VCSELA (i.e., the surface with a pointing vector perpendicular to the upper surface of the VCSEL laser die VCSELA).

[0004] Therefore, there is a desire to find a technical solution equivalent to the technical inspiration of WO 2021 140 160A1, which has the advantages of the technical inspiration of WO 2021 140 160A1, while also taking advantage of the use of VCSEL lasers. However, this is not an easy task.

[0005] For example, US 2020 / 0 326 425A1 discloses a solid-state LIDAR transmitter with matrix-addressable laser driver circuitry. The VCSEL array in US 2020 / 0 326 425A1 includes a first electrical bus providing a first voltage potential to columns of the matrix-addressable laser driver circuitry and a second electrical bus providing a second voltage potential to rows of the matrix-addressable laser driver circuitry. In the device of US 2020 / 0 326 425A1, multiple column switches connect multiple columns to the first electrical bus. In the technical teaching of US 2020 / 0 326 425A1, multiple row switches connect multiple rows to the second electrical bus. The transmitter in US 2020 / 0 326 425A1 includes multiple series diodes, each of which includes a laser diode connected in series with another diode, wherein each of the multiple series diodes is correspondingly connected between corresponding columns and rows of the matrix-addressable laser driver circuitry to form the LIDAR transmitter. In the device described in US 2020 / 0 326 425A1, at least some of the second diodes increase the total reverse breakdown voltage of the series diodes.

[0006] The disadvantage of the VCSELA array in US 2020 / 0 326 425A1 is that voltage drops occur on the columns of VCSELA lasers.

[0007] DE 10 2018 106 860 A1 describes a laser diode module. Based on the technical teachings of DE 10 2018 106 860 A1, the laser diode module in DE 10 2018 106 860 A1 includes a first semiconductor die containing an electronic switch and a second semiconductor die containing a laser diode. The second semiconductor die in DE 10 2018 106 860 A1 is bonded to the first semiconductor die using on-chip interconnect technology to provide an electrical connection between the electronic switch and the laser diode.

[0008] EP 2 002 519 B1 discloses a circuit arrangement for generating fast laser pulses using a printed circuit board. The printed circuit board in EP 2 002 519 B1 has a semiconductor chip mounted on it, which has an integrated laser driver for switching a laser diode. The laser diode is arranged on and electrically connected to the semiconductor chip. The arrangement in EP 2 002 519 B1 further includes a capacitor mounted on the printed circuit board and electrically connected to the semiconductor chip. The capacitor in the arrangement in EP 2 002 519 B1 provides additional energy to the laser driver when the laser diode switches. The capacitor in EP 2 002 519 B1 is arranged on one side of the printed circuit board, while the semiconductor chip and laser diode in EP 2 002 519 B1 are arranged on the other side of the printed circuit board. The printed circuit board in EP 2 002519B1 has a conductive strip that is connected to at least one capacitor on one side of the printed circuit board and connected to a semiconductor chip in EP 2 002 519 B1 and a laser diode arranged on the semiconductor chip in EP 2 002 519 B1 on the other side by solder balls or conductive, preferably spherical, elements.

[0009] US 2020 / 0 278 426A1 discloses an illumination module for 3D sensing applications. The illumination module in US2020 / 0 278426A1 includes a vertical-cavity surface-emitting laser (VCSEL) array that emits light, a driver configured to power the VCSEL array, and optical elements configured to receive light emitted from the VCSEL array and output a light pattern from the illumination module.

[0010] DE 11 2020 001 131 T5 discloses an optical component for a LIDAR sensor system. The optical component in DE 11 2020 001 131 T5 includes: a first photodiode for realizing a LIDAR sensor pixel in a first semiconductor structure and configured to absorb received light in a first wavelength range; a second photodiode (5120) for realizing an imaging sensor pixel in a second semiconductor structure and configured to absorb received light in a second wavelength range; and an interconnect layer including a conductive structure configured to electrically contact the second photodiode in DE 11 2020 001 131 T5. According to the technical teachings of DE 11 2020 001 131 T5, the received light in the second wavelength range has a shorter wavelength than the received light in the first wavelength range.

[0011] This paper assumes that in a VCSEL laser die VCSELA with a VCSEL array, the 2×n contact areas (bonding pads) LA1 to LAn and RA1 to RAn for electrically connecting the laser diodes of the VCSEL laser die VCSELA are typically arranged with a minimum fifth pitch PTLa, where the minimum pitch between the laser diodes L1 to Ln of the VCSEL laser array die VCSELA is, for example, approximately 50 μm. This minimum fifth pitch PTLa of the laser diodes L1 to Ln of the VCSEL laser array die VCSELA is referred to below as the laser die pitch PTLa. The lasers are typically arranged on the VCSEL laser die VCSELA along two lines parallel to the left and right edges of the VCSEL laser die at this laser die pitch. VCSEL laser die VCSELA can, for example, have a size of 5 mm × 5 mm and can have 11 to 100 lasers, which are preferably arranged in a strip shape from left to right on the VCSEL laser die VCSELA in the form of multiple strips L1 to Ln composed of multiple lasers.

[0012] The contact areas LA1 to LAn and RA1 to RAn of the electrical contacts on the VCSEL laser die VCSELA are all arranged on the top side of the VCSEL laser die VCSELA. When powered, the laser diodes of the laser stripes L1 to Ln of the VCSEL laser die VCSELA emit light perpendicular to the top side of the VCSEL laser die VCSELA.

[0013] The VCSEL laser die VCSELA has a bottom side opposite to the top side, having a bottom surface. An exemplary VCSEL laser die VCSELA preferably has a common cathode electrical contact for the common cathode of the lasers in the VCSEL laser die VCSELA. This cathode electrical contact is electrically and thermally connected to the common cathode electrode C of the circuit board PCB. The cathode contact is located on the bottom surface of the VCSEL laser die VCSELA. This document assumes that the VCSEL laser die VCSELA includes n VCSEL lasers L1 to Ln.

[0014] As is known in WO 2021 140 160A1, the device proposed herein should include a capacitor array (CAP). The capacitor array (CAP) stores electrical energy used to provide pulsed energy to the VCSEL laser array of the VCSEL laser die VCSELA. Preferably, the capacitor array (CAP) is a monolithic design. In contrast, the space requirement (spacing) of a single exemplary discrete capacitor is 300 μm × 300 μm.

[0015] Therefore, the problem lies in the significant difference between the 300 μm spacing of the capacitors in the capacitor array CAP and the 50 μm spacing of the contact areas LA1 to LAn and RA1 to RAn of the VCSEL laser terminals in the VCSEL laser array of the VCSEL laser die VCSELA. As described in WO 2021 140 160A1, the VCSEL laser die VCSELA is also typically larger than multiple lasers radiating on the side.

[0016] Regarding the controller, this document references the technical teachings of WO 2021 140 160A1, and to the extent permitted by national laws (e.g., the technical teachings presented herein are sought for protection in the event of a claim for priority of this document), the technical content of which constitutes an entire portion of the disclosure presented herein. Summary of the Invention

[0017] Task

[0018] The purpose of this paper is to provide a design for a VCSEL laser driver for a VCSEL array with the lowest possible parasitic inductance value.

[0019] Solution to the task

[0020] The first optimal method of the solution

[0021] The capacitors LC1 to LCn of the left capacitor array CAPL must be positioned with a small spacing between the terminal contact areas LA1 to LAn of the VCSEL lasers L1 to Ln on the VCSEL laser array die VCSELA. The capacitors RC1 to RCn of the right capacitor array CAPR must be positioned with a small spacing between the terminal contact areas RA1 to Ran on the VCSEL lasers L1 to Ln on the VCSEL laser array die VCSELA. This is done to minimize the lengths of the bonding lines BdL1 to BdLn and BdR1 to BdRn. Here, bonding lines BdL1 to BdLn and BdR1 to BdRn connect the terminal contact areas LA1 to LAn and RA1 to Ran of the VCSEL lasers of the VCSEL laser array VCSELA on the VCSEL laser array to the corresponding contact areas LCA1 to LCAn and RCA1 to RCAn of the capacitors LC1 to LCn and RC1 to RCn on the capacitor array CAP. Preferably, the back side of the capacitor array CAP has a back-side contact representing a common electrical node, which preferably represents another electrical contact of all capacitors LC1 to LCn and RC1 to RCn of the capacitor array CAP. This allows short optical pulses to be generated by lasers L1 to Ln, preferably according to the technical inspiration of WO 2021 140 160A1.

[0022] To illustrate the optimization problem, this article will first refer to... Figure 1 and Figure 2 .

[0023] Figure 1 The less-than-ideal possible arrangement of the equipment for the laser module of a LiDAR system with a VCSEL laser die (VCSELA) is schematically and simplified in a plan view.

[0024] The following explanation also mentions this. Figure 2 The components. Therefore, this article recommends that readers also refer to... Figure 1 and Figure 2 .

[0025] The VCSEL laser die VCSELA is electrically and thermally mounted on the common cathode electrode C of all VCSEL lasers L1 to Ln using the common cathode contact of lasers L1 to Ln.

[0026] Each VCSEL laser L1 to Ln on the VCSEL laser die VCSELA is connected on the left side to the corresponding top-side contacts LCA1 to LCAn of the corresponding left-side capacitors LC1 to LCn via a relatively long corresponding bonding line BdL1 to BdLn through one of its left-side contacts LA1 to LAn.

[0027] Each VCSEL laser L1 to Ln of the VCSEL laser die VCSELA is connected on the right side to the corresponding top-side contacts RCA1 to RCAn of the corresponding right-side capacitors RC1 to RCn via one of its right-side contacts RA1 to RAN through a relatively long corresponding bonding line BdR1 to BdRn.

[0028] The bottom contacts of each capacitor LC1 to LCn and RC1 to RCn are electrically and thermally connected to the common ground plane GNDP as the second electrical contacts of these capacitors LC1 to LCn and RC1 to RCn. Therefore, the bottom contacts of capacitors LC1 to LCn and RC1 to RCn are electrically interconnected to form a star point. This star point is the grounding node GND.

[0029] The driver circuit IC is also placed on the ground plane GNDP. The driver circuit IC includes the discharge transistor T. DIS (see Figure 2 The discharge transistor T of the drive circuit IC. DIS It has a first terminal GNDT, which is electrically connected to the ground plane GNDP via a bonding wire BdGND in a downward bonding manner. The discharge transistor T of the drive circuit IC... DIS (see Figure 2The circuit has a second terminal CT, which is electrically connected to the cathode electrode C via a bonding wire BdCT, and thus electrically connected to the cathode contacts L1 to Ln of the VCSEL laser array die VCSELA. Typically, the driver circuit IC also includes a charging circuit SUPL. For better overview, this charging circuit SUPL is illustrated in the example... Figure 1 Not shown in the figure. This document exemplarily references the technical teachings of WO2021140 160A1, which have been mentioned.

[0030] exist Figure 1 In the case of discharge, when the discharge transistor T of the drive circuit IC... DIS When turned on, the two capacitors (i.e., one of the left capacitors LC1 to LCn and one of the right capacitors RC1 to RCn) provide power to each of the lasers L1 to Ln in the laser stripe form of the VCSEL laser array die VCSELA. Power is supplied by the discharge transistor T in the drive circuit IC. DIS When closed, the charging states of these capacitors LC1 to LCn and RC1 to RCn determine which of the lasers L1 to Ln in the VCSELA laser array die emits light.

[0031] exist Figure 1 In the example, the left capacitor, which belongs to the left capacitors LC1 to LCn, always supplies power to the laser associated with that left capacitor from the left.

[0032] exist Figure 1 In the example, the right capacitor, which belongs to the right capacitors RC1 to RCn, always supplies power to the laser associated with that right capacitor from the right side.

[0033] Therefore, the time required to turn on each laser, which is powered by its right-side capacitor and its left-side capacitor, is reduced.

[0034] Figure 2 An exemplary related circuit is shown. The charging circuit SUPL provides charging current to this circuit. The charging circuit SUPL is preferably part of the driver circuit IC.

[0035] Each of the lasers L1 to Ln is associated with one of the charging switches S1 to Sn.

[0036] During the early charging phase, the controller of the driver circuit IC closes the charging switches S1 to Sn associated with the lasers L1 to Ln that will emit light pulses next. Simultaneously, the discharge switch T of the driver circuit IC... DISNormally, it is disconnected. Then, during this charging phase, the charging circuit SUPL of the drive circuit IC uses the charging current of the charging circuit SUPL to charge the capacitors C1 to Cn connected to the charging circuit SUPL. Here, refer to Figure 1 Capacitors C1 to Cn form a parallel circuit, each consisting of one left-hand capacitor from LC1 to LCn and one right-hand capacitor from RC1 to RCn. For simplicity, Figure 2 These capacitor pairs, each consisting of one left capacitor from LC1 to LCn and one right capacitor from RC1 to RCn, are shown as the common capacitor for capacitors C1 to Cn. Each of these capacitors C1 to Cn is connected to a common ground point GND via its first terminal. Figure 1 The corresponding contact areas RCA1 to RCAn and LCA1 to LCAn of the corresponding capacitors LC1 to LCn and RC1 to RCn form the corresponding second terminals of the corresponding capacitors C1 to Cn and Figure 2 The corresponding nodes A1 to An. After charging the capacitors, the controller of the drive circuit IC can initiate the discharge of the capacitors, thereby initiating the light emission of the associated laser. In order to discharge capacitors C1 to Cn, if the charging switches S1 to Sn should still be closed after the capacitors are charged, the controller of the drive circuit IC preferably opens the charging switches S1 to Sn. If the controller of the drive circuit IC now closes the discharge transistor T DIS Then the previously charged capacitors C1 to Cn pass through the discharge switch T. DIS The inductance L of the junction lines BdL1 to BdLn and BdR1 to BdRn BD 1 to L BD n is transmitted through the corresponding lasers in lasers L1 to Ln and through the inductive discharge of the cathode contact C and the junction lines BdCT and BdGND. Therefore, the corresponding lasers in lasers L1 to Ln emit laser radiation.

[0037] exist Figure 1 In this embodiment, the current transfer between the corresponding charging switches S1 to Sn, used for pre-charging the corresponding associated capacitors C1 to Cn from the charging circuit SUPL, is carried out via relatively long connection lines, but the inductance of these connection lines is independent of the time-dynamic characteristics of the discharge of the corresponding associated capacitors. Therefore, this is not a problem in itself. On the contrary, it is quite positive because the parasitic inductance present here can effectively isolate the charging circuit SUPL from the discharging capacitors C1 to Cn during pulse generation. In this case, this paper again refers to the technical teachings of WO 2021 140 160A1.

[0038] However, the problem with this solution is that the junction lines BdL1 to BdLn and BdR1 to BdRn between the terminals LA1 to Ln and RA1 to Ran of the VCSEL laser array bare VCSELA and the top-side contacts te of the capacitors C1 to Cn are relatively long and have different wiring paths. This causes the laser module to suffer severe performance degradation due to its very high inductance, thus contradicting the technical teachings of WO 2021 140 160A1. Another problem is that the left capacitors LC1 to LCn of capacitors C1 to Cn can be well arranged on the first left capacitor array CAPL, and the right capacitors RC1 to RCn of capacitors C1 to Cn can be well arranged on the second right capacitor array CAPR.

[0039] Task improvement solutions

[0040] The proposed solution is to place a common capacitor array (CAP) beneath the VCSEL laser array die (VCSELA). Therefore, this paper presents a stacked die assembly of a VCSEL laser array die (VCSELA) with a capacitor array (CAP).

[0041] As described above, typically, a VCSEL laser array die VCSELA preferably has two rows of terminals LA1 to LAn and RA1 to RAn on its surface. The VCSEL lasers L1 to Ln of the VCSEL laser array die VCSELA can emit their light pulses in a manner perpendicular to the surface of the VCSEL laser array die VCSELA.

[0042] Preferably, the left-side terminals of the left row of terminals LA1 to LAn and the corresponding right-side terminals of the right row of terminals RA1 to RAn are typically in contact with exactly one corresponding internal top-side contact of exactly one of the corresponding VCSEL lasers L1 to Ln of the VCSEL laser array die VCSELA. Preferably, the VCSEL lasers L1 to Ln have a common lower contact in the form of a common cathode, which is electrically connected to a common cathode electrode C, and preferably thermally connected to the common cathode electrode C.

[0043] On the capacitor array CAP, for example, a metallized surface is applied in an electrically isolated manner in the third metallization layer. This metallized surface is electrically and thermally connected to the common cathode electrode C and electrically isolated (isolated) from other conductive parts of the capacitor array CAP, but not thermally isolated (isolated).

[0044] like Figure 11 and Figure 12As shown, the proposed capacitor array CAP also has left-side terminals LCA1 to LCAn in the left row and right-side terminals RCA1 to RACn in the right row. The left-side terminals LCA1 to LCAn and the right-side terminals RCA1 to RACn of the capacitor array CAP are now electrically connected to each other via wires in a second metallization layer on the surface of the capacitor array CAP. These drive lines for the capacitor array CAP in the second metallization layer of the capacitor array CAP are located below the third metallization layer of the capacitor array CAP. The actual top electrodes te of the capacitors C1 to Cn of the capacitor array CAP are fabricated in the first metallization layer of the capacitor array CAP, located below the second and third metallization layers of the capacitor array CAP. Compared to the suboptimal embodiment described above, each laser L1 to Ln now requires exactly one capacitor C1 to Cn, respectively. It is no longer necessary to divide the capacitors C1 to Cn into left-side and right-side capacitors. Through-hole interconnects selectively connect the drive lines of the capacitor array CAP to the lower top electrodes te of the capacitors C1 to Cn of the capacitor array CAP. According to the proposal, the spacing ICLA between the drive lines ICL of the capacitor array CAP is based on the minimum fifth spacing PTLa of lasers L1 to Ln in the VCSEL laser array die VCSELA. Preferably, the spacing ICLA between the drive lines ICL of the capacitor array CAP is equal to the minimum fifth spacing PTLa of lasers L1 to Ln in the VCSEL laser array die VCSELA. Preferably, capacitors C1 to Cn are arranged in rows and columns in the capacitor array CAP. Now, multiple drive lines of the capacitor array CAP are located above adjacent capacitors in a row of the capacitor array CAP. Each capacitor in a row of the capacitor array CAP is electrically connected to exactly one drive line in the capacitor array CAP through a via interconnect. Therefore, in a row of the capacitor array CAP, the number of capacitors adjacent to each other in the capacitor array CAP is exactly the same as the number of drive lines that cross them in a manner electrically isolated from their top contacts. Here, exactly one of these drive lines is always electrically connected to the associated capacitor through a via interconnect. Therefore, firstly, the spacing between capacitors C1 to Cn in the capacitor array CAP can be consistent with the spacing between lasers L1 to Ln in the VCSEL laser array die VCSELA. Secondly, this allows the laser discharge current I from capacitors C1 to Cn to be... dis The capacitors are symmetrically supplied to lasers L1 through Ln from the left and right sides. Since the main portion of the capacitor array CAP is located below the VCSEL laser array die VCSELA, the mounting space is also reduced. This is due to the capacitor discharge current I... disThe different current directions, whether in a plan view or a side view, mean that the far magnetic field of these discharge currents is essentially compensated at greater distances, which improves EMC characteristics and reduces inductance. Therefore, the edge steepness of the emitted laser pulses from lasers L1 to Ln is improved.

[0045] Short bonding lines BdL1 to BdLn connect the left-side terminals LCA1 to LCAn of the capacitor array CAP to the left-side terminals LA1 to LAn of the VCSEL laser array die VCSELA.

[0046] Short bonding lines BdR1 to BdRn connect the right-side terminals RCA1 to RCAn of the capacitor array CAP to the right-side terminals RA1 to RAN of the VCSEL laser array die VCSELA.

[0047] On the capacitor array CAP, a cathode plate is metallized into the form of a common cathode electrode C, serving as the common cathode for the VCSEL lasers L1 to Ln of the VCSEL laser array die VCSELA. The common cathode electrode C is used as the discharge transistor T from the drive circuit IC. DIS The second terminal CT is connected to the common cathode electrode C and thus to the bonding line BdCT of the common cathode of the VCSEL laser array bare VCSELA laser L1 to Ln, in the placement area of ​​the bonding ball.

[0048] The common cathode electrode C is connected to the discharge transistor T of the drive circuit IC via multiple bonding wires BdCT. DIS The corresponding second terminal CT. The second terminal of the common cathode electrode C is the switching transistor T in the technical instruction of WO2021 140 160A1. dis The public stars.

[0049] In one variation, the drive lines of the drive circuit IC are connected to connection points BP1 to BP4 on the printed circuit board (PCB). Other circuit components and electrical / electronic components are preferably located on the PCB. The charging circuits of WO 2021 140 160A1 are not shown in the figures. These charging circuits are located in the drive circuit IC, or preferably in other circuits on the PCB. Preferably, the capacitors C1 to Cn of the capacitor array CAP are connected to their respective charging circuits on the PCB or in the drive circuit IC via other bonding lines and possible traces on the PCB. These other bonding lines are typically relatively long and are not shown in the figures.

[0050] Furthermore, the technical inspiration presented in this paper suggests connecting the back contacts of the capacitor array (CAP) to a thermally and electrically conductive ground plane (GNDP), such as that made of aluminum or copper, instead of a poorly thermally conductive printed circuit board (PCB). Gold-plated copper would be an ideal material for such a ground plane GNDP. For example, it could be a heatsink (HS).

[0051] For example, a printed circuit board (PCB) can also be attached to a heat sink (HS). Bonding lines BD1 to BD4 preferably establish an electrical connection between the driver circuit IC and the printed circuit board (PCB).

[0052] The capacitor array CAP preferably comprises three metal layers. The top electrodes (top electrodes te) of the capacitors C1 to Cn of the capacitor array CAP are formed in the first metal layer M1. An insulating layer INS electrically separates the first metal layer M1 from the second metal layer M2. The connecting lines ICL of the capacitors C1 to Cn of the capacitor array CAP are formed in the second metal layer M2. The connecting lines ICL in the second metal layer M2 are electrically connected to the top electrodes te in the first metal layer M1 through via interconnects DK in the insulating layer INS. The capacitor array CAP also includes a substrate SUB. The substrate SUB preferably includes the dielectric of the capacitors C1 to Cn of the capacitor array CAP. The bottom side of the capacitor array CAP is formed by substrate contacts SUBC. The regions between the top electrodes te in the first metal layer M1 and the substrate contacts SUBC respectively form the vertical capacitances of the capacitors C1 to Cn of the capacitor array CAP. Therefore, these capacitances are the vertical capacitances between the first metal layer M1 and the substrate contacts SUBC on the bottom side of the capacitor array CAP, which are shared by all the capacitors C1 to Cn of the capacitor array CAP. The substrate contact SUBC is preferably electrically connected to the ground plane GNDP. Therefore, on the back side, all capacitors C1 to Cn of the capacitor array CAP are shorted together. The respective top electrodes te of the corresponding capacitors are respectively fabricated in the first metal layer M1. The lateral connecting line ICL is fabricated in the second metal layer M2. The common cathode electrode C of the VCSEL laser array die VCSELA can preferably be fabricated in the third metal layer M3.

[0053] Main variation example A

[0054] Therefore, this document describes a first optical module LM, which includes a carrier, a capacitor array CAP, and a VCSEL laser array die VCSELA. The carrier has a top side. Preferably, the carrier has a conductive, electrically contactable ground plane GNDP on its top side. The VCSEL laser array die VCSELA preferably has a top side and a bottom side. Preferably, the VCSEL laser array die VCSELA includes n lasers L1 to Ln, where n is a positive integer greater than 0. Preferably, the VCSEL laser array die VCSELA has a left row of n electrically contactable left-side contact areas LA1 to LAn on its surface. Preferably, the VCSEL laser array die VCSELA has a right row of n electrically contactable right-side contact areas RA1 to RAn on its surface. Preferably, the anode of each laser in the VCSEL laser array die VCSELA, from lasers L1 to Ln, is electrically connected to a corresponding left-side contact area in the n contact areas LA1 to LAn of the left row, and electrically connected to a corresponding right-side contact area in the n contact areas LA1 to LAn of the right row. Preferably, the VCSEL laser array die VCSELA has a common cathode contact on its bottom side. Preferably, the cathode of each laser in the VCSEL laser array die VCSELA, from lasers L1 to Ln, is electrically connected to this common cathode contact on the bottom side of the VCSEL laser array die VCSELA. Typically, the lasers L1 to Ln of the VCSEL laser array die VCSELA have a minimum fifth spacing PTLa between them. The capacitor array CAP has a top side and a bottom side. The capacitor array CAP typically includes one or more capacitors, preferably n capacitors C1 to Cn. The capacitor array CAP includes a substrate SUB. The capacitor array CAP has electrically contactable substrate contacts (SUBC) on its bottom side. The capacitor array CAP comprises n capacitors C1 to Cn, where n is a positive integer greater than 0. The capacitor array CAP typically has a cathode electrode C on its top side, usually in a third metal layer M3. Preferably, the capacitor array CAP has a left-side row of electrically contactable left-side contact regions LC1 to LCn on its surface. Preferably, the capacitor array CAP has a right-side row of electrically contactable right-side contact regions LC1 to LCn on its surface. For each of the n capacitors C1 to Cn, the capacitor array CAP typically has exactly one upper-side top electrode te. Preferably, each top electrode te, together with the material of the substrate SUB in the region substantially defined by the range of the top electrode te, and together with the substrate electrode SUB, forms the corresponding capacitor among the capacitors C1 to Cn of the capacitor array CAP associated with that top electrode. The upper-side top electrode te is preferably fabricated in the first metal layer M1 on the substrate SUB.The n top electrodes of the capacitor array CAP, and therefore the n capacitors C1 to Cn, are preferably arranged in j rows and k columns in the substrate SUB of the capacitor array CAP, where j*k = m, and j and k are positive integers. The rows of capacitors C1 to Cn in the capacitor array CAP have a second spacing PTCY in a row of the capacitor array CAP. The columns of capacitors C1 to Cn have a third spacing PTCX in a column of the capacitor array CAP. Preferably, the capacitor array CAP typically has m connecting lines ICL in the second metal layer M2, where m is a positive integer. The connecting lines ICL are preferably aligned parallel to the rows of capacitors C1 to Cn. The fourth spacing PTCC between the connecting lines ICL is typically substantially equal to the second spacing PTCY of the rows of capacitors C1 to Cn divided by the number of columns of capacitors C1 to Cn.

[0055] The deviation of the minimum fifth spacing PTLa between the laser diodes L1 to Ln of the VCSEL laser array die VCSELA from each other relative to the minimum fourth spacing PTCC of the contact areas LCA1 to LCAn and RCA1 to RCAn of the capacitor array CAP is preferably no more than 25%, better no more than 10%, better no more than 5%, better no more than 2%, and / or better no more than 1%.

[0056] The deviation of the minimum first spacing PTL between the left contact areas LA1 to LAn of the VCSEL laser array die VCSELA from each other relative to the minimum fourth spacing PTCC of the contact areas LCA1 to LCAn and RCA1 to RCAn of the capacitor array CAP capacitors C1 to Cn is preferably no more than 25%, more preferably no more than 10%, more preferably no more than 5%, more preferably no more than 2%, and / or more preferably no more than 1%.

[0057] The deviation of the minimum first spacing PTR between the right contact regions RA1 to RAN of the VCSEL laser array die VCSELA from the minimum fourth spacing PTCC of the contact regions LCA1 to LCA1 to RCA1 to RCA1 to RCA1 of the capacitor array CAP is preferably no more than 25%, better no more than 10%, better no more than 5%, better no more than 2%, and / or better no more than 1%.

[0058] Third metal layer M3 (see Figure 12The first metal layer M1 is typically located above the second metal layer M2 and the first metal layer M1 on the surface of the substrate SUB. The second metal layer M2 is typically located above the first metal layer M1 on the surface of the substrate SUB and is typically located below the third metal layer M3. The third metal layer M3 is preferably electrically isolated from the second metal layer M2, the first metal layer M1, and the substrate SUB by an insulator INS. The second metal layer M2 is preferably electrically isolated from the first metal layer M1 and the substrate SUB by an insulator INS or the insulator INS. Preferably, each of the n connection lines ICL connects at least one corresponding top electrode te of the capacitor C1 to Cn associated with the connection line ICL to a corresponding left contact area of ​​the electrically accessible left contact area LC1 to LCn in the left row of the capacitor array CAP via a corresponding through-hole interconnect DK, and simultaneously connects to a corresponding right contact area of ​​the electrically accessible right contact area RC1 to RCn in the right row of the capacitor array CAP.

[0059] Refer again Figure 3 and Figure 4 Preferably, each of the n left-side contact regions LA1 to LAn in the left row of the VCSEL laser array die VCSELA is electrically connected to a corresponding left-side contact region LC1 to LCn in the left row of the capacitor array CAP. Preferably, each of the n right-side contact regions RA1 to RAn in the right row of the VCSEL laser array die VCSELA is electrically connected to a corresponding right-side contact region RC1 to RCn in the right row of the capacitor array CAP.

[0060] The common cathode contact C of the VCSEL laser array die VCSELA is preferably placed on and electrically connected to the cathode electrode C of the capacitor array CAP. Here, the cathode electrode C of the capacitor array CAP is electrically isolated from the capacitors C1 to Cn of the capacitor array CAP. The substrate contact SUBC of the capacitor array CAP is preferably placed on and electrically connected to the ground plane GNDP, and is preferably mechanically fixed to the ground plane GNDP.

[0061] In the first sub-variant, the optical module LM also includes a driver circuit IC (see...). Figure 3 The driver circuit IC typically has a top side and a bottom side. The driver circuit IC preferably includes a discharge transistor T. DIS (See also: Figure 2 Discharge transistor T) DIS Preferably, it has a discharge transistor T DIS The first terminal GNDT. Discharge transistor T DISPreferably, it has a discharge transistor T DIS The second terminal CT. Discharge transistor T DIS It typically has control terminals. The discharge transistor T discharges according to the electrical state of the control terminals. DIS The first terminal GNDT can be electrically isolated from its second terminal CT, or the first terminal GNDT can be electrically connected to its second terminal CT. Discharge transistor T DIS The first terminal GNDT is preferably electrically connected to the ground plane GNDP. Discharge transistor T DIS The second terminal CT is preferably electrically connected to the cathode electrode C. The bottom side of the drive circuit IC is preferably attached to the surface of the carrier. The control circuit of the drive circuit IC is controlled by the discharge transistor T. DIS The control terminal controls the discharge transistor T DIS .

[0062] In the second sub-variant example, which is the first sub-variant example, when the discharge transistor T of the drive circuit IC... DIS When turned off, the driver circuit IC can use the charging current of the capacitor array CAP to charge the capacitors C1 to Cn through the charging circuit SUPL of the driver circuit IC.

[0063] In the third sub-variant example, which is the second sub-variant example, the device components of the drive circuit IC and / or other circuits attached to or part of the carrier can control the discharge transistor T of the drive circuit IC. DIS The control terminal enables the discharge transistor T DIS The corresponding lasers L1 to Ln, associated with capacitors C1 to Cn of the capacitor array CAP via the VCSEL laser array die VCSELA, utilize the corresponding laser-specific discharge current I. dis The capacitors C1 to Cn of the capacitor array CAP are discharged. Then, a discharge current I flows through the VCSEL laser array die VCSELA. dis Lasers L1 to Ln emit light in a manner perpendicular to the surface of the VCSEL laser array die VCSELA.

[0064] In the fourth sub-variant, which is a sub-variant of the previous sub-variant, the carrier includes a printed circuit board (PCB) and / or a heat sink (HS) (see Figure 7 and Figure 8 ).

[0065] Main variant B (flip-chip assembly)

[0066] Therefore, this paper describes a first optical module LM, which includes a carrier, a capacitor array (CAP), and a VCSEL laser array die (VCSELA). In the case of a flip-chip assembly (… Figure 9The carrier has a top side. Preferably, the carrier has a conductive, electrically contactable ground plane GNDP on its top side. The VCSEL laser array die VCSELA preferably has a top side and a bottom side. Preferably, the VCSEL laser array die VCSELA includes n lasers L1 to Ln, where n is a positive integer greater than 0. Preferably, the VCSEL laser array die VCSELA includes n electrically contactable left-side contact areas LA1 to LAn in a left row on its surface. Preferably, the VCSEL laser array die VCSELA has n electrically contactable right-side contact areas RA1 to RAn in a right row on its surface. Preferably, the anode of each laser in the VCSEL laser array die VCSELA is electrically connected to the corresponding left-side contact area in the n contact areas LA1 to LAn in the left row and electrically connected to the corresponding right-side contact area in the n contact areas LA1 to LAn in the right row. Preferably, the VCSEL laser array die VCSELA has a common cathode contact C on its bottom side. Preferably, the cathode of each of the lasers L1 to Ln of the VCSEL laser array die VCSELA is electrically connected to this common cathode contact C on the bottom side of the VCSEL laser array die VCSELA. Typically, the lasers L1 to Ln of the VCSEL laser array die VCSELA have a minimum fifth spacing PTLa between each other. The capacitor array CAP has a top side and a bottom side. The capacitor array CAP typically includes one or more capacitors, preferably n capacitors C1 to Cn. The capacitor array CAP includes a substrate SUB. The capacitor array CAP has electrically contactable substrate contacts SUBC on its bottom side. The capacitor array CAP includes n capacitors C1 to Cn, where n is a positive integer greater than 0. Preferably, the capacitor array CAP has a left row of electrically contactable left-side contact areas LC1 to LCn on its surface. Preferably, the capacitor array CAP has a right row of electrically contactable right-side contact areas RC1 to RCn on its surface. For each of the n capacitors C1 to Cn, the capacitor array CAP typically has exactly one upper top electrode te. Preferably, each top electrode te, together with the material of the substrate SUB in the region substantially defined by the range of the top electrode te, and together with the substrate contacts SUB, forms the corresponding capacitor of the capacitors C1 to Cn associated with that top electrode in the capacitor array CAP. The upper top electrode te is preferably fabricated in a first metal layer M1 on the substrate SUB. The n upper top electrodes of the capacitor array CAP, and therefore the n capacitors C1 to Cn, are preferably arranged in j rows and k columns in the substrate SUB of the capacitor array CAP, where j*k = m, and j and k are positive integers. The rows of capacitors C1 to Cn have a second spacing PTCY in a row of the capacitor array CAP.The k columns of capacitors C1 to Cn have a third column spacing PTCX in one column of the capacitor array CAP. Preferably, the capacitor array CAP typically has m connecting lines ICL in the second metal layer M2, where m is a positive integer. The connecting lines ICL are preferably aligned parallel to the rows of capacitors C1 to Cn. The fourth spacing PTCC between the connecting lines ICL is typically substantially equal to the second spacing PTCY divided by the number of columns of capacitors C1 to Cn.

[0067] The deviation of the minimum fifth spacing PTLa between the laser diodes L1 to Ln of the VCSEL laser array die VCSELA from each other relative to the fourth spacing PTCC between the connecting lines ICL is preferably no more than 25%, more preferably no more than 10%, more preferably no more than 5%, more preferably no more than 2%, and / or more preferably no more than 1%.

[0068] The deviation of the first spacing PTL between the left contact areas LA1 to LAn of the VCSEL laser array die VCSELA from the fourth spacing PTCC between the connecting lines ICL is preferably no more than 25%, more preferably no more than 10%, more preferably no more than 5%, more preferably no more than 2%, and / or more preferably no more than 1%.

[0069] The deviation of the first spacing PTR between the right contact areas RA1 to RAN of the VCSEL laser array die VCSELA from each other relative to the fourth spacing PTCC between the connecting lines ICL is preferably no more than 25%, more preferably no more than 10%, more preferably no more than 5%, more preferably no more than 2%, and / or more preferably no more than 1%.

[0070] Second metal layer M2 (see Figure 12 The second metal layer M2 is typically located above the first metal layer M1 on the surface of the substrate SUB. The second metal layer M2 is preferably electrically isolated from the first metal layer M1 and the substrate SUB by an insulator INS or the insulator INS.

[0071] Preferably, each of the n connecting lines ICL electrically connects at least one corresponding top electrode te of the capacitor associated with the connecting line ICL in the capacitors C1 to Cn to the corresponding left contact area in the electrically accessible left contact area LC1 to LCn in the left row of the capacitor array CAP via a corresponding through-hole interconnection portion DK, and electrically connects to the corresponding right contact area in the electrically accessible right contact area RC1 to RCn in the right row of the capacitor array CAP.

[0072] Preferably, each of the n left-side contact regions LA1 to LAn in the left row of the VCSEL laser array die VCSELA is electrically connected via solder ball SB to the corresponding left-side contact region LC1 to LCn in the left row of the capacitor array CAP.

[0073] Preferably, each of the n right-side contact regions RA1 to RAN in the right row of the VCSEL laser array die VCSELA is electrically and mechanically fixedly connected via solder balls SB to the corresponding right-side contact regions RC1 to RCn in the right row of the capacitor array CAP.

[0074] The common cathode contact of the VCSEL laser array die VCSELA forms the cathode electrode C. The substrate contact SUBC of the capacitor array CAP is preferably placed on and electrically connected to the ground plane GNDP, and preferably mechanically fixed to the ground plane GNDP.

[0075] In the first sub-variant, the optical module LM also includes a driver circuit IC. The driver circuit IC typically has a top side and a bottom side. The driver circuit IC preferably includes a discharge transistor T. DIS Discharge transistor T DIS Preferably, it has a discharge transistor T DIS The first terminal GNDT. Discharge transistor T DIS Preferably, it has a discharge transistor T DIS The second terminal CT. Discharge transistor T DIS It typically has control terminals. The discharge transistor T discharges according to the electrical state of the control terminals. DIS The first terminal GNDT can be electrically isolated from its second terminal CT, or the first terminal GNDT can be electrically connected to its second terminal CT. Discharge transistor T DIS The first terminal GNDT is preferably electrically connected to the ground plane GNDP. Discharge transistor T DIS The second terminal CT is preferably electrically connected to the cathode electrode C. The bottom side of the drive circuit IC is preferably attached to the surface of the carrier.

[0076] In the second sub-variant example, which is the first sub-variant example, when the discharge transistor T... DIS When turned off, the drive circuit can use the charging current of the charging circuit SUPL to charge the capacitors C1 to Cn of the capacitor array CAP.

[0077] In the third sub-variant example, which is the second sub-variant example, the device components of the drive circuit IC and / or other circuits attached to or part of the carrier can control the discharge transistor T. DISThe control terminal enables the discharge transistor T DIS The corresponding lasers L1 to Ln, associated with capacitors C1 to Cn of the capacitor array CAP via the VCSEL laser array die VCSELA, utilize the specific discharge current I of the corresponding lasers. dis The capacitors C1 to Cn of the capacitor array CAP are discharged. Then, a discharge current I flows through the VCSEL laser array die VCSELA. dis Lasers L1 to Ln emit light in a manner perpendicular to the surface of the VCSEL laser array die VCSELA.

[0078] In the fourth sub-variant, which is a sub-variant of the previous sub-variant, the carrier includes a printed circuit board (PCB) and / or a heat sink (HS).

[0079] advantage

[0080] Therefore, this device is characterized by its very small inductance, while maintaining high mounting density and a compact structure. Furthermore, the reverse discharge current I... dis This reduces electromagnetic interference radiation, which further reduces inductance. Another advantage is reduced installation space. However, the advantages are not limited to this. Attached Figure Description

[0081] Figure 1 Possible suboptimal arrangements are shown.

[0082] Figure 2 The basic circuit is shown.

[0083] Figure 3 The basic principles of the preferred arrangement proposed in this paper are illustrated in a plan view.

[0084] Figure 4 It shows Figure 3 An exemplary cross-section of the structure.

[0085] Figure 5 This demonstrates how EMC optimization and inductance minimization are achieved through anti-parallel discharge current.

[0086] Figure 6 It corresponds to Figure 5 Floor plan.

[0087] Figure 7 It is proposed to use the heat sink HS as the ground plane GNDP directly instead of using the ground plane GNDP on the printed circuit board PCB.

[0088] Figure 8It is proposed to directly use the heatsink HS as the ground plane GNDP instead of the ground plane GNDP on the printed circuit board PCB, and to use, for example, screws SC electrically isolated from the heatsink HS to fix the smaller printed circuit board PCB to the heatsink HS and close to the drive circuit IC.

[0089] Figure 9 A method using a VCSEL laser array die VCSELA that emits light through the back side is proposed as the VCSEL laser array die VCSELA, and the electrical connection between the capacitor array CAP and the VCSEL laser array die VCSELA does not use bonding wires (such as...). Figures 1 to 8 (As shown), instead of through flip-chip technology or similar means, this further reduces inductance.

[0090] Figure 10 It corresponds to Figure 9 A cross-sectional view of the laser module.

[0091] Figure 11 An exemplary construction of a capacitor array (CAP) is schematically shown in cross-section.

[0092] Figure 12 An exemplary, simplified, non-scaled cross-sectional view of a capacitor array (CAP) is shown to illustrate the wiring planes at different locations of the capacitor array (CAP). Detailed Implementation

[0093] Figure 1

[0094] Figure 1 A possible suboptimal arrangement of the device components is shown. Preferably, the VCSEL laser array die VCSELA has a plurality (e.g., n) of VCSEL lasers L1 to Ln. The first terminal of each of the n VCSEL lasers L1 to Ln of the VCSEL laser array die VCSELA is electrically, mechanically, and thermally connected to a common cathode electrode C via a lower contact of the first terminal of its cathode. A bonding line BdCT connects the common cathode electrode C to the discharge transistor T of the drive circuit IC. DIS The corresponding connection region CT. The discharge transistor T DIS It is part of the driver circuit IC. Discharge transistor T DIS exist Figure 2 As shown in the image. For clarity, Figure 1 The discharge crystal T is not shown in the image. DIS The connection region CT is preferably the discharge transistor T of the drive circuit IC. DIS The second terminal. It is typically preferably formed into the discharge transistor T. DISThe drain terminal of the N-channel MOS transistor. At this point, reference has been made to... Figure 2 , Figure 2 The discharge circuit of the driver IC is shown in a schematic and simplified manner.

[0095] Preferably, the driving circuit IC (see also) Figure 2 The discharge transistor T) DIS The other terminal of the first connection area GNDT is connected to the ground plane GNDP via another bonding line BdGND. The bonding line BdGND connects the discharge transistor T of the drive circuit IC. DIS The first terminal GNDT is connected to the ground plane GNDP.

[0096] Two rows of n capacitors, RC1 to RCn and LC1 to LCn, are placed on the left and right sides of the VCSEL laser array die VCSELA, respectively. The left capacitor row consisting of the n left capacitors LC1 to LCn can be designed as a common left capacitor array CAPL. The right capacitor row consisting of the n right capacitors RC1 to RCn can be designed as a common right capacitor array CAPR. Each of these capacitors RC1 to RCn and LC1 to LCn has a lower terminal contact and corresponding upper terminal contacts LCA1 to LCAn and RCA1 to RCAn.

[0097] Preferably, the lower contacts of each of these capacitors RC1 to RCn and LC1 to LCn are electrically connected to the ground plane GNDP, and preferably are also thermally connected to the ground plane GNDP. Preferably, each of these capacitors RC1 to RCn and LC1 to LCn is attached to the ground plane GNDP.

[0098] Preferably, each of the corresponding upper contacts LCA1 to LCAn and RCA1 to RCAn of the 2×n corresponding capacitors RC1 to RCn and LC1 to LCn is electrically connected via corresponding bonding lines BdL1 to BdLn and BdR1 and BdRn to exactly one contact LA1 to LAn and RA1 to RAn of one of the VCSEL lasers L1 to Ln of the VCSEL laser array die VCSELA.

[0099] The connection between the right-side capacitors RC1 to RCn and the necessary n charging circuits is preferably achieved through the junction lines connected to the right-side contacts RCA1 to RCAn of the n right-side capacitors RC1 to RCn. For a better overview, Figure 1 These joining lines are not shown in the diagram.

[0100] The connection between the left-side capacitors LC1 to LCn and the necessary n charging circuits is preferably achieved through the bonding wires connected to the left-side contacts LCA1 to LCAn of the n left-side capacitors LC1 to LCn. For a better overview, Figure 1 These joining lines are not shown in the diagram.

[0101] The length of the junction line between the left contacts LCA1 to LCAn of the n left-side capacitors LC1 to LCn and the left contacts LA1 to LAn of the n VCSEL lasers L1 to Ln of the VCSEL laser array die VCSELA is crucial to the achievable switching speed.

[0102] The length of the junction line between the right contacts RCA1 to RCAn of the n right-side capacitors RC1 to RCn and the right contacts RA1 to RAN of the n VCSEL lasers L1 to Ln of the VCSEL laser array die VCSELA is also crucial to the achievable switching speed.

[0103] However, Figure 1 The bonding lines BdL1 to BdLn and BdR1 to BdRn in the design are too long. The problem is that the bonding lines BdL1 to BdLn and BdR1 to BdRn between the terminals LA1 to LAn and RA1 to RAn of the VCSEL laser L1 to Ln and the terminals LCA1 to LCAn and RCA1 to RCAn of the capacitors LC1 to LCn and RC1 to RCn are relatively long and of varying lengths, with different wiring paths. This leads to a severe degradation in the performance of the laser module because the inductance of these bonding lines BdL1 to BdLn and BdR1 to BdRn of varying lengths and wiring paths is very high, thus contradicting the technical instruction of WO 2021 140 160A1. Another problem is that the left capacitors LC1 to LCn can be well placed on the first left capacitor array CAPL, and the right capacitors RC1 to RCn can be well placed on the second right capacitor array CAPR. However, for further optimization, it is desirable to further compress them into a common capacitor array CAP. Therefore, the purpose of this paper is still to propose a method that is more... Figure 1 The structure shown is a better structure.

[0104] Figure 2

[0105] Figure 2 An exemplary circuit is shown. The circuit includes basic sub-components (S1 to Sn, SUPL, T) with a driver circuit IC. DIS The driver circuit IC and lasers L1 to Ln are included. The charging circuit SUPL of the driver circuit IC is... Figure 2The circuit provides the charging current. The charging circuit SUPL is preferably part of the driver circuit IC. The controller of the driver circuit IC closes the charging switches S1 to Sn associated with the laser L1 to Ln that will next emit a light pulse. Simultaneously, the discharge switch T of the driver circuit IC... DIS Normally disconnected. Then, the charging circuit SUPL of the drive circuit IC charges the n capacitors C1 to Cn of the capacitor array CAP through the closed charging switches of the n charging switches S1 to Sn connected to the charging circuit SUPL using the charging current of the charging circuit SUPL. Here, Figure 1 The n capacitors C1 to Cn represent those respectively made by Figure 1 One of the left-side capacitors LC1 to LCn and Figure 1 The parallel circuit consists of one of the right-side capacitors RC1 to RCn. For a better overview, Figure 2 The diagram shows n capacitors C1 to Cn, instead of... Figure 1 There are n left-side capacitors LC1 to LCn and n right-side capacitors RC1 to RCn. These n capacitors C1 to Cn are each connected to the common ground GND via their first terminals. Figure 1 The corresponding contact areas RCA1 to RCAn and LCA1 to LCAn of the corresponding n capacitors LC1 to LCn and RC1 to RCn form the corresponding second terminals of the corresponding capacitors C1 to Cn and Figure 2 The corresponding nodes A1 to An. To discharge n capacitors C1 to Cn, if charging switches S1 to Sn should remain closed after the capacitors are charged, the controller of the drive circuit IC preferably opens the charging switches S1 to Sn that may still be closed. If the controller of the drive circuit IC now closes the discharge transistor T... DIS Then, the capacitors C1 to Cn among the n capacitors are discharged via the discharge switch T. DIS and the junction lines BdL1 to BdLn and BdR1 to BdRn (see Figure 1 The junction line inductance L BD 1 to L BD n is discharged via the corresponding lasers of lasers L1 to Ln and the cathode contact C. Therefore, the corresponding lasers of lasers L1 to Ln emit laser radiation.

[0106] The current transfer between the corresponding charging switches S1 to Sn, used for pre-charging the respective associated capacitors C1 to Cn from the charging circuit SUPL, is carried out via relatively long corresponding connection lines, but the inductance of these connection lines is independent of the time-dynamic characteristics of the discharge of the respective associated capacitors. This is not a problem in itself, because the parasitic inductance generated here effectively isolates the charging circuit SUPL from the respective discharging capacitors of the n capacitors C1 to Cn during pulse generation. In this case, this paper again refers to the technical inspiration of WO 2021 140 160A1.

[0107] Figure 2 A typical discharge circuit is shown in a simplified and schematic manner. Since it is not necessary to distinguish between the capacitors RC1 to RCn and LC1 to LCn on the left and right sides, the capacitors C1 to Cn of the capacitor array CAP are now drawn as C1 to Cn. Each of the n laser diodes L1 to Ln is associated with exactly one corresponding charging switch from the n charging switches S1 to Sn and one of the corresponding capacitors C1 to Cn of the capacitor array CAP. Before the corresponding laser diode of the VCSEL laser array die VCSELA emits its laser L1 to Ln, the charging circuit SUPL charges this corresponding capacitor of the n capacitors C1 to Cn of the capacitor array CAP precisely through the associated charging switch from the n charging switches S1 to Sn. For this purpose, the controller closes the corresponding charging switch from the switches S1 to Sn associated with that laser diode of the n laser diodes L1 to Ln of the VCSEL laser array die VCSELA.

[0108] If the capacitor C1 to Cn of the capacitor array CAP is charged, which is associated with one of the n lasers L1 to Ln of the VCSEL laser array die VCSELA, the controller closes the discharge transistor T. DIS A discharge switch of the form. Therefore, the discharge transistor T. DIS The capacitor is discharged by a laser diode associated with it, causing a discharge current to flow through the laser diode. This discharge current causes the laser diode to emit light. The controller then disconnects the discharge transistor T again. DIS The inductor L shown BD 1 to L BD n is the inductance of the junction line between the corresponding capacitor and the laser associated with that capacitor. Therefore, the corresponding junction line must be as short as possible to minimize these inductances L. BD 1 to L BD n is minimized because they limit the steepness of the rising edge.

[0109] Figure 3

[0110] Figure 3 The basic principles of the arrangement proposed in this paper are shown.

[0111] The VCSEL laser array die VCSELA utilizes the common cathode of lasers L1 to Ln arranged on a common cathode electrode C. Preferably, the common cathode electrode C is fabricated in a third metal layer M3 of the wiring metal layer of the capacitor array CAP on the surface of the capacitor array CAP. Here, the common cathode of the VCSEL laser array die VCSELA is typically electrically and thermally connected to the common cathode electrode C. The common cathode electrode C is typically electrically isolated from other device components of the capacitor array CAP by one or more insulators INS. Preferably, each of the n capacitors C1 to Cn of the capacitor array CAP has two terminals, namely, one left terminal of the n terminals LCA1 to LCAn and a corresponding right terminal of the n terminals RCA1 to RCAn. Preferably, the two terminals of one of the n capacitors C1 to Cn of the capacitor array CAP are located on the left and right sides of the VCSEL laser array die VCSELA. For example, for the first capacitor C1, the left contact region LCA1 is placed to the left of the VCSEL laser array die VCSELA, and the right contact region RCA1 is placed to the right of the VCSEL laser array die VCSELA. As a result... Figure 11 The prior description, as already mentioned here, is in the following Figure 11 The diagram shows two contact areas, LCA1 and RCA1, contacting the top electrode te on the upper side of the first capacitor C1 (see [reference]). Figure 11 ). Figure 3 The top electrode te is not shown. In this regard, this document refers to the following... Figure 11 Therefore, the top electrode te on the upper side of the first capacitor C1 essentially short-circuits the two contact areas LCA1 and RCA1 to each other, making them essentially electrical nodes A1. This node A1 is... Figure 2 Node A1 in the diagram. This is necessary to understand why this structure is particularly advantageous. In this way, each of the nodes A1 to An of the corresponding upper top electrodes te of the respective capacitors C1 to Cn can always be electrically connected through exactly one left contact region of the left contact region LCA1 to LCAn and exactly one right contact region of the right contact region RCA1 to RCAn. This will be relevant to the following... Figure 11 The explanation becomes clearer.

[0112] Typically, a proper internal design of the capacitor array (CAP) ensures that the left-side spacing PTCL between the left-side contact regions LCA1 to LCAn of the CAP coincides with the first spacing PTL between the left-side contact regions LA1 to LAn of the VCSEL laser array die VCSELA. This ensures that the lengths of the bonding lines BdL1 to BdLn between each left-side contact region of the CAP and each left-side contact region of the VCSEL laser array die VCSELA are always approximately the same, and minimizes the length of the bonding lines.

[0113] The driver circuit IC is placed and fixed on the ground plane GNDP. The driver circuit IC is preferably, but not necessarily, electrically connected to the ground plane GNDP via its rear contacts. Preferably, the driver circuit IC has a discharge transistor T that functions as the driver circuit IC. DIS The other terminal's connection area, through which the discharge transistor T of the drive circuit IC is connected. DIS The drain contact is connected to the common anode C of the VCSEL laser array die VCSELA via one or more bonding lines.

[0114] Preferably, the discharge transistor T of the drive circuit IC DIS The source of the discharge transistor T, which is used as the driving circuit IC, is through the discharge transistor T. DIS The second connection area of ​​the first terminal, GNDT, is electrically connected to the ground plane, GNDP.

[0115] Preferably, the capacitor array CAP is electrically and mechanically fixedly connected to the ground plane GNDP using the common contact of capacitors C1 to Cn. Preferably, the common contact of capacitors C1 to Cn of the capacitor array CAP is located on the bottom side of the capacitor array CAP.

[0116] Figure 4

[0117] Figure 4 It shows Figure 3 An exemplary cross-section of the structure.

[0118] The VCSEL laser array die VCSELA is conductively placed on a common cathode electrode C via its bottom side and is electrically, preferably mechanically, connected to the common cathode electrode C. The bottom contact of the VCSEL laser array die VCSELA forms the common cathode C for the n lasers L1 to Ln of the VCSEL laser array die VCSELA. Preferably, in the die stacking method, the VCSEL laser array die VCSELA is preferably conductively fixed to and electrically connected to the common cathode electrode C by conductive bonding or welding. Preferably, the upper metallization layer of the capacitor array CAP forms the common cathode electrode C. In the example presented herein, the upper metallization layer of the exemplary capacitor array CAP is an exemplary third metal layer M3. The common cathode electrode C of the capacitor array CAP is preferably electrically isolated from the n capacitors C1 to Cn.

[0119] In this example, the exemplary capacitor array CAP utilizes the common back contact of all capacitors C1 to Cn of the capacitor array CAP to be placed on the ground plane GNDP, which is located on the surface of a printed circuit board (PCB). The printed circuit board (PCB) can be any circuit substrate for electronic components, such as an FR4 board or a ceramic circuit board. Preferably, in this example, the capacitor array CAP is electrically and mechanically fixedly connected to the ground plane GNDP using the common back contact of all capacitors C1 to Cn of the capacitor array CAP.

[0120] One can conceive of directly using a heat sink (HS) to replace the printed circuit board (PCB).

[0121] Figure 5

[0122] Figure 5 This explains that in Figure 4 Based on the anti-parallel discharge current I dis EMC optimization and inductance minimization are achieved. Due to the structural symmetry, current flows through the discharge transistor T during the discharge process. DIS (see Figure 2 The discharge current I dis The current is distributed such that approximately half of the discharge current I is... dis The discharge current I flows through one of the n left-side junction lines BdL1 to BdLn. dis A current flows through one of the n right-side junction lines BdR1 to BdRn. This is due to the discharge current I on the right-side junction line. dis / 2 Spatial direction and the discharge current I on the left junction line disThe spatial orientation of the 2 / 2 arrangement is opposite, thus the magnetic field is enhanced at a certain distance from the optical module LM. This means that the lower electromagnetic radiation from this arrangement improves the electromagnetic compatibility of the optical module LM, which is crucial for steep opening edges.

[0123] Figure 6

[0124] Figure 6 It corresponds to Figure 5 A floor plan. Similar to... Figure 5 Chinese Reference Figure 4 The explanation, Figure 6 This explains that in Figure 3 Based on the anti-parallel discharge current I dis EMC optimization and inductance minimization are achieved. (Through...) Figure 6 The junction lines BdL1 to BdLn and BdR1 to BdRn drawn in the diagram are not shown in the diagram for clarity. Figure 6 The discharge transistor T in the drive circuit IC shown in the figure DIS (see Figure 2 The transistor receives signals from device components on the printed circuit board (PCB) (not shown in the figure for clarity) and / or from other device components on the driver circuit IC to become conductive. This closes the discharge transistor T. DIS A discharge switch of the form. During discharge, the device components of the printed circuit board (PCB) and / or the device components of the drive circuit IC preferably disconnect the charging switches S1 to Sn. Thus, the discharge current I... dis Through discharge transistor T DIS The discharge switch of the form flows to the grounding point of the grounding ground in the form of GNDP, and the corresponding capacitors of n capacitors C1 to Cn are discharged through the corresponding lasers of n lasers L1 to Ln, wherein the laser then suddenly emits its laser pulse.

[0125] Then, in the case of perfect symmetry (unfortunately, this can never be achieved in reality), the discharge current I on the left side... dis / 2 flows into the corresponding laser from the left, while the numerically similar discharge current I on the right is... dis / 2 flows into the corresponding laser from the right. Since the spatial currents are in opposite directions, according to the superposition principle, the partial magnetic fields generated in space essentially cancel each other out in the far field. However, the energy stored in the magnetic field is therefore lower, resulting in a smaller effective inductance. Therefore, due to the discharge current I on the left... dis / 2 and the discharge current I on the right dis This 2 / 2 coupling allows for faster circuit speeds. It's noteworthy that one discharge current effectively absorbs another discharge current.

[0126] Figure 7

[0127] Figure 7 based on Figure 4 Here, we refer to Figure 4 The explanation. However, unlike... Figure 4 , Figure 7 A method was proposed to directly use the heatsink HS as the ground plane GNDP instead of the ground plane GNDP on the printed circuit board (PCB). Its advantage is better heat dissipation.

[0128] Figure 8

[0129] Figure 8 based on Figure 3 Here, we refer to Figure 3 Explanation. Figure 8 It corresponds to Figure 7 The floor plan. Different from... Figure 3 , Figure 8 A method was proposed that uses the heatsink HS directly as the ground plane GNDP instead of the ground plane GNDP on the printed circuit board (PCB), and a smaller PCB is mounted on the heatsink HS and placed close to the driver circuit IC. The advantage is better heat dissipation.

[0130] Figure 9

[0131] Figure 9 A back-emitting VCSEL laser array die VCSELA is proposed as the VCSEL laser array die VCSELA. Figure 9 A cross-sectional view of this exemplary structure is shown. Furthermore, this paper proposes an electrical connection between the capacitor array (CAP) and the VCSEL laser array die (VCSELA) that does not use bonding wires (such as...). Figures 1 to 8 (As shown), instead of through flip-chip technology and solder ball SB or similar methods, this further reduces inductance. Therefore, in Figure 9In the example, the VCSEL laser array die VCSELA is mounted on the capacitor array CAP with its back side facing up, for example, inverted, via solder balls SB. Preferably, the back contact of the common cathode electrode C is now fabricated on the VCSEL laser array die VCSELA. Preferably, this back contact of the common cathode electrode C is completely or partially transparent to the light radiation of the n lasers L1 to Ln of the VCSEL laser array die VCSELA. This can be achieved by creating an opening in the conductive material of the back contact of the common cathode electrode C. Another possibility is that the back contact of the common cathode electrode C comprises and / or has a material that is optically transparent to the light radiation of the lasers L1 to Ln of the VCSEL laser array die VCSELA, either completely or partially. Such a material could be, for example, indium tin oxide (also known as ITO). Some solder balls SB may be provided solely for heat dissipation purposes. The solder balls SB may also be non-spherical and interconnect a larger surface area.

[0132] Figure 10

[0133] Figure 10 It corresponds Figure 9 The plan view shows the bonding lines replaced by solder balls (SB). The VCSEL laser array die (VCSELA) covers the solder balls (SB). This design is characterized by exceptionally low parasitic inductance.

[0134] Figure 11

[0135] Figure 11 An exemplary construction of the proposed capacitor array CAP is shown in a schematically simplified planar diagram.

[0136] When the top electrode te of the capacitor is high, the n connecting lines ICL of the n capacitors C1 to Cn are more densely packed. Here, "high" refers to... Figure 11 The illustration is shown in a two-dimensional representation. In this case, the measured value PTCY corresponds to this "high". The reference numeral PTCY indicates the minimum spacing PTCY of the rows of n capacitors C1 to Cn in the capacitor array CAP. Figure 11 An example is given where the exemplary minimum spacing PTCY of capacitors C1 to Cn in a capacitor array CAP is 300 μm. Figure 11 In the diagram, the connecting line ICL between capacitors C1 and Cn is simplified and drawn as a thick line from left to right. This is based on... Figure 2 The accompanying figure labels are for clarity. Figure 2 The nodes A1 to An are the same as the left contact area LCA1 to LCAn. Figure 2Nodes A1 to An are the same as those in the right-side contact areas RCA1 to RCAn. This change in reference numerals is for clarity only. Connecting lines ICL electrically connect the right-side contact areas RCA1 to RCAn to the left-side contact areas LCA1 to LCAn. Because the connecting lines ICL for capacitors C1 to Cn are more densely packed when the capacitor is high, multiple connecting lines ICL always sweep across one of the n capacitors C1 to Cn. Figure 11 In the example, the capacitors C1 to Cn of the capacitor array CAP are arranged in rows and columns. Figure 11 In the example, there are always four capacitors in a row of the capacitor array CAP. Therefore, the four connection lines ICL always sweep across each of the capacitors C1 to Cn in the exemplary capacitor array CAP. Each connection line in ICL, which is fabricated in the second metal layer M2, is electrically connected, for example, via a via interconnect DK to the top electrode te of exactly one of its associated capacitors. Figure 11 In the diagram, black circles represent these via interconnects DK. Each connection line ICL has left-side terminal contacts in contact areas LCA1 to LCAn and right-side terminal contacts in contact areas RCA1 to RCAn, respectively. The terminal contacts in contact areas LCA1 to LCAn and RCA1 to RCAn of capacitors C1 to Cn in capacitor array CAP are typically fabricated in the first metal layer M1 and the second metal layer M2, and they are interconnected in the contact areas via via interconnects. The common cathode electrode C of VCSEL laser array die VCSELA, located above capacitor array CAP and electrically isolated from the rest of capacitor array CAP, is fabricated in the third metal layer M3. Therefore, the left-side terminal contacts in contact areas LCA1 to LCAn and the right-side terminal contacts in contact areas RCA1 to RCAn of each connection line ICL correspond to... Figure 2 One of the nodes A1 to An in the array.

[0137] The minimum fourth spacing PTCC of the contact areas LCA1 to LCAn and RCA1 to RCAn of capacitors C1 to Cn in capacitor array CAP is calculated by dividing the minimum spacing PTCY of the rows of capacitors C1 to Cn in capacitor array CAP by the number of columns in which capacitors C1 to Cn are arranged. Figure 11 An example is given where the exemplary minimum spacing PTCY of capacitors C1 to Cn in a capacitor array CAP is 300 μm. Figure 11 An example of a minimum pitch PTCC of 50 μm is provided for the contact regions LCA1 to LCAn and RCA1 to RCAn of capacitors C1 to Cn in a capacitor array CAP.

[0138] This suitable internal structure of the capacitor array (CAP) typically ensures that the right-side spacing between the right-side contact areas RCA1 and RCA1 in the CAP is consistent with the VCSEL laser array die VCSELA (see [link]). Figure 3 The first spacing PTR between the right contact regions RA1 to RAn of the capacitor array CAP is consistent with that between the right contact regions RCA1 to RCAN of the capacitor array CAP and the bonding lines BdR1 to BdRn between the right contact regions RA1 to RAn of the VCSEL laser array die VCSELA (see [link to bonding lines]). Figure 3 The lengths of the joint lines are always approximately the same, and the length of the joint line can be minimized.

[0139] A connecting line ICL electrically connects one of the right-side contact areas RCA1 to RCA1An of the capacitor array CAP to the corresponding left-side contact areas LCA1 to LCA1An of the capacitor array CAP, thereby forming... Figure 2 One of the nodes from node A1 to node An.

[0140] Preferably, the right-side spacing PTCR between the right-side contact areas RCA1 and RCAn of the capacitor array CAP and the left-side spacing PTCL between the left-side contact areas LCA1 and LCAn of the capacitor array CAP correspond to the common fourth spacing PTCC between the contact areas. Figure 1 Only the right-side spacing PTCR and left-side spacing PTCL of two independent capacitor arrays CAPL and CAPR are plotted.

[0141] However, the second spacing PTCY of the rows of capacitors C1 to Cn in the capacitor array CAP remains unchanged. Figure 11In the example, the second spacing PTCY of the rows of capacitors C1 to Cn in the capacitor array CAP is maintained, for example, at 300 μm. This ensures that the length of the bonding line between each right-side contact area of ​​the capacitor array CAP (RCA1 to RCAn) and each right-side contact area of ​​the VCSEL laser array die (RA1 to RAn) is always approximately the same, and minimizes the length of the bonding line. These bonding lines BdR1 to BdRn and BdL1 to BdLn connect the contact areas RCA1 to RCAn and LCA1 to LCAn of the capacitor array CAP to the contact areas RA1 to RAn and LA1 to LAn of the lasers L1 to Ln of the VCSEL laser array die (VCSELA), such that each laser in the VCSEL laser array die (VCSELA) is connected to one of the lasers L1 to Ln of the VCSEL laser array die (VCSELA) via two pairs of terminals consisting of the terminals of the capacitors and the terminals of the VCSEL lasers.

[0142] Figure 12

[0143] Figure 12 It shows Figure 11 An exemplary, simplified, non-scaled cross-sectional view of a capacitor array CAP is provided to illustrate the wiring planes at different locations of the capacitor array CAP.

[0144] The capacitor array CAP preferably comprises three metal layers. The top electrodes (top electrodes te) of capacitors C1 to Cn of the capacitor array CAP are formed in the first metal layer M1. An insulator INS electrically separates the first metal layer M1 from the second metal layer M2. The connecting lines ICL of capacitors C1 to Cn of the capacitor array CAP are formed in the second metal layer M2. Through-hole interconnects DK (see...) pass through the insulator INS. Figure 11 The connecting line ICL in the second metal layer M2 is electrically connected to the top electrode te in the first metal layer M1. The capacitor array CAP also includes a substrate SUB. The substrate SUB preferably includes the dielectric of the capacitors C1 to Cn of the capacitor array CAP. The bottom side of the capacitor array CAP is formed by substrate contacts SUBC. The area between the top electrode te in the first metal layer M1 and the substrate contacts SUBC respectively forms the vertical capacitances of the capacitors C1 to Cn of the capacitor array CAP. Therefore, these capacitances are the vertical capacitances shared by all capacitors C1 to Cn in the first metal layer M1 and the capacitor array CAP, located on the bottom side of the capacitor array CAP, between the substrate contacts SUBC. The substrate contacts SUBC are preferably electrically connected to the ground plane GNDP (see also...). Figure 4 , 5(7, 9). Therefore, on the back side, all capacitors C1 to Cn of the capacitor array CAP are shorted. The corresponding top electrodes te of the respective capacitors are respectively fabricated in the first metal layer M1. The lateral connecting line ICL is fabricated in the second metal layer M2. The common cathode electrode C of the VCSEL laser array die VCSELA can preferably be fabricated in the third metal layer M3. The common cathode electrode C of the VCSEL laser array die VCSELA may preferably be fabricated in the third metal layer M3, which is isolated from the second metal layer M2, the first metal layer M1, and the substrate SUB.

[0145] Cross-references to related applications

[0146] This application claims priority to German patent application DE 10 2022 103693.6, filed on February 16, 2022, and German patent application DE 10 2022 109 681.5, filed on April 21, 2022.

[0147] List of reference numerals and symbols

[0148] Capacitor connection nodes A1 to An. During the charging phase, the charging circuit SUPL supplies charging current to one of the n capacitor connection nodes A1 to An through the associated charging switch of the n charging switches S1 to Sn, which is closed during the charging phase, so as to charge the associated capacitors of the n capacitors C1 to Cn during this charging phase. For discharging, when the associated charging switch of the n charging switches S1 to Sn is opened, the laser of the n lasers L1 to Ln associated with one of the n capacitor connection nodes A1 to An draws electrical energy from the associated capacitors of the n capacitors C1 to Cn through that capacitor connection node, thereby discharging the capacitor. Figure 11 In the middle, a group consisting of one left contact area from the left contact area LCA1 to LCAn and one corresponding right contact area from the right contact area RCA1 to RCAN, together with the connecting line ICL connecting them, forms a Figure 2 The corresponding capacitor connection nodes in the n capacitor connection nodes A1 to An;

[0149] The discharge transistor T of the BdCT driver circuit IC DIS The junction line between the second terminal CT and the cathode electrode C.

[0150] The BdGND junction line connects the discharge transistor T of the drive circuit IC. DIS The first terminal GNDT is connected to the ground plane GNDP;

[0151] The first left-side junction line between the first left-side contact region LCA1 of the first left-side capacitor LC1 of the BdL1 capacitor array CAP and the first left-side contact region LA1 of the first laser L1 of the VCSEL laser die VCSLEA; The second left-side bonding line between the second left-side contact region LCA2 of the second left-side capacitor LC2 of the BdL2 capacitor array CAP and the second left-side contact region LA2 of the second laser L2 of the VCSEL laser die VCSLEA; The third left-side bonding line between the third left-side contact region LCA3 of the third left-side capacitor LC3 of the BdL3 capacitor array CAP and the third left-side contact region LA3 of the third laser L3 of the VCSEL laser die VCSLEA; The nth left-side bonding line between the nth left-side contact region LCAn of the nth left-side capacitor LCn of the BdLn capacitor array CAP and the nth left-side contact region LAn of the nth laser Ln of the VCSEL laser die VCSLEA; The first right-side junction line between the first right-side contact region RCA1 of the first right-side capacitor RC1 of the BdR1 capacitor array CAP and the first right-side contact region RA1 of the first right-side laser L1 of the VCSEL laser die VCSLEA; The second right-side junction line between the second right-side contact region RCA2 of the second right-side capacitor RC2 of the BdR2 capacitor array CAP and the second right-side contact region RA2 of the second laser L2 of the VCSEL laser die VCSLEA; The third right-side junction line between the third right-side contact region RCA3 of the third right-side capacitor RC3 of the BdR3 capacitor array CAP and the third right-side contact region RA3 of the third laser L3 of the VCSEL laser die VCSLEA. The nth right-side junction line between the nth right-side contact region RCAn of the nth right-side capacitor RCn of the BdRn capacitor array CAP and the nth right-side contact region RAN of the nth laser Ln of the VCSEL laser die VCSLEA. C. Cathode electrode. The cathode electrode is the electrical terminal of the common cathode contact of the laser L1 to Ln of the VCSEL laser array die VCSELA;

[0152] C1, the first capacitor, when discharged by switch T... DIS During discharge, the first capacitor provides power to the first laser L1. It is preferably the first capacitor in the capacitor array CAP.

[0153] C2, the second capacitor, when discharged through switch T... DIS During discharge, this second capacitor provides power to the second laser L2. It is preferably the second capacitor in the capacitor array CAP.

[0154] C3, the third capacitor, when discharged through switch T... DIS During discharge, this third capacitor provides power to the third laser L3. It is preferably the third capacitor in the capacitor array CAP.

[0155] C4, the fourth capacitor, when discharged through switch T... DIS During discharge, this fourth capacitor provides power to the fourth laser L4. It is preferably the fourth capacitor in the capacitor array CAP.

[0156] C5, the fifth capacitor, when discharged through switch T... DIS During discharge, this fifth capacitor provides power to the fifth laser L5. It is preferably the fifth capacitor in the capacitor array CAP.

[0157] C6, the sixth capacitor, when discharged through switch T... DIS During discharge, this sixth capacitor provides power to the sixth laser L6. It is preferably the sixth capacitor in the capacitor array CAP.

[0158] C7, the 7th capacitor, when discharged through switch T... DIS During discharge, this seventh capacitor provides power to the seventh laser L7. It is preferably the seventh capacitor in the capacitor array CAP.

[0159] C8, the 8th capacitor, when discharged through switch T... DIS During discharge, this eighth capacitor provides power to the eighth laser L8. It is preferably the eighth capacitor in the capacitor array CAP.

[0160] C(n-3) is the (n-3)th capacitor, when it passes through the discharge switch T. DIS During discharge, the (n-3)th capacitor provides power to the (n-3)th laser L(n-3). It is preferably the (n-3)th capacitor in the capacitor array CAP.

[0161] C(n-2) is the (n-2)th capacitor, when it passes through the discharge switch T. DIS During discharge, the (n-2)th capacitor provides power to the (n-2)th laser L(n-2). It is preferably the (n-2)th capacitor in the capacitor array CAP.

[0162] C(n-1) is the (n-1)th capacitor, when it passes through the discharge switch T. DISDuring discharge, the (n-1)th capacitor provides power to the (n-1)th laser L(n-1). It is preferably the (n-1)th capacitor in the capacitor array CAP.

[0163] The nth capacitor, Cn, when passed through discharge switch T DIS During discharge, the nth capacitor provides power to the nth laser Ln. It is preferably the nth capacitor in the capacitor array CAP.

[0164] CAP capacitor array. The capacitor array preferably comprises n capacitors C1 to Cn; CAPL left-side capacitor array. The left-side capacitor array preferably comprises n capacitors LC1 to LCn;

[0165] CAPR right-side capacitor array. The right-side capacitor array preferably comprises n capacitors RC1 to RCn;

[0166] The discharge transistor T of the CT drive circuit IC DIS The second terminal;

[0167] DK through-hole interconnect;

[0168] Discharge transistor

[0169] GND grounding node;

[0170] The discharge transistor T of the GNDT driver circuit IC DIS The first terminal;

[0171] GNDP (Ground Surface);

[0172] HS radiator;

[0173] IC driver circuit. It has a discharge transistor T DIS And circuit dies for other possible integrated circuits used to control the device;

[0174] ICL connector cable;

[0175] The surface of the ICO driver IC;

[0176] The bottom side of the ICU driver circuit IC;

[0177] L1 is the first stripe consisting of one or more lasers on a VCSEL laser die VCSELA;

[0178] L2 is the second stripe consisting of one or more lasers on a VCSEL laser die VCSELA;

[0179] L3 is the third stripe consisting of one or more lasers on a VCSEL laser die VCSELA;

[0180] L4 is the fourth stripe consisting of one or more lasers on a VCSEL laser die VCSELA;

[0181] L5 is the fifth stripe consisting of one or more lasers on a VCSEL laser die VCSELA;

[0182] L6 is the sixth stripe consisting of one or more lasers on a VCSEL laser die VCSELA;

[0183] L7 is the seventh stripe consisting of one or more lasers on a VCSEL laser die VCSELA;

[0184] L8 is the 8th strip consisting of one or more lasers on a VCSEL laser die VCSELA;

[0185] L(n-3) is the (n-3)th stripe consisting of one or more lasers on the VCSEL laser die VCSELA;

[0186] L(n-2) is the (n-2)th stripe consisting of one or more lasers on the VCSEL laser die VCSELA;

[0187] L(n-1) is the (n-1)th strip composed of one or more lasers on the VCSEL laser die VCSELA;

[0188] Ln is the nth stripe consisting of one or more lasers on a VCSEL laser die VCSELA;

[0189] The first left contact area of ​​the first laser L1 in the LA1 VCSEL laser die VCSLEA;

[0190] The second left contact area of ​​the second laser L2 in the LA2 VCSEL laser die VCSLEA;

[0191] The third left contact area of ​​the third laser L3 in the LA3 VCSEL laser die VCSLEA;

[0192] The fourth left contact area of ​​the fourth laser L4 in the LA4 VCSEL laser die VCSLEA;

[0193] The fifth left contact area of ​​the fifth laser L5 in the LA5 VCSEL laser die VCSLEA;

[0194] The sixth left contact area of ​​the sixth laser L6 in the LA6 VCSEL laser die VCSLEA;

[0195] The 7th laser L7 left-side contact area of ​​the 7th laser in the LA7 VCSEL laser die VCSLEA;

[0196] The 8th laser L8 left-side contact area of ​​the LA8 VCSEL laser die VCSLEA;

[0197] The (n-3)th left-side contact region of the (n-3)th laser L(n-3) of the LA(n-3) VCSEL laser die VCSLEA;

[0198] The left-side contact region of the (n-2)th laser L(n-2) of the (n-2)th VCSEL laser die VCSLEA;

[0199] The (n-1)th left contact region of the (n-1)th laser L(n-1) of the LA(n-1) VCSEL laser die VCSLEA;

[0200] The nth left contact area of ​​the LAn VCSEL laser die VCSLEA;

[0201] L BD 1. The common first junction line inductance of the first junction lines BdL1 and BdR1;

[0202] L BD 2. The common second junction line inductance of the second junction lines BdL2 and BdR2;

[0203] L BD 3. The common third junction inductance of the third junction lines BdL3 and BdR3;

[0204] L BD n The common nth junction line inductance of the nth junction lines BdLn and BdRn;

[0205] LC1 is the first left-side capacitor in the left-side capacitor array CAPL;

[0206] LC2 is the second left-side capacitor in the left-side capacitor array CAPL.

[0207] LC3 is the third left-side capacitor in the left-side capacitor array CAPL.

[0208] LCn is the nth left-side capacitor of the left-side capacitor array CAPL;

[0209] LCA1 is the first left-side capacitor LC1 of the left-side capacitor array CAP or the first left-side contact area LCA1 of the first capacitor C1 of the capacitor array CAP;

[0210] LCA2 is the second left-side capacitor LC2 of the left-side capacitor array CAP or the second left-side contact area LCA2 of the second capacitor C2 of the capacitor array CAP;

[0211] LCA3 is the third left-side capacitor LC3 of the left-side capacitor array CAP, or the third left-side contact area LCA3 of the third capacitor C2 of the capacitor array CAP.

[0212] LCA4 is the fourth left-side capacitor LC4 of the left-side capacitor array CAP or the fourth left-side contact area LCA4 of the fourth capacitor C4 of the capacitor array CAP.

[0213] LCA5 is the fifth left-side capacitor LC5 of the left-side capacitor array CAP or the fifth left-side contact area LCA5 of the fifth capacitor C5 of the capacitor array CAP.

[0214] LCA6 is the sixth left-side capacitor LC6 of the left-side capacitor array CAP or the sixth left-side contact area LCA6 of the sixth capacitor C6 of the capacitor array CAP.

[0215] LCA7 is the 7th left-side capacitor LC7 of the left-side capacitor array CAP or the 7th left-side contact area LCA7 of the 7th capacitor C7 of the capacitor array CAP.

[0216] LCA8 is the 8th left-side capacitor LC8 of the left-side capacitor array CAP or the 8th left-side contact area LCA8 of the 8th capacitor C8 of the capacitor array CAP.

[0217] LCA(n-3) refers to the (n-3)th left-side capacitor LC(n-3) of the left-side capacitor array CAP, or the (n-3)th left-side contact region LCA(n-3) of the (n-3)th capacitor C(n-3) of the capacitor array CAP.

[0218] LCA(n-2) refers to the (n-2)th left-side capacitor LC(n-2) of the left-side capacitor array CAP, or the (n-2)th left-side contact region LCA(n-2) of the (n-2)th capacitor C(n-2) of the capacitor array CAP.

[0219] LCA(n-1) is the (n-1)th left-side capacitor LC(n-1) of the left-side capacitor array CAP, or the (n-1)th left-side contact region LCA(n-1) of the (n-1)th capacitor C(n-1) of the capacitor array CAP.

[0220] LCAn refers to the nth left-side capacitor LCn of the left-side capacitor array CAP, or the nth left-side contact region LCAn of the nth capacitor Cn of the capacitor array CAP.

[0221] LM optical module. The optical module is preferably a laser module comprising a VCSEL laser array die (VCSELA).

[0222] The OS carrier. The carrier can be, for example, a printed circuit board (PCB) or a heatsink (HS).

[0223] PCB circuit board. The circuit board can be, for example, a printed circuit board, such as an FR4 circuit board or an epoxy resin circuit board, and / or a ceramic substrate, etc.;

[0224] The minimum spacing between capacitors C1 to Cn in the PTC capacitor array CAP. Figure 11 An example is given where the exemplary minimum spacing between capacitors C1 to Cn in a capacitor array CAP is 300 μm.

[0225] The minimum fourth spacing between the contact areas LCA1 to LCAn and RCA1 to RCAn of the capacitors C1 to Cn in the PTCC capacitor array CAP. Figure 11 An example of a minimum spacing PTCC of 50 μm is provided for the contact regions LCA1 to LCAn and RCA1 to RCAn of capacitors C1 to Cn in a capacitor array CAP.

[0226] The minimum spacing between the left capacitors LC1 to LCn of the left capacitor array CAPL in PTCL. Figure 1 An example of a minimum spacing of 300 μm is given for the left capacitors LC1 to LCn of the left capacitor array CAPL and the corresponding left contact regions LCA1 to LCAn.

[0227] The minimum spacing between the right capacitors RC1 to RCn of the right capacitor array CAPR of the PTCR. Figure 1 An example of a minimum spacing of 300 μm is given for the right capacitors RC1 to RCn and the corresponding right contact areas RCA1 to RCAn of the right capacitor array CAPR.

[0228] The minimum spacing between C1 to Cn columns of capacitors in the PTCX capacitor array CAP. Figure 11 An example is given where the minimum spacing between capacitors C1 to Cn in a capacitor array CAP is 300 μm.

[0229] PTCY is the minimum spacing between rows of capacitors C1 to Cn in a capacitor array CAP. Figure 11 An example is given where the minimum spacing between capacitors C1 to Cn in a capacitor array CAP is 300 μm.

[0230] The first spacing PTL between the left contact area LA1 and LAn of the PTL VCSEL laser array bare die VCSELA;

[0231] The minimum fifth spacing between the laser diodes L1 to Ln of the PTLa VCSEL laser array die VCSELA is also known as the laser die spacing. Figure 1 An example of a laser die spacing of 50 μm is illustrated. Preferably, the minimum spacing PTLa between the laser diodes L1 to Ln of the VCSEL laser array die VCSELA is equal to the first spacing PTL of the left contact area LA1 to LAn of the VCSEL laser array die VCSELA, and equal to the first spacing PTR of the right contact area RA1 to RAn of the VCSEL laser array die VCSELA;

[0232] The first spacing PTR in the right contact area RA1 to RAN of the PTR VCSEL laser array bare die VCSELA;

[0233] Q: Heat flow;

[0234] The first right-side contact area of ​​the first laser stripe L1 on the RA1 VCSEL laser die VCSELA;

[0235] The second right-side contact area of ​​the second laser stripe L2 on the RA2 VCSEL laser die VCSELA;

[0236] The third right-side contact area of ​​the third laser stripe L3 on the RA3 VCSEL laser die VCSELA;

[0237] The nth right-side contact region of the nth laser stripe Ln on the RAn VCSEL laser die VCSELA;

[0238] RC1 is the first right-side capacitor in the right-side capacitor array CAPR;

[0239] RC2 is the second right-side capacitor in the right-side capacitor array CAPR.

[0240] RC3 is the third right-side capacitor in the right-side capacitor array CAPR.

[0241] RCn is the nth right-side capacitor RCn of the right-side capacitor array CAPR;

[0242] RCA1 is the first right-side capacitor RC1 of the right-side capacitor array CAPR or the first right-side contact area RCA1 of the first capacitor C1 of the capacitor array CAP.

[0243] RCA2 is the second right-side capacitor RC2 of the right-side capacitor array CAPR or the second right-side contact area RCA2 of the second capacitor C2 of the capacitor array CAP.

[0244] RCA3 is the third right-side capacitor RC3 of the right-side capacitor array CAPR or the third right-side contact area RCA3 of the third capacitor C3 of the capacitor array CAP.

[0245] RCAn refers to the nth right-side capacitor RCn of the right-side capacitor array CAPR, or the nth right-side contact region RCAn of the nth capacitor Cn of the capacitor array CAP.

[0246] S1 is the first charging switch, which is used to charge the first capacitor C1 or the first left capacitor LC1 and the first right capacitor RC1 using the charging current of the charging circuit SUPL.

[0247] S2 is the second charging switch, which is used to charge the second capacitor C2 or the second left capacitor LC2 and the second right capacitor RC2 using the charging current of the charging circuit SUPL.

[0248] S3 is the third charging switch, which is used to charge the third capacitor C3 or the third left capacitor LC3 and the third right capacitor RC3 using the charging current of the charging circuit SUPL.

[0249] SC screws, which serve as exemplary fasteners for printed circuit boards (PCBs) on heat sinks (HS);

[0250] Sn is the nth charging switch, which is used to charge the nth capacitor Cn or the nth left capacitor LCn and the nth right capacitor RCn using the charging current of the charging circuit SUPL.

[0251] Substrate of SUB capacitor array CAP;

[0252] SUBC substrate contacts. The corresponding substrate contacts of capacitor arrays CAP, CAPL, and CAPR preferably form the lower bottom electrodes of the respective capacitor arrays CAP, CAPL, and CAPR. The capacitors C1 to Cn of the respective capacitor arrays CAP, CAPL, and CAPR are formed in the dielectric of the substrate SUB between the upper top electrode te and the lower substrate contacts;

[0253] SUPL charging circuit;

[0254] te is the top electrode of the capacitor;

[0255] T DIS Discharge transistor;

[0256] TR carrier;

[0257] TRG discharge transistor T DIS The control terminal (TRG) is used to turn on and off the discharge transistor T in the drive circuit IC. DIS The first terminal and the discharge transistor T of the drive circuit IC DIS Discharge transistor T between the second terminals DIS The route path; VCSELA is a bare die of a VCSEL laser array with multiple VCSEL laser diodes L1 to Ln. The VCSEL laser array die is preferably a semiconductor crystal with lasers L1 to Ln formed thereon.

[0258] The surface of VCSELAO VCSEL laser array bare die VCSELA.

Claims

1. An optical module (LM), in, The optical module (LM) includes a carrier, and The optical module (LM) includes a capacitor array (CAP), and The optical module includes a VCSEL laser array die (VCSELA), and The carrier has a top side, and The carrier has a conductive, electrically contactable ground plane (GNDP) on its top side, and The VCSEL laser array die (VCSELA) has a top side and a bottom side, and The VCSEL laser array die (VCSELA) has n lasers (L1 to Ln), where n is a positive integer greater than 0. The VCSEL laser array die (VCSELA) has a common cathode contact on its bottom side, and In this embodiment, the cathode of each laser (L1 to Ln) in the VCSEL laser array die (VCSELA) is electrically connected to the common cathode contact on the bottom side of the VCSEL laser array die (VCSELA), and The lasers (L1 to Ln) of the VCSEL laser array die (VCSELA) are spaced a fifth distance (PTLa) from each other, and The capacitor array (CAP) has a top side and a bottom side, and The capacitor array (CAP) includes a substrate (SUB), and The capacitor array (CAP) has electrically contactable substrate contacts (SUBC) on its bottom side, and The capacitor array (CAP) comprises n capacitors (C1 to Cn), and The capacitor array (CAP) has a cathode electrode (C) located in a third metal layer (M3) on its top side, and The capacitor array (CAP) has exactly one upper top electrode (te) for each capacitor (C1 to Cn), and Each of the top electrodes (te) together with the material of the substrate (SUB) in the region of the capacitor array (CAP) substantially defined by the range of the top electrode (te), and together with the substrate contacts (SUBC), forms a corresponding capacitor in the capacitors (C1 to Cn) of the capacitor array (CAP) associated with the top electrode. The upper top electrode (te) is fabricated in the first metal layer (M1) on the substrate (SUB), and The capacitor array (CAP) comprises n top electrodes and therefore n capacitors (C1 to Cn) arranged in j rows and k columns in the substrate (SUB) of the capacitor array (CAP), where j*k=n, and j and k are positive integers. The rows of capacitors (C1 to Cn) have a second spacing (PTCY) within a row of the capacitor array (CAP), and The capacitor array (CAP) has n interconnect lines (ICL) in the second metal layer (M2), and The connecting lines (ICL) are aligned parallel to the rows of the capacitors (C1 to Cn), and Wherein, the fourth spacing (PTCC) between the connecting lines (ICL) is equal to the second spacing (PTCY) of the rows of the capacitors (C1 to Cn) divided by the number of columns of the capacitors (C1 to Cn), and Wherein, the deviation of the fifth spacing (PTLa) from the fourth spacing (PTCC) does not exceed 25%, and The third metal layer (M3) is located above the second metal layer (M2) and the first metal layer (M1) on the surface of the substrate (SUB), and Wherein, the second metal layer (M2) is located above the first metal layer (M1) on the surface of the substrate (SUB) and below the third metal layer (M3), and The third metal layer (M3) is electrically isolated from the second metal layer (M2), the first metal layer (M1), and the substrate (SUB) by an insulator (INS), and The second metal layer (M2) is electrically isolated from the first metal layer (M1) and the substrate (SUB) by an insulator (INS), and The common cathode contact of the VCSEL laser array die (VCSELA) is placed on the cathode electrode (C) of the capacitor array (CAP) and is electrically and mechanically fixedly connected to the cathode electrode (C) of the capacitor array (CAP). The substrate contacts (SUBC) of the capacitor array (CAP) are placed on the ground plane (GNDP) and are electrically and mechanically fixedly connected to the ground plane (GNDP). The VCSEL laser array die (VCSELA) has n electrically contactable left-side contact areas (LA1 to LAn) arranged in a left row on its surface. The VCSEL laser array die (VCSELA) has n electrically contactable right-side contact areas (RA1 to RAN) arranged in a right row on its surface. In this embodiment, the anode of each laser (L1 to Ln) in the VCSEL laser array die (VCSELA) is electrically connected to the corresponding left-side contact area in the n contact areas (LA1 to LAn) of the left row, and In this embodiment, the anode of each laser (L1 to Ln) in the VCSEL laser array die (VCSELA) is electrically connected to the corresponding right-side contact area in the n contact areas (RA1 to RAN) of the right row, and The capacitor array (CAP) has a left-side contact area (LC1 to LCn) arranged in a left row on its surface, and The capacitor array (CAP) has a right-side contact area (RC1 to RCn) arranged in a right row on its surface, and Each of the n connecting lines (ICL) electrically connects at least one corresponding top electrode (te) of the capacitor associated with that connecting line (ICL) in the capacitor (C1 to Cn) to a corresponding left-side contact area in the electrically accessible left-side contact area (LC1 to LCn) of the left row of the capacitor array (CAP) via a corresponding through-hole interconnect (DK), and is electrically connected to a corresponding right-side contact area in the electrically accessible right-side contact area (RC1 to RCn) of the right row of the capacitor array (CAP). In this embodiment, each of the n left-side contact regions (LA1 to LAn) in the left row of the VCSEL laser array die (VCSELA) is electrically and individually connected to a corresponding left-side contact region in the electrically accessible left-side contact regions (LC1 to LCn) in the left row of the capacitor array (CAP), and Each right-side contact region of the n right-side contact regions (RA1 to RAN) of the right row of the VCSEL laser array die (VCSELA) is electrically and individually connected to the corresponding right-side contact region of the electrically accessible right-side contact regions (RC1 to RCn) of the right row of the capacitor array (CAP).

2. The optical module according to claim 1, in, The optical module (LM) includes a driver circuit (IC), and The driving circuit (IC) has a top side and a bottom side, and The driving circuit (IC) includes a discharge transistor (T). DIS ),and Among them, the discharge transistor (T) DIS ) has the discharge transistor (T) DIS The first terminal (GNDT) of ) and Among them, the discharge transistor (T) DIS ) has the discharge transistor (T) DIS The second terminal (CT) of ) and Among them, the discharge transistor (T) DIS It has control terminals, and Wherein, according to the electrical state of the control terminal, the discharge transistor (T) DIS It can electrically isolate its first terminal (GNDT) from its second terminal (CT), or it can electrically connect its first terminal (GNDT) to its second terminal (CT), and Among them, the discharge transistor (T) DIS The first terminal (GNDT) of the ) is electrically connected to the ground plane (GNDP), and Among them, the discharge transistor (T) DIS The second terminal (CT) of the cathode electrode (C) is electrically connected to the cathode electrode (C), and The driving circuit (IC) is fixed to the surface of the carrier by its bottom side.

3. The optical module according to claim 2, in, When the discharge transistor (T) DIS When the circuit is turned off, the drive circuit can charge the capacitors (C1 to Cn) of the capacitor array (CAP) using the charging current through the charging circuit (SUPL).

4. The optical module according to claim 3, in, The device components of the drive circuit (IC) and / or another circuit attached to or part of the carrier are capable of controlling the discharge transistor (T). DIS The control terminal of the discharge transistor (T) causes the discharge transistor (T) to... DIS The capacitors (C1 to Cn) of the capacitor array (CAP) are caused to discharge with a specific laser current (IL1) via the corresponding lasers (L1 to Ln) associated with the capacitors (C1 to Cn) of the capacitor array (CAP) via the VCSEL laser array die (VCSELA). dis Discharge, and The discharge current (I) flowing through the VCSEL laser array die (VCSELA) is described above. dis The lasers (L1 to Ln) then emit light in a manner perpendicular to the surface of the VCSEL laser array die (VCSELA).

5. The optical module according to any one of claims 1 to 4, in, The carrier includes a printed circuit board (PCB) or a heat sink (HS).

6. The optical module according to claim 1, in, The deviation of the fifth pitch (PTLa) from the fourth pitch (PTCC) shall not exceed 10%.

7. The optical module according to claim 6, in, The deviation of the fifth pitch (PTLa) from the fourth pitch (PTCC) shall not exceed 5%.

8. The optical module according to claim 7, in, The deviation of the fifth pitch (PTLa) from the fourth pitch (PTCC) shall not exceed 2%.

9. The optical module according to claim 8, in, The deviation of the fifth pitch (PTLa) from the fourth pitch (PTCC) does not exceed 1%.

10. An optical module (LM), in, The optical module (LM) includes a carrier, and The optical module (LM) includes a capacitor array (CAP), and The optical module includes a VCSEL laser array die (VCSELA), and The carrier has a top side, and The carrier has a conductive, electrically contactable ground plane (GNDP) on its top side, and The VCSEL laser array die (VCSELA) has a top side and a bottom side, and The VCSEL laser array die (VCSELA) has n lasers (L1 to Ln), where n is a positive integer greater than 0. The VCSEL laser array die (VCSELA) has a common cathode contact on its bottom side, and In this embodiment, the cathode of each laser (L1 to Ln) in the VCSEL laser array die (VCSELA) is electrically connected to the common cathode contact on the bottom side of the VCSEL laser array die (VCSELA), and The lasers (L1 to Ln) of the VCSEL laser array die (VCSELA) are spaced a fifth distance (PTLa) from each other, and The capacitor array (CAP) has a top side and a bottom side, and The capacitor array (CAP) includes a substrate (SUB), and The capacitor array (CAP) has electrically contactable substrate contacts (SUBC) on its bottom side, and The capacitor array (CAP) comprises n capacitors (C1 to Cn), and The capacitor array (CAP) has exactly one upper top electrode (te) for each capacitor (C1 to Cn), and Each of the top electrodes (te) together with the material of the substrate (SUB) in the region of the capacitor array (CAP) substantially defined by the range of the top electrode (te), and together with the substrate contacts (SUBC), forms a corresponding capacitor in the capacitors (C1 to Cn) of the capacitor array (CAP) associated with the top electrode. The upper top electrode (te) is fabricated in the first metal layer (M1) on the substrate (SUB), and The capacitor array (CAP) comprises n top electrodes and therefore n capacitors (C1 to Cn) arranged in j rows and k columns in the substrate (SUB) of the capacitor array (CAP), where j*k=n, and j and k are positive integers. Wherein, the rows of capacitors (C1 to Cn) have a second spacing (PTCY) in a row, and The capacitor array (CAP) has n interconnect lines (ICL) in the second metal layer (M2), and The connecting lines (ICL) are aligned parallel to the rows of the capacitors (C1 to Cn), and Wherein, the fourth spacing (PTCC) between the connecting lines (ICL) is equal to the second spacing (PTCY) divided by the number of columns of the capacitors (C1 to Cn), and Wherein, the deviation of the fifth spacing (PTLa) from the fourth spacing (PTCC) does not exceed 25%, and Wherein, the second metal layer (M2) is located above the first metal layer (M1) on the surface of the substrate (SUB), and The second metal layer (M2) is electrically isolated from the first metal layer (M1) and the substrate (SUB) by an insulator (INS), and The common cathode contact of the VCSEL laser array die (VCSELA) forms the cathode electrode (C), and The substrate contacts (SUBC) of the capacitor array (CAP) are placed on the ground plane (GNDP) and are electrically and mechanically fixedly connected to the ground plane (GNDP). The VCSEL laser array die (VCSELA) has n electrically contactable left-side contact areas (LA1 to LAn) arranged in a left row on its surface. The VCSEL laser array die (VCSELA) has n electrically contactable right-side contact areas (RA1 to RAN) arranged in a right row on its surface. In this embodiment, the anode of each laser (L1 to Ln) in the VCSEL laser array die (VCSELA) is electrically connected to the corresponding left-side contact area in the n contact areas (LA1 to LAn) of the left row, and In this embodiment, the anode of each laser (L1 to Ln) in the VCSEL laser array die (VCSELA) is electrically connected to the corresponding right-side contact area in the n contact areas (RA1 to RAN) of the right row, and The capacitor array (CAP) has a left-side contact area (LC1 to LCn) arranged in a left row on its surface, and The capacitor array (CAP) has a right-side contact area (RC1 to RCn) arranged in a right row on its surface, and Each of the n connecting lines (ICL) electrically connects at least one corresponding top electrode (te) of the capacitor associated with that connecting line (ICL) in the capacitor (C1 to Cn) to a corresponding left-side contact area in the electrically accessible left-side contact area (LC1 to LCn) of the left row of the capacitor array (CAP) via a corresponding through-hole interconnect (DK), and to a corresponding right-side contact area in the electrically accessible right-side contact area (RC1 to RCn) of the right row of the capacitor array (CAP). In this embodiment, each of the n left-side contact areas (LA1 to LAn) in the left row of the VCSEL laser array die (VCSELA) is electrically and mechanically fixedly connected via solder balls (SB) to the corresponding left-side contact area in the electrically contactable left-side contact area (LC1 to LCn) in the left row of the capacitor array (CAP), and In this embodiment, each of the n right-side contact regions (RA1 to RAN) in the right row of the VCSEL laser array die (VCSELA) is electrically and mechanically fixedly connected via solder balls (SB) to the corresponding right-side contact region in the electrically accessible right-side contact region (RC1 to RCn) in the right row of the capacitor array (CAP).

11. The optical module according to claim 10, in, The optical module (LM) includes a driver circuit (IC), and The driving circuit (IC) has a top side and a bottom side, and The driving circuit (IC) includes a discharge transistor (T). DIS ),and Among them, the discharge transistor (T) DIS ) has the discharge transistor (T) DIS The first terminal (GNDT) of ) and Among them, the discharge transistor (T) DIS ) has the discharge transistor (T) DIS The second terminal (CT) of ) and Among them, the discharge transistor (T) DIS It has control terminals, and Wherein, according to the electrical state of the control terminal, the discharge transistor (T) DIS It can electrically isolate its first terminal (GNDT) from its second terminal (CT), or it can electrically connect its first terminal (GNDT) to its second terminal (CT), and Wherein, the first terminal (GNDT) of the discharge transistor (TDIS) is electrically connected to the ground plane (GNDP), and Among them, the discharge transistor (T) DIS The second terminal (CT) of the cathode electrode (C) is electrically connected to the cathode electrode (C), and The driving circuit (IC) is fixed to the surface of the carrier by its bottom side.

12. The optical module according to claim 11, in, When the discharge transistor (T) DIS When the circuit is turned off, the drive circuit can charge the capacitors (C1 to Cn) of the capacitor array (CAP) using the charging current through the charging circuit (SUPL).

13. The optical module according to claim 12, in, The device components of the drive circuit (IC) and / or another circuit attached to or part of the carrier are capable of controlling the discharge transistor (T). DIS The control terminal of the discharge transistor (T) causes the discharge transistor (T) to... DIS The capacitors (C1 to Cn) of the capacitor array (CAP) are caused to discharge with a specific laser current (IL1) via the corresponding lasers (L1 to Ln) associated with the capacitors (C1 to Cn) of the capacitor array (CAP) via the VCSEL laser array die (VCSELA). dis Discharge, and The discharge current (I) flowing through the VCSEL laser array die (VCSELA) is described above. dis The lasers (L1 to Ln) then emit light in a manner perpendicular to the surface of the VCSEL laser array die (VCSELA).

14. The optical module according to any one of claims 10 to 13, in, The carrier includes a printed circuit board (PCB) or a heat sink (HS).

15. The optical module according to claim 10, in, The deviation of the fifth pitch (PTLa) from the fourth pitch (PTCC) shall not exceed 10%.

16. The optical module according to claim 15, in, The deviation of the fifth pitch (PTLa) from the fourth pitch (PTCC) shall not exceed 5%.

17. The optical module according to claim 16, in, The deviation of the fifth pitch (PTLa) from the fourth pitch (PTCC) shall not exceed 2%.

18. The optical module according to claim 17, in, The deviation of the fifth pitch (PTLa) from the fourth pitch (PTCC) does not exceed 1%.

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