FPGA-based lower limb exoskeleton robot joint driving control system
By employing FPGA chips and motor drives in the joint drive control system of the lower limb exoskeleton robot, combined with Hall sensors and digital incremental encoders, the control system achieves compactness and high-precision control, solving the problems of slow speed and insufficient integration in the existing technology, and improving the real-time performance and reliability of the system.
Patent Information
- Application Number
- CN202211718457.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-30
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2042-12-30
AI Technical Summary
Existing joint drive control systems for lower limb exoskeleton robots are slow when handling complex scenarios, making it difficult to meet the requirements of miniaturization and integration, and their control precision is insufficient.
An FPGA chip is used as the main control device. Combined with a motor drive, Hall sensor and digital incremental encoder, the drive connection is realized through CAN communication. The main control device, drive connection device and motor socket circuit are designed to build a compact control system.
The control system has been made more compact and miniaturized, improving control accuracy and real-time performance, and meeting the compliance and reliability requirements of lower limb exoskeleton robots.
Smart Images

Figure CN116619330B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to the technical field of driving control systems, in particular to a lower-limb exoskeleton robot joint driving control system based on FPGA. BACKGROUND
[0002] The lower-limb exoskeleton robot is a kind of man-machine combined mechanical device, which is directly sleeved on the lower limbs of the human body like a suit of armor, and assists by setting driving force at the joint to enhance the walking ability and speed of people and relieve the fatigue of people under heavy load and long-time walking. The lower-limb exoskeleton robot has wide application prospects in the fields of industry, military and medical treatment.
[0003] The lower-limb exoskeleton robot joint driving control system is an important link for realizing the main function, and the performance of the control system will directly affect the compliance, reliability, real-time performance and sensitivity of the lower-limb exoskeleton robot and other related dynamic characteristics. Meanwhile, the control system should also meet the technical characteristics of miniaturization and integration.
[0004] The joint driving control system mainly comprises a control system, a sensor, a driving element and a mechanical device main body. For the driving element, the commonly used driving elements are motor driving, air pressure driving and hydraulic driving. For the control system hardware, the main control device and the driving connection device are mainly included. For the motor driving control, the control hardware usually adopts single-chip microcomputer, DSP and the like. With the increase of data volume, the processing rate is slow, and the complex scene cannot be well handled. SUMMARY
[0005] The application aims to provide a lower-limb exoskeleton robot joint driving control system based on FPGA, which simplifies the control mode, has high control precision and realizes the compactness and miniaturization of the control system.
[0006] A lower-limb exoskeleton robot joint driving control system based on FPGA comprises a main control device, a driving connection device, a driving element and a lower-limb exoskeleton robot which are connected in sequence.
[0007] Preferably, the driving element of the application adopts a motor which is installed at the hip joint and the knee joint of the lower-limb exoskeleton robot in cooperation with a harmonic reducer to drive the joint to rotate. The motor is integrated with a Hall sensor and a digital incremental encoder. The motor is connected with the driving connection device in the form of plug-jack connection to realize data transmission.
[0008] Preferably, the driving connection device of the application comprises:
[0009] A main power supply circuit is arranged for the driving connection device to provide working voltage. The main power supply circuit comprises a power socket which is used to be connected with an external input 24V DC voltage.
[0010] The safety protection circuit provides guarantee for the safe operation of the motor, comprising a power plug for connecting with an external input 24V DC voltage; a power conversion chip for converting the 24V DC voltage into 5V DC voltage, and a driving board provided with the motor to protect the motor;
[0011] The motor socket circuit is used for connecting with the motor plug, comprising a motor socket for connecting with a three-phase plug of the motor;
[0012] The Hall sensor socket circuit is used for connecting with the Hall sensor plug, comprising a Hall sensor socket for connecting with a Hall sensor integrated on the motor;
[0013] The encoder socket circuit is used for connecting with the encoder plug, comprising an encoder socket for connecting with a digital incremental encoder integrated on the motor;
[0014] The CAN communication socket circuit is used for realizing CAN communication with the master control device, comprising a CAN communication socket for CAN communication with the master control device.
[0015] The busbar circuit is used for connecting with the driving board provided with the motor, comprising 32P and 46P busbars, wherein the pitch P of the busbars is 2.54mm.
[0016] Preferably, the master control device of the application comprises a power circuit, a power filter circuit, a clock crystal circuit, a JTAG interface circuit, a CAN communication circuit, a peripheral circuit, a storage circuit and a reset circuit, wherein the power circuit is connected with the power filter circuit, the clock crystal circuit, the JTAG interface circuit, the CAN communication circuit, the peripheral circuit, the storage circuit and the reset circuit.
[0017] The power circuit converts the input voltage into the working voltage of the FPGA processor, the clock crystal circuit, the JTAG interface circuit, the CAN communication circuit, the peripheral circuit, the storage circuit and the reset circuit; the power filter circuit is connected with the power end to filter the current pulse in the power supply; the clock crystal circuit provides a constant period clock for the FPGA processor; the JTAG interface circuit downloads the bit stream file and sends it to the FPGA processor; the CAN communication circuit is used for CAN communication with the driving connection device; the peripheral circuit is used for debugging the downloaded bit stream file; the storage circuit is used for storing the downloaded bit stream file and the bit stream data transmitted by the CAN communication, and does not lose the file after power failure; the reset circuit initializes the FPGA processor and the bit stream file.
[0018] Preferably, the power supply circuit of the present application comprises a first conversion circuit for converting an external power supply input voltage DC 12V into DC 5V, a power conversion chip model MP2359; a second conversion circuit for converting DC 5V voltage into DC 3.3V, a power conversion chip model AMS1117-3.3; a third conversion circuit for converting DC 5V voltage into DC 2.5V, a power conversion chip model AMS1117-2.5; a fourth conversion circuit for converting DC 5V voltage into DC 1.2V, a power conversion chip model AMS1117-1.2. The DC 5V voltage output by the first conversion circuit is transmitted to the second, third and fourth conversion circuits through the closure of a self-locking switch, and the self-locking switch model is TK-6850-1; the external DC 12V voltage is transmitted to the power supply circuit through a DC plug, and the DC plug model is DC005-T25.
[0019] Preferably, the power supply filter circuit of the present application is provided with at least one filter capacitor between the power supply end and the ground end, and the power supply filter circuit is arranged on the front surface of the PCB and close to the chip source end and electronic components.
[0020] The clock crystal circuit comprises an active crystal oscillator with a clock frequency of 50MHz, and the active crystal oscillator model is OSC5032-50MHz-3.3V.
[0021] The JTAG interface circuit comprises a download connector, and the download connector model is Jian Niu B-3000N10P-0110.
[0022] The CAN communication circuit comprises a CAN bus transceiver chip, and the CAN bus transceiver chip model is TJA1050.
[0023] The peripheral circuit comprises a light touch key switch and an LED lamp, the light touch key switch model is TS-1101-C-W, and the LED lamp model is 17-21 / BHC-XL2M2TY / 3T.
[0024] Preferably, the storage circuit of the present application comprises an SDRAM chip for expanding the internal memory storage space and a Flash ROM chip for storing bit stream files so as not to lose files after power failure, the SDRAM chip model is W9825G6KH-6, and the Flash ROM chip model is M25P16.
[0025] Preferably, the reset circuit of the present application comprises an upper pull resistor placed on one side of the power supply input end, and the reset is realized by using a light touch key, and the low level is effective.
[0026] The application focuses on the design innovation and combination of control system hardware, sensors and driving elements, and discloses a lower limb exoskeleton robot joint driving control system based on FPGA. For the driving element, the commonly used driving modes include motor driving, air pressure driving and hydraulic driving, and the motor driving is selected in the application, because compared with the hydraulic driving and the air pressure driving, the motor driving control mode is simple, the control precision is easy to guarantee, the working noise is small, the quality is light, and the working requirements of the military lower limb exoskeleton robot are met. The motor is installed at the hip and knee joints of the left and right legs, and in addition, the requirements of the lower limb exoskeleton robot in the aspects of compactness and miniaturization are considered, so the Hall sensor and the digital incremental encoder are integrated on the motor, and the two are combined. For the control system hardware, the main control device and the driving connection device are mainly included, and the main control chip in the main control device selects the FPGA chip, because in the driving control system of the application, the main control device not only processes four motor signals, but also establishes the bottom algorithm environment and the communication environment in the form of programming, which consumes a large amount of I / O pins and memory resources. In addition, in actual production, the control hardware of the motor driving control usually adopts single-chip microcomputer, DSP and the like, and most fuzzy PID controllers (the control algorithm adopted in the application) are also realized based on the single-chip microcomputer. However, with the continuous complication of system control, higher requirements are put forward for the control chip, for example, the data calculation speed is faster, and the available storage resources are larger. The FPGA chip is developed along with the development of super large scale integrated circuit technology, and compared with the single-chip microcomputer STM and other control chips, has the advantages of high integration, good flexibility and strong real-time performance, and in addition, the system structure of the FPGA is particularly suitable for the realization of parallel budget, so the FPGA has high practical value. The main function of the driving connection device is to play the role of intermediate connection and build a connection channel. After the principle diagrams of the control system hardware are determined, the PCB is drawn through the Altium Designer software. BRIEF DESCRIPTION OF DRAWINGS
[0027] Figure 1 It is the overall structure block diagram of the lower limb exoskeleton robot joint driving control system of the application;
[0028] Figure 2 It is the structure schematic diagram of the driving element combination of the application;
[0029] Figure 3 It is the circuit diagram of the main power supply circuit of the application;
[0030] Figure 4 It is the circuit diagram of the safety protection power supply circuit of the application;
[0031] Figure 5 It is the circuit diagram of the motor socket circuit of the application;
[0032] Figure 6 Circuit diagram of the Hall sensor socket circuit of the present application;
[0033] Figure 7 Circuit diagram of the encoder socket circuit of the present application;
[0034] Figure 8 Circuit diagram of the safety protection circuit of the present application;
[0035] Figure 9 Circuit diagram of the CAN communication socket circuit of the present application;
[0036] Figure 10 Circuit diagram of the row mother circuit of the present application;
[0037] Figure 11 is a circuit diagram of the power supply circuit of the present application; wherein (a) is a circuit diagram of the first conversion circuit; (b) is a circuit diagram of the second conversion circuit; (c) is a circuit diagram of the third conversion circuit; (d) is a circuit diagram of the fourth conversion circuit; (e) is a circuit diagram of the self-locking switch;
[0038] Figure 12 Circuit diagram of the power supply filter circuit of the present application;
[0039] Figure 13 Circuit diagram of the clock crystal circuit of the present application;
[0040] Figure 14 Circuit diagram of the JTAG interface circuit of the present application;
[0041] Figure 15 Circuit diagram of the CAN communication circuit of the present application;
[0042] Figure 16 is a circuit diagram of the peripheral circuit of the present application; (a) is a circuit diagram of the key circuit; (b) is a circuit diagram of the LED lamp circuit;
[0043] Figure 17 is a circuit diagram of the storage circuit of the present application; (a) is a circuit diagram of the SDRAM; (b) is a circuit diagram of the Flash;
[0044] Figure 18 Circuit diagram of the reset circuit of the present application. DETAILED DESCRIPTION
[0045] The technical solutions of the present application will be described in detail below in combination with the drawings:
[0046] As Figure 1 shown, a lower limb exoskeleton robot joint driving control system based on FPGA, comprising a main control device, a driving connection device, a driving element and a lower limb exoskeleton robot connected in sequence.
[0047] As Figure 2As shown, the driving element of this invention is a motor, equipped with a harmonic reducer, installed at the hip and knee joints of the lower limb exoskeleton robot to drive joint rotation. The motor integrates a Hall sensor and a digital incremental encoder. The motor is connected to the driving connection device via a plug-and-socket connection to achieve data transmission. The motor of this invention is a brushless DC motor or a DC disc motor.
[0048] The drive connection device of the present invention includes:
[0049] like Figure 3 As shown, the main power supply circuit provides the operating voltage for the drive connection device; it includes a power socket for connecting to an external 24V DC input voltage.
[0050] like Figure 4 As shown, this is a safety protection power supply circuit that ensures the safe operation of the motor; it includes a power plug for connecting to an external 24V DC input voltage; and a power conversion chip for converting the 24V DC voltage to a 5V DC voltage, which, together with the motor's own drive board, protects the motor.
[0051] like Figure 5 As shown, a motor socket circuit for connecting to a motor plug includes a motor socket for connecting to a three-phase motor plug;
[0052] like Figure 6 As shown, a Hall sensor socket circuit for connecting to a Hall sensor plug includes a Hall sensor socket for connecting to a Hall sensor integrated on a motor.
[0053] like Figure 7 As shown, an encoder socket circuit for connecting to an encoder plug includes an encoder socket for connecting to a digital incremental encoder integrated on a motor.
[0054] like Figure 9 As shown, a CAN communication socket circuit for communicating with the main control device via CAN includes a CAN communication socket for CAN communication with the main control device.
[0055] like Figure 10 As shown, the busbar circuit for connecting with the motor's own drive board includes 32P and 46P busbars, with a spacing P = 2.54mm between the busbars.
[0056] like Figure 8 As shown, this is a safety protection circuit that ensures the safe operation of the motor.
[0057] The master control device of the application can be summarized as an FPGA development board, which plays a role in data processing, and further improves and improves the control accuracy of the joints of the lower limb exoskeleton robot by writing corresponding programs such as algorithm programs and communication programs in the chip. The FPGA processor connected with the power supply circuit, power filter circuit, clock crystal circuit, JTAG interface circuit, CAN communication circuit, peripheral circuit, storage circuit and reset circuit respectively; the power supply circuit is connected with the power filter circuit, clock crystal circuit, JTAG interface circuit, CAN communication circuit, peripheral circuit, storage circuit and reset circuit respectively.
[0058] The power supply circuit converts the input voltage into the working voltage of the FPGA processor, clock crystal circuit, JTAG interface circuit, CAN communication circuit, peripheral circuit, storage circuit and reset circuit; the power filter circuit is connected with the power supply end, and is used for filtering the current pulse in the power supply; the clock crystal circuit provides a constant period clock for the FPGA processor; the JTAG interface circuit downloads the bit stream file and sends it to the FPGA processor; the CAN communication circuit is used for CAN communication with the driving connection device; the peripheral circuit is used for debugging the downloaded bit stream file; the storage circuit is used for storing the downloaded bit stream file and the bit stream data transmitted by CAN communication, and does not lose the file after power failure. On the other hand, the storage memory space is expanded to meet the large memory demand occasion; the reset circuit initializes the FPGA processor and the bit stream file.
[0059] As shown in Figure 11, the power supply circuit of the application comprises a first conversion circuit for converting the external power supply input voltage DC 12V into DC 5V, a power conversion chip model MP2359, as shown in (a) in Figure 11; a second conversion circuit for converting DC 5V voltage into DC 3.3V, a power conversion chip model AMS1117-3.3, as shown in (b) in Figure 11; a third conversion circuit for converting DC 5V voltage into DC 2.5V, a power conversion chip model AMS1117-2.5, as shown in (c) in Figure 11; a fourth conversion circuit for converting DC 5V voltage into DC 1.2V, a power conversion chip model AMS1117-1.2, as shown in (d) in Figure 11. The DC 5V voltage output by the first conversion circuit is transmitted to the second, third and fourth conversion circuits through the closure of the self-locking switch, and the self-locking switch model is TK-6850-1, as shown in (e) in Figure 11; the external DC 12V voltage is transmitted to the power supply circuit through the DC plug, and the DC plug model is DC005-T25.
[0060] As Figure 12As shown, the power filtering circuit of the present invention has at least one filter capacitor located between the power supply terminal and the ground terminal. The power filtering circuit is located on the front of the PCB board and close to the chip source terminal and electronic components.
[0061] like Figure 13 As shown, the clock crystal circuit of the present invention includes an active crystal oscillator with a clock frequency of 50MHz, wherein the active crystal oscillator is model OSC5032-50MHz-3.3V;
[0062] like Figure 14 As shown, the JTAG interface circuit of the present invention includes a download connector, the model of which is Jianniu B-3000N10P-0110;
[0063] like Figure 15 As shown, the CAN communication circuit of the present invention includes a CAN bus transceiver chip, wherein the CAN bus transceiver chip is model TJA1050;
[0064] As shown in Figure 16, the peripheral circuit of the present invention includes a tactile button switch (see (a) in Figure 16) and an LED light (see (b) in Figure 16). The tactile button switch is model TS-1101-CW; the LED light is model 17-21 / BHC-XL2M2TY / 3T.
[0065] As shown in Figure 17, the storage circuit of the present invention includes an SDRAM chip for expanding memory storage space (see (a) in Figure 17) and a Flash ROM chip for storing bitstream files so that the files are not lost after power failure (see (b) in Figure 17). The SDRAM chip is model W9825G6KH-6; the Flash ROM chip is model M25P16.
[0066] like Figure 18 As shown, the reset circuit of the present invention includes a pull-up resistor placed on the power input side, and reset is achieved by a touch button, which is active low.
[0067] The lower limb exoskeleton robot joint drive control system described in this invention integrates a DC disc motor with a Hall sensor and a digital incremental encoder, which is installed at the hip and knee joints of the lower limb exoskeleton robot to drive joint rotation. To enable the lower limb exoskeleton robot to more accurately track the gait curve of the human lower limb, corresponding Verilog HDL program segments must first be written on the Quartus II software on a PC, and the corresponding bitstream file is then downloaded via JTAG and embedded into the FPGA main control chip, thereby establishing the underlying algorithm environment and CAN communication environment.
[0068] The master control device and the driving connection device are connected through CAN bus communication form, the FPGA chip sends an enable signal to the motor through the CAN bus first, so that the motor rotates. In the process of joint rotation, the sensor integrated on the motor will generate corresponding output signal, the signal is transmitted to the motor drive board through the pin-mother for amplification and filtering processing, and then the processed signal data is transmitted to the FPGA chip of the master control device through the CAN bus, as the control input of the algorithm module, and compared with the expected rotation angle. After the algorithm operation is completed, a driving signal will be generated, which is also transmitted to the motor drive board by the CAN bus and fed back to the motor to realize angle fine tuning. After the completion of the angle processing, the FPGA chip will send an enable signal to the motor again, and the cycle will be repeated, so as to realize the closed-loop control of the lower limb exoskeleton robot and track the trajectory.
Claims
1. An FPGA-based lower extremity exoskeleton robot joint drive control system, characterized in that The lower extremity exoskeleton robot comprises a main control device, a driving connection device, a driving element and a lower extremity exoskeleton robot connected in sequence. The driving element is a motor installed at the hip joint and the knee joint of the lower extremity exoskeleton robot and drives the joint to rotate, wherein the motor is integrated with a Hall sensor and a digital incremental encoder. The motor is connected with the driving connection device through a plug-in connection to realize data transmission. The driving connection device comprises: A main power supply circuit for providing working voltage for the driving connection device, comprising a power supply socket for connecting with an external input 24V DC voltage; A safety protection circuit for ensuring the safe operation of the motor, comprising a power supply plug for connecting with an external input 24V DC voltage, a power supply conversion chip for converting the DC 24V voltage into a DC 5V voltage, and a driving board integrated with the motor for protecting the motor; A motor socket circuit for connecting with the motor plug, comprising a motor socket for connecting with the three-phase plug of the motor; A Hall sensor socket circuit for connecting with the Hall sensor plug, comprising a Hall sensor socket for connecting with the Hall sensor integrated with the motor; An encoder socket circuit for connecting with the encoder plug, comprising an encoder socket for connecting with the digital incremental encoder integrated with the motor; A CAN communication socket circuit for realizing CAN communication with the main control device, comprising a CAN communication socket for CAN communication with the main control device; A busbar circuit for connecting with the driving board integrated with the motor, comprising 32P and 46P busbars with a pitch P=2.54mm; The main control device comprises an FPGA processor connected with a power supply circuit, a power supply filter circuit, a clock crystal circuit, a JTAG interface circuit, a CAN communication circuit, a peripheral circuit, a storage circuit and a reset circuit, wherein the power supply circuit is connected with the power supply filter circuit, the clock crystal circuit, the JTAG interface circuit, the CAN communication circuit, the peripheral circuit, the storage circuit and the reset circuit; The power supply circuit converts the input voltage into the working voltage of the FPGA processor, the clock crystal circuit, the JTAG interface circuit, the CAN communication circuit, the peripheral circuit, the storage circuit and the reset circuit; the power supply filter circuit is connected with the power supply end and is used for filtering the current pulse in the power supply; the clock crystal circuit provides a constant period clock for the FPGA processor; the JTAG interface circuit downloads a bit stream file and sends it to the FPGA processor; the CAN communication circuit is used for CAN communication with the driving connection device; the peripheral circuit is used for debugging the downloaded bit stream file; the storage circuit is used for storing the downloaded bit stream file and the bit stream data transmitted by CAN communication and does not lose the file after power failure; the reset circuit initializes the FPGA processor and the bit stream file.
2. The FPGA-based lower extremity exoskeleton robot joint driving control system according to claim 1, characterized in that The power supply circuit comprises a first conversion circuit for converting an external power supply input voltage DC 12V into DC 5V, a power conversion chip model MP2359; a second conversion circuit for converting DC 5V voltage into DC 3.3V, a power conversion chip model AMS1117-3.3; a third conversion circuit for converting DC 5V voltage into DC 2.5V, a power conversion chip model AMS1117-2.5; a fourth conversion circuit for converting DC 5V voltage into DC 1.2V, a power conversion chip model AMS1117-1.2; the DC 5V voltage output by the first conversion circuit is transmitted to the second, third and fourth conversion circuits through the closure of a self-locking switch, and the self-locking switch model is TK-6850-1; the external DC 12V voltage is transmitted to the power supply circuit through a DC plug, and the DC plug model is DC005-T25.
3. The FPGA-based lower extremity exoskeleton robot joint driving control system according to claim 1, characterized in that The power supply filter circuit is provided with at least one filter capacitor between the power supply end and the ground end, and the power supply filter circuit is arranged on the front surface of the PCB and close to the chip source end and electronic components; The clock crystal circuit comprises an active crystal oscillator with a clock frequency of 50MHz, and the active crystal oscillator model is OSC5032-50MHz-3.3V; The JTAG interface circuit comprises a download connector, and the download connector model is Jian Niu B-3000N10P-0110; The CAN communication circuit comprises a CAN bus transceiver chip, and the CAN bus transceiver chip model is TJA1050; The peripheral circuit comprises a light touch key switch and an LED lamp, the light touch key switch model is TS-1101-C-W, and the LED lamp model is 17-21 / BHC-XL2M2TY / 3T.
4. The FPGA-based lower extremity exoskeleton robot joint driving control system according to claim 1, characterized in that The storage circuit comprises an SDRAM chip for expanding the internal memory storage space and a Flash ROM chip for storing bit stream files so that the files are not lost after power failure, the SDRAM chip model is W9825G6KH-6, and the Flash ROM chip model is M25P16.
5. The FPGA-based lower extremity exoskeleton robot joint driving control system according to claim 1, characterized in that The reset circuit comprises an upper pull resistor arranged on one side of the power supply input end, and the reset is realized by using a light touch key, and the low level is effective.
Citation Information
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