High-precision real-time generation method for wide-bandwidth radar signals

Abstract

The present invention relates to a high-precision, real-time method for generating wide-bandwidth radar signals. This method, which belongs to the field of signal generation technology, addresses the difficulty in generating high-precision wide-bandwidth radar signals in the prior art. The method comprises: determining the signal type of the wide-bandwidth radar signal based on signal parameters of the wide-bandwidth radar signal transmitted by a host computer; configuring registers of an FPGA real-time channel based on the signal type, generating raw data based on the signal type, and copying the raw data until the total data duration reaches a total duration threshold to obtain a transmission data file; setting an interrupt using a timer, and cyclically writing the transmission data file to the FPGA's DDR memory during each timer interrupt to obtain transmitted data; and generating a wide-bandwidth radar signal by cyclically reading the transmitted data through the FPGA. This method achieves high-precision, real-time generation of wide-bandwidth radar signals.

Description

Technical Field

[0001] The present invention relates to the technical field of signal generation, and in particular to a high-precision real-time generation method for a large-bandwidth radar signal. Background Art

[0002] With the continuous development of modern information technology and electronic technology, a large number of electronic information equipment are constantly being used, making the electromagnetic signals in the electromagnetic environment increasingly dense, and the electromagnetic environment increasingly complex.

[0003] Existing technologies are limited by the data processing capabilities of the signal generation unit and cannot generate wide-bandwidth radar signals in real time. Conventional cyclic transmission requires writing complete data based on the space size set by the FPGA (Field Programmable Gate Array). This method causes the signal emitted by the FPGA to repeat in the time domain at the set space size. When sending periodic signals, errors in certain periods or large overall period errors may occur, resulting in poor period accuracy of the generated signal.

[0004] Therefore, there is an urgent need for a solution to generate high-precision, large-bandwidth radar signals. Summary of the Invention

[0005] In view of the above analysis, the embodiments of the present invention aim to provide a high-precision real-time generation method for a wide-bandwidth radar signal, so as to solve the problem in the prior art that it is difficult to generate a high-precision wide-bandwidth radar signal.

[0006] An embodiment of the present invention provides a high-precision real-time generation method for a wide-bandwidth radar signal, the generation method comprising:

[0007] Determine the signal type of the wide-bandwidth radar signal according to the signal parameters of the wide-bandwidth radar signal sent by the host computer;

[0008] The register of the FPGA real-time channel is configured according to the signal type, and raw data is generated according to the signal type, and the raw data is copied until the total duration of the data reaches the total duration threshold, thereby obtaining a sending data file;

[0009] Using a timer to set an interrupt, during each timer interruption, the sending data file is cyclically written into the DDR memory of the FPGA to obtain the sent data;

[0010] The FPGA generates a large-bandwidth radar signal by cyclically reading the transmitted data.

[0011] Based on a further improvement of the above method, the signal type includes one or more of the following:

[0012] Radar signal under fixed period;

[0013] Radar signal under repetition frequency jitter;

[0014] Radar signal with uneven repetition frequency.

[0015] Based on a further improvement of the above method, generating raw data according to the signal type includes:

[0016] When the signal type is a radar signal under the fixed period, raw data of a complete period is generated according to the signal parameters, and the sampling rate of the raw data is the same as the sampling rate of the FPGA real-time channel.

[0017] Based on a further improvement of the above method, generating raw data according to the signal type includes:

[0018] When the signal type is the radar signal under the repetition rate jitter, obtaining the jitter range of the radar signal;

[0019] determining, based on the signal parameters and the jitter range, a number of jitter cycles for generating raw data;

[0020] Raw data of the number of jitter cycles is generated according to the signal parameters.

[0021] Based on a further improvement of the above method, generating raw data according to the signal type includes:

[0022] When the signal type is the radar signal with staggered repetition frequency, obtaining a staggered signal repetition frequency staggered period set;

[0023] According to the signal parameters, a signal of a whole cycle is generated as original data, wherein the signal of the whole cycle includes the staggered signals of each cycle in the staggered signal repetition frequency staggered cycle set.

[0024] Based on the further improvement of the above method, the generation method includes:

[0025] The total duration threshold is determined according to the read cycle of the FPGA real-time channel; the total duration threshold is twice the read cycle of the FPGA real-time channel.

[0026] Based on the further improvement of the above method, the sending data file is cyclically written into the DDR memory of the FPGA during each timer interrupt process, including:

[0027] Compare the address length between the write address and the read address with the address length corresponding to the read cycle of the FPGA real-time channel;

[0028] When the address length between the write address and the read address is less than the address length corresponding to the read cycle of the FPGA real-time channel, the timer interrupt process is directly exited; otherwise, the sending data file is written to the DDR memory corresponding to the write address.

[0029] Based on a further improvement of the above method, the step of writing the sent data file into the DDR memory corresponding to the write address further includes:

[0030] Using the file pointer as the starting address, read the sending data file with the address length corresponding to the read cycle of the FPGA real-time channel backward;

[0031] If the address length from the file pointer to the end of the file is less than the address length corresponding to the read cycle of the FPGA real-time channel, the data is read twice: the first read is from the file pointer to the end of the file, and the second read is from the file header, until the sum of the address lengths of the first and second reads reaches the address length corresponding to the read cycle of the FPGA real-time channel;

[0032] The read send data file is written into the DDR memory corresponding to the write address, and the timer interrupt process is exited.

[0033] Based on a further improvement of the above method, the step of generating a wide-bandwidth radar signal by cyclically reading the transmitted data includes:

[0034] Determine the address length of the sent data in the DDR memory of the FPGA. When the address length of the sent data in the DDR memory of the FPGA is greater than 2 times the address length corresponding to the read cycle of the FPGA real-time channel, the FPGA starts to read the sent data.

[0035] Based on a further improvement of the above method, the signal parameters include one or more of the following:

[0036] Signal type, amplitude, carrier frequency, bandwidth, period, pulse width, Doppler shift, channel parameters and frequency conversion method.

[0037] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0038] The DSP (Digital Signal Processing) of the present invention only calls the generation of raw data once and then copies it to obtain a transmission data file. During subsequent timer interrupts, the transmission data file is continuously sent to the DDR of the FPGA, consuming only the time required to send the data. This achieves real-time transmission of large-bandwidth radar signals and high-precision generation.

[0039] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following description, and some advantages will become apparent from the description or be learned through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like parts throughout the drawings.

[0041] Figure 1 A flowchart of a method for high-precision real-time generation of wide-bandwidth radar signals provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0043] In the traditional model, a signal generation system primarily consists of a host computer, a signal generation unit (DSP), and a signal synthesis unit (FPGA). The host computer is responsible for programming the control unit, setting signal parameters, and sending these data to the signal generation unit via an interface such as a network port according to a specified protocol. The signal generation unit then generates baseband signal data and related parameters such as frequency conversion based on these signal parameters, writing them into the registers and DDR of the signal synthesis unit. The signal synthesis unit then synthesizes the signal based on the relevant configuration.

[0044] During real-time transmission, the DSP generates signal data in real time and refreshes the signal data in the FPGA's DDR in real time. The FPGA reads the DDR data in a loop, and the DSP must ensure data continuity. During cyclic transmission, the DSP writes data to the corresponding FPGA DDR and configures registers to determine the FPGA's data length. The FPGA then reads the data in a loop and outputs it. The DSP no longer generates signals during the FPGA output process.

[0045] However, due to the limited hardware capabilities of FPGA, two mixed modes of cyclic transmission and real-time transmission are used to synthesize signals when generating multi-channel signals.

[0046] Existing technologies for real-time signals are limited by the data processing capabilities of the signal generation unit and cannot generate large-bandwidth radar signals in real time. Traditional cyclic transmission requires writing complete data according to the space size set by the FPGA (Field Programmable Gate Array). This method causes the signal emitted by the FPGA to repeat in the time domain at the set space size. When sending periodic signals, certain cycle errors or large overall cycle errors may occur, resulting in poor period accuracy of the generated signal.

[0047] A specific embodiment of the present invention discloses a high-precision real-time generation method for a wide-bandwidth radar signal, which can generate a high-precision wide-bandwidth radar signal. Figure 1 As shown, the generating method includes:

[0048] Step S1: determining the signal type of the wide-bandwidth radar signal according to the signal parameters of the wide-bandwidth radar signal sent by the host computer;

[0049] Step S2: configuring the register of the FPGA real-time channel according to the signal type, generating original data according to the signal type, and copying the original data until the total duration of the data reaches the total duration threshold, thereby obtaining a sending data file;

[0050] Step S3: Using a timer to set an interrupt, during each timer interruption, the sending data file is cyclically written into the DDR memory of the FPGA to obtain the sent data;

[0051] Step S4: the FPGA reads the transmitted data in a loop to generate a large-bandwidth radar signal.

[0052] Specifically, users can configure the signal parameters of the generated wide-bandwidth radar signal through the host computer. After the configuration is completed, the signal parameters are sent to the signal generation unit (DSP) through the interface to generate data. After the data is generated, the data is synthesized in the signal synthesis unit (FPGA).

[0053] Specifically, determine the configuration parameters of the FPGA real-time channel, such as the sampling rate of the FPGA real-time channel, the read cycle of the FPGA real-time channel, and the size of the DDR memory space corresponding to the FPGA real-time channel, and calculate how long the DDR memory space corresponding to the FPGA real-time channel can store data with a read time.

[0054] It's worth noting that the duration of data that can be stored in the storage space = memory space size / (sampling rate * 4). For example, if the sampling rate of the FPGA real-time channel is 75MHz, the read cycle of the FPGA real-time channel is 100ms, and the corresponding DDR memory space size of the FPGA real-time channel is 150MB, then the calculated DDR memory space corresponding to the FPGA real-time channel can store 500ms of data.

[0055] Specifically, when the signal is sent to the DSP, the DSP can calculate the signal power (signal amplitude) and carrier frequency based on the signal parameters, and configure the relevant registers of the FPGA real-time channel to facilitate the FPGA real-time channel to read the data.

[0056] Specifically, in step S1, after receiving the signal parameters of the wide-bandwidth radar signal sent by the host computer, the DSP analyzes the signal parameters sent by the host computer to determine the signal type of the wide-bandwidth radar signal.

[0057] Preferably, the signal type includes one or more of the following:

[0058] Radar signal under fixed period;

[0059] Radar signal under repetition frequency jitter;

[0060] Radar signal with uneven repetition frequency.

[0061] Specifically, the radar signal under a fixed period is used as a conventional radar signal. The length of the intra-pulse data of the radar signal is fixed, and the length of the rest period is fixed. The intra-pulse data and the rest period data constitute the signal parameter data of the conventional radar signal.

[0062] Specifically, the radar signal under repetition frequency jitter is jittered within a preset jitter range, the intra-pulse data length of the radar signal is fixed, and the rest period is periodically jittered within the jitter range. The intra-pulse data and the rest period data constitute the signal parameter data of the radar signal under repetition frequency jitter.

[0063] Specifically, the period of the radar signal under the staggered repetition frequency fluctuates within a preset period set, the intra-pulse data length of the radar signal is fixed, and the rest period fluctuates periodically within the period set. The intra-pulse data and the rest period data constitute the signal parameter data of the radar signal under the staggered repetition frequency.

[0064] It is understandable that the signal type in the present invention may also include other types of radar signals, which will not be described in detail here.

[0065] Specifically, in step S1 , after analyzing the signal parameters of the wide-bandwidth radar signal, the signal type of the wide-bandwidth radar signal can be determined.

[0066] Preferably, the signal parameters include one or more of the following:

[0067] Signal type, amplitude, carrier frequency, bandwidth, period, pulse width, Doppler shift, channel parameters and frequency conversion method.

[0068] Specifically, the signal parameters must be configured for the generation of the wide-bandwidth radar signal. According to the generated wide-bandwidth radar signal, the signal parameters are reasonably configured so that the generated wide-bandwidth radar signal is rich and diverse, and more suitable for increasingly stringent usage requirements.

[0069] Specifically, in step S2, after determining the signal type of the wide-bandwidth radar signal, the registers of the FPGA real-time channel are configured based on the signal type. Register configuration can be performed by obtaining the FPGA register configuration table and configuration method. The following parameters can also be obtained: channel center frequency, frequency shift, amplitude, or generation time of each signal, and register configuration is performed based on these parameters.

[0070] Preferably, generating raw data according to the signal type includes:

[0071] When the signal type is a radar signal with a fixed period, raw data for a complete period is generated based on the signal parameters. The sampling rate of this raw data is the same as the sampling rate of the FPGA real-time channel. It is understood that the sampling rate is a necessary parameter for signal data, but it is not a configurable parameter. Generally, each channel in the FPGA design is configured with a fixed sampling rate. When the DSP generates data, it needs to determine the sampling rate based on the written FPGA channel.

[0072] Specifically, when the signal type is determined to be a fixed-period radar signal based on the signal parameters, the period of the generated wide-bandwidth radar signal is determined based on the period in the signal parameters. Based on this fixed-period radar signal period, the DSP generates a complete cycle of signal data as the raw data. It is understood that the necessary parameters required to generate a complete cycle of radar signal data include: period, pulse width, amplitude, and signal type. The period determines the length of the generated periodic data, the pulse width determines the length of the data within the pulse, the amplitude determines the size of the data within the pulse, and the signal type determines the type of data within the pulse.

[0073] The raw data is sampled at the same rate as the FPGA real-time channel. For example, if the signal period is 6666µs and the FPGA real-time channel sampling rate is 75MHz, a complete period (6666µs) of data at a 75MHz sampling rate is generated as the raw data.

[0074] Preferably, generating raw data according to the signal type includes:

[0075] When the signal type is the radar signal under the repetition rate jitter, obtaining the jitter range of the radar signal;

[0076] determining, based on the signal parameters and the jitter range, a number of jitter cycles for generating raw data;

[0077] Raw data of the number of jitter cycles is generated according to the signal parameters.

[0078] Specifically, when the signal type is determined to be a radar signal with repetition rate jitter based on signal parameters, the jitter range of the generated wide-bandwidth radar signal is determined based on the signal parameters. Based on the jitter range, the jitter range of each cycle can be determined. For example, if the jitter range is 10% and the fixed period is 6666µs, the period of the generated wide-bandwidth radar signal can be determined to be jittered within a range of 90%*6666µs to 110%*6666µs.

[0079] The number of jitter cycles required to generate raw data is determined based on the jitter range and signal parameters. A larger jitter range requires a larger number of jitter cycles; a smaller jitter range requires a smaller number of jitter cycles, which improves the accuracy of wide-bandwidth radar signals. For example, when the jitter range is 10%, a suitable number of jitter cycles is 10, meaning 10 cycles of data are generated as raw data.

[0080] Preferably, generating raw data according to the signal type includes:

[0081] When the signal type is the radar signal with staggered repetition frequency, obtaining a staggered signal repetition frequency staggered period set;

[0082] According to the signal parameters, a signal of a whole cycle is generated as original data, wherein the signal of the whole cycle includes the staggered signals of each cycle in the staggered signal repetition frequency staggered cycle set.

[0083] Specifically, when the signal type is determined to be a radar signal with staggered repetition rates based on signal parameters, a set of staggered signal repetition rates and periods for the generated wide-bandwidth radar signal is determined based on the signal parameters. For example, if the staggered signal repetition rate and period set includes 1111us, 2222us, 4444us, and 6666us, then a signal for a full cycle includes signals for a full cycle. The DSP generates signal data for a full cycle based on the signal parameters as raw data, with a signal length of 14.443ms.

[0084] Specifically, in step S2, after the original data is generated, the original data is copied. Exemplarily, the original data is copied through memcpy() until the total data length of the copied data reaches the total length threshold, then the copying is stopped and the copied data is saved as a sending data file in the DDR memory space of the DSP.

[0085] For example, assuming the duration of the original data is t1, the total duration threshold T is generally greater than the duration t1 of the original data. During the copying process, the original data is repeatedly copied until the duration of the copied signal reaches the total duration threshold. It can be understood that the copied data is a temporal sequence of multiple original data.

[0086] Preferably, the generating method comprises:

[0087] The total duration threshold is determined according to the read cycle of the FPGA real-time channel; the total duration threshold is twice the read cycle of the FPGA real-time channel.

[0088] Specifically, the FPGA real-time channel read cycle is a fixed configuration parameter of the FPGA real-time channel. The total duration threshold can be determined based on the FPGA real-time channel read cycle. The total duration threshold is greater than the FPGA real-time channel read cycle. It is worth noting that if the total duration threshold is too short, the number of file reads will increase, thereby slowing program execution. If it is too long, it will increase memory consumption. A total duration threshold of twice the FPGA real-time channel read cycle achieves optimal results.

[0089] Specifically, through the execution of the above steps S1 and S2, the sending data file has been obtained, and the sending data file has been saved in the DDR memory space of the DSP.

[0090] In step S3, the send data file needs to be continuously sent to the FPGA's DDR memory space. Specifically, a timer interrupt is set. The timer period must be less than the read period of the FPGA's real-time channel to ensure that the write speed is faster than the read speed. During each timer interrupt, the send data file is written to the FPGA's DDR memory to obtain the sent data.

[0091] Preferably, the sending data file is cyclically written into the DDR memory of the FPGA during each timer interruption process, including:

[0092] Compare the address length between the write address and the read address with the address length corresponding to the read cycle of the FPGA real-time channel;

[0093] When the address length between the write address and the read address is less than the address length corresponding to the read cycle of the FPGA real-time channel, the timer interrupt process is directly exited; otherwise, the sending data file is written to the DDR memory corresponding to the write address.

[0094] Specifically, when the cycle time set by the timer is reached, an interrupt process is triggered. During the interrupt process, the read address of the FPGA real-time channel to the FPGA DDR memory is compared with the write address of the DSP to be sent to the FPGA DDR memory.

[0095] It's worth noting that while the FPGA is reading from the FPGA's DDR memory, the DSP cannot write the transmit data file to the corresponding FPGA's DDR memory. For example, if the FPGA's DDR memory contains 500ms of data and the FPGA's real-time channel has a read cycle of 100ms, 500ms of data can be stored in the FPGA's DDR memory. The FPGA's memory can be divided into five 100ms memories, named Memory 1, Memory 2, Memory 3, Memory 4, and Memory 5. When the FPGA is reading Memory 1, if the DSP writes the transmit data file to Memory 1, the newly written transmit data file will overwrite the old transmit data file, causing errors when the FPGA reads data from Memory 1.

[0096] Specifically, compare the address length between the write address and the read address with the address length corresponding to the read cycle of the FPGA real-time channel; if the address length between the write address and the read address is less than the address length corresponding to the read cycle of the FPGA real-time channel, directly exit the timer interrupt process; otherwise, write the sending data file to the DDR memory corresponding to the write address.

[0097] It is worth noting that, according to the timer cycle setting, it can be determined that the FPGA's reading operation on the FPGA's DDR memory is always performed after the DSP writes the send data file to the FPGA's DDR memory, and the FPGA's DDR memory has certain limitations. When the write address where the DSP writes the send data file to the FPGA's DDR memory and the read address where the FPGA reads the FPGA's DDR memory are less than the address length corresponding to the read cycle of the FPGA's real-time channel, it means that the DSP writes to the FPGA's DDR memory too fast. If the data is written, part of the data after the read address will be overwritten, resulting in data loss. Therefore, the send data file cannot be written to the write address at this time. It is necessary to wait until the FPGA reads the data at the corresponding read address before writing.

[0098] Preferably, the step of writing the sent data file into a DDR memory corresponding to a write address further comprises:

[0099] Using the file pointer as the starting address, read the sending data file with the address length corresponding to the read cycle of the FPGA real-time channel backward;

[0100] If the address length from the file pointer to the end of the file is less than the address length corresponding to the read cycle of the FPGA real-time channel, the data is read twice: the first read is from the file pointer to the end of the file, and the second read is from the file header, until the sum of the address lengths of the first and second reads reaches the address length corresponding to the read cycle of the FPGA real-time channel;

[0101] The read send data file is written into the DDR memory corresponding to the write address, and the timer interrupt process is exited.

[0102] Specifically, when the DSP saves the send data file to the DSP's DDR memory, the memory address size occupied by the send data file is not necessarily an integer multiple of the FPGA real-time channel's read cycle. However, when the DSP writes the send data file to the FPGA's memory space, it needs to write the data for the FPGA real-time channel's read cycle each time. Therefore, when the DSP's file pointer reads data from the DSP's DDR memory, if the address length from the file pointer to the end of the file is less than the address length corresponding to the FPGA real-time channel's read cycle, the address length cannot be read in one go. In this case, the data needs to be read in two steps: the first step is to read from the file pointer to the end of the file, and the second step is to read from the file header until the total address length of the first and second reads reaches the address length corresponding to the FPGA real-time channel's read cycle.

[0103] The DSP sends the data read from the DSP's DDR memory to the FPGA's DDR memory for writing, and exits the current timer interrupt process.

[0104] Specifically, in step S4, the FPGA cyclically reads the transmitted data stored in the DDR memory of the FPGA, and generates a large-bandwidth radar signal according to the read data.

[0105] Preferably, the generating of a wide-bandwidth radar signal by cyclically reading the transmitted data comprises:

[0106] Determine the address length of the sent data in the DDR memory of the FPGA. When the address length of the sent data in the DDR memory of the FPGA is greater than 2 times the address length corresponding to the read cycle of the FPGA real-time channel, the FPGA starts to read the sent data.

[0107] Specifically, because the FPGA must read the transmitted data from its DDR memory after the DSP writes the transmit data file to the FPGA's DDR memory, the time at which the FPGA begins reading the transmitted data from the FPGA's DDR memory can be set. The FPGA begins reading the transmitted data when the address length occupied by the transmitted data in the FPGA's DDR memory is greater than twice the address length corresponding to the read cycle of the FPGA's real-time channel.

[0108] The following three specific embodiments illustrate the high-precision real-time generation method of a wide-bandwidth radar signal provided by the present invention.

[0109] The implementation of this embodiment of the present invention comprises three components: a host computer for configuring signal parameters; a DSP, serving as the algorithm's core logic control unit, generating integer-cycle signal data; and an FPGA for signal synthesis, providing a DDR address space for a wide-bandwidth radar signal as the address space for the real-time channel. This embodiment describes three radar signal types separately. In the following example, the FPGA real-time channel sampling rate is 75MHz, the real-time channel signal data read cycle is 100ms, and the corresponding DDR data space size for this channel is 150MHz, meaning that the storage space is sufficient for 500ms of data.

[0110] Example 1: For radar signals with a fixed period.

[0111] 1) Configure the signal parameters of a radar signal through the host computer. Here, a linear frequency modulation signal is used as an example. The configuration period is 6666us, and the signal pulse width and other parameters follow the signal pattern and are randomly configured.

[0112] 2) After the signal is sent to the signal generation module DSP, the signal generation module DSP calculates the signal power and carrier frequency based on the sent signal parameters and configures the relevant registers of the FPGA corresponding to the real-time channel;

[0113] 3) Based on the signal parameters, generate a complete cycle (i.e., 6666us) of data at a 75M sampling rate as the original data;

[0114] 4) Copy the data of a complete cycle at a 75M sampling rate so that its total duration is greater than 200ms (here it is set to twice the signal data reading period. If the time is too short, the file will be read repeatedly, thereby slowing down the program running speed. If the time is too long, it will increase memory consumption). The copied data is used as the sending data file and saved in the DDR memory of the local DSP as a file;

[0115] 5) Set the timer period to 80ms, and use the interrupt function to write the send data file stored in the DDR memory of the DSP to the DDR memory of the FPGA to obtain the sent data;

[0116] 6) After entering the interrupt, first determine the length between the address where the data file is written to the FPGA's DDR memory and the address where the FPGA reads the FPGA's DDR memory. If it is less than 100ms (i.e., the written data is about to overwrite the original data that the FPGA has not read), exit the interrupt directly and skip this write;

[0117] 7) If there is no jump in (6), read 100ms of data backward with the file pointer as the starting address (the file pointer moves to the end of the data to be read. If the file pointer is less than 100ms from the end of the file, read it twice) and write it into the DDR of the FPGA;

[0118] 8) FPGA reads the transmitted data in a loop to generate a large-bandwidth radar signal.

[0119] Example 2: Targeting radar signals with repetition rate jitter.

[0120] 1) Configure a radar signal through the host computer. Here, a linear frequency modulation signal is used as an example. The configuration period is 6666us, the repetition rate jitter range is 10%, and the signal pulse width and other parameters are randomly configured according to the signal pattern.

[0121] 2) After the signal is sent to the signal generation module DSP, the signal generation module DSP calculates the signal power and carrier frequency based on the sent signal parameters and configures the relevant registers of the FPGA corresponding to the real-time channel;

[0122] 3) Determine the number of generated cycles to be 10, that is, generate 10 cycles of data, with the jitter of each cycle within 10%, including the upper and lower boundaries, as the original data;

[0123] 4) Copy the original data in 3) so that its total duration is greater than 200ms (here it is set to twice the signal data reading period. If the time is too short, the file will be read repeatedly, thereby slowing down the program running speed. If the time is too long, it will increase memory consumption). The copied data is used as the sending data file and saved in the DDR memory of the local DSP as a file;

[0124] 5) Set the timer period to 80ms, and use the interrupt function to write the send data file stored in the DDR memory of the DSP to the DDR memory of the FPGA to obtain the sent data;

[0125] 6) After entering the interrupt, first determine the length between the address where the data file is written to the FPGA's DDR memory and the address where the FPGA reads the FPGA's DDR memory. If it is less than 100ms (i.e., the written data is about to overwrite the original data that the FPGA has not read), exit the interrupt directly and skip this write;

[0126] 7) If there is no jump in (6), read 100ms of data backward with the file pointer as the starting address (the file pointer moves to the end of the data to be read. If the file pointer is less than 100ms from the end of the file, read it twice) and write it into the DDR of the FPGA;

[0127] 8) FPGA reads the transmitted data in a loop to generate a large-bandwidth radar signal.

[0128] Example 3: For radar signals with uneven repetition frequencies.

[0129] 1) Configure a radar signal through the host computer. Here, a linear frequency modulation signal is used as an example. The repetition frequency staggered period set is configured as 1111us, 2222us, 4444us, and 6666us. The signal pulse width and other parameters are randomly configured according to the signal pattern.

[0130] 2) After the signal is sent to the signal generation module DSP, the signal generation module DSP calculates the signal power and carrier frequency based on the sent signal parameters and configures the relevant registers of the FPGA corresponding to the real-time channel;

[0131] 3) Generate a signal containing a whole cycle period, that is, generate data with periods of 1111us, 2222us, 4444us, and 6666us in sequence, with a total signal length of 14.443ms, as the original data;

[0132] 4) Copy the original data in 3) so that its total duration is greater than 200ms (here it is set to twice the signal data reading period. If the time is too short, the file will be read repeatedly, thereby slowing down the program running speed. If the time is too long, it will increase memory consumption). The copied data is used as the sending data file and saved in the DDR memory of the local DSP as a file;

[0133] 5) Set the timer period to 80ms, and use the interrupt function to write the send data file stored in the DDR memory of the DSP to the DDR memory of the FPGA to obtain the sent data;

[0134] 6) After entering the interrupt, first determine the length between the address where the data file is written to the FPGA's DDR memory and the address where the FPGA reads the FPGA's DDR memory. If it is less than 100ms (i.e., the written data is about to overwrite the original data that the FPGA has not read), exit the interrupt directly and skip this write;

[0135] 7) If there is no jump in (6), read 100ms of data backward with the file pointer as the starting address (the file pointer moves to the end of the data to be read. If the file pointer is less than 100ms from the end of the file, read it twice) and write it into the DDR of the FPGA;

[0136] 8) FPGA reads the transmitted data in a loop to generate a large-bandwidth radar signal.

[0137] Compared with the prior art, the high-precision real-time generation method for large-bandwidth radar signals provided by the embodiments of the present invention utilizes a DSP (Digital Signal Processing) that only calls the generation of raw data once and then copies the data file to be sent. During subsequent timer interrupts, the data file is continuously sent to the FPGA's DDR memory, consuming only the time required to send the data. This achieves real-time transmission and high-precision generation of large-bandwidth radar signals.

[0138] Those skilled in the art will appreciate that all or part of the process steps of the above-described embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a magnetic disk, an optical disk, a read-only memory, or a random access memory.

[0139] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A high-precision real-time generation method for a wide-bandwidth radar signal, characterized in that: The generation method comprises: Determine the signal type of the wide-bandwidth radar signal according to the signal parameters of the wide-bandwidth radar signal sent by the host computer; The register of the FPGA real-time channel is configured according to the signal type, and raw data is generated according to the signal type, and the raw data is copied until the total duration of the data reaches the total duration threshold, thereby obtaining a sending data file; Using a timer to set an interrupt, during each timer interrupt, the sending data file is cyclically written into the DDR memory of the FPGA to obtain the sent data; The FPGA generates a large-bandwidth radar signal by cyclically reading the transmitted data.

2. The generation method according to claim 1, characterized in that The signal type includes one or more of the following: Radar signal under fixed period; Radar signal under repetition frequency jitter; Radar signal with uneven repetition frequency.

3. The generation method according to claim 2, characterized in that Generating original data according to the signal type includes: When the signal type is a radar signal under the fixed period, raw data of a complete period is generated according to the signal parameters, and the sampling rate of the raw data is the same as the sampling rate of the FPGA real-time channel.

4. The generation method according to claim 2, characterized in that Generating original data according to the signal type includes: When the signal type is the radar signal under the repetition rate jitter, obtaining the jitter range of the radar signal; determining, based on the signal parameters and the jitter range, a number of jitter cycles for generating raw data; Raw data of the number of jitter cycles is generated according to the signal parameters.

5. The generation method according to claim 2, characterized in that Generating original data according to the signal type includes: When the signal type is the radar signal with staggered repetition frequency, obtaining a staggered signal repetition frequency staggered period set; According to the signal parameters, a signal of a whole cycle is generated as original data, wherein the signal of the whole cycle includes the staggered signals of each cycle in the staggered signal repetition frequency staggered cycle set.

6. The generation method according to claim 1, characterized in that The generation method comprises: The total duration threshold is determined according to the read cycle of the FPGA real-time channel; the total duration threshold is twice the read cycle of the FPGA real-time channel.

7. The generation method according to claim 1, characterized in that During each timer interruption, the sending data file is cyclically written into the DDR memory of the FPGA, including: Compare the address length between the write address and the read address with the address length corresponding to the read cycle of the FPGA real-time channel; When the address length between the write address and the read address is less than the address length corresponding to the read cycle of the FPGA real-time channel, the timer interrupt process is directly exited; otherwise, the sending data file is written to the DDR memory corresponding to the write address.

8. The generation method according to claim 7, characterized in that The step of writing the sent data file into the DDR memory corresponding to the write address further includes: Using the file pointer as the starting address, read the sending data file with the address length corresponding to the read cycle of the FPGA real-time channel backward; If the address length from the file pointer to the end of the file is less than the address length corresponding to the read cycle of the FPGA real-time channel, the data is read twice: the first read is from the file pointer to the end of the file, and the second read is from the file header, until the sum of the address lengths of the first and second reads reaches the address length corresponding to the read cycle of the FPGA real-time channel; The read send data file is written into the DDR memory corresponding to the write address, and the timer interrupt process is exited.

9. The generation method according to claim 1, characterized in that The method of generating a large-bandwidth radar signal by cyclically reading the transmitted data includes: Determine the address length of the sent data in the DDR memory of the FPGA. When the address length of the sent data in the DDR memory of the FPGA is greater than 2 times the address length corresponding to the read cycle of the FPGA real-time channel, the FPGA starts to read the sent data.

10. The generation method according to claim 1, characterized in that The signal parameters include one or more of the following: Signal type, amplitude, carrier frequency, bandwidth, period, pulse width, Doppler shift, channel parameters and frequency conversion method.

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