Display device and driving method thereof

Abstract

The application provides a display device and a driving method thereof, and relates to the technical field of display, the display device comprising a display panel, at least two driving chips and a circuit board, the driving chips are electrically connected with the display panel, at least one driving chip comprises a detection unit; the plurality of driving chips are electrically connected with the circuit board, and the circuit board comprises a timing controller; wherein the timing controller comprises a plurality of shift register signal output ends, each shift register signal output end is configured to output a shift register signal; the detection unit of one driving chip is electrically connected with at least one shift register signal output end, and the detection unit is configured to detect whether the timing controller can normally output the shift register signal. The display device is suitable for the preparation of high-quality display products.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and a driving method thereof. BACKGROUND

[0002] With the development of display technology, people have higher and higher requirements on the picture quality and use performance of display products. In the display products of the related technology, a power supply protection device is provided to avoid damage to the screen due to power supply abnormalities. When overcurrent, over power or overvoltage occurs, the power supply protection mechanism is triggered to automatically power off the device to protect the product.

[0003] However, at present, there is no detection method for other abnormal problems of hardware or signal transmission in addition to power supply abnormalities. SUMMARY

[0004] Embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, embodiments of the present application provide a display device, comprising:

[0006] a display panel;

[0007] at least two driving chips, each of which is electrically connected to the display panel, and at least one of the driving chips comprises a detection unit;

[0008] a circuit board, each of the driving chips is electrically connected to the circuit board, and the circuit board comprises a timing controller;

[0009] The timing controller comprises a plurality of shift register signal output ends, each of which is configured to output a shift register signal. The detection unit of one of the driving chips is electrically connected to at least one of the shift register signal output ends, and the detection unit is configured to detect whether the timing controller can normally output the shift register signal.

[0010] In at least one embodiment of the present application, the display device further comprises:

[0011] a display control chip, which is electrically connected to the driving chip and is configured to provide a power supply signal to the display panel through the driving chip;

[0012] In the case that the detection unit detects the shift register signal, the detection unit is configured to control the display control chip to output the power supply signal;

[0013] In the case that the detection unit fails to detect the shift register signal, the detection unit is configured to control the display control chip to stop outputting the power supply signal.

[0014] In at least one embodiment of this application, the driver chip with the detection unit further includes a protection unit, which is electrically connected to the detection unit; the display control chip further includes an enable signal input terminal, and all the protection units are electrically connected to the enable signal input terminal.

[0015] If the detection unit fails to detect the shift register signal, the detection unit is configured to trigger the protection unit, which is configured to transmit a protection signal to the enable signal input terminal. The protection signal is configured to control the display control chip to stop outputting the power signal.

[0016] In at least one embodiment of this application, when the detection unit detects the shift register signal, the protection unit is configured to stop outputting the protection signal, and the display control chip is configured to maintain the output of the power signal.

[0017] In at least one embodiment of this application, the circuit board further includes a first signal conversion module and a second signal conversion module, and the display panel further includes a first shift register module and a second shift register module located on both sides of the display area;

[0018] The first signal conversion module and the second signal conversion module are electrically connected to at least one of the driver chips, the first signal conversion module is electrically connected to the first shift register module, and the second signal conversion module is electrically connected to the second shift register module.

[0019] In at least one embodiment of this application, each of the driver chips includes the detection unit and the protection unit, and one of the shift register signal output terminals is electrically connected to the detection unit of one of the driver chips.

[0020] In at least one embodiment of this application, each of the driver chips includes two general purpose input / output ports, wherein one of the general purpose input / output ports is electrically connected to the detection unit and the timing controller, respectively, and the other general purpose input / output port is electrically connected to the protection unit and the enable signal input terminal, respectively.

[0021] In at least one embodiment of this application, each of the driver chips is electrically connected to the first signal conversion module and the second signal conversion module.

[0022] In at least one embodiment of this application, the plurality of driver chips includes a main driver chip, the main driver chip includes the detection unit and the protection unit, and all the shift register signal output terminals are electrically connected to the detection unit of the main driver chip.

[0023] In at least one embodiment of this application, the main driver chip is electrically connected to the first signal conversion module and the second signal conversion module, respectively.

[0024] In at least one embodiment of this application, the display control chip is integrated on the circuit board;

[0025] Alternatively, the display device may further include a system motherboard, on which the display control chip is integrated.

[0026] In at least one embodiment of this application, the circuit board further includes a touch control chip, which is electrically connected to the timing controller, the system motherboard and the display panel respectively.

[0027] In at least one embodiment of this application, the display device further includes a system-side motherboard, and the circuit board further includes a voltage conversion circuit, a power management chip, a first memory, and a second memory;

[0028] The timing controller, the voltage conversion circuit, and the first memory are electrically connected to the system motherboard, and the first memory, the second memory, and the power management chip are electrically connected to the timing controller.

[0029] The voltage conversion circuit is electrically connected to the power management chip and the timing controller respectively; the power management chip is electrically connected to the timing controller, the first memory, the second memory and the driver chip respectively, and is configured to supply power to the timing controller, the first memory, the second memory and the driver chip.

[0030] Secondly, embodiments of this application provide a driving method for a display device, applied to driving the display device as described above, the method comprising:

[0031] The timing controller receives an initialization command and performs initialization;

[0032] The timing controller receives the output command and outputs the shift register signal;

[0033] The detection unit detects whether the driver chip receives the shift register signal;

[0034] When the detection unit detects the shift register signal, the detection unit controls the display control chip to output the power signal;

[0035] If the detection unit fails to detect the shift register signal, the detection unit controls the display control chip to stop outputting the power signal.

[0036] In at least one embodiment of this application, when the detection unit fails to detect the shift register signal, the step of the detection unit controlling the display control chip to stop outputting the power signal includes:

[0037] The detection unit triggers the protection unit, and the protection unit transmits a protection signal to the enable signal input terminal. The protection signal is configured to control the display control chip to stop outputting the power signal.

[0038] When the detection unit detects the shift register signal, the step of the detection unit controlling the display control chip to output the power signal includes:

[0039] The detection unit stops triggering the protection unit, the protection unit stops outputting the protection signal, and the display control chip continues to output the power signal.

[0040] In at least one embodiment of this application, after the detection unit triggers the protection unit when the detection unit fails to detect the shift register signal, and the protection unit transmits a protection signal to the enable signal input terminal, and the protection signal is configured to control the display control chip to stop outputting the power signal, the method further includes:

[0041] Return to the execution state where the timing controller receives the initialization command and performs initialization;

[0042] After the detection unit detects the shift register signal, the detection unit stops triggering the protection unit, the protection unit stops outputting the protection signal, and the display control chip continues to output the power signal, the method further includes:

[0043] The detection unit then returns to detect whether the driver chip has received the shift register signal.

[0044] Embodiments of this application provide a display device and a driving method thereof. The display device includes: a display panel, at least two driving chips, and a circuit board. The at least two driving chips are electrically connected to the display panel, and at least one of the driving chips includes a detection unit. The plurality of driving chips are electrically connected to the circuit board, and the circuit board includes a timing controller. The timing controller includes a plurality of shift register signal output terminals, each of which is configured to output a shift register signal. The detection unit of one of the driving chips is electrically connected to at least one of the shift register signal output terminals, and the detection unit is configured to detect whether the timing controller can output the shift register signal normally.

[0045] In the embodiments of this application, by setting a detection unit in the driver chip, since the detection unit can detect whether the timing controller can output the shift register signal normally, it is possible to determine and detect whether there is a communication connection or signal transmission abnormality between the timing controller and the driver chip, thereby improving the detection capability of the display device and facilitating the repair of abnormal problems.

[0046] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A schematic diagram of a driving architecture for a display device in a related art provided for embodiments of this application;

[0049] Figure 2 A simplified structural diagram of a display device provided for an embodiment of this application;

[0050] Figures 3-6 A schematic diagram of the driving architecture of four display devices provided for embodiments of this application;

[0051] Figure 7 A schematic diagram illustrating the connection relationship between the signal conversion module and the shift register module provided in an embodiment of this application;

[0052] Figure 8 A schematic diagram of the structure of a driver chip provided for an embodiment of this application;

[0053] Figure 9 A driving method for a display device provided for an embodiment of this application is illustrated in the diagram.

[0054] Figure 10 A schematic diagram of a driving architecture for a touch display device provided for an embodiment of this application;

[0055] Figure 11 A flowchart of a driving method for a display device provided in an embodiment of this application. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0057] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0058] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0059] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0060] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0061] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of said value.

[0062] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0063] The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0064] With the continuous development of AMOLED, flexible displays will be the development trend in the next few years, and the development of new technologies also brings new challenges. Currently, most medium and large-size systems use a single timing controller (TCON) paired with multiple driver chips (source ICs), such as... Figure 1 As shown, the timing controller (TCON) provides shift register signals (GOA signals) and video signals (ISP signals), the power management chip (PMIC) powers the driver chip, and the display control chip (ELIC) powers the display panel. The entire system has complex timing and communication, therefore, the hardware design needs to consider many influencing factors and the timing coordination between the various driver modules. During product manufacturing, a power supply protection device protects the display panel to prevent damage to the screen due to abnormal power supply. Overcurrent, overpower, or overvoltage events will trigger the power supply protection mechanism, automatically powering down the device to protect the product.

[0065] However, currently there is no way to detect other hardware or signal transmission abnormalities besides power supply abnormalities, which can lead to display abnormalities or screen burn-in.

[0066] Based on this, embodiments of this application provide a display device, combined with Figure 2 and Figure 3 As shown, or in combination as in 2 and Figure 4 As shown, the display device includes:

[0067] Display panel (not drawn);

[0068] At least two driver chips 2, also known as source driver chips (Source ICs), are electrically connected to the display panel. At least one driver chip 2 includes, for example, Figure 8 The detection unit 21 shown;

[0069] The circuit board PCBA has multiple driver chips 2 that are electrically connected to the circuit board PCBA. The circuit board PCBA includes a timing controller TCON.

[0070] The timing controller TCON includes multiple shift register signal output terminals (not shown), each of which is configured to output a shift register signal (also known as a GOA signal); a detection unit 21 is electrically connected to at least one shift register signal output terminal, and the detection unit 21 is configured to detect whether the timing controller TCON can output the shift register signal normally.

[0071] It should be noted that, for example, in the accompanying drawings provided in the embodiments of this application, Figure 2 , Figure 3 and Figure 4 In the diagram, only one Connector is shown. In actual applications, the location where the Connector is drawn can include multiple Connectors. This is a simplification for the sake of clarity in the diagram. The specific number of Connectors can be increased according to the actual situation.

[0072] In addition, Figure 3 , Figure 4 and Figure 10 For simplicity, only one specific connection method between the driver chip 2 and the circuit board PCBA is shown in the examples. Figure 6 In the case of the driving architecture shown, other driving chips 2 can also be electrically connected to the circuit board PCBA in a similar manner, which will not be elaborated here. Figure 6 For related information, please refer to the following text.

[0073] For example, the above-mentioned display panel can be an LCD (Liquid Crystal Display) display panel, wherein the LCD display panel can include TN (Twisted Nematic), VA (Vertical Alignment), IPS (In-Plane Switching), or ADS (Advanced Super Dimension Switch) type liquid crystal display panels.

[0074] For example, the display panel described above can be an OLED (Organic Light-Emitting Diode) display panel, such as an AMOLED (Active-Matrix Organic Light-Emitting Diode) display panel. This specification uses an AMOLED display panel as an example for illustration.

[0075] In an exemplary embodiment, the display panel can be a touch display panel. In this case, the driver chip 2 can be electrically connected to the data lines and touch lines in the display panel, and is used to provide display driving signals to the data lines and touch driving signals to the touch lines.

[0076] For example, the driver chip 2 mentioned above can be an SRIC (Source / Read-out IC) type driver chip; or, the driver chip 2 mentioned above can be a TDDIC (Touch with Display Driver IC) type driver chip; or, the driver chip 2 mentioned above can be an LTDI IC (Large Touch with Display Driver IC) type driver chip; wherein, the TDDIC chip integrates the touch chip and the display chip into a single chip, and the LTDI IC is a new technology developed on the basis of TDDIC for use in large-size display panels to meet the needs of large screens.

[0077] At least one driver chip 2 includes, for example: Figure 8 The detection unit 21 shown includes, but is not limited to, the following:

[0078] First, among all driver chips 2, only one driver chip 2 includes, for example... Figure 8 The detection unit 21 shown;

[0079] Second, some driver chips 2 include, for example Figure 8 The detection unit 21 shown; some driver chips 2 do not include, for example Figure 8 The detection unit 21 shown;

[0080] Third, all driver chips 2 include, for example Figure 8 The detection unit 21 shown.

[0081] It should be noted that, for example, in the accompanying drawings provided in the embodiments of this application, Figure 2 As shown in the figure, the COG package type of the driver chip 2 is used as an example for drawing and explanation. This does not mean that the package type of the driver chip 2 is limited. It can also be a COF or COP package type.

[0082] Among them, COF is also known as Chip On Flex or Chip On Film; COG (Chip On Glass) refers to the driver chip 2 being directly bonded to the glass substrate of the display panel; COP (Chip On Plastic) refers to the driver chip 2 being bonded to the flexible material of the display panel. For a detailed introduction to the three technologies of COF, COG and COP, please refer to the relevant technical descriptions, which will not be elaborated here.

[0083] In an exemplary embodiment, such as Figure 3 and Figure 4As shown, the function of the Timer Control Register (TCON) is to process the LVDS or EDP type video signals (including at least one of the three types of signals: RGB data signals, clock signals, and control signals) sent from the system chip SOC on the system motherboard and convert them into video signals (such as ISP type signals) that can drive the display panel.

[0084] The ISP (Image Signal Processing) mainly processes the output signal from the front end to match different display panel models. It can be understood that the timing controller TCON processes and converts the video signal transmitted from the system chip SOC to obtain a video signal (ISP signal) that can be recognized by the driver chip 2, and then transmits it to the display panel through the driver chip 2 to achieve normal image display.

[0085] When the driver chip 2 receives the video signal (ISP signal), the driver chip 2 can send a feedback signal (Lock signal) to the timing controller TCON to indicate that the driver chip 2 has successfully received the video signal (ISP signal).

[0086] like Figure 2 As shown, the display panel includes a first shift register module GOAL and a second shift register module GOAR located on both sides of the display area AA in the peripheral area BB.

[0087] In an exemplary embodiment, the shift register module GOA (Gate on Array) is a technology that integrates the gate driving circuit into the array substrate of the display panel, thereby eliminating the need for Gate IC design, reducing the bezels on the left and right sides of the display panel, improving the aesthetics of the display panel, and reducing costs.

[0088] The timing controller TCON can also generate shift register signals (such as GOA signals) and transmit them to the driver chip 2. The shift register signals (GOA signals) include, but are not limited to, multiple clock signals (CLK signals) and multiple frame synchronization signals (STV signals, STV0 signals).

[0089] Wherein, one detection unit 21 is electrically connected to at least one shift register signal output terminal, including but not limited to the following situations:

[0090] First, a detection unit 21 is electrically connected to a shift register signal output terminal;

[0091] At this point, it can be understood that each of the multiple driver chips 2 includes a detection unit 21. The number of detection units 21 is the same as the number of shift register signal output terminals. One detection unit 21 is used to detect whether one of the multiple shift register signal output terminals is outputting a shift register signal normally.

[0092] Second, one detection unit 21 is electrically connected to a portion of the shift register signal output terminal, and another detection unit 21 is electrically connected to a portion of the shift register signal output terminal; at this time, it can be understood that the detection unit 21 can detect whether the shift register signal output terminal electrically connected to it is outputting the shift register signal normally.

[0093] Third, one detection unit 21 is electrically connected to all shift register signal output terminals. That is, one detection unit 21 can detect whether all shift register signal output terminals are outputting shift register signals normally.

[0094] In the embodiments of this application, a detection unit 21 is electrically connected to at least one shift register signal output terminal. Thus, a detection unit 21 can detect whether at least one shift register signal output terminal electrically connected to it is outputting a shift register signal normally. This enables the determination and detection of whether there is a communication connection or signal transmission abnormality between the timing controller TCON and the driver chip 2, thereby improving the detection capability of the display device and facilitating the repair of abnormal problems.

[0095] In at least one embodiment of this application, the display device further includes:

[0096] The display control chip ELIC is electrically connected to the driver chip 2 and is configured to provide power signals (e.g., positive power signal ELVDD and negative power signal ELVSS) to the display panel through the driver chip 2.

[0097] When the detection unit 21 detects the shift register signal, the detection unit 21 is configured to control the display control chip ELIC to output a power signal;

[0098] If the detection unit 21 fails to detect the shift register signal, the detection unit 21 is configured to control the display control chip ELIC to stop outputting the power signal.

[0099] In an exemplary embodiment, the display control chip ELIC provides power signals (e.g., positive power signal ELVDD and negative power signal ELVSS) to the display panel through the driver chip 2. The positive power signal ELVDD can be electrically connected to the anode of the light-emitting device in the display panel, and the negative power signal ELVSS can be electrically connected to the cathode of the light-emitting device in the display panel.

[0100] In the embodiments of this application, when the detection unit 21 detects the shift register signal, the timing controller TCON in the circuit board PCBA transmits the shift register signal to the shift register module of the display panel through the driver chip 2, and the shift register signal drives the shift register module to start scanning line by line. At this time, the detection unit 21 controls the display control chip ELIC to output a power signal so that the light-emitting device in the corresponding area emits light, realizing the writing or refreshing of data line by line, and realizing the display of the screen.

[0101] It should be noted that if the detection unit 212 fails to detect the shift register signal, and the display control chip ELIC outputs a power signal (e.g., positive power signal ELVDD and negative power signal ELVSS), the power signal will be directly injected into the display panel. Since the shift register module does not receive the shift register signal, progressive scanning is not started. This can easily lead to screen burn-in during reliability testing, causing damage to the display panel. Therefore, in the embodiments of this application, by setting up the detection unit 21, and making the detection unit 21 control the display control chip ELIC to stop outputting power signals when the detection unit 21 fails to detect the shift register signal, the screen burn-in caused by the power signal being directly injected into the display panel is avoided, thereby preventing damage to the display panel.

[0102] In at least one embodiment of this application, the driver chip 2, which is provided with the detection unit 21, further includes, as follows: Figure 8 The protection unit 22 shown is electrically connected to the detection unit 21; the display control chip ELIC also includes an enable signal input terminal (not shown), and all protection units 22 are electrically connected to the enable signal input terminal; as shown Figure 5 and Figure 6 As shown, if the detection unit 21 fails to detect the shift register signal, the detection unit 21 is configured to trigger the protection unit 22. The protection unit 22 is configured to transmit a protection signal to the enable signal input terminal. The protection signal is configured to control the display control chip ELIC to stop outputting power signals (e.g., positive power signal ELVDD and negative power signal ELVSS).

[0103] In an exemplary embodiment, when the protection unit 22 is triggered, the protection signal is pulled low (e.g., the protection signal is a low-level signal). Since the protection unit 22 is electrically connected to the enable signal input terminal, the pulled-down protection signal is input to the enable signal input terminal, and controls the stop output of power signals (e.g., positive power signal ELVDD and negative power signal ELVSS), thereby preventing the power signal from being directly injected into the display panel during the reliability test and avoiding screen burn-in.

[0104] In at least one embodiment of this application, when the detection unit 21 detects a shift register signal, the protection unit 22 is configured to stop outputting a protection signal, and the display control chip ELIC is configured to maintain the output power signal (e.g., positive power signal ELVDD and negative power signal ELVSS).

[0105] In an exemplary embodiment, when the detection unit 21 detects the shift register signal, the protection unit 22 is not triggered. Although the protection unit 22 is electrically connected to the enable signal input terminal, the protection unit 22 does not output a signal and does not affect the output of the power signal, thereby allowing the power signal (e.g., the positive power signal ELVDD and the negative power signal ELVSS) to be output normally to the display panel. The display panel is scanned line by line under the drive of the shift register module to achieve normal display of the display screen.

[0106] In at least one embodiment of this application, the circuit board PCBA further includes, as follows: Figure 7 The first signal conversion module Level shifter1 and the second signal conversion module Level shifter2 shown are as follows: Figure 2 As shown, the display panel also includes a first shift register module GOAL and a second shift register module GOAR located on both sides of the display area AA;

[0107] like Figure 5 and Figure 6 As shown, the first signal conversion module Level shifter1 and the second signal conversion module Level shifter2 are electrically connected to at least one driver chip 2, the first signal conversion module Level shifter1 and the first shift register module GOAL are electrically connected, and the second signal conversion module Level shifter2 and the second shift register module GOAR are electrically connected.

[0108] In an exemplary embodiment, the first signal conversion module Level shifter1 and the second signal conversion module Level shifter2 respectively perform level conversion on the shift register signals to generate shift register signals with voltage amplitudes suitable for direct use by the shift register module. The shift register signals may include: clock signals CLK IN1~10, frame synchronization signals (STV signal, STV0 signal), reset signals (RESET signal), initialization signals (Initial signal), etc. The number and specific types of shift register signals are related to the specific design of the GOA circuit in the shift register module and are not limited here; they can be determined according to the design requirements of the display panel.

[0109] The level shifter module is mainly used in multiple power supply multiple voltage (MSMV) technology. It usually does not have logic functions, but is used to convert signal levels between power supply areas with different voltage values.

[0110] The specific circuit structure of the first signal conversion module Level shifter1 and the second signal conversion module Level shifter2 is not limited here. Any level conversion module that can satisfy the function to be implemented in the embodiments of this application is within the protection scope of this application.

[0111] For example, the circuit structures of the first signal conversion module Level shifter1 and the second signal conversion module Level shifter2 can be set to be the same.

[0112] In the display device provided in the embodiments of this application, by setting two shift register modules, which are respectively located on both sides of the display area AA, it is possible to achieve simultaneous dual-side driving, which improves the voltage drop (IR Drop) problem caused by the wiring process in large-size display devices, improves the consistency of signal transmission in the display area AA, thereby improving the brightness uniformity in the display area AA and improving the display effect.

[0113] In at least one embodiment of this application, such as Figure 6 As shown, each driver chip 2 includes a detection unit 21 and a protection unit 22, and a shift register signal output terminal is electrically connected to the detection unit 21 of a driver chip 2.

[0114] It should be noted that, in Figure 6 For simplicity, only the signal transmission of the interface electrically connected to the detection unit 21 and the protection unit 22 is shown in each driver chip 1 as an illustration, and the detection unit 21 and the protection unit 22 are not shown.

[0115] In the embodiments of this application, such as Figure 6 As shown, by setting a detection unit 21 and a protection unit 22 in each driver chip 2, a shift register signal output terminal is electrically connected to a detection unit 21 of a driver chip 2. In this way, a detection unit 21 can detect a shift register signal output from a shift register signal output terminal of a timing controller TCON.

[0116] For example, such as Figure 6As shown, the display device includes four driver chips 2. The timing controller TCON outputs four shift register signals. One shift register signal output terminal is electrically connected to a detection unit 21 of one driver chip 2. Each driver chip 2 receives a different shift register signal, and each detection unit 21 detects a different shift register signal (the four detection units 21 receive shift register signals GOA-1, GOA-2, GOA-3, and GOA-4, respectively). Each driver chip with a detection unit 21 is equipped with a protection unit 22. When at least one of the four detection units 21 detects that its electrically connected shift register signal output terminal does not output a shift register signal normally (or does not receive a shift register signal), the detection unit 21 triggers the protection unit 22 electrically connected to it. Since each protection unit 22 is electrically connected to an enable signal input terminal, when any protection unit 22 outputs a protection signal, the protection signal can control the stop of output power signals (e.g., positive power signal ELVDD and negative power signal ELVSS). In practical applications, when at least one of the multiple shift register signals is abnormal or is not transmitted to the driver chip 2, it can be detected by the detection unit 21 and trigger the protection unit 22 to stop outputting the power signal, thereby preventing the power signal from being directly injected into the display panel and avoiding screen burn-in.

[0117] In at least one embodiment of this application, each driver chip 2 is electrically connected to the first signal conversion module Levelshifter1 and the second signal conversion module Levelshifter2.

[0118] It can be understood that the first signal conversion module (Level shifter1) and the second signal conversion module (Level shifter2) need to receive all shift register signals output by the timing controller (TCON), perform level conversion, and then transmit them to the two shift register modules (GOAL and GOAR). Specifically, the first signal conversion module (Level shifter1) needs to receive all shift register signals output by the timing controller (TCON), perform level conversion, and then transmit them to the first shift register module (GOAL). The second signal conversion module (Level shifter2) needs to receive all shift register signals output by the timing controller (TCON), perform level conversion, and then transmit them to the second shift register module (GOAR). Figure 6As shown, since one shift register signal output terminal is electrically connected to the detection unit 21 of one driver chip 2, by setting each driver chip 2 to be electrically connected to the first signal conversion module Level shifter1 and the second signal conversion module Level shifter2, it can be ensured that the first signal conversion module Level shifter1 and the second signal conversion module Level shifter2 receive all the shift register signals output by the timing controller TCON, thereby ensuring the normal driving of the two shift register modules and the normal display of the display device.

[0119] In at least one embodiment of this application, such as Figure 6 As shown, each driver chip 2 includes two general purpose input / output ports (GPIO ports). One GPIO port is electrically connected to the detection unit 21 and the timing controller TCON, respectively, and the other GPIO port is electrically connected to the protection unit 22 and the enable signal input terminal, respectively.

[0120] GPIO (General-purpose input / output) is used for inputting and outputting electrical signals in a circuit. It can be used as both an input port and an output port to facilitate the control of circuit components.

[0121] In at least one embodiment of this application, such as Figure 5 As shown, the multiple driver chips 2 include a master driver chip (Master IC), which includes, as shown in the figure... Figure 8 The detection unit 21 and protection unit 22 shown in the diagram have all shift register signal output terminals electrically connected to the detection unit 21 of the master driver chip Master IC.

[0122] In an exemplary embodiment, the detection unit 21 in the master driver chip Master IC can detect whether each shift register signal output terminal of the timing controller TCON outputs its corresponding shift register signal normally.

[0123] In an exemplary embodiment, if the detection unit 21 in the master driver chip Master IC detects shift register signals output from each shift register signal output terminal of the timing controller TCON simultaneously, the detection unit 21 does not trigger the protection unit 22, and the protection unit 22 does not output a signal; if the detection unit 21 in the master driver chip Master IC detects that no shift register signal is output from any one of the shift register signal output terminals of the timing controller TCON, then the protection unit 22 is triggered, the protection unit 22 outputs a protection signal to the enable signal input terminal, and controls the display driver chip EL IC not to output power signals (e.g., ELVDD and ELVSS signals).

[0124] In at least one embodiment of this application, such as Figure 5 As shown, since the Master IC can receive the signals output from all shift register signal output terminals of the timing controller TCON, the Master IC is electrically connected to the first signal conversion module Level shifter1 and the second signal conversion module Level shifter2 respectively.

[0125] The first signal conversion module, Level shifter1, receives all shift register signals output from the timing controller TCON, performs level conversion, and then transmits them to the first shift register module, GOAL. The second signal conversion module, Level shifter2, receives all shift register signals output from the timing controller TCON, performs level conversion, and then transmits them to the second shift register module, GOAR. This ensures that both Level shifter1 and Level shifter2 receive all shift register signals output from the timing controller TCON, thereby ensuring that the two shift register modules achieve bilateral driving and ensuring the normal display of the display device.

[0126] In an exemplary embodiment, the number of GPIO ports on the master driver chip (Master IC) is greater than or equal to the sum of the number of all shift register signal inputs and protection signal outputs.

[0127] Specifically, such as Figure 5 As shown, the Master IC has five GPIO ports, including four ports for receiving shift register signals and one port for outputting protection signals.

[0128] In at least one embodiment of this application, such as Figure 3 As shown, the display control chip EL IC is integrated on the circuit board PCBA;

[0129] Or, such as Figure 4 As shown, the display device also includes a system-side motherboard (not shown), and the display control chip EL IC is integrated on the system-side motherboard. Among them, in Figure 4 In the process, the protection signal output by the protection unit 22 of the driver chip 2 is transmitted through the connector to the enable signal input terminal of the display control chip EL IC located on the system motherboard, and the power signal (such as ELVDD signal and ELVSS signal) output by the display control chip EL IC is transmitted to the driver chip 2 through the connector.

[0130] In at least one embodiment of this application, such as Figure 10 As shown, the PCBA circuit board also includes a touch control chip TIC, which is electrically connected to the timing controller TCON, the system motherboard, and the display panel.

[0131] Specifically, the touch control chip TIC is electrically connected to the system motherboard through two ports, I2C and SPI. The touch control chip TIC is electrically connected to the timing controller TCON through the Sync port. The touch control chip TIC is directly connected to the touch lines (such as RX and TX lines) in the display panel through traces to receive touch signals transmitted by the touch lines.

[0132] The I2C (Inter-Integrated Circuit) bus is a simple, bidirectional, two-wire synchronous serial bus developed by Philips. An I2C port is a port matched with the I2C bus. SPI stands for Serial Peripheral Interface, a high-speed, full-duplex, synchronous communication bus that uses only four pins on the chip, saving pins. Detailed descriptions of I2C and SPI ports can be found in relevant technical documentation and will not be repeated here.

[0133] For example, such as Figure 10 As shown, the touch control chip TIC can also receive power voltage signals (such as AVDD) from external power supply devices.

[0134] In at least one embodiment of this application, the display device further includes a system-side motherboard, such as... Figure 3 , Figure 4 and Figure 10 As shown, the PCBA also includes a voltage conversion circuit Buck, a power management chip PMIC, a first memory (e.g., Flash1) and a second memory (e.g., Flash1).

[0135] The timing controller TCON, the voltage conversion circuit Buck, and the first memory (e.g., Flash1) are electrically connected to the system motherboard, and the first memory (e.g., Flash1), the second memory (e.g., Flash2), and the power management chip PMIC are electrically connected to the timing controller TCON.

[0136] The voltage conversion circuit Buck is electrically connected to the power management chip PMIC and the timing controller TCON respectively; the power management chip PMIC is electrically connected to the timing controller TCON, the first memory (e.g., Flash1), the second memory (e.g., Flash2) and the driver chip 2 respectively, and is configured to supply power to the timing controller TCON, the first memory (e.g., Flash1), the second memory (e.g., Flash2) and the driver chip 2.

[0137] Specifically, with Figure 3 Taking the driver architecture shown as an example, the system-side motherboard and the timing controller TCON include an SPIM interface, two I2C interfaces, and one MIPI interface. SPIM (External SPI FLASH memory interface) is an external SPI-type flash memory interface; MIPI (Mobile Industry Processor Interface) is an open standard and specification for mobile application processors initiated by the MIPI Alliance. The SPIM interface is used to transmit video signals from the system-side motherboard to the timing controller TCON. One I2C interface is used to transmit signals controlling the output voltage of the display control chip ELIC, and the other I2C interface is used to transmit signals controlling the output voltage of the power management chip PMIC. The MIPI interface is used to transmit command signals to control the timing controller TCON to enter the initialization state or start outputting the GOA signal.

[0138] An I2C interface is also provided between the timing controller TCON and the display driver chip ELIC, which is used to transmit the signal from the timing controller TCON to control the output voltage of the display control chip ELIC.

[0139] An I2C interface is also provided between the timing controller TCON and the power management chip PMIC to transmit the signal from the timing controller TCON to control the output voltage of the power management chip PMIC.

[0140] The timing controller TCON and the driver chip 2 include an ISP interface, a Lock interface, and at least one interface for transmitting GOA signals. The ISP interface is used to transmit video or image signals, and the Lock interface is used to transmit feedback signals.

[0141] The first memory (e.g., Flash1) is electrically connected to the timing controller TCON via the SPI1 interface, and the second memory (e.g., Flash2) is electrically connected to the timing controller TCON via the SPI2 interface. The SPI1 and SPI2 interfaces are used to download the Bin file from the memory, so as to complete the wake-up and initialization of the timing controller TCON after receiving the corresponding instruction signal.

[0142] The voltage conversion circuit Buck is electrically connected to the power supply equipment via the connector to supply power to the circuit board PCBA. The voltage conversion circuit Buck converts the voltage provided by the power supply equipment into a voltage that matches the usage requirements of other devices. For example, the voltage conversion circuit Buck provides the timing controller TCON with a voltage signal VCORE that it requires.

[0143] The power management chip (PMIC) is electrically connected to the power supply equipment via a connector to supply power to the circuit board (PCBA). The PMIC provides voltage signals VIO to the first memory, the second memory, and the timing controller (TCON), and provides high-level voltage signals VGL, low-level voltage signals VGL, power supply voltage signal AVDD, two gamma voltage signals VGSP and VGMP, a first initialization signal Vinit1, and a second initialization signal Vinit2 to the driver chip 2.

[0144] The display device described in the embodiments of this application has a certain protective effect against hardware anomalies in the reliability verification environment. In particular, when the production line is in the process of mass production, the use of this solution can also greatly reduce the probability of the display panel being burned, avoid the waste of materials, and have considerable value for cost saving and production line yield improvement.

[0145] Embodiments of this application provide a driving method for a display device, applied to driving a display device as described above, in conjunction with... Figure 9 and Figure 11 As shown, the method includes:

[0146] S801, the timing controller TCON receives the initialization command and performs initialization (Sleep out);

[0147] Before this step, power on the display device so that the timing controller TCON can start running;

[0148] For example, the MIPI interface is used to transmit command signals to control the timing controller TCON to enter the initialization state.

[0149] S802, the timing controller TCON receives the output command and outputs the shift register signal (Display on);

[0150] For example, the MIPI interface is used to transmit command signals to control the timing controller TCON to start outputting the GOA signal.

[0151] S803, Detection unit 21 detects whether the driver chip receives a shift register signal;

[0152] In practical applications, after the timing controller TCON receives the output command and outputs the shift register signal (Displayon), after a preset delay, the detection unit 21 begins to detect whether the driver chip has received the shift register signal.

[0153] The preset time can be less than or equal to 1 to 2 seconds.

[0154] S804. When the detection unit 21 detects the shift register signal, the detection unit 21 controls the display control chip ELIC to output a power signal (e.g., positive power signal ELVDD and negative power signal ELVSS).

[0155] In an exemplary embodiment, the display control chip ELIC provides power signals (e.g., positive power signal ELVDD and negative power signal ELVSS) to the display panel through the driver chip 2. The positive power signal ELVDD can be electrically connected to the anode of the light-emitting device in the display panel, and the negative power signal ELVSS can be electrically connected to the cathode of the light-emitting device in the display panel.

[0156] In the embodiments of this application, when the detection unit 21 detects the shift register signal, the timing controller TCON in the circuit board PCBA transmits the shift register signal to the shift register module of the display panel through the driver chip 2, and the shift register signal drives the shift register module to start scanning line by line. At this time, the detection unit 21 controls the display control chip ELIC to output a power signal so that the light-emitting device in the corresponding area emits light, realizing the writing or refreshing of data line by line, and realizing the display of the screen.

[0157] S805. If the detection unit 21 fails to detect the shift register signal, the detection unit 21 controls the display control chip ELIC to stop outputting power signals (e.g., positive power signal ELVDD and negative power signal ELVSS).

[0158] It should be noted that if the detection unit 212 fails to detect the shift register signal, and the display control chip ELIC outputs a power signal (e.g., positive power signal ELVDD and negative power signal ELVSS), the power signal will be directly injected into the display panel. Since the shift register module does not receive the shift register signal, progressive scanning is not started. This can easily lead to screen burn-in during reliability testing, causing damage to the display panel. Therefore, in the embodiments of this application, by setting up the detection unit 21, and making the detection unit 21 control the display control chip ELIC to stop outputting power signals when the detection unit 21 fails to detect the shift register signal, the screen burn-in caused by the power signal being directly injected into the display panel is avoided, thereby preventing damage to the display panel.

[0159] In at least one embodiment of this application, step S805, where the detection unit controls the display control chip to stop outputting the power signal when the detection unit fails to detect the shift register signal, specifically includes:

[0160] S8051, the detection unit 21 triggers the protection unit 22, the protection unit 22 transmits a protection signal to the enable signal input terminal, and the protection signal is configured to control the display control chip ELIC to stop outputting the power signal;

[0161] In an exemplary embodiment, when the protection unit 22 is triggered, the protection signal is pulled low (e.g., the protection signal is a low-level signal). Since the protection unit 22 is electrically connected to the enable signal input terminal, the pulled-down protection signal is input to the enable signal input terminal, and controls the stop output of power signals (e.g., positive power signal ELVDD and negative power signal ELVSS), thereby preventing the power signal from being directly injected into the display panel during the reliability test and avoiding screen burn-in.

[0162] In at least one embodiment of this application, step S804, where the detection unit 21 detects a shift register signal, specifically includes the detection unit 21 controlling the display control chip ELIC to output a power signal, which includes:

[0163] S8041, the detection unit 21 stops triggering the protection unit 22, the protection unit 22 stops outputting the protection signal, and the display control chip ELIC maintains the output power signal.

[0164] In an exemplary embodiment, when the detection unit 21 detects the shift register signal, the protection unit 22 is not triggered. Although the protection unit 22 is electrically connected to the enable signal input terminal, the protection unit 22 does not output a signal and does not affect the output of the power signal, thereby allowing the power signal (e.g., the positive power signal ELVDD and the negative power signal ELVSS) to be output normally to the display panel. The display panel is scanned line by line under the drive of the shift register module to achieve normal display of the display screen.

[0165] In at least one embodiment of this application, combined with Figure 9 and Figure 11 As shown, if the detection unit 21 fails to detect the shift register signal, the detection unit 21 triggers the protection unit 22, and the protection unit 22 transmits a protection signal to the enable signal input terminal. After the protection signal is configured to control the display control chip ELIC to stop outputting the power signal, the method further includes:

[0166] S806, Return to the execution steps of receiving the initialization instruction from TCON and performing initialization;

[0167] When the detection unit 21 detects a shift register signal, the detection unit 21 stops triggering the protection unit 22, the protection unit 22 stops outputting the protection signal, and after the step of the display control chip ELIC maintaining the output power signal, the method further includes:

[0168] S807, return to the step of detecting whether the driver chip 2 has received a shift register signal.

[0169] In the embodiments of this application, if the detection unit 21 fails to detect the shift register signal, it returns to the step of receiving the initialization command from the timing controller TCON and performing initialization; if the detection unit 21 detects the shift register signal, it returns to the step of detecting whether the driver chip 2 receives the shift register signal. This enables the detection unit 21 to continuously detect whether the shift register signal is normally transmitted to the driver chip 2, continuously protecting the display device to prevent the power signal from directly entering the display panel and to avoid screen burn-in.

[0170] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display device, characterized in that, include: Display panel; At least two driver chips, both of which are electrically connected to the display panel, and at least one of the driver chips includes a detection unit; The circuit board includes multiple driver chips electrically connected to it, and the circuit board includes a timing controller. The timing controller includes multiple shift register signal output terminals, each of which is configured to output a shift register signal; a detection unit of the driver chip is electrically connected to at least one of the shift register signal output terminals, and the detection unit is configured to detect whether the timing controller can output the shift register signal normally. The display device further includes: A display control chip, which is electrically connected to the driver chip, is configured to provide a power signal to the display panel through the driver chip; When the detection unit detects the shift register signal, the detection unit is configured to control the display control chip to output the power signal; If the detection unit fails to detect the shift register signal, the detection unit is configured to control the display control chip to stop outputting the power signal.

2. The display device according to claim 1, characterized in that, The driver chip equipped with the detection unit further includes a protection unit, which is electrically connected to the detection unit; the display control chip further includes an enable signal input terminal, and all the protection units are electrically connected to the enable signal input terminal. If the detection unit fails to detect the shift register signal, the detection unit is configured to trigger the protection unit, which is configured to transmit a protection signal to the enable signal input terminal. The protection signal is configured to control the display control chip to stop outputting the power signal.

3. The display device according to claim 2, characterized in that, When the detection unit detects the shift register signal, the protection unit is configured to stop outputting the protection signal, and the display control chip is configured to maintain the output of the power signal.

4. The display device according to claim 3, characterized in that, The circuit board further includes a first signal conversion module and a second signal conversion module, and the display panel further includes a first shift register module and a second shift register module located on both sides of the display area; The first signal conversion module and the second signal conversion module are electrically connected to at least one of the driver chips, the first signal conversion module is electrically connected to the first shift register module, and the second signal conversion module is electrically connected to the second shift register module.

5. The display device according to claim 4, characterized in that, Each of the driver chips includes the detection unit and the protection unit, and one of the shift register signal output terminals is electrically connected to the detection unit of one of the driver chips.

6. The display device according to claim 5, characterized in that, Each of the driver chips includes two general purpose input / output ports, one of which is electrically connected to the detection unit and the timing controller, and the other is electrically connected to the protection unit and the enable signal input terminal.

7. The display device according to claim 5, characterized in that, Each of the driver chips is electrically connected to the first signal conversion module and the second signal conversion module.

8. The display device according to claim 4, characterized in that, The plurality of driver chips include a main driver chip, which includes the detection unit and the protection unit. All the shift register signal output terminals are electrically connected to the detection unit of the main driver chip.

9. The display device according to claim 8, characterized in that, The main driver chip is electrically connected to the first signal conversion module and the second signal conversion module, respectively.

10. The display device according to any one of claims 2-7, characterized in that, The display control chip is integrated on the circuit board; Alternatively, the display device may further include a system motherboard, on which the display control chip is integrated.

11. The display device according to claim 10, characterized in that, The circuit board also includes a touch control chip, which is electrically connected to the timing controller, the system motherboard and the display panel.

12. The display device according to claim 10, characterized in that, The display device also includes a system motherboard, and the circuit board also includes a voltage conversion circuit, a power management chip, a first memory, and a second memory. The timing controller, the voltage conversion circuit, and the first memory are electrically connected to the system motherboard, and the first memory, the second memory, and the power management chip are electrically connected to the timing controller. The voltage conversion circuit is electrically connected to the power management chip and the timing controller respectively; the power management chip is electrically connected to the timing controller, the first memory, the second memory and the driver chip respectively, and is configured to supply power to the timing controller, the first memory, the second memory and the driver chip.

13. A driving method for a display device, characterized in that, The method, applied to driving a display device as described in any one of claims 2-12, comprises: The timing controller receives an initialization command and performs initialization; The timing controller receives the output command and outputs the shift register signal; The detection unit detects whether the driver chip receives the shift register signal; When the detection unit detects the shift register signal, the detection unit controls the display control chip to output the power signal; If the detection unit fails to detect the shift register signal, the detection unit controls the display control chip to stop outputting the power signal.

14. The driving method according to claim 13, characterized in that, If the detection unit fails to detect the shift register signal, the step of the detection unit controlling the display control chip to stop outputting the power signal includes: The detection unit triggers the protection unit, and the protection unit transmits a protection signal to the enable signal input terminal. The protection signal is configured to control the display control chip to stop outputting the power signal. When the detection unit detects the shift register signal, the step of the detection unit controlling the display control chip to output the power signal includes: The detection unit stops triggering the protection unit, the protection unit stops outputting the protection signal, and the display control chip continues to output the power signal.

15. The driving method according to claim 14, characterized in that, If the detection unit fails to detect the shift register signal, the detection unit triggers the protection unit, and the protection unit transmits a protection signal to the enable signal input terminal. After the protection signal is configured to control the display control chip to stop outputting the power signal, the method further includes: Return to the execution state where the timing controller receives the initialization command and performs initialization; After the detection unit detects the shift register signal, the detection unit stops triggering the protection unit, the protection unit stops outputting the protection signal, and the display control chip continues to output the power signal, the method further includes: The detection unit then returns to detect whether the driver chip has received the shift register signal.

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