Driving method of display panel, display panel and display device

Abstract

Embodiments of the present application provide a display panel driving method, a display panel and a display device. The display panel comprises a multiplexer, a data terminal, a data line and a sub-pixel, the input end of the multiplexer is coupled with the data terminal; the multiplexer comprises at least two switches, one switch is connected with one data line, the data line extends along a first direction and is coupled with a plurality of sub-pixels, the sub-pixel comprises a first sub-pixel, a second sub-pixel and a third sub-pixel with different colors; the driving method comprises: controlling the data terminal to provide a data signal to the input end of the multiplexer, and controlling the corresponding switch to open for a preset time length to write the data signal to the data line; the data signal comprises a first data signal corresponding to the first sub-pixel; wherein the opening time length of the corresponding switch in the stage of providing the first data signal to the input end of the multiplexer is the longest. The present application can reduce the dark state voltage of the display panel and improve the line crosstalk between the data line and other signal lines.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a driving method for a display panel, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess self-emissive properties, and their application in the display field enables display panels to be thin, light, bright, low-power, fast-response, high-resolution, flexible, and highly efficient, meeting consumers' new demands for display technology. Currently, however, crosstalk issues exist in display panels, affecting display performance. Summary of the Invention

[0003] This invention provides a driving method for a display panel, a display panel, and a display device to improve the crosstalk problem in the prior art and enhance the display effect.

[0004] In a first aspect, embodiments of the present invention provide a driving method for a display panel. The display panel includes a multiplexer, data terminals, data lines, and sub-pixels. The input terminal of the multiplexer is coupled to the data terminals, and the output terminal of the multiplexer is coupled to n data lines, where n is a positive integer and n≥2. The multiplexer includes n switches connected between the input and output terminals of the multiplexer. Each switch is connected to one data line. The data lines extend along a first direction and are coupled to multiple sub-pixels. The sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel with different colors. The driving method includes:

[0005] The control data terminal provides data signals to the input of the multiplexer and controls the corresponding switch to open for a preset time to write the data signals to the data line; the data signals include a first data signal corresponding to the first sub-pixel, a second data signal corresponding to the second sub-pixel, and a third data signal corresponding to the third sub-pixel; among them, the stage of providing the first data signal to the input of the multiplexer has the longest opening time of the corresponding switch.

[0006] Secondly, based on the same inventive concept, embodiments of the present invention provide a display panel that is driven by the driving method provided in any embodiment of the present invention.

[0007] Thirdly, based on the same inventive concept, embodiments of the present invention provide a display device, the display device including a display panel, the display panel being driven by a driving method provided in any embodiment of the present invention.

[0008] The driving method, display panel, and display device provided in this embodiment of the invention have the following beneficial effects: When driving the display panel to operate, the opening duration of the corresponding switch during the stage of controlling the supply of a first data signal to the input terminal of the multiplexer is the longest. The first data signal corresponds to the first sub-pixel. A longer opening duration of the switch allows for more thorough charging of the data line, and the voltage value charged to the data line can be closer to the expected voltage of the first data signal, thereby reducing the voltage required for the first sub-pixel to reach a dark state. When the luminous efficiency of the first sub-pixel among the three color sub-pixels is the highest, the dark state voltage of the display panel depends on the dark state voltage of the first sub-pixel. Therefore, the driving method provided in this embodiment of the invention can reduce the dark state voltage of the display panel. After the dark state voltage of the display panel is reduced, when the sub-pixel driven by the data line is switched from grayscale to black, the voltage jump amplitude on the data line becomes smaller, and the voltage fluctuations of other signal lines, such as the power line, caused by data line coupling become smaller. Therefore, when the switch connected to the data line is closed and the data line is in a floating state, the voltage fluctuations of the power line, in turn, have a smaller impact on the voltage on the data line, thereby improving crosstalk between signal lines and enhancing the display effect. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0011] Figure 2 A flowchart of a display panel driving method provided in an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram of the control signal timing of a switch in an embodiment of the present invention;

[0014] Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0015] Figure 6 for Figure 5 A timing diagram of a multiplexer in the embodiment;

[0016] Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0017] Figure 8 for Figure 7 A timing diagram of a multiplexer in the embodiment;

[0018] Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0019] Figure 10 for Figure 9 A timing diagram of a multiplexer in the embodiment;

[0020] Figure 11 A timing diagram for another display panel provided in an embodiment of the present invention;

[0021] Figure 12 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0024] In one existing technology, data lines are connected to data terminals via a multiplexer, with one multiplexer connecting at least two data lines. When a switch connected to the data line in the multiplexer is turned on, it connects the data terminal to the data line, allowing the data terminal to write data signals to the data line. When the switch is turned off, the data line is in a floating state. In this floating state, the voltage signal is easily affected by coupling, causing fluctuations. If a power line is also present in the display area, extending in the same direction as the data line, there is significant coupling between them. When a sub-pixel driven by the data line switches from grayscale to black (i.e., to 0 grayscale), the voltage jump on the data line causes a voltage jump on the power line, which in turn affects the voltage on the data line. When the switch is off and the data line is in a floating state, the voltage on the data line is easily coupled, producing fluctuations similar to those on the power line. This coupling between the data line and the power line is called crosstalk, which affects the data voltage and thus the display effect. The display panel also has scan lines that intersect with the data lines, and there is also a crosstalk problem between the scan lines and the data lines.

[0025] To address the problems existing in the prior art, this invention provides a driving method for a display panel, which differentiates the charging time of data signals corresponding to different color sub-pixels. The first sub-pixel influences the dark-state voltage in the display panel. Setting the charging time of the first data signal corresponding to the first sub-pixel to be the longest increases the voltage value of the first data signal written to the data line, ensuring that the first data signal on the data line reaches the expected voltage, thereby reducing the dark-state voltage of the display panel. Since all sub-pixels in the display panel use a uniform dark-state voltage, after the dark-state voltage is reduced, when the sub-pixel driven by the data line cuts from grayscale to black, the voltage jump amplitude on the data line becomes smaller. Consequently, the voltage fluctuations on other signal lines (such as power lines) caused by the data line decrease accordingly, and the influence of other signal lines on the voltage on the data line also decreases, thereby improving crosstalk between the data line and other signal lines.

[0026] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 1As shown, the display panel includes a multiplexer 10, data terminals 20, data lines 30, and sub-pixels 40. The input terminal of the multiplexer 10 is coupled to the data terminals 20, and the output terminal of the multiplexer 10 is coupled to n data lines 30, where n is a positive integer and n≥2. The multiplexer 10 includes n switches 11, which are connected between the input and output terminals of the multiplexer 10. Each switch 11 corresponds to one data line 30. Each switch 11 includes a transistor, and the type of transistor in the switch 11 is not limited. The data lines 30 extend along a first direction y and are coupled to multiple sub-pixels 40. Each sub-pixel 40 includes a first sub-pixel 41, a second sub-pixel 42, and a third sub-pixel 43, each with a different color. Each sub-pixel 40 includes a light-emitting device and a pixel circuit. The pixel circuit drives the light-emitting device to emit light, and the light-emitting device can be an organic light-emitting device. Figure 1 Taking n=4 as an example, the output of a multiplexer 10 is connected to four data lines 30. The number of switches 11 in the multiplexer 10 is the same as the number of data lines 30 connected to the multiplexer 10. Figure 1 The arrangement of the first sub-pixel 41, the second sub-pixel 42, and the third sub-pixel 43 is for illustrative purposes only and is not intended to limit the scope of the invention. Figure 1 The switch 11 is illustrated using a p-type transistor, and the switch 11 in the following related embodiments of the present invention is also illustrated using only a p-type transistor. Optionally, the switch 11 may also be an n-type transistor.

[0027] Data terminal 20 is used to provide data signals to data line 30 through multiplexer 10. When the switch 11 connected to data line 30 is in the open state, data terminal 20 is connected to data line 30 and charges data line 30 by writing data signals. The open duration of switch 11 is equal to the charging duration of data line 30. During display driving, n switches 11 in one multiplexer 10 are opened in a time-sharing manner to charge n data lines 30 in a time-sharing manner.

[0028] Figure 2 This is a flowchart of a display panel driving method provided in an embodiment of the present invention, as shown below. Figure 2As shown, the driving method includes step S101: controlling the data terminal 20 to provide a data signal to the input terminal of the multiplexer 10, and controlling the corresponding switch 11 to open for a preset duration to write the data signal to the data line 30; the data signal includes a first data signal corresponding to the first sub-pixel 41, a second data signal corresponding to the second sub-pixel 42, and a third data signal corresponding to the third sub-pixel 43; wherein, the opening duration of the corresponding switch 11 is longest during the stage of providing the first data signal to the input terminal of the multiplexer 10. The preset duration refers to the time length for the switch 11 to open once in order to drive the display panel to display. The opening duration of the corresponding switch 11 during the stage of the data terminal 20 writing the first data signal to the data line 30 is t. 01 The stage of writing the second data signal onto data line 30, and the opening duration of the corresponding switch 11 are t. 02 The stage of writing the third data signal onto data line 30, and the opening duration of the corresponding switch 11 are t. 03 , t 01 Greater than t 02 , and t 01 Greater than t 03 In other words, the switch 11 connected to the data line 30 is turned on for the longest time when the data signal required to write the first sub-pixel 41 to the data line 30 is written.

[0029] It is understandable that when driving the display panel to display, the charging time for each data line 30 is limited, and the actual voltage value written to the data line 30 will be less than the preset data voltage. The longer the switch 11 is on, the more fully the data line 30 is charged, and the closer the voltage value of the data signal written to the data line 30 is to the preset data voltage. In this embodiment of the invention, the on-time of the corresponding switch 11 is set to be the longest during the stage of writing the first data signal, thus ensuring that the data voltage required for the first sub-pixel 41 to emit light is written more fully.

[0030] The first sub-pixel 41, the second sub-pixel 42, and the third sub-pixel 43 in the display panel emit different colors and have different luminous efficiencies. The higher the luminous efficiency of sub-pixel 40, the greater the voltage required for it to display in a dark state. Since a unified dark state voltage needs to be set for the three color sub-pixels 40 in the display panel, the dark state voltage largely depends on the dark state voltage of the sub-pixel 40 with the highest luminous efficiency. In this embodiment, the first sub-pixel 41 has the highest luminous efficiency among the three color sub-pixels, so the dark state voltage of the display panel depends on the voltage required for the first sub-pixel 41 to display in a dark state. In some embodiments, the green sub-pixel requires the highest voltage to display in a dark state among the red, green, and blue sub-pixels, so the dark state voltage of the green sub-pixel is set as the dark state voltage of the display panel. Here, the first sub-pixel 41 is a green sub-pixel, and the second sub-pixel 42 and the third sub-pixel 43 are, respectively, a red sub-pixel and a blue sub-pixel.

[0031] The existing formula for capacitor charging and discharging time is: V t =V0+(V1-V0)*[1-exp(-t / RC)]. V t Here, V0 is the initial voltage, V1 is the termination voltage (also known as the expected charging voltage), R is the resistance in the circuit, C is the capacitance, and t is the charging time. In this embodiment of the invention, the process of writing data signals to the data line 30 after the switch 11 is turned on can be considered as charging the line capacitor, thus the capacitor charging and discharging formula can be applied. Where V... t This can be considered as the voltage value of the data signal actually written onto data line 30, where V1 is the dark state voltage, V0 is the initial voltage on data line 30, and t is the charging time for writing the data signal onto data line 30. When charging data line 30, assume V... t If the charging time t remains constant, increasing the charging time t will decrease the dark state voltage V1. That is, increasing the charging time for writing data signals to data line 30 will correspondingly reduce the voltage required for the sub-pixel to display a dark state. In this embodiment of the invention, setting the on-time of the corresponding switch 11 to be the longest when providing the first data signal to the input of the multiplexer 10 will reduce the voltage required for the first sub-pixel 41 to reach a dark state.

[0032] This invention provides a driving method for a display panel, applied to a display panel where data terminals 20 charge data lines 30 via a multiplexer 10. The multiplexer 10 reduces the number of data terminals 20 in the display panel, thus reducing the number of pins in the display driver chip and lowering its manufacturing cost. During the stage of controlling the supply of a first data signal to the input of the multiplexer 10 while driving the display panel, the corresponding switch 11 has the longest on-time. Since the first data signal corresponds to the first sub-pixel 41, a longer on-time of switch 11 results in more thorough charging of the data line 30, and the voltage value charged to the data line 30 is closer to the expected voltage of the first data signal. This reduces the voltage required for the first sub-pixel 41 to reach a dark state. When the luminous efficiency of the first sub-pixel 41 is the highest among the three color sub-pixels, the dark-state voltage of the display panel depends on the dark-state voltage of the first sub-pixel 41. Therefore, the driving method provided in this invention can reduce the dark-state voltage of the display panel. Figure 1 As shown, the display panel also includes a power line 50 extending in the same direction as the data line 30. One power line 50 couples to multiple sub-pixels 40, and there is significant coupling between the data line 30 and the power line 50. It should be noted that, to distinguish between the data line 30 and the power line 50, Figure 1 The diagram only uses the power cable 50 as a thick black line and the data cable 30 as a thin line for illustration. Figure 1 The thickness of the center line is not intended to limit the invention. After the dark-state voltage of the display panel decreases, when the sub-pixel 40 driven by the data line 30 is switched from grayscale to black, the voltage jump amplitude on the data line 30 becomes smaller, and the voltage fluctuation on the power line 50 caused by the coupling of the data line 30 becomes smaller. Therefore, when the switch 11 connected to the data line 30 is closed and the data line 30 is in a floating state, the voltage fluctuation of the power line 50, in turn, has a smaller impact on the voltage on the data line 30, thereby improving the crosstalk between the data line 30 and the power line 50 and enhancing the display effect. The driving method provided by the embodiments of the present invention can improve the crosstalk between the data line 30 and other signal lines (such as power lines, scan lines, etc.) and enhance the display effect.

[0033] Furthermore, the driving method provided in this embodiment of the invention can reduce the dark-state voltage of the display panel, which in turn reduces the power supply voltage supplied by the display driver chip to the display panel, thereby reducing the power consumption of the display driver chip. On another front, the driving transistor in the pixel circuit is in a biased state for a long time, which can cause the threshold voltage of the driving transistor to drift. This threshold voltage drift leads to ghosting in the first frame during frame rate switching or screen switching. Dark-state voltage affects the amount of threshold voltage drift; reducing the dark-state voltage can improve the brightness of the first frame, thereby improving the ghosting problem. Furthermore, the longest charging time for the data line 30 when writing the first data signal results in more complete writing of the first data signal, leading to more accurate grayscale display of the first sub-pixel 41. When the first sub-pixel 41 is the sub-pixel with the highest brightness proportion when the three sub-pixels 40 are combined with white light, such as when the first sub-pixel 41 is a green sub-pixel, the visual effect of low grayscale display can be improved.

[0034] In some implementations, such as Figure 1 As shown, data line 30 includes a first data line 31 and a second data line 32. The first data line 31 is coupled to a first sub-pixel 41, and the second data line 32 is coupled to a second sub-pixel 42 or to a third sub-pixel 43. In other embodiments, Figure 3 This is another schematic diagram of a display panel provided in an embodiment of the present invention, taking n=2 as an example, as follows: Figure 3 As shown, the first data line 31 is coupled to the first sub-pixel 41, and the second data line 32 is coupled to the second sub-pixel 42 and the third sub-pixel 43. Figure 1 and Figure 3 In all embodiments, the first data line 31 is coupled only to the first sub-pixel 41; in other words, the first data line 31 only drives the first sub-pixel 41.

[0035] This invention provides another driving method, applicable to... Figure 1 and Figure 3 The display panel shown is driven in a manner where, during the stage of providing a first data signal to the input of the multiplexer 10, the corresponding switch 11 has the longest on-time, including controlling the on-time of the switch 11 connected to the first data line 31 to be longer than the on-time of the switch 11 connected to the second data line 32. In this embodiment, the first data line 31 is coupled to the first sub-pixel 41, and the first sub-pixel 41 does not share data lines with other color sub-pixels. This arrangement makes it easier to control the on-time of the switch 11 connected to the first data line 31. Figure 4 This is a schematic diagram of the control signal timing of a switch in an embodiment of the present invention. Figure 4 In the embodiment, the first control signal K1 can be used for driving. Figure 1 and Figure 3In the embodiment, the switch 11 connected to the first data line 31 is driven by the second control signal K2. Figure 1 and Figure 3 In this embodiment, switch 11 is connected to the second data line 32. Taking the switch 11 being turned on under low-level control as an example, as... Figure 4 As shown, the duration of a low level in the first control signal K1 is T1. Therefore, the duration of one opening of the switch 11 connected to the first data line 31 is T1, which is the opening duration t of the corresponding switch 11 during the time period when the data terminal 20 writes the first data signal to the data line 30. 01 =T1; The duration of a low level in the second control signal K2 is T2, then the duration of the switch 11 connected to the second data line 32 being turned on once is T2.

[0036] Figure 1 and Figure 3 In this embodiment, the first data line 31 is coupled only to the first sub-pixel 41. Therefore, the signal written to the first data line 31 each time is the first data signal, and the on-time of the switch 11 connected to the first data line 31 can be set to T1 each time. This simplifies the timing setting of the first control signal K1 of the switch 11 corresponding to the first data line 31. The first control signal K1 is a periodic pulse signal, and the duration of the effective level signal in each signal cycle is the same, making the implementation of the first control signal K1 simpler. In addition, controlling the on-time of the switch 11 connected to the first data line 31 to be longer than the on-time of the switch 11 connected to the second data line 32 ensures that the on-time of the switch 11 corresponding to the stage of providing the first data signal to the input of the multiplexer 10 is the longest, thereby reducing the voltage required for the first sub-pixel 41 to reach the dark state. The dark state voltage of the display panel depends on the dark state voltage of the first sub-pixel 41. Therefore, the driving method provided by this invention can reduce the dark state voltage of the display panel, thereby reducing the crosstalk between the data line 30 and the power line when the sub-pixel 40 is cut from grayscale to black and improving the display effect.

[0037] In some implementations, such as Figure 1 or Figure 3 As shown, switch 11 includes a first switch 11-1, which is coupled to a first data line 31; the display panel includes a control line 60, the control terminal of switch 11 is coupled to control line 60, control line 60 includes a first control line 61, and the control terminals of multiple first switches 11-1 are coupled to the same first control line 61.

[0038] Specifically, in Figure 1In this embodiment, when n=4, the output of the multiplexer 10 is coupled to two first data lines 31 and two second data lines 32. Therefore, each multiplexer 10 has two first switches 11-1, each connected to one of the two first data lines 31. The display panel has two first control lines 61, which control the two first switches 11-1 in the multiplexer 10. For each of the two first control lines 61, each multiplexer 10 has one first switch 11-1 electrically connected to one of the first control lines 61, and another first switch 11-1 electrically connected to the other first control line 61. That is, one first control line 61 connects to the first switches 11-1 in different multiplexers 10. Specifically, in... Figure 3 In this embodiment, n=2, the output of the multiplexer 10 is connected to a first data line 31 and a second data line 32, then a first switch 11-1 is provided in a multiplexer 10, and a first control line 61 is provided in the display panel, and the first control line 61 controls the first switches 11-1 in multiple multiplexers 10.

[0039] This invention also provides another driving method, which can be used for... Figure 1 or Figure 3 The display panel shown in the embodiment is driven, wherein the driving method includes step S201: the first control line 61 provides an enable signal to control multiple first switches 11-1 connected to it to be turned on simultaneously. That is, the enable signal of the first control line 61 uniformly controls the charging time of multiple first data lines 31. Optionally, the first control line 61 provides, for example, Figure 4 The first control signal K1 is shown. In the display panel, the first control line 61 can simultaneously control the operation of multiple first switches 11-1. The driving method provided by the embodiment of the present invention does not require changing the corresponding connection method between the switches 11 and the control line 60 in the multiple multiplexers 10. It only needs to adjust the duration (or duration) of the first control line 61 providing an effective level once, which can increase the charging time of the first data line 31, so that the voltage value charged to the first data line 31 can be closer to the expected voltage of the first data signal, thereby reducing the voltage required for the first sub-pixel 41 to reach the dark state. Since the dark state voltage of the display panel depends on the dark state voltage of the first sub-pixel 41, the driving method provided by the embodiment of the present invention can reduce the dark state voltage of the display panel, thereby reducing the line crosstalk between the data line 30 and the power line when the sub-pixel 40 is cut from grayscale to black, and improving the display effect.

[0040] In some implementations, such as Figure 1 or Figure 3As shown, switch 11 includes a second switch 11-2, which is coupled to a second data line 32; control line 60 includes a second control line 62, and the control terminals of multiple second switches 11-2 are coupled to the same second control line 62. Figure 1 In this embodiment, the output terminal of the multiplexer 10 is coupled to two second data lines 32. Thus, a multiplexer 10 is provided with two second switches 11-2, which are respectively connected to the two second data lines 32. The display panel is provided with two second control lines 62, which control the two second switches 11-2 in the multiplexer 10 respectively. Figure 3 In this embodiment, the output of the multiplexer 10 is connected to a second data line 32, and a second switch 11-2 is provided in one multiplexer 10. A second control line 62 is provided in the display panel, and the second control line 62 controls the second switches 11-2 in multiple multiplexers 10.

[0041] Combination Figure 4 The first control line 61 provides a first control signal K1, and the second control line 62 provides a second control signal K2. In this embodiment of the invention, the second control line 62 controls the second switch 11-2, and the second data line 32 connected to the second switch 11-2 is coupled to other color sub-pixels 40 except for the first sub-pixel 41. Step S201 includes: the first control line 61 provides an enable signal to control the simultaneous opening of the plurality of first switches 11-1 connected to it, and the second control line 62 provides an enable signal to control the simultaneous opening of the plurality of second switches 11-2 connected to it, wherein the duration of the effective level in the enable signal provided by the first control line 61 is greater than the duration of the effective level in the enable signal provided by the second control line 62. The driving method provided in this embodiment of the invention does not require changing the corresponding connection method between the switches 11 and control lines 60 in the multiple multiplexers 10, nor does it require changing the enable signal provided by the second control line 62. It only requires increasing the duration of the effective level in the enable signal provided by the first control line 61, thereby lengthening the on-time of the first switch 11-1. This allows the voltage value charged to the first data line 31 to be closer to the expected voltage of the first data signal, thus reducing the dark-state voltage of the first sub-pixel 41. Since the dark-state voltage of the display panel depends on the dark-state voltage of the first sub-pixel 41, the driving method provided in this embodiment of the invention can reduce the dark-state voltage of the display panel, thereby reducing the line crosstalk between the data line 30 and the power line when the sub-pixel 40 is cut from grayscale to black, and improving the display effect.

[0042] In this embodiment of the invention, sub-pixel 40 includes a pixel circuit, which can be any type of existing technology, such as a pixel circuit including 7 transistors and 1 storage capacitor. One pixel circuit drives one light-emitting device. Multiple pixel circuits are arranged in an array in the display panel, which can ensure the uniformity of the etching process during manufacturing and ensure that the characteristics of transistors with the same function in each pixel circuit are basically the same.

[0043] Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 5 Can be combined Figure 1 To understand, Figure 5 The diagram shows the arrangement of pixel circuits 70 in the display panel. Multiple pixel circuits 70 are arranged in a pixel circuit row 70H along the second direction x, which intersects with the first direction y. Figure 5 The display panel uses pixel circuits that distinguish different colored sub-pixels by different pattern fills. It also includes scan lines 80, with one scan line 80 driving each pixel circuit row 70H. When the display panel is in operation, multiple scan lines 80 sequentially provide enable signals to drive multiple pixel circuit rows 70H row by row. The scan lines 80 cooperate with data lines 30 to write data signals into the pixel circuits 70, enabling the pixel circuits 70 to drive the light-emitting devices to emit light.

[0044] The driving method provided in this embodiment of the invention includes: controlling multiple data terminals 20 to provide data signals to the input terminals of multiple multiplexers 10, so as to write row data signals into multiple data lines 30. The row data signals include data signals required by multiple pixel circuits 70 in pixel circuit rows 70H. The display panel includes multiple pixel circuit rows 70H. When the display panel displays a frame, each pixel circuit row 70H requires a set of row data signals. The row data signals include multiple data signals, and the number of data signals is the same as the number of pixel circuits in the pixel circuit row 70H. When driving the display panel to display, the writing process of the row data signals is coordinated with the timing of the scan line 80 providing an enable signal to achieve driving of a pixel circuit row 70H. In this implementation, during the period when row data signals are written to multiple data lines 30, a switch 11 connected to the first data line 31 and a switch 11 connected to the second data line 32 in a multiplexer 10 are each turned on once. Specifically, when the switch 11 connected to the first data line 31 is turned on, a first data signal is written to the first data line 31; when the switch 11 connected to the second data line 32 is turned on, a second data signal or a third data signal is written to the second data line 32. In this driving method, during the period of writing row data signals, two switches 11 in each multiplexer 10 are turned on at different times, meaning the two switches 11 are turned on at different times without overlap. Furthermore, the duration of the switch 11 connected to the first data line 31 is longer than the duration of the switch 11 connected to the second data line 32. Therefore, the duration of writing row data signals is approximately equal to the sum of the durations of the switches connected to the first data line 31 and the second data line 32. For a pixel circuit row 70H, it connects to sub-pixels of different colors. Therefore, during the row data signal writing phase, data voltages corresponding to the sub-pixels of different colors are written to a pixel circuit row 70H. Furthermore, since a multiplexer 10 is provided, during the row data writing period, one multiplexer controls the data writing of at least two pixel circuits 70 in pixel circuit row 70H. However, since the input of a multiplexer 10 is only connected to one data terminal 20, the method of sequentially turning on the switches in the multiplexer 10 is required to complete the writing of the data voltage for the entire pixel circuit row 70H. In this embodiment of the invention, the two switches 11 in the multiplexer 10 are turned on at different times during the row data signal writing period. The writing duration of the row data signal is determined only by the sum of the opening durations of the two switches 11. Even if the opening duration of the switch 11 connected to the first data line 31 is increased to improve the line crosstalk problem caused by the grayscale cutting of the sub-pixel 40 to black, the writing duration of the row data signal will not be too long. The writing duration of the row data signal can be matched with the scan line 80 to meet the frame refresh time of the display panel.

[0045] In some embodiments, the output of the multiplexer 10 is connected to at least one first data line 31 and at least one second data line 32; the switch 11 includes a first switch 11-1 electrically connected to the first data line 31 and a second switch 11-2 electrically connected to the second data line 32. For example... Figure 1 As shown, the output of the multiplexer 10 is connected to two first data lines 31 and two second data lines 32. Figure 3 As shown, the output of the multiplexer 10 is connected to a first data line 31 and a second data line 32. In the driving method provided in this embodiment of the invention, step S101, in which the first data signal is provided to the input of the multiplexer 10, has the longest opening duration of the corresponding switch 11. This includes: controlling the data terminal 20 to sequentially provide data signals to the input of the multiplexer 10, and controlling the first switch 11-1 and the second switch 11-2 in the multiplexer 10 to open at different time periods, that is, the first switch 11-1 and the second switch 11-2 are opened at different times and their opening periods do not overlap. The opening duration of the first switch 11-1 is longer than the opening duration of the second switch 11-2. By enabling the first switch 11-1 and the second switch 11-2 in the multiplexer 10 to be turned on at different times, the data terminal 20 can provide the data signals required by different color sub-pixels at different times, thus achieving multiplexing of the data terminal 20. The data terminal 20, the multiplexer 10, and the data line 30 work together to reduce the number of data terminals 20 in the display panel, thereby saving on the number of pins in the display driver chip and reducing costs. In addition, by increasing the on-time of the first switch 11-1, the voltage required for the first sub-pixel 41 to reach the dark state can be reduced, thereby reducing the dark state voltage of the display panel and improving the crosstalk in the display panel when the sub-pixel 40 is cut from grayscale to black.

[0046] In some implementations, such as Figure 5As shown, multiple pixel circuits 70 of multiple first sub-pixels 41 are arranged along the first direction y to form a first pixel circuit column 70L-1, and the pixel circuits 70 of the second sub-pixels 42 and the pixel circuits 70 of the third sub-pixels 43 are alternately arranged along the first direction y to form a second pixel circuit column 70L-2. The first data line 31 includes a first sub-data line 31a and a second sub-data line 31b. The first sub-data line 31a is electrically connected to the odd-numbered pixel circuit 70 in the first pixel circuit column 70L-1, and the second sub-data line 31b is electrically connected to the even-numbered pixel circuit 70 in the first pixel circuit column 70L-1. The first switch 11-1 includes a first sub-switch 11-1a electrically connected to the first sub-data line 31a and a second sub-switch 11-2b electrically connected to the second sub-data line 31b. The second data line 32 includes a third sub-data line 32c and a fourth sub-data line 32d. The third sub-data line 32c is electrically connected to the odd-numbered pixel circuit 70 in the second pixel circuit column 70L-2, and the fourth sub-data line 32d is electrically connected to the even-numbered pixel circuit 70 in the second pixel circuit column 70L-2. The second switch 11-2 includes a third sub-switch 11-2c electrically connected to the third sub-data line 32c and a fourth sub-switch 11-2d electrically connected to the fourth sub-data line 32d. The multiplexer 10 includes a first sub-switch 11-1a, a second sub-switch 11-1b, a third sub-switch 11-2c, and a fourth sub-switch 11-2d.

[0047] The driving method provided in this embodiment of the invention is applicable to Figure 5 The display panel provided in the embodiment, Figure 5 The control line 60 includes two first control lines and two second control lines. The two first control lines are the first sub-control line 61-1 and the second sub-control line 61-2, respectively. The two second control lines are the third sub-control line 62-1 and the fourth sub-control line 62-2, respectively. The control terminal of the first sub-switch 11-1a is connected to the first sub-control line 61-1, the control terminal of the second sub-switch 11-1b is connected to the second sub-control line 61-2, the control terminal of the third sub-switch 11-2c is connected to the third sub-control line 62-1, and the control terminal of the fourth sub-switch 11-2d is connected to the fourth sub-control line 62-2.

[0048] Figure 6 for Figure 5 A timing diagram of a multiplexer in this embodiment. Figure 6 It indicated Figure 5 The timing of the multiplexer 10 in operation when continuously driving four pixel circuits in line 70H. Combined with... Figure 5 and Figure 6 To understand this, controlling the first switch 11-1 and the second switch 11-2 in the multiplexer 10 to open at different times in the driving method includes: controlling the first switch 11-1 and the second switch 11-2 in the multiplexer 10 to open alternately; wherein,

[0049] During the stage of writing data signals to the odd-numbered pixel circuits in the first pixel circuit column 70L-1 and the second pixel circuit column 70L-2, the first sub-switch 11-1a and the third sub-switch 11-2c are controlled to open at different time periods, with the opening duration of the first sub-switch 11-1a being longer than that of the third sub-switch 11-2c. The order in which the first sub-switch 11-1a and the third sub-switch 11-2c are opened is not limited. During the stage of writing data signals to the even-numbered pixel circuits in the first pixel circuit column 70L-1 and the second pixel circuit column 70L-2, the second sub-switch 11-1b and the fourth sub-switch 11-2d are controlled to open at different time periods, with the opening duration of the second sub-switch 11-1b being longer than that of the fourth sub-switch 11-2d. The order in which the second sub-switch 11-1b and the fourth sub-switch 11-2d are opened is not limited.

[0050] Combination Figure 6 From this perspective, stage Z1 corresponds to Figure 5 The data signal writing stage of the first pixel circuit line 70H from the top can be understood by referring to Z2, Z3, and Z4. Figure 5 The first pixel circuit row 70H is the odd-numbered pixel circuit row, and the odd-numbered pixel circuits in the first pixel circuit column 70L-1 and the second pixel circuit column 70L-2 are located in the odd-numbered pixel circuit rows. Stage Z2 is the driving stage. Figure 5 In the stage of the second pixel circuit row 70H, the second pixel circuit row 70H is the even-numbered pixel circuit row, and the even-numbered pixel circuit in the first pixel circuit column 70L-1 and the second pixel circuit column 70L-2 is located in the even-numbered pixel circuit row.

[0051] In phase Z1: The first second control line 62-1 provides a low-level enable signal to control the third sub-switch 11-2c to turn on, and the data terminal 20 is connected to the third sub-data line 32c to write data voltage to the third sub-data line 32c. Figure 5 The left data terminal 20 writes a second data signal (corresponding to the second sub-pixel 42) to the third sub-data line 32c, and the right data terminal 20 writes a third data signal (corresponding to the third sub-pixel 43) to the third sub-data line 32c. The first control line 61-1 provides a low-level enable signal to control the first sub-switch 11-1a to turn on, and the data terminal 20 is connected to the first sub-data line 31a, and the data terminal 20 writes a first data signal (corresponding to the first sub-pixel 41) to the first sub-data line 31a. Furthermore, the duration of the low-level enable signal provided by the first control line 61-1 is greater than the duration of the low-level enable signal provided by the first second control line 62-1, thereby making the opening duration of the first sub-switch 11-1a greater than the opening duration of the third sub-switch 11-2c.

[0052] In the Z2 phase: the second control line 62-2 provides a low-level enable signal to control the fourth sub-switch 11-2d to turn on, and the data terminal 20 and the fourth sub-data line 32d are connected to write data voltage to the fourth sub-data line 32d. Figure 5 The left data terminal 20 writes a third data signal to the fourth sub-data line 32d, and the right data terminal 20 writes a second data signal to the fourth sub-data line 32d. The second first control line 61-2 provides a low-level enable signal to control the second sub-switch 11-1b to open, and the data terminal 20 is connected to the second sub-data line 31b, and the data terminal 20 writes a first data signal to the second sub-data line 31b. Furthermore, the duration of the low-level enable signal provided by the second first control line 61-2 is greater than the duration of the low-level enable signal provided by the second second control line 62-2, thereby making the opening duration of the second sub-switch 11-1b greater than the opening duration of the fourth sub-switch 11-2d.

[0053] In the driving method provided by this embodiment, the first switch 11-1 and the second switch 11-2 in the multiplexer 10 are alternately turned on. During the stage of writing row data signals to the odd-numbered pixel circuit row, the first sub-switch 11-1a and the third sub-switch 11-2c are turned on at different times. During the stage of writing row data signals to the even-numbered pixel circuit row, the second sub-switch 11-1b and the fourth sub-switch 11-2d are turned on at different times. The first sub-switch 11-1a controls the writing of data signals to the odd-numbered pixel circuit in the first pixel circuit column 70L-1, and the second sub-switch 11-1b controls the writing of data signals to the even-numbered pixel circuit in the first pixel circuit column 70L-1, so that the first sub-data line 31a and the second sub-data line 31b alternately drive the first pixel circuit column 70L-1. Similarly, the third sub-data line 32c and the fourth sub-data line 32d alternately drive the second pixel circuit column 70L-2. This configuration ensures sufficient charging time for each data line, preventing image distortion caused by insufficient charging. Furthermore, by increasing the on-time of the first sub-switch 11-1a and the second sub-switch 11-1b, the charging time for writing the first data signal onto the first data line 31 is prolonged, thereby reducing the voltage required for the first sub-pixel 41 to reach a dark state. Since the dark state voltage of the display panel depends on the dark state voltage of the first sub-pixel 41, the driving method provided in this embodiment can reduce the dark state voltage of the display panel, thereby reducing crosstalk between the data line 30 and the power line when the sub-pixel 40 transitions from grayscale to black, and improving the display effect. In addition, in this embodiment, the duration of writing the row data signal is approximately equal to the sum of the opening duration of the first switch 11-1 and the opening duration of the second switch 11-2. Therefore, the writing duration of the row data signal is determined only by the sum of the time-division opening durations of the two switches 11. Increasing the opening duration of the first switch 11-1 has little impact on the writing duration of the row data signal. The writing duration of the row data signal can be matched with the scan line 80 to meet the frame refresh time of the display panel.

[0054] In other implementations, Figure 7 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 7As shown, the pixel circuits 70 are arranged in an array, with multiple pixel circuits 70 arranged along the second direction x to form a pixel circuit row 70H. Multiple pixel circuits 70 of multiple first sub-pixels 41 are arranged along the first direction y to form a first pixel circuit column 70L-1, and the pixel circuits 70 of the second sub-pixels 42 and the pixel circuits 70 of the third sub-pixels 43 are alternately arranged along the first direction y to form a second pixel circuit column 70L-2. A first data line 31 is electrically connected to multiple pixel circuits 70 in the first pixel circuit column 70L-1, and a second data line 32 is electrically connected to multiple pixel circuits 70 in the second pixel circuit column 70L-2. The output of the multiplexer 10 is connected to one first data line 31 and one second data line 32. The multiplexer 10 includes a first switch 11-1 and a second switch 11-2, with the first switch 11-1 connected to the first data line 31 and the second switch 11-2 connected to the second data line 32. The control terminal of the first switch 11-1 is connected to the first control line 61, and the control terminal of the second switch 11-2 is connected to the second control line 62.

[0055] The driving method provided in this embodiment of the invention is applicable to Figure 7 The display panel provided in the embodiment, Figure 8 for Figure 7 A timing diagram of a multiplexer in this embodiment. Figure 8 It indicated Figure 7 Timing of the multiplexer 10 during the row data writing phase of four consecutive pixel circuit lines 70H. Combined with... Figure 7 and Figure 8 To understand this, the driving method controls the data terminal 20 to sequentially provide data signals to the input terminal of the multiplexer 10, and controls the first switch 11-1 and the second switch 11-2 in the multiplexer 10 to open at different time periods. This includes: when the data terminal 20 provides a first data signal to the input terminal of the multiplexer 10, controlling the first switch 11-1 to open so as to write the first data signal to the first data line 31; when the data terminal 20 provides a second data signal to the input terminal of the multiplexer 10, controlling the second switch 11-2 to open so as to write the second data signal to the second data line 32; when the data terminal 20 provides a third data signal to the input terminal of the multiplexer 10, controlling the second switch 11-2 to open so as to write the third data signal to the second data line 32. The second data signal corresponds to the second sub-pixel 42, and the third data signal corresponds to the third sub-pixel 43. In this embodiment, both the second sub-pixel 42 and the third sub-pixel 43 are connected to the second data line 32. Since both the second data signal and the third data signal need to be written into the second data line 32, it can be considered that the second data signal and the third data signal are the same type of data signal.

[0056] Figure 8 The intermediate stage Z1 corresponds to Figure 7The data signal writing stage of the first pixel circuit line 70H from the top can be understood by referring to Z2, Z3, and Z4.

[0057] In phase Z1: The second control line 62 provides a low-level enable signal to control the second switch 11-2 to turn on, and the data terminal 20 is connected to the second data line 32 to write data voltage to the second data line 32. Figure 7 The left data terminal 20 writes a second data signal to the second data line 32, and the right data terminal 20 writes a third data signal to the second data line 32; the first control line 61 provides a low-level enable signal to control the first switch 11-1 to turn on, the data terminal 20 is connected to the first data line 31, and the data terminal 20 writes a first data signal to the first data line 31; and the duration of the low-level enable signal provided by the first control line 61 is greater than the duration of the low-level enable signal provided by the second control line 62, thereby making the opening duration of the first switch 11-1 greater than the opening duration of the second switch 11-2.

[0058] In the Z2 phase: the second control line 62 provides a low-level enable signal to control the second switch 11-2 to turn on, and the data terminal 20 is connected to the second data line 32. Figure 7 The left data terminal 20 writes a third data signal to the second data line 32, and the right data terminal 20 writes a second data signal to the second data line 32; the first control line 61 provides a low-level enable signal to control the first switch 11-1 to turn on, the data terminal 20 is connected to the first data line 31, and the data terminal 20 writes a first data signal to the first data line 31; and the duration of the low-level enable signal provided by the first control line 61 is greater than the duration of the low-level enable signal provided by the second control line 62, so that the opening duration of the first switch 11-1 is greater than the opening duration of the second switch 11-2.

[0059] In the driving method provided by this embodiment, when driving a pixel circuit row 70, the first switch 11-1 and the second switch 11-2 in the multiplexer 10 are alternately turned on. Furthermore, the on-time of the first switch 11-1 is increased, thus lengthening the charging time for writing the first data signal onto the first data line 31. This reduces the voltage required for the first sub-pixel 41 to reach a dark state. Since the dark state voltage of the display panel depends on the dark state voltage of the first sub-pixel 41, the driving method provided by this embodiment can reduce the dark state voltage of the display panel, thereby reducing crosstalk between the data line 30 and the power line when the sub-pixel 40 is cut from grayscale to black, and improving the display effect. In addition, in this embodiment, the duration of writing the row data signal is approximately equal to the sum of the opening duration of the first switch 11-1 and the opening duration of the second switch 11-2. Therefore, the writing duration of the row data signal is determined only by the sum of the opening durations of the two switches 11. Increasing the opening duration of the first switch 11-1 has little impact on the writing duration of the row data signal. The writing duration of the row data signal can be matched with the scan lines to meet the frame refresh time of the display panel.

[0060] In other implementations, Figure 9 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 9 As shown, taking n=4 as an example, the multiplexer includes a first multiplexer 10a and a second multiplexer 10b. The switch 11 includes a first switch 11-1 electrically connected to the first data line 31 and a second switch 11-2 electrically connected to the second data line 32. The first multiplexer 10a includes the first switch 11-1, and the second multiplexer 10b includes the second switch 11-2. The output terminal of the first multiplexer 10a is connected to at least two first data lines 31, and the output terminal of the second multiplexer 10b is connected to at least two second data lines 32. The first data lines 31 are connected to multiple first sub-pixels 41, and the second data lines 32 are connected to multiple second sub-pixels 42, or the second data lines 32 are connected to multiple third sub-pixels 43.

[0061] In step S101, when the first data signal is provided to the input terminal of the multiplexer 10, the corresponding switch 11 has the longest opening duration. This includes: controlling the data terminal 20 to provide a data signal to the input terminal of the first multiplexer 10a and controlling the first switch 11-1 in the first multiplexer 10a to open during different time periods; controlling the data terminal 20 to provide a data signal to the input terminal of the second multiplexer 10b and controlling the second switch 11-2 in the second multiplexer 10b to open during different time periods, wherein the opening duration of the first switch 11-1 is longer than the opening duration of the second switch 11-2. In this embodiment, after the first switch 11-1 is turned on, the data terminal 20 is connected to the first data line 31, and the first data signal is written to the first data line 31. Increasing the on-time of the first switch 11-1 in the first multiplexer 10a allows the first data line 31 to be charged more fully, and the voltage value charged to the first data line 31 can be closer to the expected voltage of the first data signal. This reduces the voltage required for the first sub-pixel 41 to reach the dark state. When the dark state voltage of the display panel depends on the dark state voltage of the first sub-pixel 41, the dark state voltage of the display panel can be reduced. After the dark state voltage of the display panel is reduced, when the sub-pixel 40 driven by the data line 30 is cut from grayscale to black, the crosstalk between the data line 30 and other signal lines can be improved, thus enhancing the display effect.

[0062] In some implementations, such as Figure 9 As shown, multiple pixel circuits 70 are arranged in an array. Multiple pixel circuits 70 of multiple first sub-pixels 41 are arranged along the first direction y to form a first pixel circuit column 70L-1. The pixel circuits 70 of the second sub-pixels 42 and the pixel circuits 70 of the third sub-pixels 43 are arranged alternately along the first direction y to form a second pixel circuit column 70L-2. Multiple pixel circuits 70 are arranged along the second direction x to form a pixel circuit row 70H. The second direction x intersects with the first direction y.

[0063] The first data line 31 includes a first sub-data line 31a and a second sub-data line 31b. The first sub-data line 31a is electrically connected to the odd-numbered pixel circuit 70 in the first pixel circuit column 70L-1, and the second sub-data line 31b is electrically connected to the even-numbered pixel circuit 70 in the first pixel circuit column 70L-1. The first switch 11-1 includes a first sub-switch 11-1a electrically connected to the first sub-data line 31a and a second sub-switch 11-1b electrically connected to the second sub-data line 31b.

[0064] The second data line 32 includes a third sub-data line 32c and a fourth sub-data line 32d. The third sub-data line 32c is electrically connected to the odd-numbered pixel circuit 70 in the second pixel circuit column 70L-2, and the fourth sub-data line 32d is electrically connected to the even-numbered pixel circuit 70 in the second pixel circuit column 70L-2. The second switch 11-2 includes a third sub-switch 11-2c electrically connected to the third sub-data line 32c and a fourth sub-switch 11-2d electrically connected to the fourth sub-data line 32d.

[0065] The first multiplexer 10a includes two first sub-switches 11-1a and two second sub-switches 11-1b; the second multiplexer 10 includes two third sub-switches 11-2c and two fourth sub-switches 11-2d. The display panel has four first control lines and four second control lines. The two first sub-switches 11-1a and two second sub-switches 11-1b are electrically connected to the four first control lines, which are respectively: a first type first sub-control line 61-11, a first type second sub-control line 61-12, a first type third sub-control line 61-13, and a first type fourth sub-control line 61-14. The two third sub-switches 11-2c and two fourth sub-switches 11-2d are electrically connected to the four second control lines, which are respectively: a second type first sub-control line 62-21, a second type second sub-control line 62-22, a second type third sub-control line 62-23, and a second type fourth sub-control line 62-24.

[0066] Figure 10 for Figure 9 A timing diagram of a multiplexer in this embodiment. Figure 10 It indicated Figure 9 The timing of the multiplexer 10 during the row data signal writing phase of four consecutive pixel circuit lines 70H. Combined with... Figure 9 and Figure 10 To understand this, controlling the first switch 11-1 in the first multiplexer 10a to open during different time periods in the driving method includes: controlling two first sub-switches 11-1a to open during different time periods during the stage of writing data signals to the odd-numbered pixel circuit 70 in the first pixel circuit column 70L-1; controlling two second sub-switches 11-1b to open during different time periods during the stage of writing data signals to the even-numbered pixel circuit 70 in the first pixel circuit column 70L-1; controlling the second switch 11-2 in the second multiplexer 10b to open during different time periods includes: controlling two third sub-switches 11-2c to open during different time periods during the stage of writing data signals to the odd-numbered pixel circuit 70 in the second pixel circuit column 70L-2; and controlling two fourth sub-switches 11-2d to open during different time periods during the stage of writing data signals to the even-numbered pixel circuit 70 in the second pixel circuit column 70L-2.

[0067] Combination Figure 10 From this perspective, the Z1 stage corresponds to Figure 9 The timing of the row data writing stage for the first pixel circuit row 70H from top to bottom, where the first pixel circuit row 70H is the odd-numbered pixel circuit row.

[0068] In the Z1 phase: The second type of first sub-control line 62-21 provides a low-level enable signal to control the activation of a third sub-switch 11-2c in the second multiplexer 10b. Figure 9 The data terminal 20 on the left is connected to a third sub-data line 32c to write a second data signal. The second sub-control line 62-22 provides a low-level enable signal to control another third sub-switch 11-2c in the second multiplexer 10b to turn on. Figure 9 The data terminal 20 on the left is connected to another third sub-data line 32c to write a third data signal. Both third sub-switches 11-2c need to be turned on once during this stage, so they are connected to different control lines, allowing the two third sub-switches 11-2c to be turned on at different times. Additionally, the first sub-control line 61-11 provides a low-level enable signal to control the activation of one of the first sub-switches 11-1a in the first multiplexer 10a. Figure 9 The data terminal 20 on the right is connected to a first sub-data line 31a to write a first data signal. The first type of second sub-control line 61-12 provides a low-level enable signal to control another first sub-switch 11-1a in the first multiplexer 10a to turn on. Figure 9 The data terminal 20 on the right is connected to another first sub-data line 31a to write the first data signal. Both first sub-switches 11-1a need to be turned on once during this stage, so they are connected to different control lines, allowing the two first sub-switches 11-1a to be turned on at different times. In stage Z1, the duration of the low-level enable signal provided by the first type of first sub-control line 61-11 is equal to the duration of the low-level enable signal provided by the first type of second sub-control line 61-12, and is greater than the duration of the low-level enable signals provided by the second type of first sub-control line 62-21 and the second type of second sub-control line 62-22. For example... Figure 10 As shown, the low-level enable signal period provided by the first type of first sub-control line 61-11 overlaps with the low-level enable signal period of the second type of first sub-control line 62-11, and the low-level enable signal period provided by the first type of second sub-control line 61-12 overlaps with the low-level enable signal period of the second type of second sub-control line 62-22. This ensures that the row data signal writing time will not be too long, and the row data signal writing time is approximately equal to the sum of the opening times of the two first switches 11.

[0069] Referring to the description of stage Z1, we know that in stage Z2, the two fourth sub-switches 11-2d in the second multiplexer 10b are each turned on once, and the two second sub-switches 11-1b in the first multiplexer 10a are each turned on once. The operation of the multiplexers in stages Z2 to Z4 can be understood with reference to stage Z1, and will not be repeated here.

[0070] In this embodiment, the first multiplexer 10a is coupled to the first data line 31, and the second multiplexer 10b is coupled to the second data line 32. During the stage of writing data signals to the odd-numbered pixel circuits in the first pixel circuit column 70L-1 and the second pixel circuit column 70L-2, the two first sub-switches 11-1a in the first multiplexer 10a and the two third sub-switches 11-2c in the second multiplexer 10b operate. During the stage of writing data signals to the even-numbered pixel circuits in the first pixel circuit column 70L-1 and the second pixel circuit column 70L-2, the two second sub-switches 11-1b in the first multiplexer 10a operate in a time-division manner, and the two fourth sub-switches 11-2d in the second multiplexer 10b operate in a time-division manner. The on-time of the first sub-switch 11-1a and the on-time of the second sub-switch 11-1b in the first multiplexer 10a can be independently controlled. By increasing the on-time of the first sub-switch 11-1a and the second sub-switch 11-1b, the first data line 31 can be charged more fully, thereby reducing the voltage required for the first sub-pixel 41 to reach the dark state. When the dark state voltage of the display panel depends on the dark state voltage of the first sub-pixel 41, the dark state voltage of the display panel can be reduced. After the dark state voltage of the display panel is reduced, when the sub-pixel 40 driven by the data line 30 is cut from grayscale to black, the crosstalk between the data line 30 and other signal lines can be improved, thus enhancing the display effect.

[0071] In addition, combined Figure 10In the driving method, during the stage of writing data signals to the odd-numbered pixel circuit 70 in the first pixel circuit column 70L-1 and the odd-numbered pixel circuit 70 in the second pixel circuit column 70L-2, the opening time of the first sub-switch 11-1a and the opening time of the third sub-switch 11-2c overlap. During the stage of writing data signals to the even-numbered pixel circuit 70 in the first pixel circuit column 70L-1 and the even-numbered pixel circuit 70 in the second pixel circuit column 70L-2, the opening time of the second sub-switch 11-1b and the opening time of the fourth sub-switch 11-2d overlap. Since the opening duration of the third sub-switch 11-2c is shorter than the opening duration of the first sub-switch 11-1a, and the opening duration of the fourth sub-switch 11-2d is shorter than the opening duration of the second sub-switch 11-1b, the row data signal writing duration is affected by the opening durations of the first sub-switch 11-1a and the second sub-switch 11-1b. Furthermore, since the first sub-switch 11-1a and the second sub-switch 11-1b in the multiplexer are only turned on once at different times during the row data writing phase, setting the opening duration of the first sub-switch 11-1a and the second sub-switch 11-1b to be relatively long will not cause the row data signal writing time to be too long, and can ensure that the writing time of the row data signal matches the scan line to meet the frame refresh time of the display panel.

[0072] In some embodiments, the driving method provided by the present invention includes: the switch 11 corresponding to the stage of providing a first data signal to the input terminal of the multiplexer 10 has the longest opening duration, and the switch 11 corresponding to the stage of providing a second data signal to the input terminal of the multiplexer 10 has an opening duration of T. 02 The opening duration of the corresponding switch 11 during the stage of providing the third data signal to the input of the multiplexer 10 is T. 03 T 02 =T 03This implementation increases the on-time of the stage switch 11 for writing the first data signal, making the voltage charged onto the data line 30 closer to the expected voltage of the first data signal, thereby reducing the voltage required for the first sub-pixel 41 to reach the dark state. When the luminous efficiency of the first sub-pixel 41 is the highest among the three color sub-pixels, the dark state voltage of the display panel depends on the dark state voltage of the first sub-pixel 41. Therefore, the driving method provided in this embodiment can reduce the dark state voltage of the display panel. In the prior art, the writing time of the data signals corresponding to the three color sub-pixels is equal, that is, the on-time of the switch in the stage multiplexer for writing data signals to the data line is a fixed time. However, in this embodiment, the on-time of the switch is controlled to be the longest when writing the first data signal, and the on-time of the switch is controlled to be equal to the on-time of the switch when writing the second data signal. That is, only the writing time of the data signal corresponding to the first sub-pixel 41 is increased, without changing the writing time of the data signals corresponding to the second sub-pixel 42 and the third sub-pixel 43. Since a pixel circuit row 70H connects to sub-pixels of different colors, data voltages corresponding to the different colored sub-pixels are written to a pixel circuit row 70H during the row data signal writing phase. In the scheme of setting the multiplexer 10, the duration of the row data signal writing phase is related to the on-time of the switch in the multiplexer 10. This embodiment of the invention does not change the writing time of the data signals corresponding to the second sub-pixel 42 and the third sub-pixel 43, and can ensure that increasing the on-time of the switch 11 connected to the first data line has little impact on the overall duration of the row data signal writing phase. The writing duration of the row data signal can be matched with the scan line 80 to meet the frame refresh time of the display panel.

[0073] Furthermore, by ensuring that the on-time of switch 11 during the writing of the second data signal is equal to the on-time of switch 11 during the writing of the third data signal, the control method of the multiplexer 10 can be simplified. In some embodiments, this also helps to reduce the number of control lines in the display panel, which in turn helps to reduce the number of pins on the display driver chip and lower the manufacturing cost of the display driver chip.

[0074] by Figure 3 In an example embodiment, a second data line 32 connects multiple second sub-pixels 42 and multiple third sub-pixels 43. The second data line 32 is connected to a second switch 11-2 in a multiplexer 10. The second data signal corresponds to the second sub-pixel 42, and the third data signal corresponds to the third sub-pixel 43. During display, the on-time of switch 11 when writing the second data signal is equal to the on-time of switch 11 when writing the third data signal. Therefore, the control signal received by the control terminal of the second switch 11-2 has a stronger regularity. When the display panel is working, the control terminal of the second switch 11-2 receives periodic control signals, and the duration of the enable signal in the control signals is equal (e.g., ...). Figure 4 The second control signal (K2) shown in the diagram is simpler and easier to obtain.

[0075] by Figure 5 In this embodiment, the display panel is provided with two types of second data lines 32: a third sub-data line 32c and a fourth sub-data line 32d. The third sub-data line 32c connects to the sub-pixels in the odd-numbered pixel circuit row, and the fourth sub-data line 32d connects to the sub-pixels in the even-numbered pixel circuit row. The third sub-data line 32c connects to the third sub-switch 11-2c, and the fourth sub-data line 32d connects to the fourth sub-switch 11-2d. Figure 5 The diagram illustrates four pixel circuit columns. The first and third pixel circuit columns from the left are connected to the second data line 32. The odd-numbered sub-pixels in the first and third pixel circuit columns are the second sub-pixel 42 and the third sub-pixel 43, respectively. This means that the odd-numbered sub-pixels in the first and third pixel circuit columns have different colors, and the even-numbered sub-pixels in the two pixel circuit columns also have different colors. The second data signal corresponds to the second sub-pixel 42, and the third data signal corresponds to the third sub-pixel 43. During display, the on-time of switch 11 when writing the second data signal is equal to the on-time of switch 11 when writing the third data signal, enabling the following functionality: Figure 5 The connection method is as follows: the third sub-data line 32c connecting the first pixel circuit column is connected to the third sub-switch 11-2c in the multiplexer 10, the third sub-data line 32c connecting the third pixel circuit column is connected to the third sub-switch 11-2c in another multiplexer 10, and the two third sub-switches 11-2c in the two multiplexers 10 are connected to the same control line 60. This reduces the number of control lines in the display panel, which in turn helps to reduce the number of pins on the display driver chip and lowers the manufacturing cost of the display driver chip.

[0076] In some other embodiments, step S101, which controls the data terminal 20 to provide a data signal to the input of the multiplexer 10, includes: controlling the data terminal 20 to provide a first data signal to the input of the multiplexer 10 for a duration of t1, controlling the data terminal 20 to provide a second data signal to the input of the multiplexer 10 for a duration of t2, and controlling the data terminal 20 to provide a third data signal to the input of the multiplexer 10 for a duration of t3, wherein t1>t2 and t1>t3.

[0077] Figure 11 A timing diagram of another display panel provided in an embodiment of the present invention, to Figure 11 Timing diagrams are suitable for Figure 5 The display panel provided in the embodiment will be described. Figure 11Fig. 0 shows the timing of the data terminal 20 providing a data signal. Here, a high level indicates that the data terminal 20 provides a first data signal, and a low level indicates that the data terminal provides a second data signal or a third data signal. Figure 11 Fig. 0 also shows the signal timings of the first sub-control line 61-1, the second sub-control line 61-2, the third sub-control line 62-1, and the fourth sub-control line 62-2. For the operation mode of the multiplexer 10 controlled by the control lines, reference can be made to Figure 6 the relevant description for understanding, which will not be elaborated here. From Figure 11 it can be seen that t1>t2 and t1>t3.

[0078] In the driving method provided by the embodiment of the present invention, during the stage of writing the first data signal to the data line 30, the opening duration of the switch 11 connected to the data line 30 is the longest. Then, during the stage of writing the second data signal or the third data signal to the data line 30, the opening time of the corresponding switch 11 is shorter. Thus, the time for the data terminal 20 to output the second data signal and the third data signal can be appropriately reduced. Without changing the total duration of writing the data signal to the data line, the time for the data terminal 20 to output the first data signal can be appropriately increased. After the duration of the data terminal 20 outputting the first data signal increases, the opening duration of the switch 11 when writing the first data signal can be further extended, thereby further reducing the dark state voltage of the display panel.

[0079] In some embodiments, by increasing the time for the data terminal 20 to output the first data signal and correspondingly reducing the time for the data terminal 20 to output the second data signal and the third data signal, for example, during Figure 5 the process of writing the row data signal in the embodiment, a data terminal 20 needs to output the first data signal and the second data signal (or the third data signal) at different times. After the output time of the first data signal becomes longer, the output times of other data signals will become shorter. Set 1<t1 / t2≤2 and 1<t1 / t3≤2 to ensure that both the second data signal and the third data signal are relatively fully written when writing, and to avoid image distortion caused by insufficient charging.

[0080] In some embodiments, t2 = t3, and only the time for the data terminal 20 to output the first data signal is adjusted, while the times for the data terminal 20 to output the second data signal and the third data signal are set to be equal, and the control method is relatively simple.

[0081] In some embodiments, combined with Figure 11 viewed as Figure 11The low level of the first sub-control line 61-1 is used to control the switch 11 connected to the first data line 31 to turn on. The duration of the low level of the first sub-control line 61-1 is the same as the on-time of the switch 11 connected to the first data line 31, which is the on-time of the switch 11 corresponding to the stage of providing the first data signal to the input terminal of the multiplexer 10. The driving method provided in this embodiment of the invention includes: the duration t1 of the data terminal 20 providing the first data signal is greater than the on-time of the switch 11 corresponding to the stage of providing the first data signal to the input terminal of the multiplexer 10. This ensures that during the period of writing the first data signal to the data line, the data terminal 10 continuously outputs the first data signal to the input terminal of the multiplexer 10, and the on-time of the corresponding switch 11 during the writing of the first data signal is an effective writing time, ensuring that the voltage value charged on the data line 30 is closer to the expected voltage of the first data signal.

[0082] In some implementations, combined Figure 5 and Figure 6 The driving method includes controlling multiple data terminals 20 to provide data signals to the input terminals of multiple multiplexers 10 respectively, so as to write row data signals into multiple data lines 30. The row data signals include data signals required by multiple pixel circuits 70 in pixel circuit rows 70H. During the stage of writing row data signals into the multiple data lines 30, each data terminal 20 provides two data signals to the input terminal of the multiplexer 10, one being a first data signal and the other a second (or third) data signal. In this driving method, during the row data signal writing process, each data terminal 20 outputs only two data signals, one of which is the first data signal. Therefore, with the row data signal writing duration remaining constant, increasing the time for the data terminal 20 to output the first data signal has a smaller impact on the output time of the other data signal, thus avoiding image distortion caused by insufficient writing of other data signals.

[0083] Based on the same inventive concept, embodiments of the present invention also provide a display panel, which is driven by the driving method provided in any embodiment of the present invention. The display panel includes a light-emitting device, which can be an organic light-emitting device or an inorganic light-emitting device.

[0084] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 12 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 12 As shown, the display device includes a display panel 100, which is driven by the driving method provided in any embodiment of the present invention. The driving method has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, an electronic device such as a mobile phone, tablet, computer, or television.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A driving method for a display panel, characterized in that, The display panel includes a multiplexer, data terminals, data lines, and sub-pixels. The input terminal of the multiplexer is coupled to the data terminal, and one input terminal of the multiplexer is coupled to one data terminal. The output terminal of the multiplexer is coupled to n data lines, where n is a positive integer and n≥2. The multiplexer includes n switches connected between its input and output terminals. Each switch is connected to a data line. The data line extends along a first direction and is coupled to multiple sub-pixels. Each sub-pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel with different colors. The data line connected to the output terminal of one of the multiplexers includes a first data line and a second data line. The first data line is coupled to the first sub-pixel, and the second data line is coupled to the second sub-pixel and / or the third sub-pixel. The driving method includes: The control terminal provides a data signal to the input of the multiplexer, and controls the corresponding switch to open for a preset duration to write the data signal to the data line; the data signal includes a first data signal corresponding to the first sub-pixel, a second data signal corresponding to the second sub-pixel, and a third data signal corresponding to the third sub-pixel; wherein, the opening duration of the corresponding switch is the longest during the stage of providing the first data signal to the input of the multiplexer; The phases in which one of the data terminals provides the first data signal, the phases in which it provides the second data signal, and the phases in which it provides the third data signal do not overlap.

2. The driving method according to claim 1, characterized in that, The period during which the first data signal is provided to the input of the multiplexer, and the corresponding longest on-time of the switch, includes: The on-time of the switch connected to the first data line is greater than the on-time of the switch connected to the second data line.

3. The driving method according to claim 2, characterized in that, The switch includes a first switch, which is coupled to the first data line; the display panel includes a control line, the control terminal of the switch is coupled to the control line, the control line includes a first control line, and the control terminals of multiple first switches are coupled to the same first control line; The driving method includes: the first control line providing an enable signal to control multiple first switches connected thereto to be turned on simultaneously.

4. The driving method according to claim 3, characterized in that, The switch includes a second switch, which is coupled to the second data line; the control line includes a second control line, and the control terminals of multiple second switches are coupled to the same second control line. The driving method includes: the second control line provides an enable signal to control multiple second switches connected thereto to be turned on simultaneously, wherein the duration of the effective level in the enable signal provided by the first control line is greater than the duration of the effective level in the enable signal provided by the second control line.

5. The driving method according to claim 2, characterized in that, The sub-pixel includes a pixel circuit, and a plurality of the pixel circuits are arranged in a pixel circuit row along a second direction, the second direction intersecting the first direction; The driving method includes: controlling a plurality of data terminals to provide data signals to the input terminals of a plurality of multiplexers respectively, so as to write row data signals into a plurality of data lines, wherein the row data signals include data signals required by a plurality of pixel circuits in the pixel circuit row; wherein, during the period when the row data signals are written into the plurality of data lines, the switch connected to the first data line and the switch connected to the second data line in one of the multiplexers are turned on once respectively.

6. The driving method according to claim 2, characterized in that, The output of the multiplexer is connected to at least one of the first data lines and at least one of the second data lines; the switch includes a first switch connected to the first data line and a second switch connected to the second data line; The period during which the first data signal is provided to the input of the multiplexer, and the corresponding longest on-time of the switch, includes: The control terminal sequentially provides data signals to the input terminal of the multiplexer, and controls the first switch and the second switch in the multiplexer to be turned on at different time periods; wherein the on-time of the first switch is longer than the on-time of the second switch.

7. The driving method according to claim 6, characterized in that, The sub-pixel includes a pixel circuit, and the pixel circuits of a plurality of first sub-pixels are arranged in a first pixel circuit column along a first direction. The pixel circuits of the second sub-pixel and the pixel circuits of the third sub-pixel are alternately arranged in a second pixel circuit column along the first direction. The first data line includes a first sub-data line and a second sub-data line. The first sub-data line is connected to the odd-numbered pixel circuit in the first pixel circuit column, and the second sub-data line is connected to the even-numbered pixel circuit in the first pixel circuit column. The first switch includes a first sub-switch connected to the first sub-data line and a second sub-switch connected to the second sub-data line. The second data line includes a third sub-data line and a fourth sub-data line. The third sub-data line is connected to the odd-numbered pixel circuit in the second pixel circuit column, and the fourth sub-data line is connected to the even-numbered pixel circuit in the second pixel circuit column. The second switch includes a third sub-switch connected to the third sub-data line and a fourth sub-switch connected to the fourth sub-data line. The multiplexer includes a first sub-switch, a second sub-switch, a third sub-switch, and a fourth sub-switch; Controlling the first switch and the second switch in the multiplexer to be turned on at different times includes: controlling the first switch and the second switch in the multiplexer to be turned on alternately; wherein... During the stage of writing data signals to the odd-numbered pixel circuits in the first pixel circuit column and the second pixel circuit column, the first sub-switch and the third sub-switch are controlled to be turned on at different time periods, and the on-time of the first sub-switch is longer than the on-time of the third sub-switch. During the stage of writing data signals to the even-numbered pixel circuits in the first pixel circuit column and the second pixel circuit column, the second sub-switch and the fourth sub-switch are controlled to be turned on at different time periods, and the on-time of the second sub-switch is longer than that of the fourth sub-switch.

8. The driving method according to claim 6, characterized in that, The sub-pixel includes a pixel circuit, and the pixel circuits of a plurality of first sub-pixels are arranged in a first pixel circuit column along a first direction. The pixel circuits of the second sub-pixel and the pixel circuits of the third sub-pixel are alternately arranged in a second pixel circuit column along the first direction. The first data line is connected to a plurality of pixel circuits in the first pixel circuit column, and the second data line is connected to a plurality of pixel circuits in the second pixel circuit column; the output of the multiplexer is connected to one of the first data lines and one of the second data lines. Controlling the data terminal to sequentially provide data signals to the input terminal of the multiplexer, and controlling the first switch and the second switch in the multiplexer to be turned on at different time periods, including: During the stage where the first data signal is provided to the input of the multiplexer at the data terminal, the first switch is controlled to be turned on so as to write the first data signal into the first data line; During the stage where the data terminal provides the second data signal to the input of the multiplexer, the second switch is controlled to turn on to write the second data signal to the second data line; during the stage where the data terminal provides the third data signal to the input of the multiplexer, the second switch is controlled to turn on to write the third data signal to the second data line.

9. The driving method according to claim 2, characterized in that, The multiplexer includes a first multiplexer and a second multiplexer, and the switch includes a first switch connected to the first data line and a second switch connected to the second data line; the first multiplexer includes the first switch, and the second multiplexer includes the second switch; the output terminal of the first multiplexer is connected to at least two of the first data lines, and the output terminal of the second multiplexer is connected to at least two of the second data lines; The period during which the first data signal is provided to the input of the multiplexer, and the corresponding longest on-time of the switch, includes: The data terminal is controlled to provide a data signal to the input terminal of the first multiplexer, and the first switch in the first multiplexer is controlled to be turned on at different time periods. The control terminal provides a data signal to the input terminal of the second multiplexer, and controls the second switch in the second multiplexer to be turned on at different time periods, wherein the on-time of the first switch is longer than the on-time of the second switch.

10. The driving method according to claim 9, characterized in that, The sub-pixel includes a pixel circuit, and the pixel circuits of a plurality of first sub-pixels are arranged in a first pixel circuit column along a first direction. The pixel circuits of the second sub-pixel and the pixel circuits of the third sub-pixel are alternately arranged in a second pixel circuit column along the first direction. The first data line includes a first sub-data line and a second sub-data line. The first sub-data line is connected to the odd-numbered pixel circuit in the first pixel circuit column, and the second sub-data line is connected to the even-numbered pixel circuit in the first pixel circuit column. The first switch includes a first sub-switch connected to the first sub-data line and a second sub-switch connected to the second sub-data line. The second data line includes a third sub-data line and a fourth sub-data line. The third sub-data line is connected to the odd-numbered pixel circuit in the second pixel circuit column, and the fourth sub-data line is connected to the even-numbered pixel circuit in the second pixel circuit column. The second switch includes a third sub-switch connected to the third sub-data line and a fourth sub-switch connected to the fourth sub-data line. The first multiplexer includes two first sub-switches and two second sub-switches; the second multiplexer includes two third sub-switches and two fourth sub-switches. Controlling the first switch in the first multiplexer to be turned on during different time periods includes: during the stage of writing data signals to the odd-numbered pixel circuit in the first pixel circuit column, controlling the two first sub-switches to be turned on during different time periods; during the stage of writing data signals to the even-numbered pixel circuit in the first pixel circuit column, controlling the two second sub-switches to be turned on during different time periods. Controlling the second switch in the second multiplexer to be turned on during different time periods includes: controlling the two third sub-switches to be turned on during different time periods when writing data signals to the odd-numbered pixel circuit in the second pixel circuit column; and controlling the two fourth sub-switches to be turned on during different time periods when writing data signals to the even-numbered pixel circuit in the second pixel circuit column.

11. The driving method according to claim 1, characterized in that, The driving method includes: a stage of providing the second data signal to the input of the multiplexer, and a corresponding on-time T of the switch. 02 The phase in which the third data signal is provided to the input of the multiplexer, and the corresponding on-time of the switch is T. 03 T 02 =T 03 .

12. The driving method according to claim 1, characterized in that, Controlling the data terminal to provide data signals to the input of the multiplexer includes: controlling the data terminal to provide the first data signal to the input of the multiplexer for a duration of t1, controlling the data terminal to provide the second data signal to the input of the multiplexer for a duration of t2, and controlling the data terminal to provide the third data signal to the input of the multiplexer for a duration of t3, wherein t1 > t2, t1 > t3.

13. The driving method according to claim 12, characterized in that, t2 = t3.

14. The driving method according to claim 12, characterized in that, The driving method includes: providing the input terminal of the multiplexer with a time period of the first data signal and a corresponding on-time T of the switch. 01 t1 is greater than T0.

15. The driving method according to claim 12, characterized in that, The sub-pixel includes a pixel circuit, and a plurality of the pixel circuits are arranged in a pixel circuit row along a second direction, the second direction intersecting the first direction; The driving method includes: controlling a plurality of data terminals to provide data signals to the input terminals of a plurality of multiplexers respectively, so as to write row data signals into a plurality of data lines, wherein the row data signals include data signals required by a plurality of pixel circuits in the pixel circuit row; wherein, during the period when the row data signals are written into the plurality of data lines, the data terminals provide two data signals to the input terminals of the multiplexers, one of which is the first data signal and the other is the second data signal or the third data signal.

16. The driving method according to claim 12, characterized in that, 1< t1 / t2≤2, 1< t1 / t3≤2.

17. The driving method according to claim 1, characterized in that, The first sub-pixel is the green sub-pixel.

18. A display panel, characterized in that, The display panel is driven by the driving method described in any one of claims 1 to 17.

19. A display device, characterized in that, The device includes a display panel, which is driven by the driving method described in any one of claims 1 to 17.

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