Pixel unit driving circuit, array substrate, display panel and display

Abstract

The application discloses a pixel unit driving circuit, an array substrate, a display panel and a display. The pixel unit driving circuit is used for driving a pixel unit in the display panel. The pixel unit driving circuit comprises a gate driving circuit and a switch unit. The switch unit is connected with a common voltage bus and a pixel driving unit respectively. The switch unit is used for disconnecting the connection between the common voltage bus and the pixel unit when the gate driving circuit stops outputting a gate driving signal, so that a port connected with the common voltage bus on the pixel unit generates a voltage drop. According to the application, the switch unit is arranged between the gate driving circuit and the pixel unit, the voltage difference between the pixel voltage and the common voltage bus can still meet the voltage difference corresponding to each gray scale after the coupling is reduced, and the debugging process is relatively convenient.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel unit driving circuit, an array substrate, a display panel, and a display. Background Technology

[0002] Currently, with the continuous improvement of people's living standards and the continuous advancement of technology, liquid crystal display panels are gradually being widely used due to their advantages such as being lightweight, portable, and having rich colors. However, when the scanning of each row of pixels in the liquid crystal display panel ends and the voltage of the gate driving line decreases, the pixel voltage will be pulled down simultaneously due to the capacitive coupling effect. Since the pixel voltage corresponding to each gray level is different, the voltage difference after the gray level change is also different.

[0003] To ensure that the voltage difference between the pixel voltage and the common voltage still meets the voltage difference corresponding to each gray level after the coupling is reduced, optical adjustment is usually performed on the LCD panel after it is manufactured so that the voltage of each gray level meets the requirements. However, the adjustment process is cumbersome and affects production efficiency.

[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this invention is to provide a pixel unit driving circuit, an array substrate, a display panel, and a display, aiming to solve the technical problem in the prior art where adjusting the voltage of each gray level is necessary to ensure that the voltage difference between the pixel voltage and the common voltage still conforms to the voltage difference corresponding to each gray level after the coupling is reduced, which leads to a cumbersome debugging process.

[0006] To achieve the above objectives, the present invention proposes a pixel unit driving circuit, which is used to drive pixel units in a display panel. The pixel unit driving circuit includes a gate driving circuit and a switching unit.

[0007] The switching unit is connected to both the common voltage bus and the pixel driving unit.

[0008] The switching unit is used to disconnect the connection between the common voltage bus and the pixel unit when the gate driving circuit stops outputting the gate driving signal, so as to generate a voltage drop at the port on the pixel unit connected to the common voltage bus.

[0009] Optionally, the control terminal of the switching unit is connected to the previous stage reset terminal of the gate driving circuit or the current stage gate driving terminal of the gate driving circuit.

[0010] Optionally, the switching unit is also connected to a common voltage line;

[0011] The switching unit is used to disconnect the connection between the common voltage bus and the common voltage row line when the gate drive circuit stops outputting the gate drive signal, so as to generate a voltage drop on the common voltage row line.

[0012] Optionally, the common voltage row line is connected to the corresponding row of multiple cascaded pixel units, and the common voltage row lines within the display area are not connected to each other.

[0013] Optionally, the difference between the first voltage drop and the second voltage drop is within a preset range, where the first voltage drop is the voltage drop between the pixel unit and the gate driving line connected to the gate driving terminal of the same level, and the second voltage drop is the voltage drop between the common voltage line and the gate driving line.

[0014] Optionally, the capacitance value of the first coupling capacitor between the gate driving line and the pixel unit is the same as the capacitance value of the second coupling capacitor between the gate driving line and the common voltage row line.

[0015] Optionally, the switching unit includes: a first thin-film transistor;

[0016] The control terminal of the first thin-film transistor is connected to the gate driving circuit, the input terminal of the first thin-film transistor is connected to the common voltage bus, and the output terminal of the first thin-film transistor is connected to the corresponding cascaded common voltage line.

[0017] In addition, to achieve the above objectives, the present invention also provides an array substrate, the array substrate including the pixel unit driving circuit described above.

[0018] In addition, to achieve the above objectives, the present invention also provides a display panel, the display panel comprising a color filter substrate, a liquid crystal layer and the array substrate, wherein the liquid crystal layer is located between the color filter substrate and the array substrate.

[0019] In addition, to achieve the above objectives, the present invention also provides a display, the display including a backlight module and the display panel, the backlight module being disposed on the back side of the display panel, the backlight module being used to provide a backlight source to the display panel.

[0020] This invention provides a pixel unit driving circuit, an array substrate, a display panel, and a display. The pixel unit driving circuit drives pixel units within the display panel. The pixel unit driving circuit includes a gate driving circuit and a switching unit. The switching unit is connected to a common voltage bus and the pixel driving unit. The switching unit is used to disconnect the connection between the common voltage bus and the pixel unit when the gate driving circuit stops outputting the gate driving signal, thereby generating a voltage drop at the port on the pixel unit connected to the common voltage bus. In this invention, by setting a switching unit between the gate driving circuit and the pixel unit, when the gate driving circuit stops outputting the gate driving signal, the switching unit can disconnect the connection between the common voltage bus and the pixel unit. This causes a voltage drop at the port on the pixel unit connected to the common voltage bus, ensuring that the voltage difference between the pixel voltage and the common voltage bus still matches the voltage difference corresponding to each grayscale level after the coupling is reduced. Compared to existing methods that require adjustment of the voltage for each grayscale level after the LCD panel is manufactured, this invention eliminates this operation, making the debugging process more convenient. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0022] Figure 1 This is a first structural block diagram of the pixel unit driving circuit in Embodiment 1 of the present invention;

[0023] Figure 2 This is a second structural block diagram of the pixel unit driving circuit in Embodiment 1 of the present invention;

[0024] Figure 3 This is a schematic diagram of the common unit row line structure connecting the pixel unit driving circuit in Embodiment 2 of the present invention;

[0025] Figure 4 This is a schematic diagram of the common voltage row line structure of the display area in Embodiment 2 of the present invention;

[0026] Figure 5 This is a circuit diagram of the switching unit in Embodiment 2 of the present invention;

[0027] Figure 6 This is a circuit diagram of the gate driving circuit of the pixel unit driving circuit in Embodiment 3 of the present invention;

[0028] Figure 7This is a voltage change diagram after capacitive coupling in the existing gate drive circuit of Embodiment 3 of the present invention;

[0029] Figure 8 This is a diagram showing the voltage change after capacitive coupling of the improved gate drive circuit in Embodiment 3 of the present invention.

[0030] Figure 9 This is a schematic diagram of the structure of an embodiment of the display panel of the present invention;

[0031] Figure 10 This is a schematic diagram of the structure of an embodiment of the display of this application.

[0032] Explanation of icon numbers:

[0033]

[0034] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0035] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0036] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0037] Example 1

[0038] Reference Figure 1 and Figure 2 An embodiment of the pixel unit driving circuit of the present invention is presented.

[0039] Reference Figure 1 , Figure 1 This is a first structural block diagram of the pixel unit driving circuit in Embodiment 1 of the present invention; as shown... Figure 1 As shown, in this embodiment, the pixel unit driving circuit is used to drive the pixel unit 1 in the display panel. The pixel unit driving circuit includes: a gate driving circuit 2 and a switching unit 3.

[0040] The switching unit 3 is connected to the common voltage bus Vcom and the pixel driving unit, respectively.

[0041] The switching unit 3 is used to disconnect the connection between the common voltage bus Vcom and the pixel unit 1 when the gate driving circuit 2 stops outputting the gate driving signal, so as to generate a voltage drop at the port of the pixel unit 1 connected to the common voltage bus Vcom.

[0042] It should be noted that the pixel unit driving circuit provided in this embodiment can be applied in scenarios where pixel unit 1 is driven. In this embodiment, the pixel unit 1 can be the smallest unit used for imaging. The display can realize image display through a number of pixel units 1. This embodiment does not limit the specific number of pixel units 1.

[0043] It is understood that the gate driving circuit 2 mentioned above can be a circuit used to drive the pixel unit 1. Each cascade in the display can correspond to a gate driving circuit 2. The corresponding cascaded pixel unit 1 can be connected to the cascaded gate driving circuit 2 through the gate driving line so that the gate driving signal output by the gate driving circuit 2 can be transmitted to the pixel unit 1 through the gate driving line to drive it, thereby achieving the purpose of display.

[0044] It should be understood that the aforementioned common voltage bus Vcom can be a wire used to provide a common voltage to the pixel unit 1. The voltage provided by the aforementioned common voltage bus Vcom can remain constant. The specific voltage value is not limited in this embodiment. The aforementioned pixel unit 1 can be connected to the switching unit 3 through a port connected to the common voltage bus Vcom.

[0045] In a specific implementation, when the gate driving circuit 2 stops outputting the gate driving signal, the aforementioned switch unit 3 indicates that the cascaded scanning has ended, and the connection between the common voltage bus Vcom and the pixel unit 1 can be disconnected. Since there is a coupling capacitor inside the pixel unit 1, a voltage drop occurs between the port connected to the common voltage bus Vcom and the gate driving line due to the capacitive coupling effect. This ensures that the voltage difference between the pixel voltage and the common voltage bus Vcom can still meet the voltage difference corresponding to each gray level after the coupling is reduced. Compared with the existing method of adjusting the voltage of each gray level after the LCD panel is produced, this embodiment does not require this operation, which simplifies the optical debugging process after the panel is produced and makes the operation more convenient.

[0046] Furthermore, considering that the switching unit 3 only needs to disconnect the common voltage bus Vcom from the pixel unit 1 when the gate driving circuit 2 stops outputting the gate driving signal, and that when the gate driving circuit 2 stops outputting the gate driving signal, both the gate driving terminal of this stage and the reset terminal of the previous stage of the gate driving circuit 2 are in a low-level state, refer to... Figure 2 , Figure 2 This is a second structural block diagram of the pixel unit driving circuit in Embodiment 1 of the present invention; furthermore, in this embodiment, the control terminal of the switching unit 3 is connected to the previous stage reset terminal of the gate driving circuit 2 or the current stage gate driving terminal of the gate driving circuit 2.

[0047] It should be noted that the control terminal of the aforementioned switch unit 3 can be used to control the connection state between the common voltage bus Vcom and the pixel unit 1 based on whether the gate driving circuit 2 outputs a gate driving signal. If the gate driving circuit 2 stops outputting the gate driving signal, the switch unit 3 disconnects the connection between the common voltage bus Vcom and the pixel unit 1. If the gate driving circuit 2 outputs the gate driving signal, the switch unit 3 keeps the common voltage bus Vcom and the pixel unit 1 connected.

[0048] Understandably, the upper-level reset terminal of the aforementioned gate drive circuit 2 can be connected to the upper-level gate drive circuit 2 to provide a reset signal to the upper-level gate drive circuit 2. At the same time, the upper-level reset terminal of the aforementioned gate drive circuit 2 can also be connected to the lower-level gate drive circuit 2 to provide an input signal to the lower-level gate drive circuit 2.

[0049] It should be understood that the gate driving terminal of the gate driving circuit 2 described above can transmit the gate driving signal to the pixel unit 1 through the gate driving line.

[0050] Therefore, in this embodiment, the above Figure 1 This can indicate the connection between the gate drive terminal of the gate drive circuit 2 and the switching unit 3, as described above. Figure 2 This can indicate the connection between the previous stage reset terminal of the gate drive circuit 2 and the switching unit 3. Of course, the above effect can also be achieved by connecting to the switching unit 3 through other terminals, and this embodiment does not impose any restrictions.

[0051] In a specific implementation, the aforementioned switch unit 3 can be connected to the previous stage reset terminal of the gate drive circuit 2 or the current stage gate drive terminal of the gate drive circuit 2 to achieve the purpose of disconnecting the common voltage bus Vcom from the pixel unit 1 when the gate drive signal is stopped. This eliminates the need to set up a new port, resulting in a simple structure that is easy to manufacture.

[0052] This embodiment provides a pixel unit driving circuit for driving pixel units 1 in a display panel. The pixel unit driving circuit includes a gate driving circuit 2 and a switching unit 3. The switching unit 3 is connected to a common voltage bus Vcom and the pixel driving unit. The switching unit 3 is used to disconnect the connection between the common voltage bus Vcom and the pixel unit 1 when the gate driving circuit 2 stops outputting the gate driving signal, so that a voltage drop occurs at the port of the pixel unit 1 connected to the common voltage bus Vcom. In this embodiment, by setting the switching unit 3 between the gate driving circuit 2 and the pixel unit 1, when the gate driving circuit 2 stops outputting the gate driving signal, the switching unit 3 can disconnect the connection between the common voltage bus Vcom and the pixel unit 1. As a result, a voltage drop occurs at the port of the pixel unit 1 connected to the common voltage bus Vcom, ensuring that the voltage difference between the pixel voltage and the common voltage bus Vcom still conforms to the voltage difference corresponding to each gray level after the coupling is reduced. This can effectively reduce the debugging process and improve production efficiency.

[0053] Example 2

[0054] Reference Figure 3 , Figure 4 and Figure 5 A second embodiment of the pixel unit driving circuit of the present invention is presented.

[0055] Reference Figure 3 , Figure 3 This is a schematic diagram of the common unit row line structure connecting the pixel unit driving circuit in Embodiment 2 of the present invention; as shown Figure 3 As shown, the switch unit 3 is connected to the previous stage reset terminal of the gate drive circuit 2 for illustration, but this is not a limitation.

[0056] In order to directly provide a common voltage to the corresponding cascaded pixel unit 1 through the switching unit 3, in this embodiment, the switching unit 3 is also connected to the common voltage row line VcomAA Line.

[0057] The switching unit 3 is used to disconnect the connection between the common voltage bus Vcom and the common voltage line VcomAA Line when the gate drive circuit 2 stops outputting the gate drive signal, so as to generate a voltage drop on the common voltage line VcomAA Line.

[0058] It should be noted that the aforementioned common voltage line VcomAA can be used to provide a common voltage for the corresponding cascaded pixel unit 1, such as... Figure 3As shown, the common voltage row line VcomAA Line can be connected to all pixel units 1 cascaded in the corresponding row, so as to transmit the common voltage in the common voltage bus Vcom to the common voltage row line VcomAA Line through the switching unit 3, and then transmit it to each pixel unit 1 through the common voltage row line VcomAA Line.

[0059] In a specific implementation, when the aforementioned switching unit 3 stops outputting the gate drive signal in the gate drive circuit 2, it can disconnect the connection between the common voltage bus Vcom and the common voltage row line VcomAA Line, so that a capacitive coupling effect occurs between the common voltage row line VcomAA Line and the pixel unit 1, and the voltage on the common voltage row line VcomAA Line decreases.

[0060] Furthermore, since the existing common voltage bus Vcom is directly connected to each pixel unit 1 of each cascade, in order to prevent other cascades from affecting the pixel unit 1 of this cascade, in this embodiment, the common voltage row line VcomAA Line is connected to the corresponding cascaded pixel unit 1, and the common voltage row lines VcomAA Lines within the display area are not connected to each other.

[0061] For ease of understanding, please refer to Figure 4 To explain, Figure 4 This is a schematic diagram of the common voltage row line structure of the display area in Embodiment 2 of the present invention; as shown Figure 4 As shown, the display area contains several pixel units 1, and the pixel units 1 in each cascade are connected through corresponding common voltage lines VcomAA Line. Figure 4 The diagram shows five common voltage lines, VcomAA Line: VcomAA Line1, VcomAA Line2, VcomAA Line3, VcomAA Line(n-1), and VcomAA Line(n). Figure 4 It can be seen that the common voltage lines VcomAA Line inside the display area are no longer connected as a whole, but are independent of each line. Each line of the common voltage line VcomAA Line is connected to the corresponding cascaded switch unit 3.

[0062] In the specific implementation, the common voltage row line VcomAA Line is connected to the corresponding cascaded pixel unit 1, and the common voltage row lines VcomAA Lines in the display area are not connected to each other, thereby preventing interference between each cascaded unit.

[0063] Furthermore, in order to both realize the corresponding function of switch unit 3 and place switch unit 3 inside the display panel, refer to... Figure 5 , Figure 5 This is a circuit diagram of the switching unit in Embodiment 2 of the present invention. Figure 5 As shown, in this embodiment, the switching unit 3 includes: a first thin-film transistor T1;

[0064] The control terminal of the first thin-film transistor T1 is connected to the gate driving circuit 2, the input terminal of the first thin-film transistor T1 is connected to the common voltage bus Vcom, and the output terminal of the first thin-film transistor T1 is connected to the corresponding cascaded common voltage line VcomAA Line.

[0065] In a specific implementation, when the gate driving circuit 2 outputs a gate driving signal, the control terminal of the first thin-film transistor T1 becomes high, the input and output terminals of the first thin-film transistor T1 are connected, and the common voltage bus Vcom and the common voltage line VcomAA Line remain connected; when the gate driving circuit 2 stops outputting the gate driving signal, the control terminal of the first thin-film transistor T1 becomes low, the input and output terminals of the first thin-film transistor T1 are turned on, and the common voltage bus Vcom and the common voltage line VcomAA Line are disconnected.

[0066] In this embodiment, when the first thin-film transistor T1 stops outputting the gate drive signal in the gate drive circuit 2, the connection between the common voltage bus Vcom and the common voltage row line VcomAA Line can be disconnected, so that the common voltage row line VcomAA Line and the pixel unit 1 will have a capacitive coupling effect, the voltage on the common voltage row line VcomAA Line will decrease, and at the same time, it will be connected to the corresponding cascaded pixel unit 1 through the common voltage row line VcomAA Line. Moreover, the common voltage row lines VcomAA Line in the display area will not be connected to each other, thereby preventing the influence between each cascaded layer.

[0067] Example 3

[0068] Reference Figure 6 , Figure 7 and Figure 8 Embodiment 3 of the pixel unit driving circuit of the present invention is presented.

[0069] Reference Figure 6 , Figure 6 This is a circuit diagram of the gate driving circuit of the pixel unit driving circuit in Embodiment 3 of the present invention; to facilitate understanding of the structure of the gate driving circuit 2 in this embodiment, as shown... Figure 6 As shown, in this embodiment, the gate driving circuit 2 includes a first capacitor C1 and second to tenth thin-film transistors.

[0070] The control terminal of the second thin-film transistor T2 is connected to its input terminal. The input terminal of the second thin-film transistor T2 is also connected to the input terminal of the gate drive circuit 2. The input terminal of the gate drive circuit 2 is connected to the reset terminal Cout of the preceding stage of the gate drive circuit 2. The output terminal of the second thin-film transistor T2 is connected to the first terminal of the first capacitor C1, the control terminal of the third thin-film transistor T3, and the control terminal of the fourth thin-film transistor T4. The input terminal of the third thin-film transistor T3 is connected to the input terminal of the fourth thin-film transistor T4. The input terminal of the third thin-film transistor T3 is also connected to the first clock signal input terminal CLK of the gate drive circuit 2. The output terminal of transistor T3 is connected to the previous stage reset terminal Cout of gate drive circuit 2. The previous stage reset terminal Cout of gate drive circuit 2 is connected to the reset terminal Reset of the previous stage gate drive circuit 2 and the input terminal Input of the next stage gate drive circuit 2. The previous stage reset terminal Cout of gate drive circuit 2 is connected to the control terminal of the first thin film transistor T1. It should be emphasized that when the previous stage reset terminal Cout of gate drive circuit 2 is at a low level, the reset terminal Reset of the next stage gate drive circuit 2 is also at a low level. Therefore, the control terminal of the first thin film transistor T1 can also be connected to the reset terminal Reset of gate drive circuit 2.

[0071] The output terminal of the second thin-film transistor T2 is also connected to the input terminals of the fifth thin-film transistor T5 and the sixth thin-film transistor T6. The control terminal of the fifth thin-film transistor T5 is connected to the reset terminal Reset of the gate drive circuit 2. The reset terminal Reset of the gate drive circuit 2 is connected to the previous stage reset terminal Cout of the previous stage gate drive circuit 2. The output terminal of the fifth thin-film transistor T5 is connected to the output terminal of the sixth thin-film transistor T6. The output terminal of the fifth thin-film transistor T5 is also connected to the low-voltage terminal VGL of the gate drive circuit 2. The control terminal of the sixth thin-film transistor T6 is connected to the output terminal of the ninth thin-film transistor T9, the input terminal of the tenth thin-film transistor T10, and the control terminal of the seventh thin-film transistor T7. The control terminal of the ninth thin-film transistor T9 is connected to the input terminal of the ninth thin-film transistor T9. Furthermore, the input terminal of the ninth thin-film transistor T9 is also connected to the second clock signal terminal CLKB of the gate drive circuit 2; the output terminal of the tenth thin-film transistor T10 is connected to the low-voltage terminal VGL of the gate drive circuit 2; the control terminal of the tenth thin-film transistor T10 is connected to the first terminal of the first capacitor C1; the input terminal of the seventh thin-film transistor T7 is connected to the input terminal of the eighth thin-film transistor T8 and the output terminal of the fourth thin-film transistor T4; the output terminal of the seventh thin-film transistor T7 is connected to the output terminal of the eighth thin-film transistor T8 and the low-voltage terminal VGL of the gate drive circuit 2; the control terminal of the eighth thin-film transistor T8 is connected to the reset terminal Reset of the gate drive circuit 2; and the second terminal of the first capacitor C1 is connected to the output terminal of the fourth thin-film transistor T4 and the gate drive terminal Gout of the gate drive circuit 2.

[0072] according to Figure 6It can be seen that when the input terminal Input of the gate driving circuit 2 receives a high level, the second thin-film transistor T2 is turned on, and then the third thin-film transistor T3, the fourth thin-film transistor T4, and the tenth thin-film transistor T10 are turned on. The first clock signal terminal CLK of the gate driving circuit 2 transmits the received high level to the previous stage reset terminal Cout of the gate driving circuit 2 and the current stage gate driving terminal Gout of the gate driving circuit 2. The first thin-film transistor T1 is turned on, and the first thin-film transistor T1 connects the common voltage bus Vcom with the common voltage row line VcomAA inside the display area. Line is turned on; when the second clock signal terminal CLBK of the gate drive circuit 2 receives a high level, the ninth thin film transistor T9 is turned on, and then the sixth thin film transistor T6 and the seventh thin film transistor T7 connect the circuit to the low voltage terminal VGL of the gate drive circuit 2. When the reset terminal Reset of the gate drive circuit 2 receives a high level, the fifth thin film transistor T5 and the eighth thin film transistor T8 are turned on; when the first clock signal terminal CLK of the gate drive circuit 2 stops inputting the gate drive signal, the previous stage reset terminal Cout of the gate drive circuit 2 is at a low level, the first thin film transistor T1 is turned off, the common voltage bus Vcom is disconnected from the corresponding cascaded common voltage line VcomAA Line, and then the voltage on the common voltage line VcomAA Line drops because it no longer maintains a constant voltage.

[0073] Furthermore, considering that the relevant effect can be achieved simply by causing a voltage drop on the common voltage line VcomAA Line, in this embodiment, the difference between the first voltage drop and the second voltage drop is within a preset range. The first voltage drop is the voltage drop between the pixel unit 1 and the gate driving line connected to the gate driving terminal of this stage, and the second voltage drop is the voltage drop between the common voltage line VcomAA Line and the gate driving line.

[0074] It should be noted that the above preset range can be set according to needs, and this embodiment does not impose any restrictions.

[0075] In a specific implementation, when a cascaded gate drive circuit 2 is turned off, since there are coupling capacitors between the gate drive line and the pixel unit 1, and between the gate drive line and the common voltage row line VcomAA Line, and the common voltage row line VcomAA Line is no longer directly connected to the common voltage bus Vcom and therefore no longer maintains a constant voltage, both the common voltage row line VcomAA Line and the pixel voltage will experience voltage drop due to the capacitive coupling effect.

[0076] Furthermore, in order to ensure that the voltage drop between the pixel voltage and the common voltage row line VcomAA Line is the same, in this embodiment, the capacitance value of the first coupling capacitor between the gate driving line and the pixel unit 1 is the same as the capacitance value of the second coupling capacitor between the gate driving line and the common voltage row line VcomAA Line.

[0077] For ease of understanding, please refer to Figure 7 and Figure 8 To explain, Figure 7 This is a voltage change diagram after capacitive coupling in the existing gate drive circuit of Embodiment 3 of the present invention. Figure 8 This is a diagram showing the voltage change after capacitive coupling of the improved gate drive circuit in Embodiment 3 of the present invention.

[0078] like Figure 7 As stated above, SD is the source drive voltage, Vcom is the voltage of the common voltage bus, Gate is the gate drive voltage, and PXL is the pixel voltage. Figure 7 It can be observed that when the pixel voltage decreases, the voltage Vcom on the common voltage bus remains constant.

[0079] like Figure 8 As shown, SD is the source drive voltage, VcomAA is the voltage of the common voltage row line, Gate is the gate drive voltage, and PXL is the pixel voltage. Figure 7 It can be observed that when the pixel voltage decreases, since the capacitance value of the coupling capacitor between the gate driving line and the pixel unit 1 inside a single pixel unit 1 is the same as the capacitance value of the coupling capacitor between the gate driving line and the common voltage row line VcomAALine, the pixel voltage PXL and the voltage VcomAA on the common voltage row line can be kept the same, and the voltage difference between the two remains constant.

[0080] It should be emphasized that the capacitance value of the coupling capacitor between the gate driving line and pixel unit 1 and the capacitance value of the coupling capacitor between the gate driving line and the common voltage row line VcomAA Line can both be realized by the capacitance simulation function built into the panel drawing software. Of course, it can also be realized by other methods, and this embodiment does not impose any limitations.

[0081] In this embodiment, by keeping the capacitance value of the coupling capacitor between the gate driving line and the pixel unit 1 the same as the capacitance value of the coupling capacitor between the gate driving line and the common voltage row line VcomAA Line, the pixel voltage and the voltage drop on the common voltage row line VcomAA Line can be the same, which has a better effect.

[0082] Furthermore, this application also proposes an array substrate 70, which includes the aforementioned pixel unit driving circuit.

[0083] Since this array substrate 70 adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0084] Furthermore, this application also proposes a display panel, referring to... Figure 9 , Figure 9 This is a schematic diagram of the structure of a display panel embodiment of the present invention. The display panel includes the array substrate 70, the color filter substrate 90 disposed opposite to the array substrate 70, and the liquid crystal layer 80 sandwiched between the array substrate 70 and the color filter substrate 90.

[0085] Furthermore, embodiments of this application also propose a display, referring to... Figure 10 , Figure 10 This is a schematic diagram of the structure of a display embodiment of the present application. The display includes a display panel 100 as described above and a backlight module 110. The backlight module 110 is disposed on the back side of the display panel 100 and is used to provide a backlight source to the display panel 100.

[0086] Since this display adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0087] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0088] Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0089] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0090] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, the user should consider such a combination of technical solutions to be non-existent and not within the scope of protection claimed in this application.

Claims

1. A pixel unit driving circuit, wherein the pixel unit driving circuit is used to drive pixel units in a display panel, characterized in that, The pixel unit driving circuit comprises a gate driving circuit and a switch unit; The switch unit is connected with the common voltage bus and the pixel unit respectively; The switch unit is used for disconnecting the connection between the common voltage bus and the pixel unit when the gate driving circuit stops outputting the gate driving signal, so that a voltage drop is generated on a port of the pixel unit connected with the common voltage bus; wherein, The control end of the switch unit is connected with the next-stage reset end of the gate driving circuit, the input end of the switch unit is connected with the common voltage bus, and the output end of the switch unit is connected with the common voltage row line. The gate driving circuit comprises second to tenth thin film transistors, and the gate driving circuit is configured to enable the second thin film transistor to conduct under the driving of a high level, so as to switch the third thin film transistor, the fourth thin film transistor and the tenth thin film transistor from the off state to the on state, trigger the high level provided by the first clock signal end to flow to the control end of the switch unit and the gate driving end of the current stage via the third thin film transistor and the fourth thin film transistor in the on state, and trigger the switch unit to conduct the common voltage bus and the common voltage row line under the driving of the high level until the ninth thin film transistor triggers the sixth thin film transistor and the seventh thin film transistor to lower the circuit level under the driving of the high level provided by the second clock signal end, so as to enable the sixth thin film transistor and the seventh thin film transistor to lower the high level connected with the second thin film transistor and the gate driving end of the current stage under the driving of the high level provided by the reset end of the current stage, stop outputting the gate driving signal representing the high level to the switch unit, and determine that the voltage drop is generated on the common voltage row line when the switch unit disconnects the connection between the common voltage bus and the common voltage row line; wherein, The capacitance value of the first coupling capacitor between the gate driving line and the pixel unit is the same as the capacitance value of the second coupling capacitor between the gate driving line and the common voltage row line, so that the difference between the first voltage drop and the second voltage drop is within a preset range, the first voltage drop is the voltage drop between the pixel unit and the gate driving line connected with the gate driving end of the current stage, and the second voltage drop is the voltage drop between the common voltage row line and the gate driving line.

2. The pixel unit driving circuit according to claim 1, wherein The control end of the switch unit is connected with the next-stage reset end of the gate driving circuit or the gate driving end of the current stage of the gate driving circuit.

3. The pixel unit driving circuit according to claim 1 or 2, wherein The switch unit is also connected with the common voltage row line. The switch unit is used for disconnecting the connection between the common voltage bus and the common voltage row line when the gate driving circuit stops outputting the gate driving signal, so that a voltage drop is generated on the common voltage row line.

4. The pixel unit driving circuit according to claim 3, wherein The switch unit comprises a first thin film transistor. The control end of the first thin film transistor is connected with the gate driving circuit, the input end of the first thin film transistor is connected with the common voltage bus, and the output end of the first thin film transistor is connected with the corresponding cascaded common voltage row line.

5. An array substrate, characterized by, The array substrate comprises the pixel unit driving circuit according to any one of claims 1 to 4.

6. A display panel, characterized by, The display panel comprises a color filter substrate, a liquid crystal layer and the array substrate according to claim 5, and the liquid crystal layer is located between the color filter substrate and the array substrate.

7. A display, characterized by The display comprises the display panel according to claim 6 and a backlight module, the backlight module is arranged on the back of the display panel, and the backlight module is used for providing a backlight source for the display panel.

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