Method of manufacturing a semiconductor element

Abstract

A method for manufacturing a semiconductor device includes forming a mask layer on a stack structure on a substrate, wherein the mask layer has a first region and a second region, the first region has a patterned structure; etching an opening on the stack structure through the patterned structure, wherein etching residues are accumulated on the second region; forming a barrier layer to cover the mask layer, inner walls of the opening and the etching residues; forming a protection layer on the barrier layer; removing a portion of the protection layer, a portion of the barrier layer and the etching residues to expose the mask layer; and etching the mask layer and portions of the protection layer and the barrier layer outside the opening to expose the stack structure. The method reduces the structural loss of the semiconductor device during the manufacturing process and improves the performance of the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing semiconductor devices. Background Technology

[0002] As semiconductor devices shrink in size, their manufacturing technology advances accordingly. Semiconductor processes involve multiple deposition and etching steps, and precise control of material placement and removal is crucial during the alternating deposition and etching processes to avoid impacting subsequent processes. For example, residual material from etching may accumulate in other parts of the semiconductor device. Failure to precisely remove this residue will affect subsequent manufacturing processes and further reduce the performance of the manufactured semiconductor device.

[0003] Therefore, how to propose a method for manufacturing semiconductor devices that can solve the above problems is one of the issues that the industry is currently eager to invest research and development resources to address. Summary of the Invention

[0004] In view of this, one objective of this disclosure is to provide a method for manufacturing semiconductor devices that can effectively solve the above-mentioned problems.

[0005] This disclosure relates to a method of manufacturing a semiconductor device comprising: forming a mask layer on a stacked structure located on a substrate, wherein the mask layer has a first region and a second region, the first region having a patterned structure; etching an opening on the stacked structure through the patterned structure, wherein etching residue is deposited on the second region; forming a barrier layer to cover the mask layer, the inner wall of the opening, and the etching residue; forming a protective layer on the barrier layer; removing a portion of the protective layer, a portion of the barrier layer, and the etching residue to expose the mask layer; and etching the portions of the mask layer, the protective layer, and the barrier layer outside the opening to expose the stacked structure.

[0006] In some current embodiments, the substrate has contacts that are exposed on the upper surface of the substrate, and the contacts are located at the bottom of the openings by etching openings on the stacked structure through a patterned structure.

[0007] In some current embodiments, the stacked structure includes a metal layer, an insulating layer, a first nitride layer, an oxide layer, and a second nitride layer stacked sequentially on a substrate, and the step of etching openings on the stacked structure by patterning a structure exposes at least one surface of each of the metal layer, the insulating layer, the first nitride layer, the oxide layer, and the second nitride layer.

[0008] In some current embodiments, the step of forming a barrier layer to cover the masking layer, the inner wall of the opening, and the etching residue results in the barrier layer covering the metal layer, the insulating layer, the first nitride layer, the oxide layer, the second nitride layer, and the portion of the contact located within the opening.

[0009] In some current embodiments, the step of etching the portion of the mask layer and the portion of the protective layer and barrier layer located outside the opening is to fully expose the surface of the second nitride layer.

[0010] In some current implementations, the steps of removing portions of the protective layer, the barrier layer, and the etching residue are performed using a chemical mechanical polishing process.

[0011] In some current implementations, the step of forming a barrier layer to cover the masking layer, the inner wall of the opening, and the etching residue includes conformally forming the barrier layer on the inner wall of the opening.

[0012] In some current implementations, the step of forming a protective layer on a barrier layer includes conformally forming the protective layer on the barrier layer.

[0013] In some current implementations, the steps of removing portions of the protective layer, portions of the barrier layer, and etching residue expose the surface of the masking layer away from the stacked structure.

[0014] In some current implementations, the steps of removing portions of the protective layer, the barrier layer, and the etching residue make the surface of the mask layer flush with the first and second regions.

[0015] In summary, the method for manufacturing semiconductor devices disclosed herein employs a two-step removal process to reduce the impact of etching residues accumulated on the mask layer due to etching openings on mask layer removal. First, etching residues are removed using a chemical mechanical polishing (CMP) process, and the mask layer thickness is made flush, allowing for better control of mask layer removal via isotropic etching in the second step. Furthermore, the barrier layer and protective layer protect the stacked structure from structural erosion during the aforementioned removal process. Simultaneously, the barrier layer and protective layer also increase the stability of the stacked structure. For these reasons, the semiconductor device manufactured using this method can maintain a more complete and robust stacked structure, resulting in a semiconductor device with superior performance. Attached Figure Description

[0016] The best understanding of this disclosure can be obtained by reading it in conjunction with the accompanying figures, as described in the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0017] Figure 1This is a schematic diagram illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0018] Figure 2A This is a schematic cross-sectional view of one stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0019] Figure 2B This is a schematic cross-sectional view of one stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0020] Figure 2C This is a schematic cross-sectional view of one stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0021] Figure 2D This is a schematic cross-sectional view of one stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 2E This is a schematic cross-sectional view of one stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0023] Figure 2F This is a schematic cross-sectional view of one stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or instances of various features for implementing the provided objectives. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0025] Additionally, for simplicity, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another (other) element or feature, as shown in the figures. These spatial relative terms are intended to cover different orientations of elements in use or operation, in addition to those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0026] As used herein, “approximately,” “about,” “close to,” or “substantially” generally means falling within twenty percent, or ten percent, or five percent of a given value or range. The numerical values ​​given herein are approximate, and the terms used, such as “approximately,” “about,” “close to,” or “substantially,” can be inferred unless explicitly stated otherwise.

[0027] Figure 1 This is a schematic diagram illustrating a method M1 for manufacturing a semiconductor device according to some embodiments of this disclosure. Please refer to... Figure 1 This disclosure relates to a method M1 for manufacturing a semiconductor device, comprising forming a mask layer on a stacked structure located on a substrate, wherein the mask layer has a first region and a second region, the first region having a patterned structure (step S101); etching an opening on the stacked structure through the patterned structure, wherein etching residue accumulates on the second region (step S102); forming a barrier layer to cover the mask layer, the inner wall of the opening, and the etching residue (step S103); forming a protective layer on the barrier layer (step S104); removing a portion of the protective layer, a portion of the barrier layer, and the etching residue to expose the mask layer (step S105); and etching the portions of the mask layer, the protective layer, and the barrier layer located outside the opening to expose the stacked structure (step S106).

[0028] Figure 2A This is a schematic cross-sectional view of one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2A The diagram illustrates a substrate 110 and a stacked structure 120 situated on the substrate 110. The stacked structure 120 is composed of multiple layers sequentially stacked on top of the substrate 110. In some embodiments, the stacked structure 120 includes a metal layer 122, an insulating layer 124, a first nitride layer 126a, an oxide layer 128, and a second nitride layer 126b sequentially stacked on the substrate 110. However, in other embodiments, the stacked structure 120 may be composed of other materials or other different multiple layers. Furthermore, in some embodiments, the substrate 110 has contacts 112 exposed on the upper surface of the substrate 110. Figure 2A In the illustrated embodiment, the stacked structure 120 on the substrate 110 covers a plurality of contacts 112. However, the contacts 112 can be formed at any location on the substrate 110 as required.

[0029] Figure 2AIn the drawing method M1, a mask layer is formed on a stacked structure located on a substrate, wherein the mask layer has a first region and a second region, and the first region has a patterned structure in step S101. Specifically, the mask layer 130 completely covers the top surface of the stacked structure 120, but this disclosure is not limited thereto. The mask layer 130 may partially cover only the top surface of the stacked structure 120 as needed. The first region 132 and the second region 134 of the mask layer 130 may be distinguished by whether or not they have a patterned structure. Specifically, the patterned structure may consist of multiple openings (as described later). Figure 2B (Opening 140). The patterning of the mask layer 130 can be performed by any suitable means, such as photolithography.

[0030] Figure 2B This is a schematic cross-sectional view of one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2B In step S102 of the illustrated method M1, an opening is etched into the stacked structure by patterning a structure, wherein etching residue accumulates on a second region. Specifically, the opening 140 is extended into the stacked structure 120 by the etching process, and in the illustrated embodiment, step S102 causes the contacts 112 to be located at the bottom of the opening 140. The location of the opening 140 may correspond to the location of the contacts 112 in the substrate 110, and the surface of the contacts 112 is fully exposed by etching the opening 140; however, the location of the opening 140 may also be adjusted to other locations as needed to partially expose or not expose the contacts 112. Continuing with the aforementioned multiple layers of the stacked structure 120, in some embodiments, step S102 causes at least one surface of each of the metal layer 122, the insulating layer 124, the first nitride layer 126a, the oxide layer 128, and the second nitride layer 126b to be exposed. Specifically, the opening 140 completely penetrates the stacked structure 120, exposing a portion of the substrate 110 and the contact 112, and the inner wall of the opening 140 exposes the surfaces of multiple layers of the stacked structure 120.

[0031] Continue to refer to Figure 2B After etching the opening 140, the semiconductor material left over from the etching process will accumulate in the second region 134, forming etching residue 150. The mask layer 130 of the second region 134 is partially or completely covered by the etching residue 150. The accumulation of etching residue 150 will hinder the removal of the mask layer 130. If it is necessary to remove the mask layer 130 without damaging the stacked structure 120, the etching residue 150 must be removed first.

[0032] Figure 2C This is a schematic cross-sectional view of one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2CThe illustration describes step S103 in method M1, which involves forming a barrier layer to cover the mask layer, the inner wall of the opening, and etching residue. In some embodiments, step S103 includes conformally forming a barrier layer 160 on the inner wall of the opening 140, but this disclosure is not limited thereto. Furthermore, in Figure 2C In the illustrated embodiment, the barrier layer 160 is conformally formed along the top surface of the mask layer 130, the inner wall of the opening 140, and the surface of the etch residue 150. Furthermore, step S103 causes the barrier layer 160 to cover the metal layer 122, the insulating layer 124, the first nitride layer 126a, the oxide layer 128, the second nitride layer 126b, and the portion of the contact 112 located within the opening 140. Furthermore, in Figure 2C In the illustrated embodiment, because opening 140 exposes contact 112, barrier layer 160 also covers contact 112 and a portion of the substrate 110 surface, but this disclosure is not limited thereto. If opening 140 does not expose contact 112, then barrier layer 160 will only cover the portion of substrate 110 surface exposed by opening 140. The function of barrier layer 160 is to better secure the different material layers below and above barrier layer 160. For example, barrier layer 160 can strengthen the connection between protective layer 170 (mentioned below) and the multiple layers of stacked structure 120, masking layer 130, and contact 112.

[0033] Figure 2D This is a schematic cross-sectional view of one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2D The illustration shows step S104 of method M1, which involves forming a protective layer on a barrier layer. In some embodiments, step S104 includes conformally forming a protective layer 170 on a barrier layer 160. However, in other embodiments, the protective layer 170 may also be partially formed on the barrier layer 160 as needed. The purpose of the protective layer 170 is to protect the structure covered by the protective layer 170 from erosion during the etching process. However, depending on the thickness of the protective layer 170, portions of the barrier layer 160 and the protective layer 170 may still be removed during the etching process. In some embodiments, the protective layer 170 may also be conformally formed directly on the mask layer 130, the etching residue 150, and the inner wall of the opening 140. Furthermore, the inner wall of the opening 140 covered by the barrier layer 160 and the protective layer 170 may have better support, and the stacked structure 120 separated by the opening 140 will be less prone to tipping over.

[0034] Figure 2E This is a schematic cross-sectional view of one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2EThe illustration shows step S105 in method M1, which involves removing a portion of the protective layer, a portion of the barrier layer, and etching residue to expose the masking layer. In step S105, the etching residue 150 covering the masking layer 130 is removed. In some embodiments, step S105 is performed using a chemical mechanical polishing process, but this disclosure is not limited thereto. Specifically, any method that can achieve partial removal of the etching residue 150 without damaging the masking layer 130 and the stacked structure 120 and substrate 110 located below the masking layer 130 can be used. The reason for removing the etching residue 150 first in step S105 is that if the etching residue 150 and the masking layer 130 are removed directly by isotropic etching, the local area of ​​the masking layer 130 covered by the etching residue 150 cannot be completely removed due to the coverage of the etching residue 150. Therefore, step S105 uses a chemical mechanical polishing process to polish the surface of the masking layer 130 to remove the etching residue 150. In some embodiments, step S105 exposes the surface of the mask layer 130 away from the stack structure 120. Specifically, in addition to removing etch residue 150, the chemical mechanical polishing process may also cause partial removal of the mask layer 130; however, the stack structure 120 is not exposed by the chemical mechanical polishing process. In some embodiments, step S105 flushes the surface of the mask layer 130 with the surface of the first region 132 and the second region 134. The purpose of step S105 is to remove the mask layer 130 more completely in the subsequent removal step.

[0035] Figure 2F This is a schematic cross-sectional view of one stage of a method M1 for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2F The step S106 in method M1 involves etching the portion of the mask layer, protective layer, and barrier layer located outside the opening to expose the stacked structure. Specifically, step S106 can be performed by isotropic etching, where the mask layer 130, protective layer 170, and barrier layer 160 are removed in equal amounts until a portion of the stacked structure 120 is exposed. In some embodiments, step S106 completely exposes the surface of the second nitride layer 126b (i.e., the mask layer 130 is completely removed). Thereby, Figure 2F The semiconductor element 100 shown in the figure is then manufactured.

[0036] The detailed description of the specific embodiments disclosed above clearly shows that the method for manufacturing semiconductor devices disclosed herein removes the mask layer in two steps to reduce the impact of etching residues accumulated on the mask layer due to etching openings on the mask layer removal. The etching residues are first removed by a chemical mechanical polishing process, and the thickness of the mask layer is made flush, so that the removal of the mask layer can be better controlled by an isotropic etching process in the second step of mask layer removal. Furthermore, the protection of the barrier layer and the protective layer can prevent structural erosion of the stacked structure during the aforementioned removal process. At the same time, the barrier layer and the protective layer can also increase the stability of the stacked structure. For the foregoing reasons, the semiconductor device manufactured by this method can maintain a more complete and stable stacked structure, resulting in a semiconductor device with better performance.

[0037] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and replacements can be made herein without departing from the spirit and scope of this disclosure.

[0038] [Symbol Explanation]

[0039] 100: Semiconductor components

[0040] 110: Substrate

[0041] 112:Contact

[0042] 120: Stacked structure

[0043] 122: Metal layer

[0044] 124: Insulation layer

[0045] 126a, 126b: Nitrided layers

[0046] 128: Oxide layer

[0047] 130: Mask layer

[0048] 132: Area 1

[0049] 134: Second Area

[0050] 140: Opening

[0051] 150: Etching Residue

[0052] 160: Barrier Layer

[0053] 170: Protective layer

[0054] M1: Method

[0055] S101, S102, S103, S104, S105, S106: Steps.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A masking layer is formed on a stacked structure located on a substrate, wherein the masking layer has a first region and a second region, the first region having a patterned structure; Multiple openings are etched on the stacked structure through the patterned structure, wherein etching residues accumulate on the second region; A barrier layer is formed to cover the masking layer, the inner walls of the openings, and the etching residue; A protective layer is formed on the barrier layer; A portion of the protective layer, a portion of the barrier layer, and the etching residue are removed to expose the masking layer, wherein the step of removing the portion of the protective layer, the portion of the barrier layer, and the etching residue is performed using a chemical mechanical polishing process. as well as The portion of the masking layer, the protective layer, and the barrier layer located outside the openings is etched to expose the stacked structure.

2. The method of manufacturing a semiconductor element according to claim 1, wherein the substrate has a plurality of contacts exposed on the upper surface of the substrate, and the step of etching the openings on the stacked structure by the patterned structure such that the contacts are respectively located at the bottom of the openings.

3. The method of manufacturing a semiconductor device according to claim 2, wherein the stacked structure comprises a metal layer, an insulating layer, a first nitride layer, an oxide layer and a second nitride layer sequentially stacked on the substrate, and the step of etching the openings on the stacked structure by the patterned structure exposes at least one surface of each of the metal layer, the insulating layer, the first nitride layer, the oxide layer and the second nitride layer.

4. The method of manufacturing a semiconductor element according to claim 3, wherein the step of forming the barrier layer to cover the mask layer, the inner walls of the openings and the etching residue causes the barrier layer to cover the metal layer, the insulating layer, the first nitride layer, the oxide layer, the second nitride layer and the portions of the contacts located within the openings.

5. The method of manufacturing a semiconductor element according to claim 3, wherein the step of etching the portion of the mask layer and the portion of the protective layer and the barrier layer located outside the openings is to fully expose the surface of the second nitride layer.

6. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the barrier layer to cover the mask layer, the inner walls of the openings and the etching residue comprises conformally forming the barrier layer on the inner walls of the openings.

7. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the protective layer on the barrier layer comprises conformally forming the protective layer on the barrier layer.

8. The method of manufacturing a semiconductor element according to claim 1, wherein the step of removing the portion of the protective layer, the portion of the barrier layer, and the etching residue exposes the surface of the mask layer away from the stacked structure.

9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of removing the portion of the protective layer, the portion of the barrier layer, and the etching residue causes the surface of the mask layer to be flush with the first region and the second region.

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