Defect detection based on region of interest

Abstract

A system and method are provided to assist in defect detection on semiconductor samples. The method includes obtaining a first graph providing information about a plurality of areas of interest (CAs) to be inspected on a die; creating a plurality of bounding rectangles (BRs) enclosing the plurality of CAs; and compressing the plurality of BRs into a compressed set of rectangles to satisfy a predefined inspection capacity while attempting to minimize the non-CA area enclosed by the compressed set of rectangles, thereby generating a second graph providing information about the compressed set of rectangles. The compression includes constructing an R-tree structure representing the plurality of BRs and the compressed rectangles, and selecting a set of nodes from the R-tree structure based on the predefined inspection capacity, the set of nodes representing the compressed set of rectangles. The second graph can be used to filter a defect map indicating the distribution of defect candidates on the die.

Description

Technical Field

[0001] The disclosed subject matter relates generally to the field of semiconductor sample inspection, and more particularly, to defect detection based on areas of interest (CAs). Background Art

[0002] The current demand for high density and high performance associated with ultra-large-scale integration of manufactured devices requires submicron features, higher transistor and circuit speeds, and increased reliability. As semiconductor processes advance, pattern sizes (such as liner widths) and other types of critical dimensions continue to shrink. These demands require device features to be formed with high precision and uniformity, which in turn requires careful monitoring of the manufacturing process, including automated inspection of the devices while they are still in the form of semiconductor wafers.

[0003] Runtime inspection can employ a two-stage process, for example, inspecting a sample and then reviewing sample locations for potential defects. Inspection generally involves generating a specific output (e.g., an image, a signal, etc.) for the sample by directing light or electrons onto a wafer and detecting the light or electrons from the wafer. During the first stage, the surface of the sample is inspected at high speed and relatively low resolution. Defect detection is typically performed by applying a defect detection algorithm to the inspection output. A defect map is generated to display suspected locations on the sample with a high probability of defects. During the second stage, at least some of the suspected locations are more thoroughly analyzed at relatively high resolution.

[0004] The inspection can be performed using a non-destructive testing tool during or after the sample is manufactured. Various non-destructive testing tools include, as non-limiting examples, scanning electron microscopes, atomic force microscopes, optical inspection tools, and the like. In some cases, these two stages can be performed by the same inspection tool, and in other cases, the two stages are performed by different inspection tools.

[0005] Inspection processes are used at various steps during semiconductor manufacturing to detect defects on samples and improve yield. Often, the goal of inspection is to provide high sensitivity for detecting defects of interest (which, if not corrected, could cause the final device to fail to meet required performance or malfunction, negatively impacting yield) while also improving the efficiency of rejecting false positives / interference and noise based on the inspection results.

[0006] Inspection effectiveness can be enhanced by using auxiliary processes. Regions of interest (ROIs) are specific areas of a sample that require special inspection. In some cases, ROIs can be used to distinguish areas of the sample that will be inspected differently. ROIs can also facilitate defect detection and noise suppression. Summary of the Invention

[0007] According to certain aspects of the presently disclosed subject matter, a computerized system for assisting defect detection on a semiconductor sample is provided, the system comprising a processing and memory circuit system (PMC) configured to: obtain a first graph providing information of a plurality of areas of interest (CAs) to be inspected on a die of the semiconductor sample; create a plurality of bounding rectangles (BRs) enclosing the plurality of CAs; and compress the plurality of BRs into a compressed set of rectangles to satisfy a predefined inspection capacity while attempting to minimize the non-CA area enclosed by the compressed set of rectangles, thereby producing a second graph providing information of the compressed set of rectangles, wherein the compression comprises: constructing an R-tree structure comprising a bottom layer and one or more upper layers, the bottom layer comprising a plurality of leaf nodes representing the plurality of BRs, each of the one or more upper layers comprising one or more non-leaf nodes, each given non-leaf node representing a compressed rectangle enclosing one or more rectangles represented by one or more child nodes of the given non-leaf node; and selecting a set of nodes from the leaf nodes and non-leaf nodes of the R-tree structure based on the predefined inspection capacity, the set of nodes representing the compressed set of rectangles; wherein the second graph can be used to filter a defect map indicating a distribution of defect candidates on the die.

[0008] In addition to the features described above, the system according to this aspect of the disclosed subject matter may include one or more of the features (i) to (x) listed below, in any desired combination or arrangement that is technically possible:

[0009] (i). The first graph may be derived based on the design data of the die.

[0010] (ii). Multiple BRs may be created by dividing the first image into multiple grid cells according to a grid, thereby generating multiple grid cells each containing at least one CA or a portion thereof, and, for each grid cell in the multiple grids, approximating a bounding rectangle (BR) surrounding the at least one CA or a portion thereof in the grid cell, thereby generating multiple BRs corresponding to the multiple grid cells.

[0011] The R-tree structure can be constructed by sequentially inserting multiple BRs into the bottom layer according to the order, and forming one or more upper layers of non-leaf nodes based on the number of child nodes of each non-leaf node, while taking into account the minimum expansion of the non-CA area covered by each non-leaf node during construction.

[0012] The order may be defined by associating each grid cell in the plurality of grid cells with a unique index and assigning the unique index of the grid cell in the plurality of grid cells to the BR of the grid cell. The plurality of BRs may be inserted into the bottom layer according to the unique indexes of the plurality of BRs.

[0013] The unique index may be a Hilbert index derived from a Hilbert curve traversing the plurality of grid cells.

[0014] The node set may be selected by: selecting a given layer of the R-tree, where the total number of nodes of the given layer is within the inspection capacity; placing the nodes of the given layer into the set; consuming the remaining capacity by selecting one or more nodes from the nodes of the given layer based on the purity of the nodes of the given layer; and replacing each node in the selected nodes in the set with one or more child nodes in the set, where the nodes of the given layer other than the selected node and the child nodes of the selected node constitute the node set.

[0015] Node sets may be selected across multiple levels of the R-tree to optimize the overall purity of the selected node sets.

[0016] A set of nodes may be selected in the following manner: starting from an upper layer, placing one or more nodes of the upper layer into a priority queue; replacing a node with the lowest purity among the one or more nodes with one or more child nodes of the node; and repeating the replacement until the number of nodes in the priority queue meets the inspection capacity.

[0017] The R-tree structure can be a balanced binary tree in which each non-leaf node has at most two child nodes. The PMC is further configured to filter the defect map by aligning the second graph with the defect map and extracting one or more defect candidates that fall within the compressed rectangle set to form a filtered defect map. The filtered defect map can be used for defect review using a review tool.

[0018] According to other aspects of the disclosed subject matter, a method for assisting defect detection on a semiconductor sample is provided, the method being performed by a processing and memory circuit system (PMC) and comprising: obtaining a first graph providing information of a plurality of areas of interest (CAs) to be inspected on a die; creating a plurality of bounding rectangles (BRs) enclosing the plurality of CAs; and compressing the plurality of BRs into a compressed set of rectangles to satisfy a predefined inspection capacity while attempting to minimize the non-CA area enclosed by the compressed set of rectangles, thereby generating a second graph providing information of the compressed set of rectangles. The compression comprises constructing an R-tree structure comprising a bottom layer and one or more upper layers, the bottom layer comprising a plurality of leaf nodes representing the plurality of BRs, each of the one or more upper layers comprising one or more non-leaf nodes, each given non-leaf node representing a compressed rectangle enclosing one or more rectangles represented by one or more child nodes of the given non-leaf node; and selecting a set of nodes from the leaf nodes and non-leaf nodes of the R-tree structure based on the predefined inspection capacity, the set of nodes representing the compressed set of rectangles. The second graph may be used to filter a defect map indicating a distribution of defect candidates on the die.

[0019] This aspect of the disclosed subject matter may comprise mutatis mutandis one or more of the features (i) to (x) listed above with respect to the system in any desired combination or permutation technically possible.

[0020] According to another aspect of the disclosed subject matter, a non-transitory computer-readable storage medium is provided, the non-transitory computer-readable storage medium comprising instructions that, when executed by a computer, cause the computer to perform a method for assisting defect detection on a semiconductor sample, the method comprising: obtaining a first graph providing information about a plurality of areas of interest (CAs) to be inspected on a die of the semiconductor sample; creating a plurality of bounding rectangles (BRs) enclosing the plurality of CAs; and compressing the plurality of BRs into a compressed set of rectangles to satisfy a predefined inspection capacity while attempting to minimize the non-CA area enclosed by the compressed set of rectangles, thereby generating a second graph providing information about the compressed set of rectangles. The compressing comprises constructing an R-tree structure comprising a bottom layer and one or more upper layers, the bottom layer comprising a plurality of leaf nodes representing the plurality of BRs, each of the one or more upper layers comprising one or more non-leaf nodes, each given non-leaf node representing a compressed rectangle enclosing one or more rectangles represented by one or more child nodes of the given non-leaf node; and selecting a set of nodes from the leaf nodes and non-leaf nodes of the R-tree structure based on the predefined inspection capacity, the set of nodes representing the compressed set of rectangles. The second graph may be used to filter a defect map indicating a distribution of defect candidates on the die.

[0021] This aspect of the disclosed subject matter may comprise mutatis mutandis one or more of the features (i) to (x) listed above with respect to the system in any desired combination or permutation technically possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to understand the present disclosure and to see how it may be carried out in practice, embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0023] Figure 1 A functional block diagram of an inspection system for inspecting semiconductor samples and a subsystem for assisting defect detection according to certain embodiments of the disclosed subject matter is shown.

[0024] Figure 2 A general flow chart for assisting defect detection on a semiconductor sample, according to certain embodiments of the disclosed subject matter, is shown.

[0025] Figure 3 A general flow diagram illustrating an exemplary process for creating multiple bounding rectangles (BRs) according to certain embodiments of the disclosed subject matter is shown.

[0026] Figure 4A general flow chart illustrating an exemplary process for constructing an R-tree according to certain embodiments of the presently disclosed subject matter is shown.

[0027] Figure 5 A general flow diagram illustrating an exemplary process for selecting a set of nodes according to certain embodiments of the disclosed subject matter is shown.

[0028] Figure 6 A general flow diagram illustrating another exemplary process for selecting a set of nodes according to certain embodiments of the disclosed subject matter is shown.

[0029] Figure 7 An example of a portion of a CA graph is shown, according to some embodiments of the presently disclosed subject matter.

[0030] Figure 8 An example of multiple BRs according to certain embodiments of the presently disclosed subject matter is shown.

[0031] Figure 9 An example of a second diagram providing information for compressing a set of rectangles is shown, according to some embodiments of the presently disclosed subject matter.

[0032] Figure 10 Shown are examples of Hilbert indices derived from a Hilbert curve, according to certain embodiments of the disclosed subject matter.

[0033] Figure 11 Shown are examples of R-trees and corresponding rectangles represented by the R-trees, according to some embodiments of the presently disclosed subject matter.

[0034] Figure 12 FIG. 1 shows a schematic diagram of ... Figure 5 An example of an R-tree that describes node selection.

[0035] Figure 13 FIG. 1 shows a schematic diagram of ... Figure 6 An example of an R-tree that describes node selection. DETAILED DESCRIPTION

[0036] In the detailed description that follows, numerous specific details are set forth to provide a thorough understanding of the present disclosure. However, those skilled in the art will appreciate that the present disclosure may be practiced without these specific details. In other cases, well-known methods, processes, components, and circuits have not been described in detail to avoid obscuring the present disclosure.

[0037] Unless otherwise specifically stated, it will be apparent from the following discussion that terms such as "assist," "obtain," "compress," "construct," "select," "filter," "partition," "approximate," "insert," "form," "associate," "allocate," "place," "consume," "replace," "align," "extract," and the like, used throughout the specification, to refer to the action(s) and / or process(es) by which a computer manipulates data and / or transforms data into other data, the data being represented as physical (such as electronic) quantities and / or the data representing physical objects. The term "computer" should be broadly interpreted to encompass any kind of hardware-based electronic device with data processing capabilities, including, by way of non-limiting example, inspection systems, subsystems that assist in defect detection, and their corresponding portions disclosed in this application.

[0038] As used herein, the terms "non-transitory memory" and "non-transitory storage medium" should be broadly interpreted to encompass any volatile or non-volatile computer memory suitable for the subject matter of the present disclosure. These terms should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. These terms should also be considered to include any medium that can store or encode a set of instructions for execution by a computer and cause the computer to perform any one or more of the methods of the present disclosure. Therefore, these terms should be considered to include, but are not limited to, read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and the like.

[0039] The term "sample" as used in this specification should be broadly interpreted to encompass any kind of physical object or substrate, including wafers, masks, reticles, and other structures used to manufacture semiconductor integrated circuits, magnetic heads, flat panel displays, and other semiconductor fabricated articles, combinations thereof, and / or portions thereof. Samples are also referred to herein as semiconductor samples and can be produced by fabrication equipment performing a corresponding fabrication process.

[0040] The term "inspection" as used in this specification should be broadly interpreted to cover any type of operation related to defect detection, defect review and / or various types of defect classification and / or metrology operations during and / or after the sample manufacturing process. Inspection is performed using non-destructive testing tools during or after the manufacture of the sample to be inspected. As non-limiting examples, the inspection process may include runtime scanning (single or multiple scans), imaging, sampling, inspection, review, measurement, classification and / or other operations provided for the sample or part thereof, using the same or different inspection tools. Similarly, inspection may be provided before the sample to be inspected is manufactured and may include, for example, generating (multiple) inspection recipes and / or other setup operations. It should be noted that, unless otherwise specifically stated, the term "inspection" or its derivatives used in this specification are not limited to the resolution or size of the inspection area. Various non-destructive testing tools include, as non-limiting examples, scanning electron microscopes (SEMs), atomic force microscopes (AFMs), optical inspection tools, etc.

[0041] The term "defect," as used in this specification, should be broadly interpreted to encompass any type of anomaly or unwanted feature / functionality that develops on a sample. In some cases, a defect may be a defect of interest (DOI), which is a true defect that has some impact on the functionality of the manufactured device and therefore is in the customer's interest to detect. For example, any "killer" defect that could result in yield loss could be designated as a DOI.

[0042] In some other cases, the defect may be a nuisance (also called a "false positive" defect), which refers to an unwanted or uninteresting defect that does not affect yield and should therefore be ignored because it does not affect the functionality of the completed device.

[0043] The term "defect candidate" as used in this specification should be broadly interpreted to encompass suspected defect locations on a sample that are detected with a relatively high probability of being a defect of interest (DOI). Therefore, upon review, a defect candidate may actually be a DOI, or in some other cases, it may be noise as described above, or random noise that may be caused by different variations during inspection (e.g., process variations, color variations, mechanical and electrical variations, etc.).

[0044] The term "design data" as used in this specification should be broadly interpreted to encompass any data indicative of the hierarchical physical design (layout) of a sample. The design data may be provided by a corresponding designer and / or may be derived from the physical design (e.g., through complex simulations, simple geometry and Boolean operations, etc.). The design data may be provided in various formats, such as, for example, GDSII format, OASIS format, etc. The design data may be presented in vector format, grayscale intensity image format, or other formats.

[0045] It should be understood that, unless otherwise specifically stated, certain features of the disclosed subject matter described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, the various features of the disclosed subject matter described in the context of a single embodiment may also be provided individually or in any suitable subcombination. In the detailed description that follows, many specific details are set forth to provide a thorough understanding of the method and apparatus.

[0046] With this in mind, attention turns to Figure 1 , shows a functional block diagram of an inspection system for inspecting semiconductor samples and a subsystem for assisting defect detection according to certain embodiments of the disclosed subject matter.

[0047] Figure 1 The inspection system 100 shown in FIG. 1 can be used for inspection of semiconductor samples (e.g., wafers, dies, and / or components thereof) as part of a fabrication-on-a-batch (FAB) process. As noted above, reference to inspection herein can be interpreted as encompassing any type of operation related to defect inspection and detection, various types of defect classification, and / or metrology operations on a sample or portion thereof. According to certain embodiments of the disclosed subject matter, the inspection system 100 shown includes a computer-based system 101 capable of assisting / optimizing defect detection on a sample.

[0048] The inspection system 100 may include one or more inspection tools configured to capture images and / or review the captured image(s) and / or enable or provide measurements related to the captured image(s).

[0049] The term "inspection tool(s)" as used in this specification should be broadly interpreted to cover any tool that can be used for inspection-related processes, including, as non-limiting examples, imaging, scanning (single or multiple scans), sampling, review, measurement, classification and / or other processes provided with respect to a sample or portion thereof. The inspection tool may include inspection tool(s) and / or review tool(s). The inspection tool is configured to scan a sample (e.g., an entire wafer, an entire die or portion thereof) to capture inspection images (typically at relatively high speed and / or low resolution) to detect potential defects. The review tool is configured to capture review images of at least some of the defects detected by the inspection tool(s) to determine whether the potential defects are indeed defects. Such review tools are typically configured to inspect segments of the die one at a time (typically at relatively low speed and / or high resolution). The inspection tool and review tool may be different tools located in the same or different locations, or a single tool operating in two different modes. In some cases, at least one inspection tool may have a metrology function.

[0050] According to some embodiments, the inspection system 100 may include one or more inspection tools 110 and / or one or more review tools 114, such as Figure 1 Specifically, the inspection tool 110 can scan a sample to capture an inspection image and detect potential defects based on a defect detection algorithm. The output of the defect detection is a defect map indicating the distribution of defect candidates across the semiconductor sample. In some cases, a list of defect candidates can be selected from the defect map as candidates with a higher probability of being a defect of interest (DOI), for example, using a defect classifier and / or interference filter.

[0051] The selected defect candidate list can be provided to the review tool 114. The review tool 114 is configured to capture a review image at the location of each defect candidate in the list and review the review image to determine whether the defect candidate is indeed a DOI. The output of the review tool may include label data associated with each defect candidate list, the label data providing information about the type of defect candidate.

[0052] Without limiting the scope of the present disclosure in any way, it should also be noted that the inspection tool(s) 110 and / or the review tool(s) 114 may be implemented as various types of inspection machines, such as optical imaging machines, electron beam machines, etc. In some cases, the same inspection tool may provide both low-resolution image data and high-resolution image data.

[0053] As previously described, the inspection system 100 includes a computer-based system 101 that is capable of assisting / optimizing defect detection on a sample based on a region of interest of the sample. A region of interest (CA) refers to a specific portion of a sample that is of particular interest / important to be inspected. For example, a region of interest can be represented as a polygon on a map and used as a mask to be applied to an inspection image and / or defect map of the sample to indicate which areas to inspect for defects. In some cases, the region of interest can be used to distinguish areas on the sample that will be inspected in different manners (e.g., by using different inspection parameters, such as detection sensitivity, thresholds, etc.). Thus, the region of interest can be used to facilitate the process of detecting DOIs and interference / noise suppression. For example, a CA map can be used to filter a defect map of a sample so that only defect candidates that fall within the CA region are retained for further inspection.

[0054] Regions of interest or CA maps can be generated in a variety of ways. For example, a CA map can be derived based on the design data of a sample (e.g., a chip design pattern printed on a sample). Regions of interest can be manually derived by a user or automatically derived by using certain scripts and / or tools to extract specific areas, such as coverage patterns of interest or locations of interest. Because these regions are derived from the chip design, these regions can provide high accuracy for inspection tools that assist in defect detection. However, because regions of interest are typically derived in tiny sizes and high volumes (e.g., in terms of millions or billions of polygons from a die), the amount of data representing the CA typically exceeds the inspection budget / capacity of the inspection tool.

[0055] The terms "inspection budget" and "inspection capacity" are used interchangeably and refer to the limit on the number of regions of interest (or the amount of data representing the regions of interest) that can be processed by an inspection tool due to tool limitations (such as memory, storage, and / or processing limitations). For example, each region of interest can be stored in memory using data representing the coordinates of the region of interest in a map and its dimensions. Maps with millions or billions of regions of interest inevitably consume a large amount of system memory space and require considerable processing power to read and process the data, which often exceeds the inspection capacity of the inspection tool.

[0056] Therefore, a large number of regions of interest need to be compressed / grouped into a relatively small set of compressed regions (requiring less system storage and processing) to meet the inspection capacity of the tool. However, since the initially derived small-sized regions of interest will be compressed into compressed regions with larger sizes (e.g., each compressed region contains one or more regions of interest), the compressed regions will inevitably include non-CA regions that were not originally intended to be inspected. Therefore, a compressed region map that includes such non-CA regions will result in an increase in false positives / interference falling into these regions when used to filter defect maps. The detection of such false positives / interference is disadvantageous for various reasons. For example, it may be necessary to further filter out these interferences from the inspection results by performing additional post-processing on the defect map. In addition, interference detection may limit the sensitivity that can ultimately be achieved by the inspection system for a particular application. The increase in interference may also overload the runtime processing capacity of the inspection system, thereby reducing throughput and / or resulting in yield loss.

[0057] According to certain embodiments of the presently disclosed subject matter, system 101 is configured to effectively compress the sample's regions of interest. Compression can effectively meet the inspection capacity constraints of the inspection tool while attempting to minimize non-CA regions, thereby ultimately reducing false positives / noise in defect maps falling within these regions.

[0058] System 101 includes a processor and memory circuitry (PMC) 102 (also referred to as a processing unit) operatively connected to a hardware-based I / O interface 126. PMC 102 is configured to provide the processing necessary to operate system 101, as described in detail in the accompanying drawings. Figures 2 to 6 As further described in detail, and including a processor (not separately shown) and a memory (not separately shown), the processor of the PMC 102 can be configured to execute several functional modules according to computer-readable instructions implemented on a non-transitory computer-readable memory included in the PMC. Such functional modules are hereinafter referred to as being included in the PMC.

[0059] According to some embodiments, the functional modules included in PMC 102 may include a bounding rectangle (BR) module 104, a compression module 106, and optionally a defect map filtering module 108. PMC 102 may be configured to obtain a first map via I / O interface 126, the first map providing information of a plurality of areas of interest (CAs) to be inspected on a die of a semiconductor sample. The first map (also referred to as a CA map) may be received, for example, from a design data server 120 configured to store design data of the semiconductor sample or a portion thereof.

[0060] The BR module 104 can be configured to create multiple bounding rectangles (BRs) that enclose multiple CAs. The compression module 106 can be configured to compress the multiple BRs into a compressed rectangle set to meet a predefined inspection capacity while attempting to minimize the non-CA area enclosed by the compressed rectangle set, thereby generating a second graph that provides information about the compressed rectangle set. The compression may include R-tree construction and node selection. Specifically, the constructed R-tree structure includes a bottom layer and one or more upper layers. The bottom layer includes multiple leaf nodes representing multiple BRs. Each of the one or more upper layers includes one or more non-leaf nodes. Each given non-leaf node represents a compressed rectangle that encloses one or more rectangles represented by one or more child nodes of the given non-leaf node. A node set is selected from the leaf nodes and non-leaf nodes of the R-tree structure based on the predefined inspection capacity. The node set represents the compressed rectangle set.

[0061] The second map providing information of the compressed set of rectangles may be used by, for example, the defect map filtering module 108 or the inspection tool 110 to filter the defect map indicating the distribution of defect candidates on the die.

[0062] It should be noted that the term "first" used throughout the specification, drawings, and claims does not mean the first instance, etc. Instead, "first" is used to distinguish from a "second" instance, etc. For example, the second figure is a figure generated based on the first figure and is therefore different from the first figure.

[0063] The operation of system 100, system 101, PMC 102 and the functional modules therein will refer to Figures 2 to 6 Described in further detail.

[0064] According to certain embodiments, the system 100 may include a storage unit 122. The storage unit 122 may be configured to store any data required for operating the system 101, such as data related to the input and output of the system 101, and intermediate processing results generated by the system 101. For example, the storage unit 122 may be configured to store (a plurality of) CA maps received from a design data server, and / or (a plurality of) defect maps of a sample generated by an inspection tool, and / or a second map providing information on a compressed rectangle set, and / or (a plurality of) filtered defect maps generated using the second map, etc. Therefore, the stored input data may be retrieved from the storage unit 122 and provided to the PMC 102 for further processing, and the output data from the PMC 102 may be sent to the storage unit 122 when necessary.

[0065] In some embodiments, the system 101 may optionally include a computer-based graphical user interface (GUI) 124 configured to enable user-specified input and / or present processing output associated with the system 101. For example, a visual representation of a first map of the region of interest may be presented to the user (e.g., via a display forming part of the GUI 124). Optionally, the user may be provided with options through the GUI to define certain operating parameters, such as, for example, the inspection capacity of the inspection tool, R-tree structure parameters, etc. The user may also view certain operational results, such as, for example, a second map, a defect map, a filtered defect map, etc., on the GUI. In some cases, the system 101 may also be configured to send the second map to the inspection tool 110 via the I / O interface 126 for filtering the defect map. In some cases, the system 101 may further be configured to send some of the results to the storage unit 122 and / or an external system (e.g., a yield management system (YMS) of the FAB).

[0066] According to certain embodiments, in addition to the system 101, the inspection system 100 may further include one or more inspection modules, such as, for example, a defect detection module(s) and / or an automatic defect review module (ADR) and / or an automatic defect classification module (ADC) and / or a metrology-related module and / or other modules that can be used to perform semiconductor sample inspection. One or more inspection modules may be implemented as standalone computers, or their functionality (or at least a portion thereof) may be integrated with the inspection tool 110 and / or the review tool 114. In some embodiments, the output obtained from the system 101 may be used by the inspection tool 110 and / or the review tool 114 and / or one or more inspection modules (or portions thereof) for further inspection of the semiconductor sample.

[0067] Those skilled in the art will readily appreciate that the teachings of the presently disclosed subject matter are not limited to Figure 1 The present invention is not limited to the constraints of the system shown in ; equivalent and / or modified functionality may be combined or divided in another manner and may be implemented in any suitable combination of software and firmware and / or hardware.

[0068] It should be noted that Figure 1 The system shown can be implemented in a distributed computing environment, where the aforementioned functional modules included in PMC102 and / or Figure 1 The components shown can be distributed across several local and / or remote devices and can be linked via a communication network. It should also be noted that in various embodiments, one or more of the inspection tool 110, review tool 114, design data server 120, storage unit 122, and / or GUI 124 can be internal or external to the system 101 and, when needed, communicate data with the system 101 via the I / O interface 126. The system 101 can be implemented as (multiple) stand-alone computers for use in conjunction with inspection tools. Alternatively, in some cases, the corresponding functions of the system 101 can be at least partially integrated with one or more inspection tools to facilitate and enhance the functionality of the inspection tools in inspection-related processes.

[0069] Although not necessarily so, the operation of system 101 and system 100 may correspond to the operation of Figures 2 to 6 Some or all of the stages of the method described. Figures 2 to 6 The described method and its possible implementations can be implemented by the system 101 and the system 100. Therefore, it should be noted that, with respect to Figures 2 to 6 The discussed embodiments of the described method may also be implemented mutatis mutandis as various embodiments of the system 101 and the system 100 , and vice versa.

[0070] Reference Figure 2 , shows a general flow chart for assisting defect detection on a semiconductor sample according to certain embodiments of the disclosed subject matter.

[0071] A first map providing information about a plurality of areas of interest (CAs) to be inspected on a die of a semiconductor sample can be obtained (202) (e.g., by PMC 102 in system 101). As described above, areas of interest (CAs) refer to specific regions of the sample that are of particular interest / importance to be inspected. In some embodiments, the first map (also referred to herein as a CA map) can be derived based on design data for the die. For example, CA regions can be identified (manually by a user or automatically by a script / tool) as regions covering specific patterns of interest and / or locations of interest, etc.

[0072] Figure 7An example of a portion of a CA map according to certain embodiments of the presently disclosed subject matter is shown. As shown, the regions of interest in the CA map 700 can be represented as polygons (e.g., rectangles) of various sizes. For example, the CA map 700 can be stored in a memory unit as data representing the coordinates of each given region of interest in the map and / or the dimensions of the given region of interest. For example, a rectangular-shaped CA can be represented by the x and y coordinates of one vertex and the length and width dimensions of the rectangle, or alternatively, by the x and y coordinates of two vertices of the rectangle.

[0073] Since regions of interest are typically derived in large quantities from high-precision design data, millions or billions of CAs will result in a large amount of representative data to be stored and processed, which often exceeds the inspection capacity of the inspection tool. Certain embodiments of the present disclosure provide a method and system for compressing / grouping such regions of interest into a relatively small number of compressed regions using a unique tree structure (e.g., R-tree) to efficiently meet the inspection capacity of the inspection tool while attempting to minimize the non-CA areas that are inevitably included in the compressed regions to reduce false positives / noise falling within these regions, as described above.

[0074] An R-tree is a tree data structure that is commonly used for spatial access purposes in geographic coordinate systems and navigation systems. The "R" in R-tree stands for rectangle. R-trees are used to group nearby objects and represent them with their minimum bounding rectangles at the next higher level of the tree. At the leaf level, each rectangle describes a single object, while at higher levels, aggregate rectangles represent more and more objects. R-trees are often used to optimize spatial queries for certain objects within the tree (i.e., to quickly and efficiently retrieve objects based on their spatial location) by determining the subtree(s) to search.

[0075] Certain embodiments of the present disclosure propose unconventional uses of R-tree structures for different purposes. Specifically, R-trees are used in the specific application of region of interest compression to assist in semiconductor sample inspection. The R-tree is constructed in a specific way to represent the region of interest of the CA map and its compression, and the compression regions / rectangles are specifically selected from the constructed tree. Both the tree construction process and the selection of compression rectangles from the tree are specifically configured to optimize the inclusion of non-CA regions (e.g., trying to minimize the size of non-CA regions) while meeting the inspection capacity of the inspection tool, which will be referred to below. Figures 2 to 6 Described in further detail.

[0076] A plurality of bounding rectangles (BRs) may be created (204) (e.g., by the bounding rectangle module 104 in the PMC 102) to encompass a plurality of CAs. Bounding rectangles may be created in a variety of ways, and the present disclosure is not limited to a particular implementation. For example, each CA may be included in a corresponding BR. As another example, a BR may be derived to encompass a plurality of CAs that are adjacent to each other. Figure 3 A general flow diagram illustrating an exemplary process for creating multiple bounding rectangles (BRs) according to certain embodiments of the disclosed subject matter is shown.

[0077] Specifically, the first image (i.e., the CA image) may be divided (302) into multiple grid cells according to the grid, thereby generating a plurality of grid cells each containing at least one CA or a portion thereof. For each grid cell in the plurality of grid cells, a bounding rectangle (BR) may be approximated (304) to enclose the at least one CA or a portion thereof in the grid cell, thereby generating a plurality of BRs corresponding to the plurality of grid cells. According to certain embodiments of the presently disclosed subject matter, in Figure 8 An example of multiple BRs derived as described above is shown in FIG.

[0078] As shown, a grid 800 is applied to a CA map (only a portion of the figure is shown for illustrative purposes), which divides the CA map into multiple grid cells. After the division, some grid cells (such as cell 801) may be empty because there is no region of interest within these cells. Some grid cells (such as cell 802) may contain one or more CAs, and in the case where some CAs span two or more grid cells, some grid cells (such as cell 804) may contain one or more partial CAs (and sometimes one or more complete CAs). For each non-empty grid cell (i.e., a grid cell that includes at least one CA or a portion thereof), a bounding rectangle (BR) is approximated to enclose any CA or portion thereof within the grid cell. For example, in the case where there are one or more complete CAs in a grid cell (such as in cell 802), the BR can be approximated as the smallest (or near-smallest) rectangle that can enclose the one or more CAs (e.g., some portions of the BR edge can outline some edges of the CA). In the case of one or more partial CAs in a grid cell (such as in cell 804), the BR can be approximated as a minimum (or near-minimum) rectangle that encloses the partial CAs within the cell (e.g., portions of the BR edge can outline the boundaries of the grid cell spanned by these CAs) and the additional CAs (if any) in the grid cell.

[0079] In some cases, the size of the grid / grid cell may be predetermined based on certain factors, such as, for example, the memory limitations of the system 101 (for storing the BRs to be processed) and the purity requirements of the compression, etc. For example, the finer the grid, the higher the BR purity (as defined in further detail below) will be, because the approximated BR will contain less white space (i.e., non-CA areas) in the finer grid cells.

[0080] The plurality of BRs may be compressed (206) (e.g., by compression module 106 in PMC 102) into a compressed rectangular set to satisfy a predefined inspection capacity while attempting to minimize a non-CA area enclosed by the compressed rectangular set, thereby generating a second map providing information of the compressed rectangular set.

[0081] It should be noted that the terms "minimum," "minimized," or "minimized" as used in this disclosure should be broadly interpreted to encompass exact minimum / minimum conditions or conditions close to minimum / minimum conditions (e.g., close to an exact minimum value to a certain extent (the extent may be defined by a certain percentage / threshold)). For example, the minimum rectangle mentioned above may be a rectangle that just encloses the edge of the CA and thus covers the minimum space, or may be a bounding rectangle of the CA that is slightly larger (to a certain extent) in size relative to the exact minimum rectangle. The attempt to minimize the non-CA area as described above can be interpreted as an attempt to minimize the non-CA area or to approach the minimized non-CA area (to a certain extent).

[0082] Specifically, compression may include an R-tree construction process (208) and a node selection process (210). The constructed (208) R-tree structure includes a bottom layer and one or more upper layers. The bottom layer includes a plurality of leaf nodes representing a plurality of BRs (as created with reference to block 204). Each of the one or more upper layers includes one or more non-leaf nodes. Each given non-leaf node represents a compressed rectangle that encloses one or more rectangles represented by one or more child nodes of the given non-leaf node. Once the R-tree is constructed, a set of nodes may be selected (210) from the leaf nodes and non-leaf nodes of the R-tree structure based on a predefined inspection capacity. The set of nodes represents a set of compressed rectangles.

[0083] An R-tree is a balanced tree structure and can be constructed in a variety of ways. For example, an R-tree can be constructed by a dynamic method, for example, when a BR is encountered, the BR is inserted into the tree. For example, multiple BRs can be inserted into the tree sequentially and the R-tree is constructed in a bottom-up manner. As another example, an R-tree can be constructed by a static method, for example, the tree is constructed only when all BRs are available. For example, multiple BRs can be loaded into the tree in batches, and the tree can be constructed in a bottom-up manner or a top-down manner (for example, by using a node splitting algorithm). An R-tree can be constructed with different numbers of child nodes of non-leaf nodes. For example, an R-tree can be a binary tree in which each non-leaf node has at most two child nodes. As another example, an R-tree can be constructed with another number of child nodes of each non-leaf node.

[0084] Figure 4 A general flow chart of an exemplary process for constructing an R-tree according to certain embodiments of the presently disclosed subject matter is shown. As shown, the R-tree structure can be constructed by sequentially inserting (402) a plurality of BRs into a bottom layer of the R-tree according to an order, and forming / constructing (408) one or more upper layers of non-leaf nodes based on the number of child nodes of each non-leaf node, while taking into account the minimum expansion of the non-CA area covered by each non-leaf node during construction.

[0085] The purity of a node, or the purity of the rectangle (BR or compressed rectangle) represented by the node, is calculated based on the area of the CA included in the rectangle and the area of the rectangle. Purity can be used as an indicator of the size of the non-CA area included in the rectangle. Minimal expansion of the non-CA area can be reflected in the acquisition of a node / compressed rectangle with higher purity.

[0086] Specifically, the order in which BRs are inserted into the bottom layer can be defined by associating each grid cell in the plurality of grid cells with a unique index (404) and assigning (406) the unique index of the grid cell in the plurality of grid cells to the BR of the grid cell. Thus, the plurality of BRs can be inserted into the bottom layer according to their unique indexes. Various indices for spatial sorting can be used to define the insertion order. For example, the grid cells (and their BRs) can be sorted according to their x-coordinates or y-coordinates. As another example, the unique index can be a Hilbert index derived from a Hilbert curve that traverses the plurality of grid cells.

[0087] The Hilbert curve is a continuous space-filling curve consisting of a collection of piecewise linear curves. The graph of the Hilbert curve is a compact set, homeomorphic to the closed unit interval, where the Hausdorff dimension is 2. The Hilbert curve is useful because it gives a mapping between 1D and 2D space that preserves locality well, and two data points that are close to each other in 1D space will also be close to each other after being folded by the curve. The Hilbert curve can be used to impose a linear ordering on rectangles according to the Hilbert index derived from it. The Hilbert index is based on the Hilbert value of the grid cell containing the BR (e.g., the length of the Hilbert curve from the origin to the corresponding grid cell).

[0088] Figure 10 An example of a Hilbert index derived from a Hilbert curve according to certain embodiments of the presently disclosed subject matter is shown. As shown, the Hilbert curve is shown as a collection of piecewise linear curves passing through the grid cells. Each grid cell is associated with a Hilbert index derived based on the Hilbert value of the grid cell (e.g., based on the length of the Hilbert curve from the origin to the grid cell). Any BR that falls within a grid cell is assigned the Hilbert index of that cell. For example, cell 1002 and any of its BRs are assigned a Hilbert index of 15, while its neighboring cells are assigned Hilbert indices of 13, 14, and 16. By using the correct Hilbert curve order ( Figure 10 The order of the Hilbert curve shown in is 3), and a unique Hilbert index can be assigned to each BR. For example, the required order of the Hilbert curve can be expressed as: log2(max(number of grid cells)).

[0089] Inserting BRs into the bottom layer of the R-tree according to their Hilbert index can make it possible to group rectangles that are close to each other together, thereby minimizing the area of the resulting compressed rectangle (minimizing the overall area of the compressed rectangle is essentially equivalent to minimizing the non-CA area in the compressed rectangle). For example, assuming that each non-leaf node can have two children, and assuming that during construction, the compressed / grouped rectangles that have been formed will not be subdivided again when new leaf nodes / BRs are inserted later. First, index 1 (according to Figure 10 BR 1 with the Hilbert index shown in FIG1 is inserted into the bottom layer as a leaf node, and then BR 2 with index 2 is inserted, where BR 1 and BR 2 are compressed into the first (upper) layer node 1 (for the sake of simplicity of the figure, the exemplary BR is not shown in FIG1 ). Figure 10As shown in ). Assuming that the grid cell with index 3 is empty (i.e., there is no BR in this cell), the next BR to be inserted is BR 4 with index 4, followed by BR 5 with index 5. These two BRs are therefore grouped into the first-level node 2. Assuming that only one BR 8 with index 8 remains to be inserted, considering that BR 8 is closer to the first-level node 2, BR 8 and the first-level node 2 will be combined to form a second-level node, which will then be grouped into the third-level node together with the first-level node 1. This grouping method is more optimized than first grouping BR 8 with the first-level node 1. The first-level node 1 is farther away from BR 8 than from the first-level node 2, and therefore will inevitably result in a larger total area of the compressed rectangle. Therefore, when inserting new BRs and forming upper-level nodes, care should be taken to ensure that the expansion of the area covered by the compressed rectangle is minimized.

[0090] It should be noted that the above examples are described for simplicity and illustration purposes only and should not be construed as limiting the present disclosure in any way. Other ways of forming upper nodes can be used to supplement or replace the above methods. For example, the number of child nodes of each non-leaf node can be configured, and in order to further optimize (minimize) the area to be included in the compressed rectangle, the upper node representing the compressed rectangle previously formed can be divided again when a newer BR is inserted later.

[0091] Figure 11 Shown are examples of R-trees and corresponding rectangles represented by the R-trees, according to some embodiments of the presently disclosed subject matter.

[0092] Black dot 1102 indicates that Figure 3 The created bounding rectangle (BR) (also represented as the original rectangle) is inserted into the bottom layer of the R-tree as a leaf node 1104 (due to the limitations of the illustration of the accompanying drawings, not all BRs are shown at the bottom layer). The upper layers of the tree represent different compression levels of the BRs. As shown in the figure, according to the above construction process, for example, based on the number of child nodes of each non-leaf node and taking into account the minimum expansion of the area covered by the compressed rectangle, the BRs are grouped into the first upper layer of R1 to R9. R1 to R9 are further grouped into the second upper layer of R10 to R12 in a similar manner. If necessary, R10 to R12 can be grouped into the root node. The R-tree is constructed as described above, and each non-leaf node of the tree is expected to cover the minimum area / non-CA area when constructed.

[0093] According to certain embodiments, the R-tree structure can be constructed as a balanced binary tree in which each non-leaf node has at most two child nodes. Although a binary R-tree may take longer to query a rectangle, it can provide higher purity than an R-tree constructed with other numbers of child nodes (such as, for example, three or more child nodes). Specifically, since the R-tree in the present disclosure is specifically used for the purpose of focusing on region compression rather than its conventional purpose of region query, the use of a binary R-tree can be beneficial in minimizing non-CA regions, thereby improving the purity of the compressed rectangle.

[0094] Once all the BRs are inserted and the R-tree is constructed, a node set may be selected (210) from the leaf nodes and non-leaf nodes of the R-tree structure based on a predefined inspection capacity. The node set represents a compressed rectangle set.

[0095] Figure 5 A general flow chart of an exemplary process for selecting a set of nodes according to certain embodiments of the presently disclosed subject matter is shown. Specifically, a given layer of an R-tree structure may be selected (502) where the total number of its nodes is within a check capacity, and the nodes of the given layer may be (temporarily) placed in a set. Remaining capacity (if any) may be consumed (504) by selecting one or more nodes from the nodes of the given layer based on the purity of the nodes of the given layer and replacing each selected node in the selected nodes with one or more child nodes of each selected node in the selected nodes. The nodes in the given layer other than the selected node, and the child nodes of the selected node, together constitute the node set.

[0096] Now refer to Figure 12 , showing some embodiments according to the presently disclosed subject matter with respect to Figure 5 An example of an R-tree that describes node selection.

[0097] Assume that the inspection capacity of the inspection tool is predefined as 7 million rectangles that can be processed by the inspection tool due to tool limitations. The example R-tree includes a bottom layer and four upper layers (including a top layer with a root node). Assume that the bottom layer includes 16 million rectangles (e.g., BR), the first upper layer includes 8 million rectangles, the second upper layer includes 4 million rectangles, and the third upper layer includes 2 million rectangles. Therefore, the number of nodes in the second upper layer (i.e., 4 million) is just within the inspection capacity of 7 million because the number of nodes included in the next layer (i.e., 8 million) has exceeded the capacity. Therefore, the second upper layer is selected, and the node 1202 of the second upper layer can be temporarily placed in the node set.

[0098] Since there is 3 million remaining capacity in the inspection capacity, the remaining capacity can be consumed by selecting one or more nodes from the selected layer (for example, based on the purity of the nodes in the selected layer). For example, the purity of each node from the second upper layer can be calculated, and the nodes can be sorted according to the purity value of the node. The first node with the lowest purity can be selected and replaced with a child node of the first node (the child node has a higher purity than the first node) from the set. The next node with the lowest purity in the new set (the node of the second upper layer, except the first node now replaced by the child node of the first node) can be selected and replaced with its child node (from the new set). The process can be repeated until the remaining 3 million capacity is consumed. The final selected node set will include nodes of the given layer except the selected (and replaced) nodes, as well as the child nodes of the selected nodes.

[0099] To simplify the example, assume that the check capacity is 7 (instead of 7 million) and the second upper layer includes 4 (instead of 4 million) nodes, as shown in the figure. Four nodes 1202 are first selected and placed in the set (as a temporary set). Since there is still a remaining capacity of 3 nodes, the purity of the four nodes 1202 is calculated. Assuming that node 1204 has the lowest purity among the four nodes, node 1204 is removed from the set and replaced by the two child nodes of node 1204 in the first upper layer. The set now includes 5 nodes, with a remaining capacity of 2 nodes. Assuming that node 1206 has the lowest purity among the 5 nodes in the set, node 1206 is removed from the set and replaced by the two child nodes of node 1206 in the first upper layer. The set now includes 6 nodes, with a remaining capacity of 1 node. Similarly, the next node 1208 in the set (assuming it has the lowest purity) is replaced by its two child nodes, so that the set has 7 nodes and meets the check capacity. The final set includes the remaining node 1210 and the child nodes of nodes 1204 , 1206 , and 1208 from the second upper layer.

[0100] The above examples are for illustrative purposes only and should not be construed as limiting the present disclosure in any way. Different embodiments may employ different specific implementations. For example, when a node is removed from a set, its replacement child nodes may be direct child nodes in the lower layer, or alternatively, the replacement child nodes may include all of its leaf nodes. For example, in the above example, when node 1204 is removed, the replacement child nodes may be the four leaf nodes that are indirectly connected to node 1204. As another example, the purity ranking may be within the nodes of the selected layer only, or may be within a new set that includes the replacement child nodes.

[0101] Alternatively, rather than selecting a given layer and then replacing some of the nodes therein to satisfy the inspection capacity, a set of nodes may be selected (602) across multiple layers of the R-tree in order to optimize (e.g., attempt to maximize) the overall purity of the selected set of nodes, as Figure 6 As shown, Figure 6 A general flow chart illustrating another exemplary process of selecting a set of nodes according to certain embodiments of the presently disclosed subject matter. Similarly, the term "maximize" as used herein should be interpreted as encompassing an exact maximization condition or a condition that approaches maximization (to some extent).

[0102] Specifically, a priority queue can be used to iteratively select a set of nodes. For example, starting from a layer in the upper layer, one or more nodes of the layer can be placed (604) into the priority queue. The node with the lowest purity in the one or more nodes can be replaced (606) from the priority queue with one or more of its child nodes (e.g., its direct child nodes). If the number of nodes in the priority queue does not meet the check capacity (608), the replacement step 606 can be repeated until the number of nodes in the priority queue meets the check capacity. When the check capacity is met, the nodes in the priority queue can be output (610) as a node set representing the compressed rectangle.

[0103] Now refer to Figure 13 , showing some embodiments according to the presently disclosed subject matter with respect to Figure 6 An example of an R-tree that describes node selection.

[0104] For example, starting from the top level, root node 1302 is placed in the priority queue. Since there is only one node in the queue, this root node 1302 is replaced by its direct child nodes 1304 and 1306. Assuming the check capacity is 8, the check capacity is not met because there are only two nodes in the queue. Node 1304 has a lower purity, and node 1304 is removed from the queue and replaced by its direct child nodes 1308 and 1310. Now there are three nodes in the queue, and the check capacity is still not met. Node 1306 has the lowest purity among the three nodes and is replaced by its direct child nodes 1312 and 1314. This process can continue until the check capacity is met. As shown in the figure, 8 nodes from different layers of the tree (marked as solid nodes) are finally selected, representing a set of compressed rectangles whose total purity is optimized / maximized.

[0105] It should be noted that the reference Figure 5 and Figure 12 process or reference Figure 6 and Figure 13 The present disclosure is not limited to the specific implementations thereof.

[0106] Once the compression (206) is complete and a second map providing information about the compressed set of rectangles is generated, the second map can be used to filter a defect map indicating a distribution of defect candidates on the die. In some embodiments, the filtering can optionally be performed by the system 101. For example, the system 101 (e.g., the defect map filtering module 108 in the PMC 102) can be configured to obtain a defect map from the inspection tool 110 and filter (212) the defect map using the second map. In some other cases, the second map can be provided to the inspection tool 110 for use by the tool in filtering the defect map.

[0107] In some embodiments, the second image can be used as a mask to be applied to the defect map to indicate defect candidates that should be further reviewed. For example, the defect map can be filtered by aligning the second image with the defect map and extracting one or more defect candidates that fall within a compressed set of rectangles to form a filtered defect map. The filtered defect map can be used for defect review by a review tool.

[0108] In a further embodiment, the second map may be used as a mask to be applied to an inspection image of the sample and indicate the pixels of the image that should be inspected.

[0109] Figure 9 An example of a second graph providing information about a set of compressed rectangles according to certain embodiments of the presently disclosed subject matter is shown. As shown, the second graph 900 includes compressed rectangles 902 surrounding one or more regions of interest. As described above, the compressed rectangles inevitably include empty space representing non-CA regions. As described above, the tree construction and node selection processes take into account optimization of non-CA regions during the process, striving to minimize the size of non-CA regions to reduce false positives / noise that fall into these regions when the defect map is filtered using the second graph.

[0110] According to certain embodiments, as described above with reference to Figures 2 to 6 The defect detection assistance process may be included as part of an inspection recipe that can be used by the system 101 and / or the system 100 and / or the inspection tool 110 for in-line sample inspection at runtime. Thus, the disclosed subject matter also includes systems and methods for generating an inspection recipe during a recipe setup phase, wherein the recipe includes reference to Figures 2 to 6 It should be noted that the term "inspection recipe" should be interpreted broadly to encompass any recipe that can be used to perform operations related to any kind of sample testing as described above.

[0111] It should be noted that the examples illustrated in this disclosure (such as, for example, the R-tree structure, various tree construction processes, and node selection processes described above) are illustrated for illustrative purposes and should not be considered to limit the present disclosure in any way. Other appropriate examples / implementations may be used to supplement or replace the above.

[0112] One advantage of certain embodiments of the defect detection assistance process described herein is that efficient region of interest compression is achieved through the use of an R-tree structure. The compression can effectively meet the inspection capacity constraints of the inspection tool while attempting to minimize non-CA areas to reduce any false positives / noise that fall into these areas when the defect map is filtered using the compressed rectangle.

[0113] In particular, the R-tree is constructed in a specific way to represent the region of interest of the CA graph and its compression. Both the tree construction process (e.g., by considering the minimum expansion of the area covered by the tree) and the selection of compression rectangles from the tree (e.g., based on the purity of the nodes) are specifically configured to optimize the inclusion of non-CA regions (e.g., minimizing the size of non-CA regions) while meeting the inspection capacity of the inspection tool.

[0114] It is to be understood that the disclosure is not limited in its application to the details set forth in the description contained herein or illustrated in the drawings.

[0115] It should also be understood that the system according to the present disclosure can be implemented at least in part on a suitably programmed computer. Likewise, the present disclosure contemplates a computer program readable by a computer for performing the method of the present disclosure. The present disclosure also contemplates a non-transitory computer-readable memory tangibly embodying a program of instructions executable by a computer to perform the method of the present disclosure.

[0116] The present disclosure may have other embodiments and may be practiced and implemented in various ways. Therefore, it should be understood that the expressions and terms used herein are for descriptive purposes and should not be considered as limiting. Therefore, those skilled in the art will understand that the concepts upon which the present disclosure is based can be easily used as the basis for designing other structures, methods and systems to achieve the several purposes of the presently disclosed subject matter.

[0117] It will be readily appreciated by those skilled in the art that various modifications and changes can be applied to the embodiments of the present disclosure as described above without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A computerized system for assisting defect detection on a semiconductor sample, the system comprising processing and memory circuitry (PMC), the PMC configured to: obtaining a first map providing information of a plurality of areas of interest CA to be inspected on a die of the semiconductor sample; Creating a plurality of bounding rectangles BR surrounding the plurality of CAs; as well as Compressing the plurality of BRs into a compressed rectangular set to satisfy a predefined inspection capacity while attempting to minimize a non-CA area enclosed by the compressed rectangular set, thereby generating a second map providing information of the compressed rectangular set, wherein the compressing comprises: constructing an R-tree structure including a bottom layer and one or more upper layers, the bottom layer including a plurality of leaf nodes representing the plurality of BRs, each of the one or more upper layers including one or more non-leaf nodes, each given non-leaf node representing a compressed rectangle surrounding the one or more rectangles represented by the one or more child nodes of the given non-leaf node; and selecting a node set from the leaf nodes and the non-leaf nodes of the R-tree structure based on the predefined inspection capacity, the node set representing the compressed rectangle set; The second map may be used to filter a defect map indicating a distribution of defect candidates on the die.

2. The computerized system of claim 1, wherein the first map is derived based on design data of the die.

3. The computerized system of claim 1 , wherein the PMC is configured to create the plurality of BRs by dividing the first image into multiple grid cells according to a grid, thereby generating a plurality of grid cells each containing at least one CA or a portion thereof, and, for each of the plurality of grid cells, approximating a bounding rectangle BR surrounding the at least one CA or a portion thereof in the grid cell, thereby generating the plurality of BRs corresponding to the plurality of grid cells.

4. The computerized system of claim 3 , wherein the PMC is configured to construct the R-tree structure by sequentially inserting the plurality of BRs into the bottom layer according to an order, and forming the one or more upper layers of non-leaf nodes based on the number of child nodes of each non-leaf node, while taking into account a minimum expansion of the non-CA area covered by each non-leaf node during construction.

5. The computerized system of claim 4 , wherein the order is defined by associating each grid cell in the plurality of grid cells with a unique index and assigning the unique index of a grid cell in the plurality of grid cells to the BR of the grid cell, and wherein the plurality of BRs are inserted into the bottom layer according to the unique indexes of the plurality of BRs.

6. The computerized system of claim 5, wherein the unique index is a Hilbert index derived from a Hilbert curve traversing the plurality of grid cells.

7. A computerized system according to claim 1, wherein the PMC is configured to select the node set in the following manner: select a given layer of the R-tree, wherein the total number of nodes of the given layer is within the inspection capacity; place the nodes of the given layer into the set; consume the remaining capacity by selecting one or more nodes from the nodes of the given layer based on the purity of the nodes of the given layer; and replace each selected node in the selected nodes in the set with one or more child nodes of each selected node in the selected nodes in the set, wherein the nodes of the given layer other than the selected node and the child nodes of the selected node constitute the node set.

8. The computerized system of claim 1, wherein the PMC is configured to select the set of nodes across multiple levels of the R-tree to optimize the overall purity of the selected set of nodes.

9. A computerized system according to claim 8, wherein the PMC is configured to select the set of nodes in the following manner: starting from the upper layer, one or more nodes of the upper layer are placed in a priority queue; a node with the lowest purity among the one or more nodes is replaced with one or more child nodes of the node; and the replacement is repeated until the number of nodes in the priority queue meets the inspection capacity.

10. The computerized system of claim 1, wherein the R-tree structure is a balanced binary tree in which each non-leaf node has at most two child nodes.

11. The computerized system of claim 1 , wherein the PMC is further configured to filter the defect map by aligning the second map with the defect map and extracting one or more defect candidates falling within the compressed rectangle set to form a filtered defect map, wherein the filtered defect map can be used for defect review by a review tool.

12. A computerized method of assisting defect detection on a semiconductor sample, the method being performed by a processing and memory circuitry (PMC) and comprising: obtaining a first map providing information of a plurality of areas of interest CA to be inspected on a die of the semiconductor sample; Creating a plurality of bounding rectangles BR surrounding the plurality of CAs; as well as Compressing the plurality of BRs into a compressed rectangular set to satisfy a predefined inspection capacity while attempting to minimize a non-CA area enclosed by the compressed rectangular set, thereby generating a second map providing information of the compressed rectangular set, wherein the compressing comprises: constructing an R-tree structure including a bottom layer and one or more upper layers, the bottom layer including a plurality of leaf nodes representing the plurality of BRs, each of the one or more upper layers including one or more non-leaf nodes, each given non-leaf node representing a compressed rectangle surrounding the one or more rectangles represented by the one or more child nodes of the given non-leaf node; and selecting a node set from the leaf nodes and the non-leaf nodes of the R-tree structure based on the predefined inspection capacity, the node set representing the compressed rectangle set; The second map may be used to filter a defect map indicating a distribution of defect candidates on the die.

13. The computerized method of claim 12 , wherein the creating comprises dividing the first image into a plurality of grid cells according to a grid, thereby generating a plurality of grid cells each containing at least one CA or a portion thereof, and for each grid cell in the plurality of grid cells, approximating a bounding rectangle BR surrounding the at least one CA or a portion thereof in the grid cell, thereby generating the plurality of BRs corresponding to the plurality of grid cells.

14. The computerized method of claim 13, wherein said constructing said R-tree structure comprises: The multiple BRs are sequentially inserted into the bottom layer according to an order, and the one or more upper layers of non-leaf nodes are formed based on the number of child nodes of each non-leaf node, while taking into account the minimum expansion of the non-CA area covered by each non-leaf node during construction.

15. The computerized method of claim 14, wherein the order is defined by associating each grid cell in the plurality of grid cells with a unique index and assigning the unique index of a grid cell in the plurality of grid cells to the BR of the grid cell, and wherein the plurality of BRs are inserted into the bottom layer according to the unique indexes of the plurality of BRs.

16. The computerized method of claim 15, wherein the unique index is a Hilbert index derived from a Hilbert curve traversing the plurality of grid cells.

17. The computerized method of claim 12, wherein said selecting said set of nodes comprises: selecting a given layer of the R-tree, wherein a total number of nodes of the given layer is within the inspection capacity; Put the nodes of the given layer into the collection; The remaining capacity is consumed by selecting one or more nodes from the nodes of the given layer based on the purity of the nodes of the given layer; and each selected node in the selected nodes in the set is replaced with one or more child nodes of each selected node in the selected nodes in the set, wherein the nodes of the given layer other than the selected nodes and the child nodes of the selected nodes constitute a node set.

18. The computerized method of claim 12, wherein the node sets are selected across multiple levels of the R-tree to optimize the overall purity of the selected node sets.

19. The computerized method of claim 18, wherein said selecting said set of nodes comprises: Starting from the upper layer, one or more nodes in the upper layer are placed into a priority queue; replacing a node with the lowest purity among the one or more nodes with one or more child nodes of the node; And repeating the replacement until the number of nodes in the priority queue meets the checking capacity.

20. A non-transitory computer-readable storage medium tangibly embodying a program of instructions that, when executed by a computer, causes the computer to perform a method of assisting defect detection on a semiconductor sample, the method comprising: obtaining a first map providing information of a plurality of areas of interest CA to be inspected on a die of the semiconductor sample; Creating a plurality of bounding rectangles BR surrounding the plurality of CAs; as well as Compressing the plurality of BRs into a compressed rectangular set to satisfy a predefined inspection capacity while attempting to minimize a non-CA area enclosed by the compressed rectangular set, thereby generating a second map providing information of the compressed rectangular set, wherein the compressing comprises: constructing an R-tree structure including a bottom layer and one or more upper layers, the bottom layer including a plurality of leaf nodes representing the plurality of BRs, each of the one or more upper layers including one or more non-leaf nodes, each given non-leaf node representing a compressed rectangle surrounding the one or more rectangles represented by the one or more child nodes of the given non-leaf node; and selecting a node set from the leaf nodes and the non-leaf nodes of the R-tree structure based on the predefined inspection capacity, the node set representing the compressed rectangle set; The second map may be used to filter a defect map indicating a distribution of defect candidates on the die.

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