Method of making semiconductor packages and carrier boards used therein

Abstract

A method for manufacturing a semiconductor package, a carrier plate used in the method, and a method for manufacturing the carrier plate, include providing a temporary substrate including a plate body, a first copper foil disposed on the plate body, and a second copper foil disposed on the first copper foil, forming a sintering portion on a partial region of an interface between the first copper foil and the second copper foil to combine the first copper foil and the second copper foil with each other, and performing a semiconductor packaging process on the second copper foil.

Description

Technical Field

[0001] This invention relates to a temporary substrate for semiconductor manufacturing processes, and more particularly to a method for manufacturing a semiconductor package and the substrate and manufacturing method used therein. Background Technology

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multi-functionality and high performance. In order to meet the packaging requirements of miniaturization of semiconductor packaging components, fan-out packaging technology has been developed.

[0003] Figures 1A to 1G This is a cross-sectional schematic diagram of the manufacturing process of an existing semiconductor package 9.

[0004] like Figure 1A As shown, a temporary substrate 1 is provided, which includes a plate 10, a thick copper foil 11 disposed on the plate 10, and a thin copper foil 12 disposed on the thick copper foil 11. The thin copper foil 12 is used in the electroplating process. In order to avoid the thin copper foil 12 from being easily broken during transportation due to its thinness, the thin copper foil 12 is electrostatically adsorbed (interface S as shown in the figure) onto the thick copper foil 11 to thicken the copper structure and strengthen the overall structural strength of the copper foil.

[0005] like Figure 1B As shown, an encapsulation area A and a removal area B are defined on the thin copper foil 12. A resist layer 13 is formed on the surface of the encapsulation area A of the thin copper foil 12, exposing the surface of the removal area B. The resist layer 13 is a dry film, which is bonded to the entire surface of the thin copper foil 12 by lamination. Then, a portion of the material of the thin copper foil 12 is removed by exposure and development to expose the surface of the removal area B.

[0006] like Figure 1C As shown, all the material of the thin copper foil 12 in the removal area B is removed by etching, and part of the material of the thick copper foil 11 below the removal area B is further removed.

[0007] like Figure 1D As shown, the resist layer 13 is peeled off to expose the encapsulation area A, making the encapsulation area A a protruding platform.

[0008] like Figure 1E As shown, semiconductor packaging processes, such as die placement, wiring, and molding, are performed on the packaging area A and the thick copper foil 11 to form a semiconductor package 9.

[0009] like Figure 1FAs shown, a dicing process is performed along the edge of the packaging area A to remove the material surrounding the semiconductor package 9, wherein the dicing path L of the dicing process passes through the packaging area A.

[0010] like Figure 1G As shown, the thick copper foil 11 and the thin copper foil 12 are separated by peeling to remove the plate 10, and then the thin copper foil 12 under the semiconductor package 9 is removed by etching to obtain the semiconductor package 9.

[0011] However, in the existing semiconductor package 9 manufacturing method, a protruding platform needs to be formed on the package area A by means of the resist layer 13, thus requiring multiple processes (such as... Figures 1B to 1D The process shown in the diagram requires multiple machines and numerous steps (such as...) to configure the resist layer 13. Figure 1B The process shown is complex and time-consuming. Therefore, before manufacturing the semiconductor package 9, the process is not only complicated and time-consuming, but also the cost of manufacturing the semiconductor package 9 is greatly increased due to the need to use different equipment in the dry film preparation process.

[0012] Furthermore, since the thin copper foil 12 and the thick copper foil 11 are joined by electrostatic adsorption, their positioning is poor. Therefore, during the semiconductor packaging process, the thin copper foil 12 is easily displaced by external forces, resulting in poor accuracy in subsequent die placement and wiring operations.

[0013] In addition, this semiconductor packaging process is used on uneven surfaces (such as...) Figure 1E The molding process is performed on the encapsulation area A and the thick copper foil 11 shown, rather than on a flat surface. Therefore, when the molding process is performed on the encapsulation area A and the thick copper foil 11, the flowability of the encapsulating colloid is not easy to control, which can easily cause problems such as uneven stress distribution.

[0014] Therefore, overcoming the various problems of the existing technologies has become a pressing issue that the industry urgently needs to address. Summary of the Invention

[0015] In view of the various deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor package and the carrier plate and manufacturing method thereon, which can avoid problems such as stress concentration.

[0016] The method for manufacturing a carrier plate according to the present invention includes: providing a temporary substrate comprising a plate body, a first copper foil disposed on the plate body, and a second copper foil disposed on the first copper foil; and forming a sintering area at a portion of the interface between the first copper foil and the second copper foil, thereby bonding the first copper foil and the second copper foil together.

[0017] In the aforementioned method of manufacturing the carrier plate, other areas at the interface between the first copper foil and the second copper foil are electrostatically attracted to each other.

[0018] In the aforementioned method of manufacturing the carrier plate, the sintering area is formed by laser sintering.

[0019] The present invention also provides a carrier plate, comprising: a plate body; a first copper foil disposed on the plate body; and a second copper foil disposed on the first copper foil, wherein a sintering area is formed in a portion of the interface between the first copper foil and the second copper foil, so that the first copper foil and the second copper foil are bonded together as a whole.

[0020] In the aforementioned carrier plate, the thickness of the first copper foil is greater than the thickness of the second copper foil.

[0021] In the aforementioned carrier plate, other areas at the interface between the first copper foil and the second copper foil are electrostatically attracted to each other.

[0022] The present invention also provides a method for manufacturing a semiconductor package, comprising: providing a aforementioned carrier plate; performing a semiconductor packaging process on the second copper foil; removing the sintering site and the structures above and below it to form a semiconductor package; and removing the plate, the first copper foil and the second copper foil.

[0023] In the aforementioned method for manufacturing semiconductor packages, other areas at the interface between the first copper foil and the second copper foil are electrostatically attracted to each other.

[0024] In the aforementioned semiconductor package manufacturing method, the sintering area is formed by laser sintering.

[0025] In the aforementioned semiconductor package manufacturing method, the sintered area and its upper and lower sides are removed by cutting.

[0026] As can be seen from the above, the semiconductor package manufacturing method of the present invention and the carrier and manufacturing method used therein mainly rely on the design of the sintering point to bond the first copper foil and the second copper foil together, thereby greatly simplifying the pre-processing of the semiconductor packaging process and eliminating the need for existing resist layers such as dry films. Therefore, it is not necessary to use different equipment required for dry film preparation. Thus, compared with the prior art, the manufacturing method of the present invention is not only simple and time-saving before the semiconductor packaging process, but also greatly reduces the cost of manufacturing the semiconductor package because it only requires the use of the machine for forming the sintering point.

[0027] Furthermore, since the first copper foil and the second copper foil are fixed together by the sintering point, the positioning between them is excellent. Therefore, compared with the prior art, when the semiconductor packaging process is carried out, the second copper foil will not be displaced due to external force, thus effectively improving the reliability of the semiconductor packaging process.

[0028] Furthermore, since the semiconductor package manufacturing method of the present invention does not require the creation of an existing protruding platform, the semiconductor packaging process can be carried out on a flat surface (i.e., the second copper foil). Therefore, compared with the prior art, when the semiconductor packaging process of the present invention performs molding operations on the second copper foil, it can effectively control the flowability of the encapsulating colloid, so as to facilitate stress dispersion and avoid problems such as stress concentration. Attached Figure Description

[0029] Figures 1A to 1G This is a cross-sectional schematic diagram of the manufacturing process of existing semiconductor packages.

[0030] Figures 2A to 2E This is a cross-sectional schematic diagram illustrating the manufacturing method of the semiconductor package of the present invention.

[0031] The reference numerals in the attached figures are explained as follows:

[0032] 1, 2a: Temporary substrate

[0033] 10, 20: plate body

[0034] 11: Thick copper foil

[0035] 12: Thin copper foil

[0036] 13: Barrier layer

[0037] 2: Carrier board

[0038] 21: First Copper Foil

[0039] 22: Second copper foil

[0040] 9: Semiconductor packages

[0041] 9a: Semiconductor package

[0042] A: Packaging area

[0043] B: Removal Area

[0044] E: Sintering area

[0045] L: Cutting path

[0046] S: Interface

[0047] t1, t2: thickness.

[0048] Z: Laser Detailed Implementation

[0049] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0050] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "below," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0051] Figures 2A to 2E This is a cross-sectional schematic diagram illustrating the manufacturing method of the semiconductor package 9 of the present invention.

[0052] like Figure 2A As shown, a temporary substrate 2a is provided, which includes a plate 20, a first copper foil 21 disposed on the plate 20, and a second copper foil 22 disposed on the first copper foil 21, wherein the thickness t1 of the first copper foil 21 is greater than the thickness t2 of the second copper foil 22, and an encapsulation area A and a removal area B adjacent to the encapsulation area A are defined on the second copper foil 22.

[0053] In this embodiment, the second copper foil 22 is electrostatically adsorbed (at the interface S shown in the figure) onto the first copper foil 21.

[0054] like Figure 2B As shown, the inner edge of the packaging area A is sintered by laser Z to form a sintering area E on a portion of the interface S between the first copper foil 21 and the second copper foil 22, so that the first copper foil 21 and the second copper foil 22 are bonded together to form a carrier plate 2.

[0055] In this embodiment, the high temperature of the laser Z melts the copper material, causing the first copper foil 21 and the second copper foil 22 to fuse together without any interface. After cooling and solidification, the sintering area E is formed in a portion of the interface S corresponding to the edge of the encapsulation area A, while the other areas of the interface S between the first copper foil 21 and the second copper foil 22 remain electrostatically attracted to each other.

[0056] like Figure 2C As shown, semiconductor packaging processes, such as die placement, wiring, and molding, are performed on the entire surface of the second copper foil 22 to form a semiconductor package 9a.

[0057] like Figure 2DAs shown, a dicing process is performed along the edge of the packaging area A to remove excess structures (such as those corresponding to structures located on the removal area B) of the semiconductor package 9a, while the remaining structures (such as those corresponding to structures located on the packaging area A) serve as the semiconductor package 9. The dicing process's cutting path L passes through the mark or boundary formed by the sintering point E to remove the sintering point E and the structures above and below it.

[0058] like Figure 2E As shown, since there is no longer a sintered joint E between the first copper foil 21 and the second copper foil 22, the first copper foil 21 and the second copper foil 22 can be separated by peeling to remove the plate 20. Then, the second copper foil 22 beneath the semiconductor package 9 is removed by etching to obtain the semiconductor package 9.

[0059] Therefore, in the manufacturing method of the semiconductor package 9 of the present invention, only a sintering operation is required by laser Z (e.g., Figure 2B As shown, the first copper foil 21 and the second copper foil 22 can be bonded together, which greatly simplifies the pre-processing of the semiconductor packaging process. It also eliminates the need for existing resist layers such as dry films, and therefore eliminates the need for different equipment required for dry film preparation. Therefore, compared with the prior art, the manufacturing method of the present invention is not only simple and time-saving before manufacturing the semiconductor package 9, but also greatly reduces the cost of manufacturing the semiconductor package 9 because it only requires a laser machine for sintering.

[0060] Furthermore, since the first copper foil 21 and the second copper foil 22 are fixed together by sintering, the positioning between them is excellent. Therefore, compared with the prior art, when the semiconductor packaging process is carried out, the second copper foil 22 will not be displaced due to external force, thus effectively maintaining the accuracy of subsequent die placement and wiring operations.

[0061] Furthermore, since the semiconductor package manufacturing method of the present invention does not require the fabrication of an existing protruding platform, the semiconductor packaging process can be carried out on a flat surface (i.e., the second copper foil 22). Therefore, compared with the prior art, when the present invention performs molding operations on the second copper foil 22, it can effectively control the flowability of the encapsulating colloid to facilitate stress dispersion and avoid problems such as stress concentration.

[0062] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A method for manufacturing a carrier plate, comprising: providing a temporary substrate for semiconductor package manufacturing process, which comprises a plate body, a first copper foil disposed on the plate body, and a second copper foil disposed on the first copper foil, and a package area and a removal area adjacent to the package area are defined on the second copper foil; and forming a sintering portion on a partial area of an interface between the first copper foil and the second copper foil by laser sintering an inner edge of the package area, so that the first copper foil and the second copper foil are fused into one body without an interface, wherein a mark or a boundary formed by the sintering portion is a cutting path of a singulation process of the semiconductor package manufacturing process.

2. The method of making a carrier plate of claim 1, wherein, Other areas of the interface between the first copper foil and the second copper foil are electrostatically adsorbed to each other.

3. A carrier plate, comprising: a plate body for semiconductor package manufacturing process; a first copper foil disposed on the plate body; and a second copper foil disposed on the first copper foil, and a package area and a removal area adjacent to the package area are defined on the second copper foil, wherein a sintering portion is formed on a partial area of an interface between the first copper foil and the second copper foil by laser sintering an inner edge of the package area, so that the first copper foil and the second copper foil are fused into one body without an interface. A thickness of the first copper foil is greater than a thickness of the second copper foil.

4. The carrier panel of claim 3, wherein, Other areas of the interface between the first copper foil and the second copper foil are electrostatically adsorbed to each other.

5. The carrier panel of claim 3, wherein, 6. A semiconductor package manufacturing process, comprising: providing a carrier plate as claimed in claim 3; performing semiconductor package manufacturing process on the second copper foil; performing a singulation process along an edge of the package area to remove the sintering portion and structures above and below the sintering portion by cutting, wherein a cutting path of the singulation process passes through a mark or a boundary formed by the sintering portion to form a semiconductor package; and removing the plate body, the first copper foil, and the second copper foil. Other areas of the interface between the first copper foil and the second copper foil are electrostatically adsorbed to each other.

7. The method of making a semiconductor package of claim 6, wherein, ​

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