Method, device and medium for dc bias suppression of dual active bridge dc converter

Abstract

The application provides a DC bias suppression method, device and medium for a dual active bridge DC converter, which comprises the following steps: generating a non-synchronous carrier when the dual active bridge DC converter is stably running, adopting a modulation method for the non-synchronous carrier, selecting different working modes according to the type of the modulation method, and finally distributing the driving signals of the switching tubes of the dual active bridge DC converter according to the selection of the working modes after comparing the non-synchronous carrier and the modulation wave, so as to eliminate the inductance current bias and excitation current bias in the transient process. In terms of applicability, the application can be applied to single phase-shift modulation, 1st side extended phase-shift modulation strategy, 2nd side extended phase-shift modulation strategy, triple phase-shift modulation strategy and double phase-shift modulation strategy. In terms of complexity, the application does not need any transient calculation and realizes automatic suppression of DC bias by using an improved modulation algorithm.

Description

Technical Field

[0001] This invention belongs to the field of DC-DC conversion technology in the field of power electronics technology, specifically relating to a DC bias suppression method, device and medium for dual active bridge DC-DC converters. Background Technology

[0002] Dual Active Bridge (DAB) DC-DC converters offer advantages such as electrical isolation, bidirectional controllable power transfer, zero-voltage soft switching, and simple control, and are widely used in rail transit power supply, data center power supply, and power electronic transformers. For different power ranges and voltage regulation ranges, DABs employ different modulation methods to improve steady-state operating efficiency, reduce return current power, and ensure zero-voltage soft switching. These include Single-phase Shift (SPS), Extended-phase Shift (EPS), Dual-phase Shift (DPS), and Triple-phase Shift (TPS).

[0003] During sudden changes in load and input voltage, the phase shift angle may suddenly increase, decrease, or reverse, causing asymmetry in the voltage at the primary and secondary bridge ports. This results in transient DC bias in the inductor current and transformer magnetizing current. DC bias in the inductor current increases the current stress on the switching transistors, leading to increased switching losses. DC bias in the transformer magnetizing current reduces the flux swing margin of the magnetic core, and may even cause flux saturation, leading to core overheating and burnout. Therefore, suppressing DC bias in a dual active bridge DC-DC converter is crucial for reliable operation.

[0004] Existing DC bias suppression methods are only applicable to specific modulation schemes. For example, Chinese patent CN104467434B, "A Transient Phase-Shift Control Method for Dual Active Full-Bridge DC-DC Converters," proposes adjusting the turn-on and turn-off times of the switching transistors to eliminate transient bias in the first cycle after a sudden change in the phase-shift duty cycle, specifically for single-phase-shift control. However, this method is only applicable to single-phase-shift modulation where both the primary and secondary sides have phase-shift duty cycles. Chinese patent CN111628655A, "A General Phase-Shift Control Method for Transient DC Bias in Dual Active Bridge DC-DC Converters," proposes a method for eliminating bias current in single-phase, dual-phase, and triple-phase-shift modulation, but the control process is complex and not applicable to extended phase-shift modulation. Existing DC bias suppression methods also require complex calculations, which is not conducive to practical engineering applications. Summary of the Invention

[0005] This invention provides a DC bias suppression method, apparatus, and medium for a dual active DC-DC converter, which solves the problems that existing DC bias suppression methods are only applicable to specific modulation schemes and involve complex calculations. This invention compares the asynchronous carrier wave with the modulation wave to allocate the drive signal of the switching transistors of the dual active bridge DC-DC converter, thereby eliminating the inductor current bias and excitation current bias generated during transient processes.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] A method for suppressing DC bias in a dual active bridge DC-DC converter includes the following steps:

[0008] S1: When the dual active bridge DC-DC converter is operating stably, it generates an asynchronous carrier, which includes: a reference sawtooth carrier T. ref The triangular carrier T of the half-bridge circuit 1A 1A The triangular carrier T of half-bridge circuit 1B 1B The triangular carrier T of the 2A half-bridge circuit 2A The triangular carrier T of half-bridge circuit 2B 2B ;

[0009] S2: A modulation method is applied to the asynchronous carrier, including: single phase shift modulation, first-side extended phase shift modulation, second-side extended phase shift modulation, double phase shift modulation, and triple phase shift modulation;

[0010] S3: Depending on the type of modulation method, different operating modes are selected for the modulation wave. These operating modes include Mode 1 and Mode 2. The modulation wave includes the modulation wave C of the half-bridge circuit 1A. 1A The modulation wave C of half-bridge circuit 1B 1B The modulation wave C of the half-bridge circuit 2A 2A The modulation wave C of half-bridge circuit 2B 2B ;

[0011] S4: Based on the selection of the working mode, after comparing the asynchronous carrier wave and the modulation wave, the drive signals of the switching transistors of the dual active bridge DC converter are allocated, and the inductor current bias and excitation current bias of the transient process are eliminated according to the allocation of the drive signals.

[0012] Furthermore, in S3, when using single-phase-shift modulation, first-side extended phase-shift modulation, second-side extended phase-shift modulation, or triple-phase-shift modulation, the modulation wave selection mode is 1; when using dual-phase-shift modulation, the modulation wave selection mode is 2.

[0013] Further, in S2, the external phase shift duty cycle of the single-phase-shift modulation is D2; the primary-side internal phase shift duty cycle of the primary-side extended phase shift modulation is D. 11The external phase shift duty cycle is D2; the primary side internal phase shift duty cycle of the secondary side extended phase shift modulation is D. 12 The external phase shift duty cycle is D2; the primary phase shift duty cycle of the triple phase shift modulation is D. 11 The duty cycle of the second-side internal phase shift is D. 12 The duty cycle of the outer phase shift is D2; the duty cycle of the inner phase shift on both sides of the dual phase shift modulation is D1, and the duty cycle of the outer phase shift is D2.

[0014] Furthermore, in S3, when the modulation wave is mode 1, the modulation wave C of the half-bridge circuit 1A... 1A = (1+D) 11 +D 12 ) / 4, the modulation wave C of half-bridge circuit 1B 1B =(3-D 11 +D 12 ) / 4, the modulation wave C of the half-bridge circuit 2A 2A = (1+D) 11 +D 12 +2D2) / 4, the modulation wave C of the half-bridge circuit 2B 2B =(3+D) 11 -D 12 +2D2) / 4.

[0015] Furthermore, in S3, when the modulation wave is mode 2, the modulation wave C of the half-bridge circuit 1A... 1A = (1+D1) / 4, the modulation wave C of half-bridge circuit 1B 1B = (3-D1) / 4, the modulation wave C of the 2A half-bridge circuit 2A = (1+D1+2D2) / 4, the modulation wave C of half-bridge circuit 2B 2B = (3-D1+2D2) / 4.

[0016] Furthermore, in S4, the comparison of the asynchronous carrier and the modulated wave specifically includes: when the reference sawtooth carrier T ref The modulation wave C equal to 1A of the half-bridge circuit 1A At that time, the triangular carrier T of half-bridge circuit 1A 1A Reset to 0; when the reference sawtooth carrier T ref The modulated wave C equals that of half-bridge circuit 1B 1B At that time, the triangular carrier T of half-bridge circuit 1B 1B Reset to 0; when the reference sawtooth carrier T ref The modulation wave C equal to 2A of the half-bridge circuit 2A At that time, the triangular carrier T of the half-bridge circuit 2A 2A Reset to 0; when the reference sawtooth carrier T ref The modulated wave C is equal to that of the half-bridge circuit 2B. 2B At that time, the triangular carrier T of half-bridge circuit 2B2B Reset to 0.

[0017] Furthermore, in S4, the drive signal for allocating the switching transistors of the dual active bridge DC-DC converter includes: when T 1A When T = 1, the drive signal for the upper switch transistor of the half-bridge circuit 1A is set to high level, and the drive signal for the lower switch transistor is set to low level; when T 1B When T = 1, the upper switch drive signal of half-bridge circuit 1B is set to high level, and the lower switch drive signal is set to low level; when T 2A When T = 1, the upper switch drive signal of half-bridge circuit 2A is set to high level, and the lower switch drive signal is set to low level; when T 2B When = 1, the upper switch drive signal of half-bridge circuit 2B is set to high level, and the lower switch drive signal is set to low level.

[0018] Furthermore, in S4, the drive signal for allocating the switching transistors of the dual active bridge DC-DC converter also includes: when T 1A When T = 0, the upper switch drive signal of half-bridge circuit 1A is set to low level, and the lower switch drive signal is set to high level; when T 1B When T = 0, the upper switch drive signal of half-bridge circuit 1B is set to low level, and the lower switch drive signal is set to high level; when T 2A When T = 0, the upper switch drive signal of half-bridge circuit 2A is set to low level, and the lower switch drive signal is set to high level; when T 2B When = 0, the upper switch drive signal of half-bridge circuit 2B is set to low level, and the lower switch drive signal is set to high level.

[0019] An apparatus for DC bias suppression of a dual active bridge DC converter includes a memory and a processor. The memory stores a DC bias suppression program for the dual active bridge DC converter that runs on the processor. When the processor executes the DC bias suppression program for the dual active bridge DC converter, it implements the steps of the DC bias suppression method for the dual active bridge DC converter.

[0020] A storage medium stores a DC bias suppression program for a dual active bridge DC converter. The suppression program for the dual active bridge DC converter can be executed by one or more processors to implement the steps of the DC bias suppression method for the dual active bridge DC converter.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] This invention provides a DC bias suppression method for a dual active bridge DC-DC converter. By comparing an asynchronous carrier wave with a modulation wave, the method allocates the switching transistor drive signals of the dual active bridge DC-DC converter, eliminating the inductor current bias and magnetizing current bias generated during transient processes. In terms of applicability, this invention can be applied to single-phase-shift modulation, primary-side extended phase-shift modulation strategies, secondary-side extended phase-shift modulation strategies, triple-phase-shift modulation strategies, and dual-phase-shift modulation strategies. In terms of complexity, this invention requires no transient calculations and utilizes an improved modulation algorithm to achieve automatic DC bias suppression. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is the main circuit of a dual active bridge DC-DC converter;

[0025] Figure 2 This is the waveform diagram for mode 1.

[0026] Figure 3 This is the waveform diagram for mode 2.

[0027] Figure 4 The transient bias current suppression waveform of mode 1 when D2 increases;

[0028] Figure 5 D 11 When the current is reduced, the waveform of transient bias current suppression in mode 1 is shown.

[0029] Figure 6 The transient bias current suppression waveform of mode 2 when D1 increases;

[0030] Figure 7 The waveform of transient bias current suppression experiment in mode 1 when D2 increases;

[0031] Figure 8 This is a schematic diagram of the device used in this invention. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. The content described herein is for explanation rather than limitation of the present invention.

[0033] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification and claims of this invention are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such processes, methods, systems, products, or devices.

[0034] This invention provides a DC bias suppression method for a dual active DC-DC converter. This method uses a comparison between an asynchronous carrier wave and a modulation wave to allocate the switching transistor drive signal of the dual active bridge DC-DC converter, thereby eliminating the inductor current bias and magnetizing current bias during transient processes.

[0035] The dual active bridge converter consists of half-bridge circuit 1A, half-bridge circuit 1B, half-bridge circuit 2A, half-bridge circuit 2B, auxiliary inductor, and intermediate frequency transformer. Each half-bridge circuit includes two switching transistors.

[0036] The dual active bridge converter operates under a single phase-shift modulation strategy, a primary-side extended phase-shift modulation strategy, a secondary-side extended phase-shift modulation strategy, a triple phase-shift modulation strategy, or a dual phase-shift modulation strategy.

[0037] The control variable for the single-phase-shift modulation strategy is the external phase-shift duty cycle D2;

[0038] The control variables of the primary-side extended phase-shift modulation strategy include: the primary-side internal phase-shift duty cycle D. 11 and the duty cycle D2 of the outward-shifting phase;

[0039] The control variables of the secondary side extended phase-shift modulation strategy include: the primary side internal phase-shift duty cycle D. 12 and the duty cycle D2 of the outward-shifting phase;

[0040] The control variables of the triple phase-shift modulation strategy include: the primary phase-shift duty cycle D. 11 2nd side internal phase shift duty cycle D 12 and the duty cycle D2 of the outward-shifting phase;

[0041] The control variables of the dual phase-shift modulation strategy include the dual-side inner phase-shift duty cycle D1 and the outer phase-shift duty cycle D2.

[0042] The asynchronous carrier consists of a reference sawtooth carrier T. ref The triangular carrier T of the half-bridge circuit 1A 1A The triangular carrier T of half-bridge circuit 1B 1B The triangular carrier T of the 2A half-bridge circuit 2A and the triangular carrier T of the half-bridge circuit 2B 2B composition.

[0043] The modulation wave is divided into mode 1 and mode 2. The modulation wave of mode 1 includes: the modulation wave C of half-bridge circuit 1A. 1A = (1+D) 11 +D 12 ) / 4, Modulation wave C of half-bridge circuit 1B 1B =(3-D 11 +D 12 ) / 4, Modulation wave C of half-bridge circuit 2A 2A = (1+D) 11 +D 12 The modulation wave C of +2D2) / 4 and half-bridge circuit 2B 2B =(3+D) 11 -D 12 +2D2) / 4; The modulation wave of mode 2 includes: the modulation wave C of half-bridge circuit 1A. 1A = (1+D1) / 4, the modulation wave C of half-bridge circuit 1B 1B = (3-D1) / 4, the modulation wave C of the 2A half-bridge circuit 2A = (1+D1+2D2) / 4, the modulation wave C of half-bridge circuit 2B 2B = (3-D1+2D2) / 4.

[0044] When the dual active bridge converter adopts a single phase-shift modulation strategy, a primary-side extended phase-shift modulation strategy, a secondary-side extended phase-shift modulation strategy, or a triple phase-shift modulation strategy, the modulation wave operates in mode 1; when the dual active bridge converter adopts a dual phase-shift modulation strategy, the modulation wave operates in mode 2.

[0045] When Tref = C 1A At that time, T 1A Reset to 0; when Tref = C 1B At that time, T 1B Reset to 0; when Tref = C 2A At that time, T 2A Reset to 0; when Tref = C 2B At that time, T 2B Reset to 0;

[0046] When T iX When i = 1 (i = 1, 2) (X = A, B), the upper transistor drive signal of the half-bridge circuit iX is set high, and the lower transistor drive signal is set low; when T iX When i = 0 (i = 1, 2) (X = A, B), the upper drive signal of the half-bridge circuit iX is set low, and the lower drive signal is set high.

[0047] like Figure 8As shown, the present invention provides a device for DC bias suppression of a dual active bridge DC converter, including a memory and a processor. The memory stores a DC bias suppression program for the dual active bridge DC converter that runs on the processor. When the DC bias suppression program for the dual active bridge DC converter is executed by the processor, it implements the steps of the DC bias suppression method for the dual active bridge DC converter.

[0048] The present invention provides a storage medium storing a DC bias suppression program for a dual active bridge DC converter. The suppression program for the dual active bridge DC converter can be executed by one or more processors to implement the steps of the DC bias suppression method for the dual active bridge DC converter.

[0049] Figure 1 This is the main circuit of a dual active bridge DC-DC converter, including half-bridge circuit 1A, half-bridge circuit 1B, half-bridge circuit 2A, half-bridge circuit 2B, and auxiliary inductor L. pri The intermediate frequency transformer T has primary voltage input terminals P1 and N1, and secondary voltage input terminals P2 and N2. The primary input voltage is V1, and the secondary input voltage is V2.

[0050] Figure 2 The diagram shows the waveform of the modulated wave in mode 1 of this invention. At time t1, the modulated wave C... 1A C 1B C 2A C 2B Update; at time t2, the modulated wave C 1A With carrier T ref Intersection, causing carrier T 1A Set to zero; at time t3, the modulated wave C 2A With carrier T ref Intersection, causing carrier T 2A Set to zero; at time t4, the modulated wave C 1B With carrier T ref Intersection, causing carrier T 1B Set to zero; at time t5, the modulated wave C 2B With carrier T ref Intersection, causing carrier T 2B Set to zero. When using single-phase-shift modulation, D 11 =0,D 12 =0; When using the first-side extended phase-shift modulation method, D 12 =0; When using the second-side extended phase-shift modulation method, D 11 =0; When using triple phase-shift modulation, D 11 ≠0, D 12 ≠0.

[0051] Figure 3The diagram shows the working waveform of the modulated wave in mode 2 of this invention, which is in a dual phase-shift modulation mode, with the duty cycle of the inner phase shift on both sides being D1.

[0052] Figures 4-7 In the middle, the excitation current is i m The inductor current is i pri .

[0053] Figure 4 An example is shown illustrating the transient bias current suppression waveform in Mode 1 when the external phase shift duty cycle D2 increases to D2'. The theoretical proof of bias current suppression is given below:

[0054] according to Figure 1 The circuit connection shown indicates that the magnetizing inductance of the intermediate frequency transformer T is determined by the secondary bridge voltage v. CD In clamping mode, the condition for no bias current in the magnetizing inductor is v. CD The integral value has no DC bias; auxiliary inductor L pri The voltage v at the primary side bridge port AB and the voltage v at the secondary side bridge port CD For common clamping, according to the superposition theorem, the condition for no bias current in the auxiliary inductor is v. AB and v CD The integral values ​​are all without DC bias. This is due to the modulation wave C of the primary side bridge arm. 1A and C 1B Regardless of D2, when D2 increases to D2', the voltage at the primary side bridge port v AB There is no transient process, and its integral value is always 0. Therefore, it is guaranteed that v CD The integral value can be obtained without DC bias to ensure that there is no bias current in both the magnetizing inductor and the auxiliary inductor.

[0055] In steady state, according to C 2A and C 2B The expression, v CD The voltage transition times are as follows:

[0056]

[0057] Where Ts is the switching period.

[0058] Let t A Time v CD The integral value is I(t) A Then at each jump point, v CD The integral value can be expressed as:

[0059]

[0060] In steady state, v CDThe integral value has no DC bias, meaning the average value of the integral value over the switching cycle is zero.

[0061]

[0062] Substituting equations (1) and (2) into equation (3), we get:

[0063]

[0064] In the transient state, v CD The jump point expressions are as follows:

[0065]

[0066] According to equation (2), at the end of the transient state t F v CD The integral value can be expressed as:

[0067]

[0068] Substituting equation (4) into equation (6), we get

[0069]

[0070] The above equation shows that after a transient period, v CD The integral value transitions to the initial value of the new steady state. According to equations (3) and (4), this initial value ensures that there is no DC bias in the new steady state cycle, that is, the increase of the external phase shift duty cycle D2 to D2' will not cause bias current in the magnetizing inductor and the auxiliary inductor.

[0071] Figure 5 An example is shown showing the internal phase shift duty cycle D. 11 The transient bias current suppression waveform of Mode 1 when the duty cycle D2 increases. Referring to the analysis process of increasing the external phase shift duty cycle D2, D... 11 Sudden transients also do not generate excitation or inductor current bias.

[0072] Figure 6 An example is shown, illustrating the transient bias current suppression waveform in Mode 2 when the dual-sided internal phase shift duty cycle D1 increases. After experiencing the transient period, the excitation current and inductor current enter a new unbiased steady state.

[0073] Figure 7 An example is shown, illustrating the transient bias current suppression experimental waveforms in Mode 1 when the external phase shift duty cycle D2 increases. After experiencing the transient period, the excitation current and inductor current enter a new unbiased steady state.

[0074] As is known from common technical knowledge, the present invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones; all modifications within the scope of the present invention or equivalent to the scope of the present invention are included in the present invention.

Claims

1. A method for suppressing DC bias in a dual active bridge DC-DC converter, characterized in that, Includes the following steps: S1: When the dual active bridge DC-DC converter is operating stably, it generates an asynchronous carrier, which includes: a reference sawtooth carrier T. ref The triangular carrier T of the half-bridge circuit 1A 1A The triangular carrier T of half-bridge circuit 1B 1B The triangular carrier T of the 2A half-bridge circuit 2A The triangular carrier T of half-bridge circuit 2B 2B ; S2: A modulation method is applied to the asynchronous carrier, including: single phase shift modulation, first-side extended phase shift modulation, second-side extended phase shift modulation, double phase shift modulation, and triple phase shift modulation; S3: Depending on the type of modulation method, different operating modes are selected for the modulation wave. These operating modes include Mode 1 and Mode 2. The modulation wave includes the modulation wave C of the half-bridge circuit 1A. 1A The modulation wave C of half-bridge circuit 1B 1B The modulation wave C of the half-bridge circuit 2A 2A The modulation wave C of half-bridge circuit 2B 2B ; S4: Based on the selection of the working mode, after comparing the asynchronous carrier wave and the modulation wave, the drive signals of the switching transistors of the dual active bridge DC converter are allocated, and the inductor current bias and excitation current bias of the transient process are eliminated according to the allocation of the drive signals. In S2, the external phase shift duty cycle of the single-phase-shift modulation is D2; the internal phase shift duty cycle of the primary-side extended phase shift modulation is D. 11 The external phase shift duty cycle is D2; the primary internal phase shift duty cycle of the secondary side extended phase shift modulation is D. 12 The external phase shift duty cycle is D2; the primary phase shift duty cycle of the triple phase shift modulation is D. 11 The duty cycle of the second-side internal phase shift is D. 12 The duty cycle of the outer phase shift is D2; the duty cycle of the inner phase shift on both sides of the dual phase shift modulation is D1, and the duty cycle of the outer phase shift is D2; In S3, when the modulation wave is mode 1, the modulation wave C of the half-bridge circuit 1A 1A =(1+D 11 +D 12 ) / 4, Modulation wave of half-bridge circuit 1B The modulation wave C of the half-bridge circuit 2A 2A =(1+D 11 +D 12 +2D2) / 4, the modulation wave of half-bridge circuit 2B ; In S3, when the modulation wave is mode 2, the modulation wave C of the half-bridge circuit 1A 1A =(1+D1) / 4, the modulation wave of half-bridge circuit 1B The modulation wave C of the half-bridge circuit 2A 2A =(1+D1+2D2) / 4, the modulation wave of half-bridge circuit 2B .

2. The DC bias suppression method for a dual active bridge DC-DC converter according to claim 1, characterized in that, In S3, when using single-phase-shift modulation, first-side extended phase-shift modulation, second-side extended phase-shift modulation, or triple-phase-shift modulation, the modulation wave selects mode 1; when using dual-phase-shift modulation, the modulation wave selects mode 2.

3. The DC bias suppression method for a dual active bridge DC-DC converter according to claim 1, characterized in that, In S4, the comparison of the asynchronous carrier and the modulated wave specifically includes: When the reference sawtooth carrier T ref The modulation wave C equal to 1A of the half-bridge circuit 1A At that time, the triangular carrier T of half-bridge circuit 1A 1A Reset to 0; When the reference sawtooth carrier T ref The modulated wave C equals that of half-bridge circuit 1B 1B At that time, the triangular carrier T of half-bridge circuit 1B 1B Reset to 0; When the reference sawtooth carrier T ref The modulation wave C equal to 2A of the half-bridge circuit 2A At that time, the triangular carrier T of the half-bridge circuit 2A 2A Reset to 0; When the reference sawtooth carrier T ref The modulated wave C is equal to that of the half-bridge circuit 2B. 2B At that time, the triangular carrier T of half-bridge circuit 2B 2B Reset to 0.

4. The DC bias suppression method for a dual active bridge DC-DC converter according to claim 1, characterized in that, In S4, the drive signals for allocating the switching transistors of the dual active bridge DC-DC converter include: When T 1A When =1, the upper switch drive signal of half-bridge circuit 1A is set to high level, and the lower switch drive signal is set to low level. When T 1B When =1, the upper switch drive signal of half-bridge circuit 1B is set to high level, and the lower switch drive signal is set to low level. When T 2A When =1, the upper switch drive signal of half-bridge circuit 2A is set to high level, and the lower switch drive signal is set to low level. When T 2B When =1, the upper switch drive signal of half-bridge circuit 2B is set to high level, and the lower switch drive signal is set to low level.

5. The DC bias suppression method for a dual active bridge DC-DC converter according to claim 1, characterized in that, In S4, the drive signals for allocating the switching transistors of the dual active bridge DC-DC converter also include: When T 1A When =0, the upper switch drive signal of half-bridge circuit 1A is set to low level, and the lower switch drive signal is set to high level. When T 1B When =0, the upper switch drive signal of half-bridge circuit 1B is set to low level, and the lower switch drive signal is set to high level. When T 2A When =0, the upper switch drive signal of half-bridge circuit 2A is set to low level, and the lower switch drive signal is set to high level. When T 2B When =0, the upper switch drive signal of half-bridge circuit 2B is set to low level, and the lower switch drive signal is set to high level.

6. A device for suppressing DC bias in a dual active bridge DC-DC converter, characterized in that, The device includes a memory and a processor. The memory stores a DC bias suppression program for a dual active bridge DC converter that runs on the processor. When the processor executes the DC bias suppression program for the dual active bridge DC converter, it implements the steps of the DC bias suppression method for the dual active bridge DC converter according to any one of claims 1 to 5.

7. A storage medium, characterized in that, The storage medium stores a DC bias suppression program for a dual active bridge DC converter. The DC bias suppression program for the dual active bridge DC converter can be executed by one or more processors to implement the steps of the DC bias suppression method for the dual active bridge DC converter according to any one of claims 1 to 5.

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