Optimal adjustment method and system for FPGA high-speed transceiver parameters

Abstract

The present application relates to FC fiber channel network communication technical field, and more particularly to a kind of optimization adjustment method and system of FPGA high-speed transceiver parameter.The optimization adjustment method of FPGA high-speed transceiver parameter in the present application increases a group of parameter adjustment modules in FPGA chip for each GT, when node device FPGA chip interconnects, can be carried out online, automated, accurate GT parameter optimization adjustment by control module, improves the efficiency and accuracy of GT parameter adjustment of FPGA chip in online interconnection stage, reduces the workload of manual operation, effectively improves the debugging efficiency of communication equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of FC fiber channel network communication technology, and in particular to a method and system for optimizing adjustment of FPGA high-speed transceiver parameters. BACKGROUND

[0002] Airborne data bus technology is a technology for interconnection between airborne devices, subsystems and modules. From the perspective of computer concept, various avionics devices are equivalent to microcomputers, and bus communication technology is a channel and link connecting the microcomputers, so that the avionics devices form a network with complete functions. FC (Fibre Channel) is a channel standard proposed by the American National Standards Institute (ANSI) in 1988, aiming to meet the growing demand for high-speed data channels inside aerospace vehicles. The FC serial transmission rate can reach 133 Mbps-1.0625 Gbps.

[0003] FC fiber channel is a standard-based network structure, which has the advantages of both channel and network, so that the same physical interface can run the current mainstream channel standards and network protocols. The huge data throughput makes it possible to transmit a large amount of data between different systems, and the same equipment can be used to establish any topology to meet different connection characteristics, such as point-to-point communication network, arbitration ring communication network, switching network, etc., to realize high-speed communication between node devices.

[0004] In the communication topology structure of FC fiber channel, a node device is usually configured with one or more fiber channel ports (FC ports). The node device is connected to the host through a PCIE interface, and communicates with the host to send service messages to the host, receive configuration information of the node device (FPGA, DDR storage, optical signal processing, etc.) from the host, and connect the host to the FC topology network through the FC port.

[0005] The performance of the high-speed transceiver (Gigabyte Transceiver, also known as GT) in the FPGA chip is crucial in the communication process, and its performance directly affects whether the communication between the two parties can be normally connected and communicated. In the daily debugging process, adjusting the working mode and pre-emphasis parameters of the GT is an important means to adjust its performance.

[0006] With the continuous expansion of the performance and resources of the FPGA chip, the number of GT resources is also increasing from several to dozens, and the performance difference between GTs leads to the inability to use the same set of parameters to configure all GT performance, thus facing a huge parameter debugging work. The current GT parameter debugging work mostly relies on manual adjustment, and usually a set of parameters is used to configure all GT ports, which cannot achieve precise configuration of each GT parameter. Such operation may cause the parameter deviation of some ports to be too large, resulting in individual port errors or even communication failure, which causes a huge stability risk for the use of the device.

[0007] The Vivado design suite is an integrated design environment EDA tool released by the FPGA manufacturer Xilinx Corporation, and through the ibert tool of the Vivado design suite, the hardware debugging of the GT of the FPGA can be performed on the board, the bit error rate can be obtained, and the optimal parameter searching algorithm can be used to adjust the parameters of the serial transceiver, verify the stability and integrity of the signal, etc., but the Vivado running ibert can only be used in the state of single device self-loop test, and cannot realize the parameter optimization in the interconnection state of the device.

[0008] In the actual test of the GT of the FPGA, it is found that the optimal parameters in the self-loop state are not the optimal parameters in the device interconnection state, so it is impossible to automatically adjust the parameters in the device interconnection state. SUMMARY

[0009] The present application aims to provide a kind of optimal adjustment method and system of FPGA high-speed transceiver parameter, it can be applicable to the FPGA configuration of FC fiber channel node device, it can automatically adjust parameters in the interconnection state of node device, and it is efficient to realize automatic GT parameter adjustment.

[0010] According to the first aspect of the object of the present application, an optimal adjustment system of FPGA high-speed transceiver parameter is provided, comprising:

[0011] At least one first FPGA chip is configured with a first GT and a first parameter adjustment module, and the first parameter adjustment module is connected with the transceiver end of the first GT in communication;

[0012] At least one second FPGA chip is configured with a second GT and a second parameter adjustment module, and the second GT is connected with the first GT in communication, and the second parameter adjustment module is connected with the transceiver end of the second GT in communication;

[0013] A control module is connected with the first parameter adjustment module and the second parameter adjustment module in communication through an independent configuration interface;

[0014] The control module sends configuration parameters to the corresponding first parameter adjustment module and second parameter adjustment module respectively through the configuration interface and receives the corresponding error code statistical result, and optimizes the GT configuration parameters based on the error code statistical result.

[0015] Therefore, in the embodiment of the application, by adding parameter adjustment modules in the FPGA chip, each GT is configured with a parameter adjustment module and connected with the transceiving end of the GT, and in the interconnection state of the FPGA chip (node device), the corresponding number of parameter adjustment modules can be configured according to the number of GTs to optimize the transmission parameters, so as to automatically optimize and accurately adjust the configuration parameters that affect the communication quality, such as the communication mode (LPM mode or DFE mode) and the pre-emphasis parameter (such as TXDIFFCTRL, TXPRECURSOR and TXPOSTCURSOR), reduce the error rate problem and communication abnormal risk caused by the deviation of the port transmission parameters, and efficiently realize the automatic optimization adjustment of the FPGA chip (node device) in the online interconnection state.

[0016] In the embodiment of the application, each parameter adjustment module includes a register, a parameter configuration module and an error code statistical module.

[0017] For example, the first parameter adjustment module includes a first register, a first parameter configuration module and a first error code statistical module, and the first register is in communication connection with the control module through the first configuration interface. The first parameter configuration module and the first error code statistical module are both connected with the first register; the first parameter configuration module is connected with the sending end of the first GT, used to send configuration information to the sending end of the first GT to adjust the sending performance of the first GT; the first error code statistical module is connected with the receiving end of the first GT, used to read the error code mark signal output by the first GT and count the number of error codes, and send the error code statistical result in a predetermined time period to the first register, and the first register transmits the error code statistical result to the control module through the first configuration interface.

[0018] The second parameter adjustment module includes a second register, a second parameter configuration module and a second error code statistical module, and the second register is in communication connection with the control module through the second configuration interface. The second parameter configuration module and the second error code statistical module are both connected with the second register; the second parameter configuration module is connected with the sending end of the second GT, used to send configuration information to the sending end of the second GT to adjust the sending performance of the second GT; the second error code statistical module is connected with the receiving end of the second GT, used to read the error code mark signal output by the second GT and count the number of error codes, and send the error code statistical result in a predetermined time period to the second register, and the second register transmits the error code statistical result to the control module through the second configuration interface.

[0019] In the embodiments of the present application, the control module, for example, is configured in a higher-bit machine mode, and optimizes the configuration parameters of the first GT in the following manner:

[0020] The control module sends the configuration parameters, including initial values of the communication mode and the pre-emphasis parameters, to the first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface;

[0021] After receiving the initial configuration parameters, the first register modifies the transmission parameters of the transmission end of the first GT via the first parameter configuration module;

[0022] The control module sends the error code statistical instruction to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface, and the second register clears the counter in the second error code statistical module and starts timing after receiving the instruction. The second error code statistical module receives the error code marking signal from the receiving end of the second GT and performs error code number statistics. When the statistical time reaches the predetermined time period, the counting is stopped, and the error code statistical result is sent to the second register. The second register sends the statistical value to the control module via the second configuration interface;

[0023] The control module records the error code number statistical value sent by the second register of the second parameter adjustment module. After adjusting the configuration parameters according to the preset optimal value algorithm, the updated configuration parameters are sent to the first register of the first parameter adjustment module again to perform transmission parameter configuration adjustment and optimization. The above operation is repeated until the optimal parameter value of the transmission end of the first GT is obtained according to the preset optimal value algorithm.

[0024] In some other embodiments, the control module is configured to optimize the configuration parameters of the second GT in the following manner:

[0025] The control module sends the configuration parameters, including initial values of the communication mode and the pre-emphasis parameters, to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface;

[0026] After receiving the initial configuration parameters, the second register modifies the transmission parameters of the transmission end of the second GT via the second parameter configuration module;

[0027] The control module sends an error code statistics instruction to a first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface, the first register clears a counter in the first error code statistics module after receiving the instruction and starts timing, the first error code statistics module receives an error code marking signal from a receiving end of the first GT and performs error code number statistics, stops counting when the statistics time reaches a predetermined time period, and sends the error code statistics result to the first register, and the first register sends the statistics value to the control module through the first configuration interface;

[0028] The control module records the error code number statistics value sent by the first register of the first parameter adjustment module, adjusts the configuration parameters according to the preset optimal value algorithm, sends the updated configuration parameters to the second register of the second parameter adjustment module again, performs sending parameter configuration adjustment and optimization, and repeatedly performs the above operation until the optimal parameter value of the sending end of the second GT is obtained according to the preset optimal value algorithm.

[0029] In an optional embodiment, when the first FPGA chip and the second FPGA chip perform full-duplex communication, the optimal adjustment of the configuration parameters of the GTs on both sides is performed synchronously.

[0030] According to a second aspect of the object of the application, a method for optimal adjustment of FPGA high-speed transceiver parameters is further provided, and the method comprises the following steps:

[0031] The sending end and the receiving end configured by the first GT of the first FPGA chip and the second GT of the second FPGA chip are connected to each other, that is, the sending end of the first GT is connected to the receiving end of the second GT, and the sending end of the second GT is connected to the receiving end of the first GT.

[0032] The first parameter adjustment module and the second parameter adjustment module are respectively connected to the control module through independent first and second configuration interfaces.

[0033] The control module sends configuration parameters to the corresponding first and second parameter adjustment modules through the first and second configuration interfaces respectively, receives corresponding error code statistics results, and performs optimal adjustment of the configuration parameters of the first and second GTs based on the error code statistics results.

[0034] In an optional embodiment, the optimal adjustment process of the configuration parameters of the first GT comprises:

[0035] The control module sends configuration parameters, including the initial values of the communication mode and the pre-emphasis parameter, to the first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface.

[0036] After receiving the initial configuration parameters, the first register modifies the sending parameters of the sending end of the first GT through the first parameter configuration module;

[0037] The control module sends an error code statistical instruction to a second register of a second parameter adjustment module in a second FPGA chip via the second configuration interface, the second register clears the counter in the second error code statistical module after receiving the instruction and starts timing, the second error code statistical module receives error code marking signals from the receiving end of the second GT and performs error code number statistics, stops counting when the statistical time reaches a predetermined time period, and sends the error code statistical result to the second register, and the second register sends the statistical value to the control module via the second configuration interface;

[0038] The control module records the error code number statistical value sent by the second register of the second parameter adjustment module, adjusts the configuration parameters according to the preset optimal value algorithm, sends the updated configuration parameters to the first register of the first parameter adjustment module again, performs sending parameter configuration adjustment and optimization, and repeats the above operations until the optimal parameter value of the sending end of the first GT is obtained according to the preset optimal value algorithm.

[0039] In an optional embodiment, the optimal adjustment process of the configuration parameters of the second GT includes:

[0040] The control module sends configuration parameters including initial values of a communication mode and a pre-emphasis parameter to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface;

[0041] After receiving the initial configuration parameters, the first register modifies the sending parameters of the sending end of the first GT through the first parameter configuration module;

[0042] The control module sends an error code statistical instruction to a first register of a first parameter adjustment module in a first FPGA chip via the first configuration interface, the first register clears the counter in the first error code statistical module after receiving the instruction and starts timing, the first error code statistical module receives error code marking signals from the receiving end of the first GT and performs error code number statistics, stops counting when the statistical time reaches a predetermined time period, and sends the error code statistical result to the first register, and the first register sends the statistical value to the control module via the first configuration interface;

[0043] The control module records the error code number statistical value sent by the first register of the first parameter adjustment module, adjusts the configuration parameters according to the preset optimal value algorithm, sends the updated configuration parameters to the second register of the second parameter adjustment module again, performs sending parameter configuration adjustment and optimization, and repeats the above operations until the optimal parameter value of the sending end of the second GT is obtained according to the preset optimal value algorithm

[0044] Based on the above embodiments of the present invention, this invention addresses the issue of optimizing the transmitter configuration parameters in the online interconnection state of FPGA chips in FC fiber channel networks. It proposes adding a parameter adjustment module within the FPGA chip for each ground plane (GT), which, in conjunction with the control of the host computer, enables automatic and precise GT parameter adjustment, obtaining accurate parameters for each GT port. This parameter optimization adjustment method significantly improves the efficiency and accuracy of GT parameter adjustment in the online interconnection phase of the FPGA chip, reduces the workload of manual operation, and effectively improves the debugging efficiency of communication equipment.

[0045] It should be understood that all combinations of the foregoing concepts and the additional concepts described in more detail below may be considered part of the inventive subject matter of this disclosure, provided that such concepts do not contradict each other. Furthermore, all combinations of the claimed subject matter are considered part of the inventive subject matter of this disclosure.

[0046] The foregoing and other aspects, embodiments, and features of the teachings of the present invention will be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the invention, such as features and / or beneficial effects of exemplary embodiments, will become apparent from the following description or may be learned through practice of specific embodiments according to the teachings of the present invention. Attached Figure Description

[0047] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures may be denoted by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the invention will now be described by way of example and with reference to the accompanying drawings.

[0048] Figure 1 This is a schematic diagram of the module for adjusting the configuration parameters of each GT of the FPGA chip according to an embodiment of the present invention.

[0049] Figure 2 This is a schematic diagram showing the connection relationship between each GT and the corresponding parameter adjustment module in an embodiment of the present invention.

[0050] Figure 3 This is a schematic diagram of the GT parameter optimization adjustment system for two interconnected FPGA chips according to an embodiment of the present invention. Detailed Implementation

[0051] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0052] Aspects of the present disclosure are described herein with reference to the drawings, in which are shown by way of illustration various embodiments. Embodiments of the present disclosure are not necessarily intended to include all aspects of the present disclosure. It should be understood that various concepts and embodiments introduced in this summary include combinations, subsets, and / or equivalents of the various aspects described and / or shown herein. Additionally, it should be understood that various concepts and embodiments introduced in this summary include combinations, subsets, and / or equivalents of the various aspects described and / or shown herein.

[0053] In combination Figures 1-3 The embodiment shown is intended to optimize the sending end configuration parameters of the FC node device FPGA chip in the online interconnection state, and to add a set of parameter adjustment modules for each GT in the FPGA chip, cooperate with the control of the upper computer, realize the automatic and accurate GT parameter adjustment, and obtain the accurate parameters of each GT port.

[0054] As Figure 1 shown, the GT parameter configuration method of the FPGA chip high-speed transceiver proposed by the present application is intended to optimize the parameters in the GT configuration parameters which have a key impact on the communication quality, such as the communication mode (LPM mode or DFE mode) and the pre-emphasis parameters (such as TXDIFFCTRL, TXPRECURSOR, TXPOSTCURSOR), as shown in the combination Figure 1 、 2 In the FPGA chip, a parameter adjustment module corresponding to the GT is added, and the online, automatic, and accurate parameter optimization adjustment can be performed through the control of the upper computer (control module) during the interconnection of the node device, thereby improving the efficiency and accuracy of the GT parameter adjustment of the FPGA chip in the online interconnection stage, reducing the workload of manual operation, and effectively improving the debugging efficiency of the communication equipment.

[0055] Optimized adjustment system of FPGA high-speed transceiver parameters

[0056] As shown in the embodiment of the FPGA high-speed transceiver parameter optimization adjustment system of Figure 1 、 2 and 3, it includes at least one first FPGA chip (such as Figure 3 shown as #1) and at least one first FPGA chip (such as Figure 3 shown as #2).

[0057] In combination Figure 2 、 3 , the first FPGA chip (such as Figure 3 shown as #1) is configured with a first GT and a first parameter adjustment module, and the first parameter adjustment module is in communication connection with the transceiving end of the first GT.

[0058] The second FPGA chip (e.g., #2) is configured with a second GT and a second parameter adjustment module, the second GT is in communication connection with the first GT, and the second parameter adjustment module is in communication connection with the transceiving end of the second GT. Figure 3

[0059] As shown in Figure 3 The first GT and the second GT are both configured with a sending end and a receiving end and are connected with each other, wherein the sending end of the first GT is connected with the receiving end of the second GT, and the sending end of the second GT is connected with the receiving end of the first GT.

[0060] The control module is configured in the form of an upper computer, for example, and is in communication connection with the first parameter adjustment module and the second parameter adjustment module through independent configuration interfaces.

[0061] It should be understood that in the embodiments of the present application, each parameter adjustment module can be connected with the configuration interface of the FPGA chip board card, and the configuration interface can be a UART, an Ethernet port, etc. The upper computer can be connected with each corresponding parameter adjustment module of the FPGA chip through the configuration interface to realize data communication and instruction issuing.

[0062] In the embodiments of the present application, the control module sends configuration parameters to the corresponding first parameter adjustment module and second parameter adjustment module through the configuration interface, respectively, receives corresponding error code statistical results, and optimizes the GT configuration parameters based on the error code statistical results.

[0063] In combination with the examples shown in Figure 2 , 3 The first parameter adjustment module includes a first register, a first parameter configuration module and a first error code statistical module, and the first register is in communication connection with the control module via a first configuration interface.

[0064] The first parameter configuration module and the first error code statistical module are both connected with the first register.

[0065] The first parameter configuration module is connected with the sending end of the first GT, and is configured to send configuration information to the sending end of the first GT to adjust the sending performance of the first GT.

[0066] The first error code statistical module is connected with the receiving end of the first GT, and is configured to read the error code mark signal output by the first GT, count the number of error codes, send the error code statistical result in a predetermined time period to the first register, and transmit the error code statistical result to the control module through the first configuration interface by the first register.

[0067] In combination with the examples shown in Figure 2 , 3 ​In the shown example, the second parameter adjustment module comprises a second register, a second parameter configuration module and a second error code statistics module, and the second register is in communication connection with the control module via a second configuration interface.

[0068] The second parameter configuration module and the second error code statistics module are both connected with the second register.

[0069] The second parameter configuration module is connected with the sending end of the second GT, and is used to send configuration information to the sending end of the second GT to adjust the sending performance of the second GT.

[0070] The second error code statistics module is connected with the receiving end of the second GT, and is used to read the error code mark signal output by the second GT and to count the error code number, and to send the error code statistics result in a predetermined time period to the second register, and to transmit the error code statistics result to the control module by the second register via the second configuration interface.

[0071] In the embodiment of the application, the control module is arranged to optimize the configuration parameters of the first GT in the following manner:

[0072] The control module sends the configuration parameters, including the initial values of the communication mode and the pre-emphasis parameter, to the first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface;

[0073] After receiving the initial configuration parameters, the first register modifies the sending parameters of the sending end of the first GT by the first parameter configuration module;

[0074] The control module sends the error code statistics instruction to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface, and the second register clears the counter in the second error code statistics module after receiving the instruction and starts timing, the second error code statistics module receives the error code mark signal from the receiving end of the second GT and counts the error code number, and stops counting when the counting time reaches the predetermined time period and sends the error code statistics result to the second register, and the second register sends the statistics value to the control module via the second configuration interface;

[0075] The control module records the error code number statistics value sent by the second register of the second parameter adjustment module, adjusts the configuration parameters according to the preset optimal value algorithm, and then sends the updated configuration parameters to the first register of the first parameter adjustment module again to perform sending parameter configuration adjustment and optimization, and the above operation is repeated until the optimal parameter value of the sending end of the first GT is obtained according to the preset optimal value algorithm.

[0076] In the embodiment of the application, the control module is arranged to optimize the configuration parameters of the second GT in the following manner:

[0077] The control module sends configuration parameters, including communication mode and initial value of pre-emphasis parameter, to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface;

[0078] After receiving the initial configuration parameters, the second register modifies the transmission parameters of the transmission end of the second GT through the second parameter configuration module;

[0079] The control module sends an error code statistical instruction to the first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface, and the first register clears the counter in the first error code statistical module and starts timing after receiving the instruction. The first error code statistical module receives the error code marking signal from the receiving end of the first GT and performs error code number statistics, stops counting when the statistical time reaches the predetermined time period, and sends the error code statistical result to the first register. The first register sends the statistical value to the control module through the first configuration interface;

[0080] The control module records the error code number statistical value sent by the first register of the first parameter adjustment module, adjusts the configuration parameters according to the preset optimal value algorithm, and then sends the updated configuration parameters to the second register of the second parameter adjustment module again to perform transmission parameter configuration adjustment and optimization. The above operation is repeated until the optimal parameter value of the transmission end of the second GT is obtained according to the preset optimal value algorithm.

[0081] It should be understood that the aforementioned host computer can be configured to be implemented by a computer system, for example, a computer system installed with a Vivado design suite configured with an ibert tool, which can find the optimal parameters according to the received error code rate, and then send the parameters to the parameter adjustment module of the FPGA chip. Through cyclic optimization, the optimal parameter value of the GT transmission end is ultimately obtained.

[0082] In the embodiments of the present application, the optimal adjustment method is combined with the GT transmission parameter configuration method shown in the prior art. Figure 1 、 3 It can be seen that the plurality of GTs in the FPGA chip can be synchronized and optimized according to the optimal adjustment method of the present application.

[0083] In the optional embodiments, when the first FPGA chip and the second FPGA chip are in full-duplex communication, the optimal adjustment of the configuration parameters is performed synchronously for the GTs on both sides, and the individual and accurate configuration of the parameters of each GT port is efficiently realized.

[0084] Optimized adjustment method of FPGA high-speed transceiver parameters

[0085] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 、 2The implementation of the optimization adjustment system of the FPGA high-speed transceiver parameters of the embodiments 1, 2, 3 and above, according to the embodiments of the present application, further proposes an optimization adjustment method of the FPGA high-speed transceiver parameters of the FC node device, which comprises the following steps:

[0086] The sending end and the receiving end configured by the first GT of the first FPGA chip and the second GT of the second FPGA chip are connected to each other, that is, the sending end of the first GT is connected to the receiving end of the second GT, and the sending end of the second GT is connected to the receiving end of the first GT;

[0087] The first parameter adjustment module and the second parameter adjustment module are respectively connected to the control module through independent first and second configuration interfaces;

[0088] The control module sends configuration parameters to the corresponding first and second parameter adjustment modules through the first and second configuration interfaces respectively and receives the corresponding error code statistical results, and optimizes the configuration parameters of the first and second GTs based on the error code statistical results.

[0089] The optimization adjustment process of the configuration parameters of the first GT comprises:

[0090] The control module sends configuration parameters including the initial values of the communication mode and the pre-emphasis parameters to the first register of the first parameter adjustment module in the first FPGA chip through the first configuration interface;

[0091] After receiving the initial configuration parameters, the first register modifies the sending parameters of the sending end of the first GT through the first parameter configuration module;

[0092] The control module sends an error code statistical instruction to the second register of the second parameter adjustment module in the second FPGA chip through the second configuration interface, the second register clears the counter in the second error code statistical module after receiving the instruction and starts timing, the second error code statistical module receives the error code marking signal from the receiving end of the second GT and performs error code number statistics, stops counting when the statistical time reaches the predetermined time period, and sends the error code statistical result to the second register, and the second register sends the statistical value to the control module through the second configuration interface;

[0093] The control module records the error code number statistical value sent by the second register of the second parameter adjustment module, adjusts the configuration parameters according to the preset optimal value algorithm, and then sends the updated configuration parameters to the first register of the first parameter adjustment module again to perform sending parameter configuration adjustment and optimization, and the above operation is repeated until the optimal parameter value of the sending end of the first GT is obtained according to the preset optimal value algorithm.

[0094] The optimal adjustment process of the configuration parameters of the second GT comprises:

[0095] The control module sends configuration parameters, including initial values of the communication mode and the pre-emphasis parameter, to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface;

[0096] After receiving the initial configuration parameters, the second register modifies the transmission parameters of the transmission end of the second GT through the second parameter configuration module;

[0097] The control module sends an error code statistical instruction to the first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface, and the first register clears the counter in the first error code statistical module after receiving the instruction and starts timing. The first error code statistical module receives the error code marking signal from the receiving end of the first GT and performs error code number statistics. When the statistical time reaches the predetermined time period, the counting is stopped, and the error code statistical result is sent to the first register. The first register sends the statistical value to the control module through the first configuration interface;

[0098] The control module records the error code number statistical value sent by the first register of the first parameter adjustment module. After adjusting the configuration parameters according to the preset optimal value algorithm, the updated configuration parameters are sent to the second register of the second parameter adjustment module again to perform transmission parameter configuration adjustment and optimization. The above operation is repeated until the optimal parameter value of the transmission end of the second GT is obtained according to the preset optimal value algorithm.

[0099] The implementation of the above optimal adjustment process will be described below with reference to the accompanying drawings. Figure 3

[0100] In the actual test process, the real use scene of the device is simulated, and the GT parameter adjustment is performed in the way that two power-saving device FPGAs are connected. Taking the connection of one GT port in the device as an example, the test environment is built as shown in Figure 3

[0101] The GT parameter optimal adjustment process according to the embodiment of the application comprises the implementation of the following steps 1-5:

[0102] 1. The GT ports to be tested of two node devices are connected to each other. The transmission end (TX#1) of the GT on the FPGA#1 side is connected to the receiving end (RX#2) of the GT on the FPGA#2 side, and the transmission end (TX#2) of the GT on the FPGA#2 side is connected to the receiving end (RX#1) of the GT on the FPGA#1 side;

[0103] ​​2. The control module sends configuration parameters to register #1 in the parameter adjustment module #1 of FPGA #1 through configuration interface #1. The first transmission is the initial communication mode and the initial values ​​of pre-emphasis parameters TXDIFFCTRL, TXPRECURSOR, and TXPOSTCURSOR. After receiving the configuration parameters, register #1 transmits them to the parameter configuration module #1 of parameter adjustment module #1. The parameter configuration module #1 modifies the transmission parameters of the transmitting end TX #1.

[0104] 3. The control module sends an error rate statistics command to register #2 in the parameter adjustment module #2 of FPGA #2 through configuration interface #2. Register #2 clears the counter in the error rate statistics module #2 and starts timing. The error rate statistics module #2 receives the error mark signal from RX #2 and counts the number of errors within the timing period (i.e., within the predetermined time period). When the predetermined time period is reached, the counting stops and the error rate statistics are sent to register #2. Register #2 sends the statistical value to the control module through configuration interface #2.

[0105] 4. The control module records the error count statistics transmitted from FPGA#2, adjusts the configuration parameters according to the optimal value algorithm, and then sends the updated configuration parameters back to FPGA#1 for parameter adjustment.

[0106] 5. Repeat steps 2-4. Based on the preset optimal value algorithm of the Vivado design kit, the control module can obtain the optimal parameter value of the transmitter TX#1 of a certain GT in FPGA#1. Similarly, parameters are sent to the transmitter TX#2 of FPGA#2, and error statistics are performed on the receiver RX#1 of FPGA#1. Through the optimal value algorithm, the optimal parameter value of the transmitter TX#2 of a certain GT in FPGA#2 can be obtained.

[0107] This enables the optimal adjustment of the parameters of the ground plane (GT) of an interconnected FPGA.

[0108] Combination Figure 3 This example illustrates the parameter optimization process of a certain GT in an FPGA chip. Multiple GTs in the FPGA can be synchronously optimized according to this process, and synchronous optimization can be performed on both sides when two FPGAs are communicating in full-duplex mode. This allows for efficient and personalized configuration of the parameters of each GT port.

[0109] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A system for optimizing the parameters of a high-speed FPGA transceiver, characterized in that, include: At least one first FPGA chip is configured with a first GT and a first parameter adjustment module, and the first parameter adjustment module establishes a communication connection with the transceiver end of the first GT; At least one second FPGA chip is configured with a second GT and a second parameter adjustment module. The second GT is communicatively connected to the first GT, and the second parameter adjustment module establishes a communicative connection with the transceiver end of the second GT. The control module establishes communication connections with the first parameter adjustment module and the second parameter adjustment module respectively through independent configuration interfaces. The control module sends configuration parameters to the corresponding first parameter adjustment module and second parameter adjustment module through the configuration interface and receives the corresponding bit error statistics results, and performs optimal adjustment of GT configuration parameters based on the bit error statistics results. The control module is configured to optimize the configuration parameters of the first GT in the following manner: The control module sends configuration parameters, including the communication mode and the initial value of the pre-emphasis parameter, to the first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface. After receiving the initial configuration parameters, the first register modifies the transmission parameters of the first GT's transmitter through the first parameter configuration module; The control module sends a bit error statistics instruction to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface. After receiving the instruction, the second register clears the counter in the second bit error statistics module and starts timing. The second bit error statistics module receives the bit error mark signal from the receiver of the second GT and counts the number of bit errors. When the counting time reaches the predetermined time period, the counting stops and the bit error statistics result is sent to the second register. The second register sends the statistical value to the control module through the second configuration interface. The control module records the number of bit errors sent by the second register of the second parameter adjustment module. After adjusting the configuration parameters according to the preset optimal value algorithm, the updated configuration parameters are sent to the first register of the first parameter adjustment module again to adjust and optimize the transmission parameter configuration. The above operation is repeated until the optimal parameter value of the first GT's transmitting end is obtained according to the preset optimal value algorithm. The control module is configured to optimize the configuration parameters of the second GT in the following manner: The control module sends configuration parameters, including the communication mode and the initial value of the pre-emphasis parameter, to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface. After receiving the initial configuration parameters, the second register modifies the transmission parameters of the second GT's transmitter through the second parameter configuration module; The control module sends a bit error statistics instruction to the first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface. After receiving the instruction, the first register clears the counter in the first bit error statistics module and starts timing. The first bit error statistics module receives the bit error mark signal from the receiver of the first GT and counts the number of bit errors. When the counting time reaches the predetermined time period, the counting stops and the bit error statistics result is sent to the first register. The first register sends the statistical value to the control module through the first configuration interface. The control module records the number of bit errors sent by the first register of the first parameter adjustment module. After adjusting the configuration parameters according to the preset optimal value algorithm, the updated configuration parameters are sent to the second register of the second parameter adjustment module again to adjust and optimize the transmission parameter configuration. The above operation is repeated until the optimal parameter value of the second GT's transmitting end is obtained according to the preset optimal value algorithm.

2. The FPGA high-speed transceiver parameter optimization system according to claim 1, characterized in that, Both the first GT and the second GT are equipped with a transmitter and a receiver, and are interconnected: The transmitting end of the first GT is connected to the receiving end of the second GT; The transmitter of the second GT is connected to the receiver of the first GT.

3. The FPGA high-speed transceiver parameter optimization system according to claim 1, characterized in that, The first parameter adjustment module includes a first register, a first parameter configuration module, and a first error rate statistics module. The first register is connected to the control module via a first configuration interface. Both the first parameter configuration module and the first bit error statistics module are connected to the first register; The first parameter configuration module is connected to the transmitter of the first GT and is used to send configuration information to the transmitter of the first GT to adjust the transmission performance of the first GT. The first bit error statistics module is connected to the receiver of the first GT and is used to read the bit error marking signal output by the first GT, count the number of bit errors, send the bit error statistics results within a predetermined time period to the first register, and then transmit them to the control module through the first configuration interface.

4. The FPGA high-speed transceiver parameter optimization system according to claim 3, characterized in that, The second parameter adjustment module includes a second register, a second parameter configuration module, and a second error statistics module. The second register is connected to the control module via a second configuration interface. Both the second parameter configuration module and the second error statistics module are connected to the second register. The second parameter configuration module is connected to the transmitter of the second GT and is used to send configuration information to the transmitter of the second GT to adjust the transmission performance of the second GT. The second bit error statistics module is connected to the receiver of the second GT and is used to read the bit error marking signal output by the second GT, count the number of bit errors, send the bit error statistics results within a predetermined time period to the second register, and then transmit them to the control module through the second configuration interface.

5. The FPGA high-speed transceiver parameter optimization system according to claim 1, characterized in that, The first configuration interface and the second configuration interface are either UART or Ethernet, and are used to realize communication between the first parameter adjustment module, the second parameter adjustment module and the control module.

6. The FPGA high-speed transceiver parameter optimization system according to claim 1, characterized in that, When the first FPGA chip and the second FPGA chip communicate in full-duplex mode, the configuration parameters of the GT on both sides are optimized.

7. The FPGA high-speed transceiver parameter optimization system according to claim 1, characterized in that, In the configuration of the first FPGA chip and the second FPGA chip, each GT is configured with a parameter adjustment module.

8. A method for optimizing the parameters of an FPGA high-speed transceiver, applied to the FPGA high-speed transceiver parameter optimization system as described in claim 1, characterized in that, The method includes the following steps: The transmitting and receiving ends configured on the first GT of the first FPGA chip and the second GT of the second FPGA chip are interconnected, that is: the transmitting end of the first GT is connected to the receiving end of the second GT, and the transmitting end of the second GT is connected to the receiving end of the first GT. The first parameter adjustment module and the second parameter adjustment module establish communication connections with the control module through independent first configuration interfaces and second configuration interfaces, respectively. The control module sends configuration parameters to the corresponding first parameter adjustment module and second parameter adjustment module through the first configuration interface and the second configuration interface, respectively, and receives the corresponding bit error statistics results. Based on the bit error statistics results, it optimizes the configuration parameters of the first GT and the second GT.

9. The method for optimizing the parameters of a high-speed FPGA transceiver according to claim 8, characterized in that, The optimization process for the configuration parameters of the first GT includes: The control module sends configuration parameters, including the communication mode and the initial value of the pre-emphasis parameter, to the first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface. After receiving the initial configuration parameters, the first register modifies the transmission parameters of the first GT's transmitter through the first parameter configuration module; The control module sends a bit error statistics instruction to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface. After receiving the instruction, the second register clears the counter in the second bit error statistics module and starts timing. The second bit error statistics module receives the bit error mark signal from the receiver of the second GT and counts the number of bit errors. When the counting time reaches the predetermined time period, the counting stops and the bit error statistics result is sent to the second register. The second register sends the statistical value to the control module through the second configuration interface. The control module records the number of bit errors sent by the second register of the second parameter adjustment module. After adjusting the configuration parameters according to the preset optimal value algorithm, the updated configuration parameters are sent to the first register of the first parameter adjustment module again to adjust and optimize the transmission parameter configuration. The above operation is repeated until the optimal parameter value of the first GT's transmitting end is obtained according to the preset optimal value algorithm.

10. The method for optimizing the parameters of a high-speed FPGA transceiver according to claim 8, characterized in that, The optimization process for the configuration parameters of the second GT includes: The control module sends configuration parameters, including the communication mode and the initial value of the pre-emphasis parameter, to the second register of the second parameter adjustment module in the second FPGA chip via the second configuration interface. After receiving the initial configuration parameters, the second register modifies the transmission parameters of the second GT's transmitter through the second parameter configuration module; The control module sends a bit error statistics instruction to the first register of the first parameter adjustment module in the first FPGA chip via the first configuration interface. After receiving the instruction, the first register clears the counter in the first bit error statistics module and starts timing. The first bit error statistics module receives the bit error mark signal from the receiver of the first GT and counts the number of bit errors. When the counting time reaches the predetermined time period, the counting stops and the bit error statistics result is sent to the first register. The first register sends the statistical value to the control module through the first configuration interface. The control module records the number of bit errors sent by the first register of the first parameter adjustment module. After adjusting the configuration parameters according to the preset optimal value algorithm, the updated configuration parameters are sent to the second register of the second parameter adjustment module again to adjust and optimize the transmission parameter configuration. The above operation is repeated until the optimal parameter value of the second GT's transmitting end is obtained according to the preset optimal value algorithm.

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