A method for clock calibration in a wireless communication system based on reception time

Abstract

The application provides a clock calibration method based on receiving time for a wireless communication system, which comprises that a first device periodically sends a plurality of groups of signaling packets to a second device through a wireless channel, the first device is provided with a standard clock with zero clock bias, the second device receives the signaling packets and records the receiving time stamp of the signaling packets, when the number of groups of the current signaling packet received by the second device is different from the number of groups of the previous signaling packet, the second device performs error estimation, the error estimation is that the second device obtains clock error according to the data and the receiving time stamp of the current signaling packet and the data and the receiving time stamp of the previous signaling packet, and the second device calibrates the clock to be calibrated according to the clock error. The application adopts wireless communication technology, obtains clock error through the received signaling packet and the receiving time stamp, and then calibrates the clock to be calibrated according to the clock error, so that the effect of flexible and reliable clock calibration with high efficiency, low cost and wide application range is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of wireless communication technology, in particular to a clock calibration method for wireless communication system based on receiving time. BACKGROUND

[0002] In embedded wireless communication system, the clock tolerance of electromagnetic frequency (RF) of the system to the crystal oscillator source has a higher requirement. 1ppm refers to one millionth of the frequency error, and at 100MHz frequency, the frequency error of 1ppm is 100Hz. The frequency deviation of Bluetooth BLE system is ±150KHz, and the carrier frequency is 2.4GHz. Substituting the formula four can obtain the allowable frequency deviation of Bluetooth BLE system, which is ±62.5ppm.

[0003] Formula four:

[0004]

[0005] Wherein D ppm is the frequency deviation of the system, Δf is the frequency deviation of the system, and f is the carrier frequency of the system.

[0006] As Figure 1 shown, the general system selects an external 24M passive crystal oscillator as the system clock source, which leads to the fact that the 24M crystal itself has a certain deviation, usually about ±50ppm, and on the other hand, the passive crystal will involve the matching problem of the internal oscillation circuit of the chip and the crystal. The actual deviation may reach ±100-300ppm, so the final deviation of the whole system is ±150-350ppm, which exceeds the allowable frequency deviation of the system and does not meet the requirements of the clock tolerance of the electromagnetic frequency (RF) of the system to the crystal oscillator source.

[0007] Therefore, there is an urgent need for a clock calibration method with small calibration error and fast product clock error, which can adjust the matching capacitance in the chip after selecting the crystal in the production of the product, improve the matching relationship between the chip and the peripheral crystal, and ensure that the system frequency deviation is within the electromagnetic frequency (RF) interaction tolerance range. SUMMARY

[0008] The present application provides a clock calibration method for wireless communication system based on receiving time, which is mainly used to solve the problem of large clock error of the device in the wireless communication system, which does not meet the requirements of the clock tolerance of the electromagnetic frequency (RF) of the system to the crystal oscillator source, so as to achieve the effect of small calibration error and fast product clock error to calibrate the system clock of the device.

[0009] The present application realizes the above-mentioned purpose through the following technical scheme:

[0010] A clock calibration method for a wireless communication system based on receiving time, comprising:

[0011] S1: a first device periodically sends a plurality of groups of signaling packets to a second device through a wireless channel, the first device is provided with a standard clock with zero clock bias, and the second device is provided with a clock to be calibrated.

[0012] It can be seen that the calibration method uses wireless communication between the first device and the second device, multiple second device nodes can be deployed simultaneously, and one-to-many parallel clock calibration is performed, which greatly saves the clock calibration time of a single device and improves the clock calibration efficiency of the device.

[0013] S2: the second device receives the signaling packets and records the receiving time stamp of the signaling packets, the second device checks the signaling packets, and when the signaling packets pass the check, the second device saves the signaling packets and the receiving time stamp.

[0014] S3: the signaling packets include group number configuration, and the second device determines whether the group number configuration value of the current signaling packet is the same as the group number configuration value of the previous signaling packet.

[0015] S4: when the group number configuration value of the current signaling packet is the same as the group number configuration value of the previous signaling packet, the second device updates the receiving time stamp and continues to receive the next signaling packet, and repeats the above steps S2-S3; when the group number configuration value of the current signaling packet is different from the group number configuration value of the previous signaling packet, the second device estimates the error of the clock to be calibrated.

[0016] S5: the error estimation is that the second device obtains the clock error according to the data and receiving time stamp of the current signaling packet and the data and receiving time stamp of the previous signaling packet, and the second device calibrates the clock to be calibrated according to the clock error.

[0017] It can be seen that the clock error can be obtained by the second device receiving the signaling packets and the receiving time stamp, and the second device calibrates the clock to be calibrated according to the clock error, which ensures that the matching parameters of the chip and the selected crystal are consistent in the production link, so as to ensure that the system frequency deviation is within the electromagnetic frequency (RF) interaction tolerance range.

[0018] Further, the signaling packet further comprises a number configuration, the first device sends a preset maximum number of signaling packets in a period, when the number configuration is less than the preset maximum number, the first device sends one signaling packet in a period, the number configuration is increased by one, when the number configuration is equal to the preset maximum number, the number configuration is increased by one, and the number configuration is cleared.

[0019] Further, the signaling packet further comprises an ID configuration, the ID configuration is an ID value of the first device, the first device sets the ID configuration initially, and clears the number configuration.

[0020] Further, when the second device receives the signaling packet and the signaling packet is verified, the second device judges the ID configuration of the signaling packet, when the second device does not record the ID configuration of the current signaling packet, the second device saves the current signaling packet and a receiving time stamp, when the ID configuration of the current signaling packet is the same as the ID configuration of the previous signaling packet, the step S4 is executed.

[0021] Further, the interval time between the current signaling packet and the previous signaling packet is obtained by formula one.

[0022] The formula one is:

[0023]

[0024] Wherein, T' heart is the interval time between the current signaling packet and the previous signaling packet, TimeStamp n is the receiving time stamp of the current signaling packet, TimeStamp m is the receiving time stamp of the previous signaling packet, Grp n , Seq y are the number configuration value and the number configuration value of the current signaling packet, respectively, Grp m , Seq x are the number configuration value and the number configuration value of the previous signaling packet, respectively, T pkt is the time required for sending one signaling packet, and T IFS is the interval time between two adjacent signaling packets sent by the first device in a period.

[0025] It can be seen that the calibration method calculates the clock error by using the signaling packet and the receiving time stamp, does not need to reserve any test point, and does not need a special jig, which simplifies the process of clock calibration, and reduces the cost of clock calibration.

[0026] Further, the clock error is obtained by Formula II.

[0027] The Formula II is:

[0028] D ppm2 = T heart -T heart

[0029] Wherein, the D ppm2 is the clock error, the T heart is a packet sending period, and the packet sending period is an interval time between a sending start of a group of the signaling packets and a sending start of an adjacent group of the signaling packets.

[0030] Further, a time interval between two groups of the signaling packets sent by the first device adjacently is a packet interval, and a first signaling packet sent by the first device in a period is aligned with an edge of the packet interval.

[0031] Further, an edge error exists in the group of the signaling packets sent by the first device at the edge of the packet interval, and the edge error is obtained by Formula III.

[0032] The Formula III is:

[0033]

[0034] Wherein, the D ppm3 is the edge error value, the f s is a sampling frequency of a sampling clock of the second device.

[0035] Further, the edge error is an error introduced by the second device, and the edge error is controlled within an error allowable range of the second device by reducing the packet sending period.

[0036] It can be seen that the clock calibration method has a wide range of application, the calibration precision of the clock calibration method is high, and the clock calibration method can completely meet the clock calibration needs of the wireless communication system, and thus can be applied to any clock calibration scheme required by the wireless communication device.

[0037] In the embodiment, the preset maximum value is determined according to the size of the packet sending period.

[0038] It can be seen that the clock calibration method is flexible and reliable, the error introduced by the second device can be obtained by calculating the edge error, and thus the number of the signaling packets in a group and the packet sending period can be adjusted flexibly according to actual precision needs, so as to ensure the reliability of the scheme.

[0039] The application will be further described in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a prior art SOC crystal oscillator connection scheme diagram.

[0041] Figure 2 is a one-to-many parallel clock calibration system diagram for wireless communication of the present application.

[0042] Figure 3 is a signaling packet sending diagram of the first device of the present application.

[0043] Figure 4 is a signaling packet receiving diagram of the second device of the present application.

[0044] Figure 5 is an operation flowchart of the first device of the present application.

[0045] Figure 6 is an operation flowchart of the second device of the present application.

[0046] Figure 7 is a receiving processing flowchart of the second device of the present application.

[0047] Figure 8 is a signaling packet interaction diagram of the first device and the second device of the present application.

[0048] Figure 9 is a waveform diagram of the second device introducing edge error of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely below in combination with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0050] A clock calibration method for a wireless communication system based on receiving time

[0051] Referring to Figures 5-7 , the clock calibration method for a wireless communication system based on receiving time of the present application comprises:

[0052] S1: The first device Gold Board periodically sends a plurality of groups of signaling packets to the second device IUT through a wireless channel, the first device Gold Board is provided with a standard clock with a clock deviation of zero, and the second device IUT is provided with a clock to be calibrated.

[0053] Specifically, the first device Gold Board and the second device IUT are connected through a whip antenna or wireless connection.

[0054] The channel configuration of the first device Gold Board is an out-of-band frequency in a 1M baseband, i.e., a channel outside 2402MHz-2480MHz, and the channel configuration of the second device IUT is fixed as the transmission channel of the first device Gold Board.

[0055] The first device Gold Board and the second device IUT select one Channel as an interaction frequency band. In the case of multiple systems, the first device Gold Board and the second device IUT can select multiple Channels to meet different needs.

[0056] Specifically, the wireless communication system of the embodiment is deployed in a shielding environment to reduce external interference and improve the reliability of clock calibration.

[0057] Referring to Figure 2 , specifically, the first device Gold Board can simultaneously send multiple groups of signaling packets to multiple second devices IUT. The multiple second devices IUT are respectively device IUT x , device IUT y , device IUT z , etc. The first device Gold Board and the multiple second devices IUT are each provided with a baseband chip BB, a modem Modem, and a radio frequency (RF) device. The modem Modem is connected to the baseband chip BB and is used to realize the modulation and demodulation functions required for communication between the first device Gold Board and the multiple second devices IUT. The radio frequency (RF) device is used to send or receive the signaling packets.

[0058] It can be seen that the calibration method uses wireless communication between the first device Gold Board and the second device IUT, multiple second device IUT nodes can be deployed simultaneously, and one-to-many parallel clock calibration is performed, which greatly saves the clock calibration time of a single second device IUT and improves the clock calibration efficiency of the second device IUT.

[0059] S2: The second device IUT receives the signaling packet and records the receiving time stamp TimeStamp of the signaling packet. The second device IUT checks the signaling packet, and when the signaling packet passes the check, the second device IUT saves the signaling packet and the receiving time stamp TimeStamp.

[0060] Specifically, in step S21, the second device IUT continuously opens a receiving window to receive the signaling packet.

[0061] Specifically, in step S22 of this embodiment, when the signaling packet verification passes, the second device IUT considers the signaling packet to be a correct signaling packet and allows the second device IUT to execute step S23 on the signaling packet. When the signaling packet verification fails, the second device IUT terminates the processing of the signaling packet.

[0062] S3: The signaling packet includes the group number configuration Grp. The second device IUT compares the group number configuration Grp value of the current signaling packet with the group number configuration Grp value of the previous signaling packet. last Are the values ​​the same?

[0063] S4: The group number configuration Grp value of the current signaling packet is the same as the group number configuration Grp value of the previously stated signaling packet. last If the values ​​are the same, the second device IUT updates the received timestamp (TimeStamp) and continues to receive the next signaling packet, repeating steps S2-S3 above; the group number configuration Grp value of the current signaling packet is the same as the group number configuration Grp value of the previous signaling packet. last When the values ​​are different, the second device (IUT) estimates the error of the clock to be calibrated.

[0064] S5: The error estimation is obtained by the second device IUT based on the data of the current signaling packet and the received timestamp TimeStamp0, the data of the previous signaling packet and the received timestamp TimeStamp1, to obtain the clock error D. ppm2 The second device IUT is based on the clock error D ppm2 The clock to be calibrated is calibrated.

[0065] As can be seen, this calibration method can obtain the clock error D from the signaling packets received by the second device IUT and the received timestamp (TimeStamp). ppm2 The second device IUT is based on the clock error D ppm2 For clock calibration, ensure that the matching parameters of the chip SOC and the selected crystal are consistent during the production process, so as to ensure that the system frequency deviation of the second device IUT is within the electromagnetic frequency (RF) interaction tolerance range.

[0066] See Figures 3-4 In this embodiment, the signaling packet also includes a count configuration Seq, and the number of signaling packets sent by the first device, Gold Board, in one cycle is a preset maximum value. In step S13, when the value of the count configuration Seq is less than the preset maximum value, the value of the count configuration Seq is incremented by one for each signaling packet sent by the first device, Gold Board, in one cycle. In steps S15 and S12, when the value of the count configuration Seq is equal to the preset maximum value, the value of the group configuration Grp is incremented by one, and the value of the count configuration Seq is cleared to zero.

[0067] In the embodiment, the signaling package further comprises an ID configuration, which is an ID value of the first device Gold Board. In step S11, the first device Gold Board sets the ID configuration initially and clears the group number configuration Grp.

[0068] In the embodiment, in step S11-1, after the signaling package received by the second device IUT is verified, in steps S232-S233, the second device IUT judges the ID configuration of the signaling package. When the second device IUT does not record the ID configuration of the current signaling package, the second device IUT saves the current signaling package and the receiving time stamp TimeStamp. When the ID configuration of the current signaling package is the same as that of the previous signaling package, the above step S4 is performed.

[0069] Specifically, in step S231, the second device IUT needs to extract the ID configuration of the previous signaling package.

[0070] Specifically, the signaling package of the embodiment further comprises an AccessCode configuration and a verification configuration CRC. The AccessCode configuration is fixedly broadcast as 0x8E89BED6 as its Access Code. The receiving threshold of the AccessCode configuration is 4 bits. At this time, the fault tolerance of the second device IUT to the signaling package is 4 bits, that is, the second device IUT still recognizes the signaling package with an error within 4 bits as a correct signaling package.

[0071] Among them, the second device IUT has a frequency offset when it works, so there will be some errors when the second device IUT receives the signaling package. In steps S221-S222, after the communication system sync of the second device IUT confirms the gain gain of the received signaling package, the header+payload+crc in step S223 is used to ensure the correctness of the signaling package.

[0072] Among them, the fault tolerance of the second device IUT to the signaling package is to adapt to the shielding environment and the open environment, the wired connection and the wireless connection and other factory actual production conditions, so as to improve the anti-interference ability of clock calibration.

[0073] Among them, in steps S223-S224, the verification configuration CRC adopts the 24-bit CRC rule of BLE, and the initial value is 0x555555 and the polynomial is x24+x10+x9+x6+x4+x3+x+1.

[0074] In the embodiment, the interval time T between the current signaling package and the previous signaling package is heart The formula one is obtained from formula one.

[0075] The formula one is:

[0076]

[0077] wherein, T' heart is the interval time between the current signaling packet and the previous signaling packet, TimeStamp n is the receiving time stamp of the current signaling packet, TimeStamp m is the receiving time stamp of the previous signaling packet, Grp n , Seq y are the group number configuration value and the number configuration value of the current signaling packet, respectively, Grp m , Seq x are the group number configuration value and the number configuration value of the previous signaling packet, respectively, T pkt is the time required for sending one signaling packet, T IFS is the interval time between the sending of two adjacent signaling packets in one period by the first device Gold Board.

[0078] In the embodiment, the clock error D ppm2 is obtained by Formula Two.

[0079] The Formula Two is:

[0080] D ppm2 = T heart - T heart

[0081] wherein, the D ppm2 is the clock error, the T heart is the packet sending period, and the packet sending period is the interval time between the sending start of one group of signaling packets and the sending start of the adjacent group of signaling packets.

[0082] It can be seen that the calibration method calculates the clock error D ppm2 using the signaling packet and its receiving time stamp, without reserving any test point or using special fixture, thus simplifying the clock calibration process and reducing the cost of clock calibration.

[0083] Referring to Figure 8 , specifically, the second device IUT first receives a signaling packet with the group number configuration Grp=0 and the number configuration Seq1=1, and the receiving time stamp of the signaling packet is TimeStamp0; and then receives a signaling packet with the group number configuration Grp=1 and the number configuration Seq1=0, and the receiving time stamp of the signaling packet is TimeStamp1, T pkt = 88 μs, T IFS = 150 μs, and Formula Four is obtained by substituting Formula One.

[0084] Formula Four:

[0085] T' heart = (TimeStamp1) - (TimeStamp0 - (150 + 88))

[0086] Assuming TimeStamp0 = 288.000 μs, TimeStamp1 = 10055.000 μs, T heart = 10000 μs, substituting the values into Formula Four, T' heart = 10005.000 μs.

[0087] Substituting T heart = 10000 μs, T' heart = 10005.000 μs into Formula Two, the clock error of the second device IUT is: D ppm2 = 500 ppm.

[0088] It can be seen that the to-be-calibrated clock of the second device IUT is slower than the standard clock of the first device Gold Board, and the matching capacitance of the second device IUT needs to be adjusted to make the to-be-calibrated clock of the second device IUT faster.

[0089] In the embodiment, the time interval between two groups of signaling packets sent by the first device Gold Board adjacently is a packet sending interval, and in step S14, the first signaling packet sent by the first device Gold Board in a period is aligned with the edge of the packet sending interval.

[0090] Referring to Figure 9 , in the embodiment, there is an edge error of a group of signaling packets sent by the first device Gold Board at the edge of the packet sending interval, and the edge error is obtained by Formula Three.

[0091] The Formula Three is:

[0092]

[0093] wherein, D ppm3 is the edge error value, and f s is the sampling frequency of the sampling clock of the second device IUT.

[0094] In the embodiment, the edge error is the error introduced by the second device IUT, and the edge error is controlled within the error allowable range of the second device IUT by reducing the packet sending period.

[0095] Specifically, the embodiment assumes that T heart = 1 s, and the frequency of the sampling clock is f s = 24 MHz, and the edge error is:

[0096]

[0097] Specifically, the embodiment assumes that T heart = 10 ms, and the frequency of the sampling clock is f s = 24 MHz, then the edge error is:

[0098]

[0099] In actual engineering, clock calibration usually needs to be performed quickly, even if the packet sending period T heart is selected as 10 ms, an 8.333 ppm precision clock can still be calibrated.

[0100] It can be seen that the clock calibration method has a wide range of applications, and the clock calibration method of the application has high calibration precision, completely meeting the needs of clock calibration of a wireless communication system, and thus can be applied to any clock calibration scheme required by a wireless communication device.

[0101] In the embodiment, the preset maximum value is determined according to the size of the packet sending period.

[0102] Specifically, in the system of the embodiment, the packet sending period T heart has the greatest impact on performance, and the number of signaling packets in each group is the second, the former determines the precision and speed of the system, and the latter only improves the reliability of the second device IUT receiving signaling packets in an interference environment, and does not affect the final calibration result. As can be seen from equation three, theoretically, the larger the packet sending period T heart of the first device Gold Board, the smaller the error introduced by the second device IUT, and the more accurate the clock calibration.

[0103] In actual calibration systems, the rapidity of factory calibration needs to be considered, and the larger the packet sending period T heart , the slower the clock calibration speed, and the packet sending period T heart needs to be balanced for the precision of clock calibration, and the number of signaling packets in each group needs to be selected according to the need. The larger the packet sending period T heart , the more the number of signaling packets in each group, generally, the packet sending period T heart is 10 ms, and the number of signaling packets in each group is 10, the packet sending period T heart is 1 s, and the number of signaling packets in each group is 100, and so on.

[0104] It can be seen that the clock calibration method is flexible and reliable, and the error introduced by the second device can be obtained through the calculation of the edge error, and thus the number of signaling packets in each group and the packet sending period T heart can be flexibly adjusted according to the actual precision requirement, to ensure the reliability of the scheme.

[0105] The above embodiments are only the preferred embodiments of the present application, and cannot be used to limit the scope of protection of the present application. Any non-essential changes and substitutions made by those skilled in the art based on the present application shall fall within the scope of protection of the present application.

Claims

1. A method for clock calibration in a wireless communication system based on receive time stamp, the method comprising: The method comprises the following steps: S1: a first device periodically transmits a plurality of groups of signaling packets to a second device through a wireless channel, the first device is provided with a standard clock with a clock bias of zero, and the second device is provided with a clock to be calibrated; S2: the second device receives the signaling packets and records the receiving time stamp of the signaling packets, the second device checks the signaling packets, and when the signaling packets pass the check, the second device saves the signaling packets and the receiving time stamp; S3: the signaling packets comprise a group number configuration, and the second device determines whether the group number configuration value of the current signaling packet is the same as that of the previous signaling packet; S4: when the group number configuration value of the current signaling packet is the same as that of the previous signaling packet, the second device updates the receiving time stamp and continues to receive the next signaling packet, and repeats the steps S2-S3; when the group number configuration value of the current signaling packet is different from that of the previous signaling packet, the second device estimates the error of the clock to be calibrated; S5: the error estimation is that the second device obtains the clock error according to the data and the receiving time stamp of the current signaling packet and the data and the receiving time stamp of the previous signaling packet, and the second device calibrates the clock to be calibrated according to the clock error; wherein the data of the current signaling packet comprises the group number configuration value and the number configuration value, and the data of the previous signaling packet comprises the group number configuration value and the number configuration value.

2. The wireless communication system clock calibration method according to claim 1, wherein: the signaling packet further comprises a number configuration, the number of signaling packets transmitted by the first device in one period is a preset maximum value, when the number configuration value is less than the preset maximum value, the first device transmits one signaling packet in one period, and the number configuration value is incremented by one, when the number configuration value is equal to the preset maximum value, the group number configuration value is incremented by one, and the number configuration value is cleared.

3. The wireless communication system clock calibration method according to claim 2, wherein: the signaling packet further comprises an ID configuration, the ID configuration is an ID value of the first device, the first device sets the ID configuration initially and clears the group number configuration.

4. The wireless communication system clock calibration method according to claim 3, wherein: after the second device receives the signaling packet and the signaling packet passes the check, the second device judges the ID configuration of the signaling packet, when the second device does not record the ID configuration of the current signaling packet, the second device saves the current signaling packet and the receiving time stamp of the current signaling packet, and when the ID configuration of the current signaling packet is the same as that of the previous signaling packet, the step S4 is performed.

5. The wireless communication system clock calibration method according to claim 2, wherein: the interval time between the current signaling packet and the previous signaling packet is obtained by formula one; the formula one is: ​ ​ ​ ​ wherein, is the interval time between the current said signaling packet and the previous said signaling packet, is the receiving time stamp of the current said signaling packet, is the receiving time stamp of the previous said signaling packet, , are respectively the group number configuration value and the number configuration value of the current said signaling packet, , are respectively the group number configuration value and the number configuration value of the previous said signaling packet, is the time required for transmitting one said signaling packet, is the interval time between the transmission of two adjacent said signaling packets in one cycle by the first device.

6. The wireless communication system clock calibration method of claim 5, wherein: the clock error is obtained by Equation Two; Equation Two is: The signaling packet comprises a clock error and a packet sending period. The clock error is a time difference between a sending time of a signaling packet and a sending time of a next signaling packet. The packet sending period is a time interval between a sending start of a group of signaling packets and a sending start of a next group of signaling packets.

7. The wireless communication system clock calibration method of claim 6, wherein: a time interval between two groups of signaling packets sent by the first device adjacently is a packet sending interval, and a first signaling packet sent by the first device in a period is aligned with an edge of the packet sending interval.

8. The wireless communication system clock calibration method of claim 7, wherein: an edge error exists in an edge of a group of signaling packets sent by the first device, and the edge error is obtained by Equation Three; Equation Three is: wherein, is the edge error value, is a sampling frequency of a sampling clock of the second device.

9. The wireless communication system clock calibration method of claim 8, wherein: the edge error is an error introduced by the second device, and the edge error is controlled within an error allowable range of the second device by reducing the packet sending period.

10. The wireless communication system clock calibration method of claim 6, wherein: the preset maximum value is determined according to a size of the packet sending period.

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