Pixel circuit

Abstract

The present application provides a pixel circuit. The pixel circuit includes a driving circuit, a data writing circuit, a first voltage adjuster and a second voltage adjuster. The driving circuit generates a conduction current according to a voltage level of a driving terminal. The data writing circuit provides a data voltage to an input terminal according to a source driving signal. The first voltage adjuster adjusts voltage levels of the input terminal and a first control terminal according to the source driving signal and a first reference voltage. The second voltage adjuster adjusts voltage levels of a second control terminal and the driving terminal according to the first reference voltage, a light emitting control signal, the source driving signal and the voltage level of the first control terminal.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device, and in particular to a pixel circuit. BACKGROUND

[0002] In the prior art, the display panel is susceptible to the threshold voltage variation of the transistors in the pixel circuit and / or the switching action of the ramp voltage (or ramp signal), resulting in difficulty in controlling the gray scale level of the display image.

[0003] In addition, when the drive transistor is in a large current state and the light emitting element is turned on for a long time, the power consumption of the pixel circuit as a whole will be too high. Furthermore, the drive circuit in the pixel circuit is susceptible to the line resistance of the transmission path, resulting in different end point voltages for each pixel, and thus errors in the on current flowing through the light emitting element in each pixel.

[0004] Therefore, how to improve the gray scale control capability of the pixel circuit and effectively reduce the power consumption of the pixel circuit to improve the display quality of the display image is an important issue for those skilled in the art. SUMMARY

[0005] The present application provides a pixel circuit capable of improving the accuracy of gray scale control of the pixel circuit using pulse-width modulation (PWM) control and effectively reducing the power consumption of the pixel circuit.

[0006] The pixel circuit of the present application comprises a drive circuit, a data writing circuit, a first voltage regulator and a second voltage regulator. The drive circuit has a drive end for generating an on current according to the voltage level of the drive end. The data writing circuit has an input end for providing a data voltage to the input end according to a source driving signal. The first voltage regulator has a first control end, and is coupled to the data writing circuit for adjusting the voltage levels of the input end and the first control end according to the source driving signal and a first reference voltage. The second voltage regulator has a second control end, and is coupled to the drive circuit and the first voltage regulator for adjusting the voltage levels of the second control end and the drive end according to the first reference voltage, a light emitting control signal, the source driving signal and the voltage level of the first control end.

[0007] Based on the above, the pixel circuit according to the embodiments of the present application can improve the switching efficiency and the accuracy of gray scale control of the circuit and effectively reduce the power consumption of the pixel circuit as a whole by the circuit architecture of the voltage regulator and the compensation for the threshold voltage variation of the related transistors. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a timing chart of a pixel circuit according to an embodiment of the present application.

[0009] Figure 2 is a timing chart of a pixel circuit according to an embodiment of the present application. Figure 1

[0010] Figures 3A to 3F is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present application. Figure 1

[0011] SYMBOL EXPLANATION

[0012] 100: pixel circuit

[0013] 110: drive circuit

[0014] 120: data write circuit

[0015] 130, 140: voltage adjuster

[0016] C1-C3: capacitor

[0017] CT1, CT2: control terminal

[0018] CP: compensation phase

[0019] DIP: data write phase

[0020] EM: emission control signal

[0021] EP: emission phase

[0022] EP1, EP2: sub-phase

[0023] ID: on current

[0024] LED: light emitting element

[0025] P1: node

[0026] PD: drive terminal

[0027] PIN: input terminal

[0028] RP: reset phase

[0029] S1: source drive signal

[0030] T1-T12: transistor

[0031] TD: drive transistor

[0032] TFR: pixel period

[0033] TP: turn-off phase​​

[0034] VDD: system high voltage

[0035] VSS: system low voltage

[0036] VDATA: data voltage

[0037] VSWEEP: sweep voltage

[0038] VREF1, VREF2: reference voltage

[0039] VH: high voltage

[0040] VL: low voltage DETAILED DESCRIPTION

[0041] The term "coupled" (or connected) used in the disclosure throughout the specification including claims can mean either a direct or indirect connection. For example, if a first device is described as being coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or that the first device can be indirectly connected to the second device through other devices or some connection means. In addition, wherever possible, like elements / constructions / steps are denoted by like reference numerals throughout the drawings and the embodiments. Elements / constructions / steps denoted by like reference numerals or using like terms in different embodiments can be cross-referenced with the relevant descriptions.

[0042] Figure 1 is a schematic diagram of a pixel circuit according to an embodiment of the present application. Please refer to Figure 1 In the present embodiment, the pixel circuit 100 includes a driving circuit 110, a data writing circuit 120, a voltage adjuster 130, and a voltage adjuster 140. The driving circuit 110 includes a driving transistor TD and a light emitting element LED. The first end of the driving transistor TD is coupled to a system high voltage VDD, and the control end of the driving transistor TD is coupled to a driving end PD. The anode end of the light emitting element LED is coupled to the second end of the driving transistor TD, and the cathode end of the light emitting element LED is coupled to a system low voltage VSS.

[0043] Specifically, the driving transistor TD of the driving circuit 110 of the present embodiment can generate a conduction current ID according to the voltage level of the driving end PD, and the driving circuit 110 can correspondingly light up the light emitting element LED according to the conduction current ID. The light emitting element LED of the present embodiment can be, for example, an organic light emitting diode (OLED), a mini LED, or other micro light emitting element, and the present application is not particularly limited.

[0044] The data write circuit 120 of the embodiment can provide a data voltage VDATA to the input terminal PIN according to the source driving signal S1. The data write circuit 120 includes transistors T1-T2 and a capacitor C1. The first terminal of the transistor T1 is coupled to the data voltage VDATA, and the second terminal and the control terminal of the transistor T1 are coupled to each other. The transistor T1 can form a diode according to a diode connection. The first terminal of the transistor T2 is coupled to the second terminal and the control terminal of the transistor T1, the second terminal of the transistor T2 is coupled to the input terminal PIN, and the control terminal of the transistor T2 receives the source driving signal S1. The first terminal of the capacitor C1 is coupled to the ramp voltage VSWEEP, and the second terminal of the capacitor C1 is coupled to the input terminal.

[0045] In another aspect, the voltage adjuster 130 is coupled to the data write circuit 120. The voltage adjuster 130 includes transistors T3-T6 and a capacitor C2. The first terminal of the transistor T3 is coupled to the reference voltage VREF2, the second terminal of the transistor T3 is coupled to the control terminal CT1, and the control terminal of the transistor T3 is coupled to the input terminal PIN. The first terminal of the transistor T4 is coupled to the input terminal PIN, the second terminal of the transistor T4 is coupled to the node P1, and the control terminal of the transistor T4 receives the source driving signal S1. The first terminal of the transistor T5 is coupled to the control terminal CT1, the second terminal of the transistor T5 is coupled to the node P1, and the control terminal of the transistor T5 receives the source driving signal S1. The first terminal of the transistor T6 is coupled to the low voltage VL, the second terminal of the transistor T6 is coupled to the node P1, and the control terminal of the transistor T6 is coupled to the control terminal CT1. The first terminal of the capacitor C2 is coupled to the control terminal CT1, and the second terminal of the capacitor C2 is coupled to the low voltage VL.

[0046] In particular, the voltage adjuster 130 of the embodiment can adjust the voltage levels of the input terminal PIN, the node P1, and the control terminal CT1 according to the state of the source driving signal S1 and through the ramp voltage VSWEEP, the low voltage VL, and the reference voltage VREF2.

[0047] The voltage regulator 140 is coupled to the driving circuit 110 and the voltage regulator 130. In the embodiment, the voltage regulator 140 includes transistors T7-T12. The first end of the transistor T7 is coupled to the low voltage VL, and the control end of the transistor T7 is coupled to the reference voltage VREF2. The first end of the transistor T8 is coupled to the second end of the transistor T7, and the control end of the transistor T8 receives the light emitting control signal EM. The first end of the transistor T9 is coupled to the second end of the transistor T8, the second end of the transistor T9 is coupled to the control end CT2, and the control end of the transistor T9 receives the source driving signal S1. The first end of the transistor T10 is coupled to the high voltage VH, the second end of the transistor T10 is coupled to the control end CT2, and the control end of the transistor T10 receives the source driving signal S1. The first end of the transistor T11 is coupled to the reference voltage VREF1, the second end of the transistor T11 is coupled to the driving end PD, and the control end of the transistor T11 receives the light emitting control signal EM. The first end of the transistor T12 is coupled to the system high voltage VDD, the second end of the transistor T12 is coupled to the control end CT2, and the control end of the transistor T12 is coupled to the control end CT1. The capacitor C3 is coupled between the control end CT2 and the driving end PD.

[0048] In particular, the voltage regulator 140 of the embodiment can adjust the voltage levels of the control end CT2 and the driving end PD according to the reference voltage VREF2, the light emitting control signal EM, the source driving signal S1, and the voltage level of the control end of the transistor T12 (i.e., the control end CT1).

[0049] It is particularly mentioned that, in the embodiment, the transistor T6 and the transistor T12 are matched with each other, the transistor T1 and the transistor T3 are matched with each other, and the driving transistor TD and the transistor T7 are matched with each other. The above-mentioned matching can mean that the sizes of the transistors are the same and / or the threshold voltages of the transistors are the same.

[0050] In addition, in the design of the driving transistor TD and the transistors T1-T12, the transistor T2, the transistor T5, the transistor T6, the transistor T10, and the transistor T12 of the embodiment can be taken as N-type transistors, and the transistor T1, the transistor T3, the transistor T4, the transistor T7, the transistor T8, the transistor T9, the transistor T11, and the driving transistor TD can be taken as P-type transistors, but the embodiment of the present application is not limited thereto.

[0051] It is noted that, in the present embodiment, the relationship between the voltage levels (or voltage values) of the respective voltages can be in the order of data voltage VDATA, high voltage VHand reference voltage VREF2, reference voltage VREF1, low voltage VL, system high voltage VDD, and system low voltage VSS, from high to low (or from large to small).

[0052] Figure 2 is in accordance with the present invention Figure 1 a timing diagram of the pixel circuit of the present embodiment. Please refer to Figure 2 In the present embodiment, one pixel period TFR of the pixel circuit 100 can be divided into a reset phase RP, a data write phase DIP, a compensation phase CP, an emission phase EP, and a turn-off phase TP. The pixel circuit 100 can be operated in the reset phase RP, the data write phase DIP, the compensation phase CP, the emission phase EP, and the turn-off phase TP in this order. The reset phase RP, the data write phase DIP, the compensation phase CP, the emission phase EP, and the turn-off phase TP do not overlap with each other. The emission phase EP can include sub-phases EP1-EP2.

[0053] For the detailed implementation of the pixel circuit 100, please refer to Figure 2 and Figures 3A to 3F , Figures 3A to 3F is in accordance with the present invention Figure 1 an equivalent circuit diagram of the pixel circuit of the present embodiment. It is noted that, for the sake of convenience, the transistors that are turned off are shown in cross-hatching, while the transistors that are turned on are shown in un-cross-hatching. Figures 3A to 3F For the detailed implementation of the pixel circuit 100, please refer to

[0054] and Figure 2 In the present embodiment, Figure 3A is an equivalent circuit diagram of the pixel circuit 100 when operated in the reset phase RP. Specifically, in the reset phase RP, the source driving signal S1 and the emission control signal EM can be set to a low voltage level, while the ramp voltage VSWEEP can be set to a high voltage level. Figure 3A In detail, in the reset phase RP, the voltage adjuster 130 can provide the low voltage VL to the node P1 and the input terminal PIN through the turned-on paths of the transistors T4 and T6 in accordance with the source driving signal S1 being pulled low, so as to correspondingly pull down the voltage levels of the node P1 and the input terminal PIN to a voltage value equal to the low voltage VL.

[0055]

[0056] ​Next, the transistor T3 of the voltage regulator 130 can be turned on according to the voltage level of the input terminal PIN (i.e., the low voltage VL), so that the voltage regulator 130 can provide the reference voltage VREF2 to the control terminal CT1 through the on-path of the transistor T3 to perform a charging action on the control terminal CT1, and the voltage level of the control terminal CT1 is correspondingly pulled up to a voltage value equal to the reference voltage VREF2. In this way, the transistor T6 can be in the on-state according to the voltage level of the control terminal CT1 (i.e., the reference voltage VREF2).

[0057] In another aspect, the transistor T12 of the voltage regulator 140 can be turned on according to the voltage level of the control terminal CT1, so that the voltage regulator 140 can provide the system high voltage VDD to the control terminal CT2 through the on-path of the transistor T12, and the voltage level of the control terminal CT2 is correspondingly pulled up to a voltage value equal to the system high voltage VDD.

[0058] Next, the voltage regulator 140 can provide the reference voltage VREF1 to the driving terminal PD according to the pulled-down light-emitting control signal EM, so that the voltage level of the driving terminal PD is correspondingly pulled up to a voltage value equal to the reference voltage VREF1. At this time, the driving circuit 110 can be turned off according to the voltage level of the driving terminal PD.

[0059] After the reset actions of the nodes are completed, please refer to Figure 2 and Figure 3B In the present embodiment, Figure 3B is an equivalent circuit diagram of the pixel circuit 100 when operating in the data writing phase DIP. Specifically, in the data writing phase DIP, the source driving signal S1 and the ramp voltage VSWEEP can be set to a high voltage level, and the light-emitting control signal EM can be set to a low voltage level.

[0060] In detail, in the data writing phase DIP, the data writing circuit 120 can provide the data voltage VDATA to the input terminal PIN through the on-paths of the transistors T1 and T2 according to the pulled-up source driving signal S1, so that the voltage level of the input terminal PIN is pulled up to a voltage difference (i.e., VDATA - |VTH1|) between the voltage value of the data voltage VDATA and the voltage value of the threshold voltage VTH1 of the transistor T1.

[0061] Next, the voltage adjuster 130 can provide the low voltage VL to the node P1 and the control terminal CT1 through the conduction paths of the transistors T5 and T6 according to the pulled-up source driving signal S1, so that the voltage level of the node P1 and the control terminal CT1 is pulled up to the sum of the voltage value of the low voltage VL and the voltage value of the threshold voltage VTH6 of the transistor T6 (i.e., VL+VTH6). In this way, the transistor T6 can be in the conduction state according to the voltage level of the control terminal CT1.

[0062] In another aspect, the voltage adjuster 140 can provide the high voltage VH to the control terminal CT2 through the conduction path of the transistor T10 according to the pulled-up source driving signal S1, so that the voltage level of the control terminal CT2 is pulled up to the voltage value equal to the high voltage VH. Also, the voltage adjuster 140 can provide the reference voltage VREF1 to the driving terminal PD according to the pulled-down light emitting control signal EM, so that the voltage level of the driving terminal PD is correspondingly pulled up to the voltage value equal to the reference voltage VREF1. At this time, the driving circuit 110 can be turned off according to the voltage level of the driving terminal PD.

[0063] Next, please refer to Figure 2 and Figure 3C In this embodiment, Figure 3C is an equivalent circuit diagram of the pixel circuit 100 when operating in the compensation phase CP. Specifically, in the compensation phase CP, the source driving signal S1 and the light emitting control signal EM can be set to a low voltage level, and the ramp voltage VSWEEP can be set to a high voltage level.

[0064] In detail, in the compensation phase CP, the voltage adjuster 130 can maintain the voltage level of the input terminal PIN at the voltage difference between the voltage value of the data voltage VDATA and the voltage value of the threshold voltage VTH1 of the transistor T1 (i.e., VDATA-|VTH1|) according to the pulled-down source driving signal S1. Also, through the conduction path of the transistor T4, the voltage adjuster 130 can adjust the voltage level of the node P1 to the voltage difference between the voltage value of the data voltage VDATA and the voltage value of the threshold voltage VTH1 of the transistor T1 (i.e., VDATA-|VTH1|) according to the pulled-down source driving signal S1 and the voltage level of the input terminal PIN.

[0065] In addition, since the transistors T3, T5 and T6 of the voltage adjuster 130 are in the off state, the voltage adjuster 130 can maintain the voltage level of the control terminal CT1 at the sum of the voltage value of the low voltage VL and the voltage value of the threshold voltage VTH6 of the transistor T6 (i.e., VL+VTH6) in the compensation phase CP.

[0066] In another aspect, the voltage adjuster 140 can discharge the control terminal CT2 through the conduction paths of the transistors T7-T9 in accordance with the pull-down of the emission control signal EM, the source driving signal S1 and the reference voltage VREF2, so that the voltage level of the control terminal CT2 is adjusted to the sum of the voltage value of the reference voltage VREF2 and the voltage value of the threshold voltage VTH7 of the transistor T7 (i.e., VREF2+|VTH7|).

[0067] Also, the voltage adjuster 140 can provide the reference voltage VREF1 to the driving terminal PD in accordance with the pull-down of the emission control signal EM, so that the voltage level of the driving terminal PD is maintained at the voltage value of the reference voltage VREF1. At this time, the driving circuit 110 can be turned off in accordance with the voltage level of the driving terminal PD.

[0068] It is worth mentioning that, in the present embodiment, based on the transistors T1 and T3 matching each other and the voltage level of the control terminal (i.e., the input terminal PIN) of the transistor T3 being VDATA-|VTH1|, the voltage adjuster 130 can compensate the threshold voltage variation of the transistor T3 through the threshold voltage VTH1 of the transistor T1. Similarly, based on the transistors T6 and T12 matching each other and the voltage level of the control terminal (i.e., the control terminal CT1) of the transistor T12 being VL+VTH6, the voltage adjuster 130 can compensate the threshold voltage variation of the transistor T12 through the threshold voltage VTH6 of the transistor T6.

[0069] Next, please refer to Figure 2 and Figure 3D In the present embodiment, Figure 3D is an equivalent circuit diagram when the pixel circuit 100 operates in the sub-stage EP1 of the emission phase EP. Specifically, in the sub-stage EP1 of the emission phase EP, the source driving signal S1 can be set to a low voltage level, the emission control signal EM can be set to a high voltage level, and the voltage level of the ramp voltage VSWEEP can decrease at a fixed slope.

[0070] In detail, in the sub-stage EP1 of the emission phase EP, the voltage adjuster 130 can adjust the voltage level of the input terminal PIN to the difference between the voltage value of the data voltage VDATA, the voltage value of the threshold voltage VTH1 of the transistor T1 and the voltage variation amount AVSWEEP of the ramp voltage VSWEEP in accordance with the pull-down of the source driving signal S1 and through the coupling effect of the capacitor C1. That is, the voltage level of the input terminal PIN at this time is VDATA-|VTH1|-AVSWEEP.

[0071] Furthermore, through the on-path of the transistor T4, the voltage adjuster 130 can adjust the voltage level of the node P1 to be the difference between the voltage value of the data voltage VDATA, the voltage value of the threshold voltage VTH1 of the transistor T1, and the voltage variation AVSWEEP of the ramp voltage VSWEEP (i.e., VDATA - |VTH1 | - AVSWEEP) according to the source driving signal S1 being pulled low and the voltage level of the input terminal PIN.

[0072] Furthermore, since the transistors T3, T5, and T6 of the voltage adjuster 130 are in the off state, the voltage adjuster 130 can maintain the voltage level of the control terminal CT1 at the sum of the voltage value of the low voltage VL and the voltage value of the threshold voltage VTH6 of the transistor T6 (i.e., VL + VTH6) in the sub-stage EP1 of the emission stage EP.

[0073] On the other hand, since the transistors T7, T8, T10, and T12 of the voltage adjuster 140 are in the off state, the voltage adjuster 140 can maintain the voltage level of the control terminal CT2 at the sum of the voltage value of the reference voltage VREF2 and the voltage value of the threshold voltage VTH7 of the transistor T7 (i.e., VREF2 + |VTH7|) in the sub-stage EP1 of the emission stage EP. Furthermore, the voltage adjuster 140 can maintain the voltage level of the driving terminal PD at the voltage value of the reference voltage VREF1 according to the emission control signal EM being pulled high. At this time, the driving circuit 110 can be turned off according to the voltage level of the driving terminal PD.

[0074] It is worth mentioning that, according to the states of the voltage levels of the respective nodes of the pixel circuit 100, Figure 3D If the transistors T3 and T12 are to be turned on so that the driving circuit 110 can light up the light emitting element LED according to the on current ID, the voltage difference between the first terminal and the control terminal (i.e., the input terminal PIN) of the transistor T3 needs to be greater than the threshold voltage of the transistor T3. That is, the on condition of the transistor T3 should satisfy VREF2 - VDATA + |VTH1 | + AVSWEEP > |VTH3|.

[0075] In other words, in the pixel circuit 100, when the voltage variation AVSWEEP of the ramp voltage VSWEEP is greater than the difference between the voltage value of the data voltage VDATA and the voltage value of the reference voltage VREF2 (i.e., AVSWEEP > VDATA - VREF2), the transistors T3 and T12 can be turned on, thereby enabling the driving circuit 110 to light up the light emitting element LED.

[0076] Furthermore, if the voltage change ΔVSWEEP of the ramp voltage VSWEEP is greater than the difference between the voltage value of the data voltage VDATA and the voltage value of the reference voltage VREF2, the pixel circuit 100 can continue to operate in the sub-stage EP2 of the light emission stage EP.

[0077] Please refer to the following at the same time Figure 2 as well as Figure 3E In this embodiment, Figure 3E This is an equivalent circuit diagram of the pixel circuit 100 operating in sub-stage EP2 of the light-emitting stage EP. Specifically, in sub-stage EP2 of the light-emitting stage EP, the source drive signal S1 can be set to a low voltage level, the light-emitting control signal EM can be set to a high voltage level, and the voltage level of the ramp voltage VSWEEP can decrease at a fixed slope, and the voltage level of the ramp voltage VSWEEP can be greater than the difference between the voltage value of the data voltage VDATA and the voltage value of the reference voltage VREF2.

[0078] In detail, in the sub-stage EP2 of the light-emitting stage EP, the voltage regulator 130 can provide a low voltage VL to node P1 and input terminal PIN through the conduction paths of transistors T4 and T6 according to the pulled-down source drive signal S1, thereby causing the voltage level of node P1 and input terminal PIN to be pulled down to the voltage value equal to the low voltage VL.

[0079] In this situation, transistor T3 can operate in the linear region and be turned on according to the voltage level of the input terminal PIN. Then, voltage regulator 130 can provide a reference voltage VREF2 to control terminal CT1 through the conduction path of transistor T3, thereby charging control terminal CT1 and correspondingly pulling the voltage level of control terminal CT1 up to the value of the reference voltage VREF2. Thus, transistor T6 can be turned on according to the voltage level of control terminal CT1 (i.e., the reference voltage VREF2).

[0080] On the other hand, the transistor T12 of the voltage regulator 140 can be turned on according to the voltage level of the control terminal CT1, so that the voltage regulator 140 can provide the system high voltage VDD to the control terminal CT2 through the conduction path of the transistor T12, and the voltage level of the control terminal CT2 is correspondingly pulled up to the voltage value equal to the system high voltage VDD.

[0081] Then, by the coupling effect of capacitor C3, voltage regulator 140 can cause the voltage level of drive terminal PD to be adjusted to the sum of the voltage value of system high voltage VDD, the difference between the voltage value of reference voltage VREF2 and the voltage value of threshold voltage VTH7, and the voltage value of reference voltage VREF1. That is, the voltage level of drive terminal PD at this time is VDD-VREF2-|VTH7|+VREF1.

[0082] In the case that voltage regulator 140 pulls down the voltage level of drive terminal PD, drive transistor TD can generate a conduction current ID according to the voltage level of drive terminal PD, and correspondingly light up light emitting element LED.

[0083] At this time, the conduction current ID flowing through light emitting element LED can be shown in the following equation:

[0084] ID=K(VDD-VREF1+VREF2+|VTH7|-VDD-|VTHD|)^2

[0085] =K(VREF2-VREF1)^2

[0086] wherein ID is the current value of conduction current ID; K is the process parameter of drive transistor TD; VDD is the voltage value of system high voltage VDD; VREF1 is the voltage value of reference voltage VREF1; VREF2 is the voltage value of reference voltage VREF2; VTH7 is the voltage value of threshold voltage of transistor T7; and VTHD is the voltage value of threshold voltage of drive transistor TD.

[0087] According to the above equation, when pixel circuit 100 operates in the sub-stage EP2 of emitting stage EP, since drive transistor TD and transistor T7 match each other (i.e., threshold voltage VTHD is equal to threshold voltage VTH7), the conduction current ID generated by pixel circuit 100 can be independent of threshold voltage VTHD of drive transistor TD and the voltage value of system high voltage VDD. In this way, pixel circuit 100 can improve the effect of threshold voltage shift of drive transistor TD caused by process difference or long-time operation. Moreover, the conduction current ID generated by pixel circuit 100 is less likely to be affected by the line resistance in the path of system high voltage VDD and system low voltage VSS.

[0088] In addition, since the path of conduction current ID only has one transistor (e.g., drive transistor TD), pixel circuit 100 can reduce the required voltage difference between system high voltage VDD and system low voltage VSS, so as to save power consumption.

[0089] In addition, in the pixel circuit 100 of the present embodiment, in the case where the voltage level of the input terminal PIN is not affected by the switching action of the ramp voltage VSWEEP, the voltage adjuster 130 can cause the input terminal PIN to be adjusted to the voltage value of the low voltage VL based on the circuit architecture of the transistors T3 and T6. In this way, the transistor T3 can quickly perform a charging action on the control terminal CT1 in a state of operating in the linear region, so that the drive circuit 110 can smoothly light up the light emitting element LED in accordance with the voltage levels of the control terminal CT1 and the drive terminal PD, thereby improving the switching efficiency of the circuit.

[0090] Furthermore, in the case where the threshold voltage variations of the transistors T3 and T12 have been compensated, the pixel circuit 100 can improve the gray scale control capability to improve the accuracy of the gray scale control of the pixel circuit using pulse-width modulation (PWM) control.

[0091] Next, please refer to Figure 2 and Figure 3F In the present embodiment, Figure 3F is an equivalent circuit diagram of the pixel circuit 100 when operating in the cutoff phase TP. Specifically, in the cutoff phase TP, the source driving signal S1 and the light emitting control signal EM can be set to the low voltage level, and the ramp voltage VSWEEP can be set to the high voltage level.

[0092] In detail, in the cutoff phase TP, the voltage adjuster 130 can provide the low voltage VL to the node P1 and the input terminal PIN through the conduction paths of the transistors T4 and T6 in accordance with the source driving signal S1 being pulled low, thereby causing the voltage levels of the node P1 and the input terminal PIN to be correspondingly pulled low to the voltage value equal to the low voltage VL.

[0093] Next, the transistor T3 of the voltage adjuster 130 can be turned on in accordance with the voltage level of the input terminal PIN (i.e., the low voltage VL), so that the voltage adjuster 130 can provide the reference voltage VREF2 to the control terminal CT1 through the conduction path of the transistor T3 to perform a charging action on the control terminal CT1, and cause the voltage level of the control terminal CT1 to be correspondingly pulled high to the voltage value equal to the reference voltage VREF2. In this way, the transistor T6 can be in the on state in accordance with the voltage level of the control terminal CT1 (i.e., the reference voltage VREF2).

[0094] On the other hand, the transistor T12 of the voltage adjuster 140 can be turned on in accordance with the voltage level of the control terminal CT1, so that the voltage adjuster 140 can provide the system high voltage VDD to the control terminal CT2 through the conduction path of the transistor T12, and cause the voltage level of the control terminal CT2 to be correspondingly pulled high to the voltage value equal to the system high voltage VDD.

[0095] Next, the voltage adjuster 140 can provide the reference voltage VREF1 to the driving end PD according to the pulled-down light-emitting control signal EM, so that the voltage level of the driving end PD is correspondingly pulled up to a voltage value equal to the reference voltage VREF1. At this time, the driving circuit 110 can stop lighting the light-emitting element LED according to the voltage levels of the driving end PD and the control end CT2.

[0096] In summary, the pixel circuit according to the embodiments of the present application can improve the switching efficiency and the accuracy of gray scale control of the circuit, and effectively reduce the overall power consumption of the pixel circuit, by the circuit architecture of the voltage adjuster and the compensation of the threshold voltage variation of the related transistors.

Claims

1. A pixel circuit, comprising: a driving circuit having a driving terminal to generate a driving current according to a voltage level of the driving terminal; a data writing circuit having an input terminal to provide a data voltage to the input terminal according to a source driving signal; a first voltage adjuster having a first control terminal, the first voltage adjuster coupled to the data writing circuit to adjust voltage levels of the input terminal and the first control terminal according to the source driving signal and a first reference voltage; a second voltage adjuster having a second control terminal, the second voltage adjuster coupled to the driving circuit and the first voltage adjuster to adjust voltage levels of the second control terminal and the driving terminal according to the first reference voltage, a light emitting control signal, the source driving signal and a voltage level of the first control terminal, wherein the driving circuit comprises: a driving transistor having a first terminal coupled to a system high voltage, a control terminal coupled to the driving terminal; and a light emitting element having an anode terminal coupled to a second terminal of the driving transistor, a cathode terminal coupled to a system low voltage, wherein the data writing circuit comprises: a first transistor having a first terminal coupled to the data voltage, a second terminal and a control terminal coupled to each other; a second transistor having a first terminal coupled to the second terminal and the control terminal of the first transistor, a second terminal coupled to the input terminal, a control terminal receiving the source driving signal; and a first capacitor having a first terminal coupled to a ramp voltage, a second terminal coupled to the input terminal, wherein the first voltage adjuster comprises: a third transistor having a first terminal coupled to the first reference voltage, a second terminal coupled to the first control terminal, a control terminal coupled to the input terminal; a fourth transistor having a first terminal coupled to the input terminal, a control terminal receiving the source driving signal; a fifth transistor having a first terminal coupled to the first control terminal, a second terminal coupled to a second terminal of the fourth transistor, a control terminal receiving the source driving signal; a sixth transistor having a first terminal coupled to a low voltage, a second terminal coupled to the second terminal of the fifth transistor, a control terminal coupled to the first control terminal; and a second capacitor having a first terminal coupled to the first control terminal, a second terminal coupled to the low voltage, wherein the second voltage adjuster comprises: a seventh transistor having a first terminal coupled to the low voltage, a control terminal coupled to the first reference voltage; an eighth transistor having a first terminal coupled to a second terminal of the seventh transistor, a control terminal receiving the light emitting control signal; a ninth transistor having a first terminal coupled to the second terminal of the eighth transistor, a second terminal coupled to the second control terminal, a control terminal receiving the source driving signal; a tenth transistor having a first terminal coupled to a high voltage, a second terminal coupled to the second control terminal, a control terminal receiving the source driving signal; an eleventh transistor having a first terminal coupled to a second reference voltage, a second terminal coupled to the driving terminal, a control terminal receiving the light emitting control signal; ​ a twelfth transistor having a first end coupled to the system high voltage, a second end coupled to the second control end, and a control end coupled to the first control end; and a third capacitor coupled between the second control end and the driving end.

2. The pixel circuit of claim 1, wherein in a reset phase, the first voltage adjuster lowers a voltage level of the input end and raises a voltage level of the first control end according to the first reference voltage and the source driving signal being pulled low.

3. The pixel circuit of claim 2, wherein in the reset phase, the second voltage adjuster provides a system high voltage to raise a voltage level of the second control end according to the voltage level of the first control end, and provides a second reference voltage to raise a voltage level of the driving end according to the light emitting control signal being pulled low.

4. The pixel circuit of claim 1, wherein in a data write phase, the data write circuit provides the data voltage to raise a voltage level of the input end according to the source driving signal being pulled high.

5. The pixel circuit of claim 1, wherein in a compensation phase, the second voltage adjuster discharges the second control end according to the first reference voltage, the light emitting control signal, and the source driving signal.

6. The pixel circuit of claim 1, wherein in a first sub-phase of a light emitting phase, the first voltage adjuster adjusts a voltage level of the input end according to a voltage variation of a ramp voltage.

7. The pixel circuit of claim 6, wherein in a second sub-phase of the light emitting phase, the first voltage adjuster provides a low voltage to lower a voltage level of the input end and raise a voltage level of the first control end according to the first reference voltage and the source driving signal being pulled low.

8. The pixel circuit of claim 7, wherein in the second sub-phase of the light emitting phase, the second voltage adjuster lowers a voltage level of the driving end according to the voltage level of the second control end, and causes the driving circuit to generate the on current.

9. The pixel circuit of claim 1, wherein in an off phase, the driving circuit is turned off according to the voltage level of the second control end being pulled high and the light emitting control signal being pulled low.

10. The pixel circuit of claim 1, wherein the sixth transistor and the twelfth transistor are matched with each other, the first transistor and the third transistor are matched with each other, and the driving transistor and the seventh transistor are matched with each other.

11. The pixel circuit of claim 1, wherein the second transistor, the fifth transistor, the sixth transistor, the tenth transistor, and the twelfth transistor are N-type transistors, and the first transistor, the third transistor, the fourth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the eleventh transistor, and the driving transistor are P-type transistors.

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