Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a plurality of pixel circuit columns, one pixel circuit column is electrically connected with two data lines, and one data line transmits a data signal and a bias signal to the pixel circuits in the pixel circuit column in time. According to the embodiment of the application, the double data line design is utilized, and the data signal and the bias signal are transmitted in time by the data line, which is beneficial to realize high-frequency driving.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] With the continuous updates in display panel technology, users have increasingly higher requirements for display quality.

[0003] In related technologies, pixel circuits can be paired with on-state bias stress (OBS) circuit modules to add a bias signal to periodically reset the source or drain of the driving transistor, thereby improving the hysteresis phenomenon that may occur in the driving transistor during long-term operation, reducing flicker, and improving image quality.

[0004] However, the addition of a bias signal presents a challenge in achieving high-frequency driving for the display panel. Summary of the Invention

[0005] This application provides a display panel and display device that utilizes a dual data line design and uses the data lines to transmit data signals and bias signals in a time-division manner, which is beneficial for achieving high-frequency driving.

[0006] In a first aspect, embodiments of this application provide a display panel including multiple pixel circuit columns, each pixel circuit column being electrically connected to two data lines, and one data line transmitting data signals and bias signals to the pixel circuits in the pixel circuit column in a time-division multiplexing manner.

[0007] Based on the same inventive concept, in a second aspect, embodiments of this application provide a display device including a display panel as described in the first aspect embodiment.

[0008] According to the display panel and display device provided in the embodiments of this application, a column of pixel circuits is connected to two data lines, and the data lines transmit data signals and bias signals in a time-division manner. In this way, a data line not only transmits data signals, but also alternately transmits bias signals, which can realize high-frequency signal transmission and is beneficial to realize high-frequency driving of the display panel. Attached Figure Description

[0009] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0010] Figure 1 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application;

[0011] Figure 2This illustration shows a schematic diagram of a data cable connection in a display panel provided in an embodiment of this application;

[0012] Figure 3 This illustration shows a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application;

[0013] Figure 4 This diagram illustrates a timing schematic of a display panel provided in an embodiment of this application.

[0014] Figure 5 This illustration shows another timing diagram of the display panel provided in an embodiment of this application;

[0015] Figure 6 This illustration shows another structural diagram of the pixel circuit in the display panel provided in an embodiment of this application;

[0016] Figure 7 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0017] Figure 8 This illustration shows another connection diagram of the data cable in the display panel provided in an embodiment of this application;

[0018] Figure 9 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0019] Figure 10 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0020] Figure 11 This illustration shows yet another structural diagram of the pixel circuit in the display panel provided in an embodiment of this application;

[0021] Figure 12 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0022] Figure 13 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0023] Figure 14 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0024] Figure 15 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0025] Figure 16 This illustration shows another structural diagram of the display panel provided in an embodiment of this application;

[0026] Figure 17This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0027] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0028] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0029] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0030] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0031] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0032] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0033] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0034] As described in the background section, the addition of a bias signal presents a challenge to how the display panel can achieve high-frequency driving.

[0035] To address the aforementioned problems, this application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0036] like Figure 1 As shown, the display panel 100 may include multiple pixel circuit columns 10a, which may be arranged in the row direction X, and may include multiple pixel circuits 10 arranged in the column direction Y. One pixel circuit column 10a may be electrically connected to two data lines 20, and one data line 20 may transmit data signals and bias signals to the pixel circuits 10 in the pixel circuit column 10a in a time-division multiplexing manner.

[0037] Understandably, in this embodiment of the application, one pixel circuit array 10a can be electrically connected to two data lines 20, which can be referred to as a double data line (DDL) design. Each data line 20 can transmit data signals and bias signals to the pixel circuits 10a in a time-division multiplexing manner.

[0038] The pixel circuit 10 can be electrically connected to the light-emitting element. The pixel circuit 10 generates a driving current according to the data signal to drive the light-emitting element to emit light. Different data signals result in different driving currents generated by the pixel circuit 10, which in turn causes the light-emitting element to emit light of different brightness.

[0039] The bias signal (DVH signal) can be transmitted to the source or drain of the driving transistor in the pixel current 10 to reset the source or drain of the driving transistor, thereby improving the hysteresis phenomenon that may occur in the driving transistor during long-term operation.

[0040] In this embodiment, a column of pixel circuits is connected to two data lines, and the data lines transmit data signals and bias signals in a time-division manner. In this way, a data line not only transmits data signals, but also alternately transmits bias signals, which can realize high-frequency signal transmission and is beneficial for realizing high-frequency driving of the display panel.

[0041] For example, pixel circuit 10 may include a first pixel circuit 11, a second pixel circuit 12, and a third pixel circuit 13. For example, the first pixel circuit 11 may be used to drive a red light-emitting element, the second pixel circuit 12 may be used to drive a green light-emitting element, and the third pixel circuit 13 may be used to drive a blue light-emitting element.

[0042] As an example, in two adjacent pixel circuit columns 10a, one pixel circuit column 10a may include a first pixel circuit 11 and a third pixel circuit 13 that are alternately distributed in the column direction Y, and the other pixel circuit column 10a may include a plurality of second pixel circuits 12 arranged in the column direction Y.

[0043] It should be noted that, Figure 1 The arrangement of the pixel circuits shown is merely an example and is not intended to limit this application.

[0044] In some embodiments, such as Figure 2 As shown, two adjacent pixel circuit columns 10a can be connected to different data signal terminals Source via data line 20. The data signal terminal Source can be used to provide data signals.

[0045] For example, in two adjacent pixel circuit columns 10a, one pixel circuit column 10a can be connected to the first data signal terminal Source1 via data line 20, and the other pixel circuit column 10a can be connected to the second data signal terminal Source2 via data line 20.

[0046] In this embodiment, by electrically connecting different pixel circuit columns 10a to different data signal terminals Source, it is beneficial to facilitate the accurate transmission of data signals to the pixel circuits.

[0047] Figure 2 The example shown is that two data lines electrically connected to a pixel circuit array 10a are connected to a single data signal terminal. Of course, the two data lines electrically connected to a pixel circuit array 10a can also be connected to different data signal terminals, which will be described in subsequent embodiments.

[0048] In some embodiments, such as Figure 2 As shown, the two data lines 20 connected to the pixel circuit column 10a may include a first data line 21 and a second data line 22.

[0049] As described above, data signals can be used to generate drive current in pixel circuits, while bias signals can be used to adjust the bias state of the drive transistors in the pixel circuits. Data signals and bias signals are different signal types. These different signal types can be understood as data signals and bias signals having different functions. Both data signals and bias signals can be voltage signals. The voltage values ​​of the data signals and bias signals can be set to be the same or different depending on the actual situation.

[0050] At the same time, the first data line 21 and the second data line 22 connected to the same pixel circuit column 10a transmit different signal types, the first data line 21 connected to two adjacent pixel circuit columns 10a transmits the same signal type, and the second data line 22 connected to two adjacent pixel circuit columns 10a transmits the same signal type.

[0051] For ease of explanation, such as Figure 2 As shown, in two adjacent pixel circuit columns 10a, the first data line 21 electrically connected to the first pixel circuit column 10a is marked as data line data1, the second data line 22 electrically connected to the first pixel circuit column 10a is marked as data line data3, the first data line 21 electrically connected to the second pixel circuit column 10a is marked as data line data2, and the second data line 22 electrically connected to the second pixel circuit column 10a is marked as data line data4.

[0052] For example, during the same time period, data lines data1 and data2 can be used to transmit data signals, while data lines data3 and data4 can be used to transmit bias signals. As another example, during a different time period, data lines data1 and data2 can be used to transmit bias signals, while data lines data3 and data4 can be used to transmit data signals.

[0053] In this embodiment, during the same time period, the data lines data1 and data3 electrically connected in the same pixel circuit column transmit different signal types, and the data lines data2 and data4 transmit different signal types. For example, while data line data1 transmits a data signal, data line data3 transmits a bias signal; or while data line data1 transmits a bias signal, data line data3 transmits a data signal. This can increase the frequency of signal transmission and achieve high-frequency driving of the two types of data signals. In addition, during the same time period, the data lines data1 and data2 transmit the same signal type, and the data lines data3 and data4 transmit the same signal type. This eliminates the need for very precise time division, which is more conducive to achieving high-frequency driving.

[0054] In some embodiments, the data line can be connected to the data signal terminal and the bias signal terminal via a gating circuit. For example... Figure 2As shown, the display panel may further include a first gating circuit 31 and a second gating circuit 32. The two data lines 20 connected to the pixel circuit column 10a are connected to the data signal terminal Source through the first gating circuit 31, and the two data lines 20 connected to the pixel circuit column 10a are connected to the bias signal terminal DVH through the second gating circuit 32. The first gating circuit 31 is used to transmit the data signal provided by the data signal terminal Source to the data line 20 in a time-division manner, and the second gating circuit 32 is used to transmit the bias signal provided by the bias signal terminal DVH to the data line 20 in a time-division manner.

[0055] In this embodiment of the application, by controlling the conduction status of the first gating circuit 31 and the second gating circuit 32, the signals of the data signal terminal and the bias signal terminal can be written to the data line at specific times, thereby realizing the sequential switching of the data signal and the bias signal on the data line.

[0056] For example, the first gating circuit 31 and the pixel circuit column 10a can be configured in a one-to-one correspondence, and the second gating circuit 32 and the pixel circuit column 10a can be configured in a one-to-one correspondence. For instance, in two adjacent pixel circuit columns 10a, the data lines data1 and data3 connected to one pixel circuit column 10a can be connected to the first data signal terminal Source1 through the first gating circuit 31, and the data lines data1 and data3 can be connected to the bias signal terminal DVH through the first second gating circuit 32; the data lines data2 and data4 connected to the other pixel circuit column 10a can be connected to the second data signal terminal Source2 through the second gating circuit 31, and the data lines data2 and data4 can be connected to the bias signal terminal DVH through the second second gating circuit 32.

[0057] When the bias signal required by each pixel circuit is the same, each data line can be electrically connected to the same bias signal terminal DVH.

[0058] In some embodiments, such as Figure 2 As shown, the two data lines 20 connected to the pixel circuit column 10a include a first data line 21 and a second data line 22.

[0059] The first gating circuit 31 and the second gating circuit 32 may each include two switches. The first gating circuit 31 may include a first switch T1 and a second switch T2. The first terminals of both switches T1 and T2 are connected to the data signal terminal Source. The second terminal of the first switch T1 is connected to the first data line 21, and the second terminal of the second switch T2 is connected to the second data line 22. The second gating circuit 32 may include a third switch T3 and a fourth switch T4. The first terminals of both switches T3 and T4 are connected to the bias signal terminal DVH. The second terminal of the third switch T3 is connected to the first data line 21, and the second terminal of the fourth switch T4 is connected to the second data line 22.

[0060] The first switch T1 and the fourth switch T4 are simultaneously turned on or off under the control of the first control signal line mux1, and the second switch T2 and the third switch T3 are simultaneously turned on or off under the control of the second control signal line mux2; the first switch T1 and the second switch T2 are turned on or off sequentially under the control of the first control signal line and the second control signal line, respectively.

[0061] For example, the first switch T1, the second switch T2, the third switch T3, and the fourth switch T4 can all be transistors.

[0062] When the control signal on the first control signal line mux1 is at the ON level, the first switch T1 and the fourth switch T4 are turned on, allowing the data signal at the data signal terminal Source to be transmitted to the first data line 21, and the bias signal at the bias signal terminal DVH to be transmitted to the second data line 22. When the control signal on the second control signal line mux2 is at the ON level, the data signal at the data signal terminal Source can be transmitted to the second data line 22, and the bias signal at the bias signal terminal DVH can be transmitted to the first data line 21. This allows each data line to transmit data signals and bias signals in a time-division multiplexing manner.

[0063] Understandably, the signals on the first control signal line mux1 and the second control signal line mux2 are sequentially at the on level.

[0064] In some embodiments, the pixel circuitry may be connected to one of the first data line and the second data line. Please refer to... Figure 2 The pixel circuits in the odd-numbered rows of pixel circuit column 10a are connected to the first data line 21, and the pixel circuits in the even-numbered rows of pixel circuit column 10a are connected to the second data line 22.

[0065] For example, taking the columns where the first pixel circuit 11 and the third pixel circuit 13 are located as an example, the first pixel circuit 11 can be located in an odd-numbered row, the third pixel circuit 13 can be located in an even-numbered row, the first pixel circuit 11 can be connected to the first data line 21, and the third pixel circuit 13 can be connected to the second data line 22.

[0066] In this embodiment, the pixel circuits of odd-numbered rows and even-numbered rows are connected to different data lines, which helps to avoid signal interference between different rows and improves the accuracy of signal transmission.

[0067] In some embodiments, where the pixel circuit is connected to one of the first data line and the second data line, different functional modules can be used to transmit the data signal and the bias signal respectively. For example... Figure 3 As shown, the pixel circuit 10 may include a driving module 101, a data writing module 102, and a bias module 103. The data writing module 102 is used to transmit data signals to the driving module 101, and the bias module 103 is used to transmit bias signals to the driving module 101.

[0068] Please refer to Figure 2 and Figure 3 When the pixel circuit is connected to one of the first data line and the second data line, the data writing module 102 and the bias module 103 of the pixel circuit 10 in the odd-numbered rows of the pixel circuit 10 in the pixel circuit column 10a can be connected to the first data line 21, and the data writing module 102 and the bias module 103 of the pixel circuit 10 in the even-numbered rows of the pixel circuit 10 in the pixel circuit column 10a can be connected to the second data line 22.

[0069] In this embodiment, based on the presence of a gating circuit, the data writing module 102 provides a data signal to the driving module 101, and the bias module 103 provides a bias signal to the driving module 101, which can easily avoid crosstalk between different signals. Furthermore, the data writing module 102 and the bias module 103 of the same pixel circuit are connected to the same data line, which facilitates efficient utilization of the data line.

[0070] For example, the data signal terminal Source is used to provide a data signal, and the bias signal terminal DVH is used to provide a bias signal. The data writing module 102 and the bias module 103 in the pixel circuit 10 can be electrically connected to the data signal terminal Source and the bias signal terminal DVH through the same data line. It can be understood that this data line is connected to the data signal terminal Source through a first gating circuit and connected to the bias signal terminal DVH through a second gating circuit.

[0071] For example, the data writing module 102 can be turned on or off under the control of the scan line S2, and the bias module can be turned on or off under the control of the scan line SP. In all embodiments of this application, the example of a low-level conduction level is used for illustration.

[0072] In some embodiments, where a gating circuit is provided, the pixel circuit is connected to one of the first data line and the second data line, and the pixel circuit includes a data writing module 102 and a bias module 103, please refer to... Figure 4During the display time of one frame, the operation of the pixel circuit may include a data writing stage, which may include a data writing sub-stage and a first bias sub-stage.

[0073] To facilitate the differentiation of sub-stages in different rows of pixel circuits, Figure 4 In the diagram, the data writing sub-stage d(i) and the first bias sub-stage p1(i) correspond to the i-th row of pixel circuits, and the data writing sub-stage d(i+1) and the first bias sub-stage p1(i+1) correspond to the (i+1)-th row of pixel circuits, where i is an integer greater than 0.

[0074] During the data writing sub-stage, the data writing module 102 of the pixel circuit 10 is turned on, and the data signal on the data line can be written to the driving module 101.

[0075] In the first bias sub-stage, the bias module 103 of the pixel circuit 10 can be turned on, and the bias signal on the data line can be written into the driver module 101.

[0076] During the data writing phase, the control signals on the first control signal line mux1 and the second control signal line mux2 are sequentially at the on level.

[0077] As an example, such as Figure 4 As shown, for the same row of pixel circuits, the first bias sub-stage can be after the data writing sub-stage. For example, for the i-th row of pixel circuits, its first bias sub-stage p1(i) is after the data writing sub-stage d(i). For the (i+1)-th row of pixel circuits, its first bias sub-stage p1(i+1) is after the data writing sub-stage d(i+1).

[0078] The first bias sub-stage p1(i) of the i-th row pixel circuit and the data writing sub-stage d(i+1) of the (i+1)-th row pixel circuit can at least partially overlap in time.

[0079] Please refer to the reference. Figure 2 , Figure 3 and Figure 4 For two adjacent rows of pixel circuits, the change process of the control signals on the first control signal mux1 and the second control signal line mux2 can include stages a1 to a4. The working process of the display panel can be as follows:

[0080] First, during at least a portion of stage a1, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the i-th row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the i-th row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0081] In the data writing sub-stage d(i), the scan line S2 connected to the i-th row pixel circuit is at the on level, the data writing module 102 of the i-th row pixel circuit is turned on, the data signal data R on the data line data1 is written to the driving module 101 of the first pixel circuit 11 in the i-th row, and the data signal data G on the data line data2 is written to the driving module 101 of the second pixel circuit 12 in the i-th row.

[0082] Next, during at least a portion of stage a2, the signal on the second control signal line mux2 is at the on level. At this time, the second switch T2 and the third switch T3 are simultaneously turned on. The data signal data B provided by the first data signal terminal Source1 to the pixel circuit located in the (i+1)th row can be transmitted to the data line data3 through the second switch T2. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (i+1)th row can be transmitted to the data line data4 through the second switch T2. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data1 and data2 respectively through the third switch T3.

[0083] In the first bias sub-stage p1(i), the scan line SP connected to the i-th row pixel circuit is at the on level, the bias module 103 of the i-th row pixel circuit is turned on, the bias signal on the data line data1 is written into the driving module 101 of the i-th row first pixel circuit 11, and the bias signal on the data line data2 is written into the driving module 101 of the i-th row second pixel circuit 12.

[0084] The data writing sub-stage d(i+1) and the first bias sub-stage p1(i) can overlap.

[0085] In the data writing sub-stage d(i+1), the scan line S2 connected to the pixel circuit of the (i+1)th row is at the on level, the data writing module 102 of the pixel circuit of the (i+1)th row is turned on, the data signal data B on the data line data3 is written to the driving module 101 of the third pixel circuit 13 of the (i+1)th row, and the data signal data G on the data line data4 is written to the driving module 101 of the second pixel circuit 12 of the (i+1)th row.

[0086] Next, during at least a portion of stage a3, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the (i+2)th row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (i+2)th row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0087] In the first bias sub-stage p1(i+1), the scan line SP connected to the pixel circuit of the (i+1)th row is at the on level, the bias module 103 of the pixel circuit of the (i+1)th row is turned on, the bias signal on the data line data3 is written into the driving module 101 of the first pixel circuit 11 of the (i+1)th row, and the bias signal on the data line data4 is written into the driving module 101 of the second pixel circuit 12 of the (i+1)th row.

[0088] And so on.

[0089] Figure 4 Only the timing of two rows of pixel circuits is shown. It can be understood that the first bias sub-stage p1(i+1) of the (i+1)th row pixel circuit and the data writing sub-stage d(i+2) of the (i+2)th row pixel circuit can overlap at least partially in time.

[0090] For example, i can take the value 1.

[0091] As another example, such as Figure 5 As shown, for the same row of pixel circuits, the first bias sub-stage can be before the data writing sub-stage. For example, for the j-th row of pixel circuits, its first bias sub-stage p1(j) is before the data writing sub-stage d(j). For the (i+1)-th row of pixel circuits, its first bias sub-stage p1(j+1) is before the data writing sub-stage d(j+1), where j is an integer greater than 0.

[0092] The data writing sub-stage d(j) of the j-th row pixel circuit and the first bias sub-stage p1(j+1) of the (j+1)-th row pixel circuit can at least partially overlap in time.

[0093] Please refer to the reference. Figure 2 , Figure 3 and Figure 5 The operation of the display panel can be described as follows:

[0094] First, during at least a portion of the time in phase a1, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the j-th row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the j-th row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0095] At this time, the scan lines S2 and SP connected to the pixel circuit in row j and the scan lines S2 and SP connected to the pixel circuit in row j+1 are all at the cutoff level, so the data line signal is not written into the pixel circuit in row j and the pixel circuit in row j+1.

[0096] Next, during at least a portion of stage a2, the signal on the second control signal line mux2 is at the on level. At this time, the second switch T2 and the third switch T3 are simultaneously turned on. The data signal data B provided by the first data signal terminal Source1 to the pixel circuit located in the (j+1)th row can be transmitted to the data line data3 through the second switch T2. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (j+1)th row can be transmitted to the data line data4 through the second switch T2. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data1 and data2 respectively through the third switch T3.

[0097] In the first bias sub-stage p1(j), the scan line SP connected to the j-th row pixel circuit is at the on level, the bias module 103 of the j-th row pixel circuit is turned on, the bias signal on the data line data1 is written into the driving module 101 of the i-th row first pixel circuit 11, and the bias signal on the data line data2 is written into the driving module 101 of the i-th row second pixel circuit 12.

[0098] Next, during at least a portion of stage a3, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the j+2 row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the j+2 row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0099] In the data writing sub-stage d(j), the scan line S2 connected to the j-th row pixel circuit is at the on level, the data writing module 102 of the j-th row pixel circuit is turned on, the data signal data R on the data line data1 is written to the driving module 101 of the j-th row first pixel circuit 11, and the data signal data G on the data line data2 is written to the driving module 101 of the j-th row second pixel circuit 12.

[0100] The first bias sub-stage p1(j+1) and the data writing sub-stage d(j) can overlap.

[0101] In the first bias sub-stage p1(j+1), the scan line SP connected to the (j+1)th row pixel circuit is at the on level, the bias module 103 of the (j+1)th row pixel circuit is turned on, the bias signal on the data line data3 is written into the driving module 101 of the first pixel circuit 11 in the (j+1)th row, and the bias signal on the data line data4 is written into the driving module 101 of the second pixel circuit 12 in the (j+1)th row.

[0102] Next, during at least a portion of stage a4, the signal on the second control signal line mux2 is at the on level. At this time, the second switch T2 and the third switch T3 are simultaneously turned on. The data signal data B provided by the first data signal terminal Source1 to the pixel circuit located in the j+3 row can be transmitted to the data line data3 through the second switch T2. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the j+3 row can be transmitted to the data line data4 through the second switch T2. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data1 and data2 respectively through the third switch T3.

[0103] In the data writing sub-stage d(j+1), the scan line S2 connected to the pixel circuit of the (j+1)th row is at the on level, the data writing module 102 of the pixel circuit of the (j+1)th row is turned on, the data signal data B on the data line data3 is written to the driving module 101 of the third pixel circuit 13 of the (j+1)th row, and the data signal data G on the data line data4 is written to the driving module 101 of the second pixel circuit 12 of the (j+1)th row.

[0104] And so on.

[0105] For example, j can take the value 1.

[0106] Figure 5 Only the timing of two rows of pixel circuits is shown. It can be understood that the first bias sub-stage p1(j+2) of the (j+2)th row pixel circuit and the data writing sub-stage d(j+1) of the (j+1)th row pixel circuit can overlap at least partially in time.

[0107] Figure 4 or Figure 5 In the illustrated embodiment, the purpose of transmitting data signals and bias signals to the driver module using the same data line is achieved by having the data writing sub-stage of one row of pixel circuits at least partially overlap with the first bias sub-stage of the other row of pixel circuits.

[0108] In some embodiments, when a gating circuit is provided, data signals and bias signals can be transmitted in a time-division multiplexing manner using the same functional module. For example... Figure 6 As shown, the pixel circuit 10 may include a driving module 101 and a data writing module 102. The data writing module 102 is used to transmit data signals and bias signals to the driving module 101 in a time-division multiplexing manner. Figure 6 and Figure 3 The difference is that, Figure 6 The pixel circuit shown does not require an additional module for transmitting bias signals.

[0109] Please refer to Figure 2 and Figure 6 When the pixel circuit is connected to one of the first data line and the second data line, the data writing module 102 of the odd-numbered row pixel circuit 10 in the pixel circuit column 101a can be connected to the first data line 21, and the data writing module 102 of the even-numbered row pixel circuit 10 in the pixel circuit column 10a can be connected to the second data line 22.

[0110] In this embodiment of the application, when a gating circuit is provided, the data writing module 102 transmits data signals and bias signals to the driving module 101 in a time-division manner, which can reduce the number of functional modules in the pixel circuit and is beneficial to improving the resolution of the display panel.

[0111] For example, the data signal terminal Source is used to provide a data signal, and the bias signal terminal DVH is used to provide a bias signal. The data writing module 102 in the pixel circuit 10 can be electrically connected to the data signal terminal Source and the bias signal terminal DVH through the same data line. It is understood that this data line is connected to the data signal terminal Source through a first gating circuit and to the bias signal terminal DVH through a second gating circuit.

[0112] In some embodiments, where a gating circuit is provided and the pixel circuit's data writing module 102 is used for time-division multiplexing of data signals and bias signals, please refer to... Figure 7 During the display time of one frame, the operation of the pixel circuit includes a data writing stage, which comprises a data writing sub-stage and a first bias sub-stage. To facilitate differentiation of the sub-stages of different rows of pixel circuits, Figure 7 In the diagram, the data writing sub-stage d(k) and the first bias sub-stage p1(k) correspond to the k-th row of pixel circuits, and the data writing sub-stage d(k+1) and the first bias sub-stage p1(k+1) correspond to the (k+1)-th row of pixel circuits, where k is an integer greater than 0.

[0113] In the data writing sub-stage, the pixel circuit driving module 101 writes the data signal, and in the first bias sub-stage, the pixel circuit driving module 101 writes the bias signal.

[0114] For example, the pixel circuit may also include a threshold compensation module 104. The threshold compensation module 104 can be turned on or off under the control of the scan line S2, and the data writing module 102 can be turned on or off under the control of the scan line S3.

[0115] During the data writing sub-stage, both the data writing module 102 and the threshold compensation module 104 of the pixel circuit can be turned on, and the data signal can be written to the control terminal of the driving module 101. During the first bias sub-stage, the threshold compensation module 104 is turned off, the data writing module 102 is turned on, and the bias signal can be written to the source or drain of the driving transistor M3 of the driving module 101.

[0116] During the data writing phase, the control signals on the first control signal line mux1 and the second control signal line mux2 are sequentially at the on level.

[0117] As an example, such as Figure 7As shown, for the same row of pixel circuits, the first bias sub-stage can be after the data writing sub-stage. For example, for the k-th row of pixel circuits, its first bias sub-stage p1(k) is after the data writing sub-stage d(k). For the (k+1)-th row of pixel circuits, its first bias sub-stage p1(k+1) is after the data writing sub-stage d(k+1).

[0118] The first bias sub-stage p1(k) of the k-th row pixel circuit and the data writing sub-stage d(k+1) of the (k+1)-th row pixel circuit can at least partially overlap in time.

[0119] Please refer to the reference. Figure 2 , Figure 6 and Figure 7 The operation of the display panel can be described as follows:

[0120] First, during at least a portion of stage a1, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the k-th row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the k-th row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0121] In the data writing sub-stage d(k), the scan lines S2 and S3 connected to the k-th row pixel circuit are at the on level, the data writing module 102 and the threshold compensation module 104 of the k-th row pixel circuit are turned on, the data signal dataR on the data line data1 is written to the control terminal of the driving module 101 of the first pixel circuit 11 in the k-th row, and the data signal dataG on the data line data2 is written to the control terminal of the driving module 101 of the second pixel circuit 12 in the k-th row.

[0122] Next, during at least a portion of stage a2, the signal on the second control signal line mux2 is at the on level. At this time, the second switch T2 and the third switch T3 are simultaneously turned on. The data signal data B provided by the first data signal terminal Source1 to the pixel circuit located in the k+1 row can be transmitted to the data line data3 through the second switch T2. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the k+1 row can be transmitted to the data line data4 through the second switch T2. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data1 and data2 respectively through the third switch T3.

[0123] In the first bias sub-stage p1(k), the scan line S3 connected to the k-th row pixel circuit is at the on level, the data writing module 102 of the k-th row pixel circuit is turned on, the bias signal on the data line data1 is written to the driving module 101 of the first pixel circuit 11 in the k-th row, and the bias signal on the data line data2 is written to the driving module 101 of the second pixel circuit 12 in the k-th row.

[0124] The data writing sub-stage d(k+1) and the first bias sub-stage p1(k) can overlap.

[0125] In the data writing sub-stage d(k+1), the scan lines S2 and S3 connected to the (k+1)th row pixel circuit are at the on level, the data writing module 102 and the threshold compensation module 104 of the (k+1)th row pixel circuit are turned on, the data signal data B on the data line data3 is written to the control terminal of the driving module 101 of the (k+1)th row third pixel circuit 13, and the data signal data G on the data line data4 is written to the control terminal of the driving module 101 of the (k+1)th row second pixel circuit 12.

[0126] Next, during at least a portion of stage a3, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the k+2 row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the k+2 row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0127] In the first bias sub-stage p1(k+1), the scan line S3 connected to the (k+1)th row pixel circuit is at the on level, the data writing module 102 of the (k+1)th row pixel circuit is turned on, the bias signal on the data line data1 is written to the driving module 101 of the first pixel circuit 11 in the (k+1)th row, and the bias signal on the data line data2 is written to the driving module 101 of the second pixel circuit 12 in the (k+1)th row.

[0128] And so on.

[0129] Figure 7 The timing diagram only shows two rows of pixel circuits. It can be understood that the first bias sub-stage p1(k+1) of the (k+1)th row pixel circuit and the data writing sub-stage d(k+2) of the (k+2)th row pixel circuit can at least partially overlap in time.

[0130] For example, k can take the value 1.

[0131] In other embodiments, the two data lines electrically connected to the pixel circuit include a first data line and a second data line, and the pixel circuit can be connected to both the first data line and the second data line.

[0132] Please refer to Figure 8 Each pixel circuit in pixel circuit column 10a is electrically connected to the first data line 21 and the second data line 22.

[0133] In this embodiment, since a pixel circuit is connected to different data lines, it is advantageous to use different data lines to transmit data signals and bias signals to the pixel circuit respectively, which helps to avoid interference between signals received by the same pixel circuit and improves the accuracy of signal transmission.

[0134] In some embodiments, when the pixel circuit connects both the first data line and the second data line, different functional modules can be used to transmit the data signal and the bias signal respectively. For example... Figure 3 As shown, the pixel circuit 10 may include a driving module 101, a data writing module 102, and a bias module 103. The data writing module 102 is used to transmit data signals to the driving module 101, and the bias module 103 is used to transmit bias signals to the driving module 101.

[0135] Please refer to Figure 8 and Figure 3 The data writing module 102 of the odd-numbered row pixel circuit 10 in pixel circuit column 10a is connected to the first data line 21, and the bias module 103 of the odd-numbered row pixel circuit 10 in pixel circuit column 10a is connected to the second data line 22.

[0136] The data writing module 102 of the even-numbered row pixel circuit 10 in pixel circuit column 10a is connected to the second data line 22, and the bias module 103 of the even-numbered row pixel circuit 10 in pixel circuit column 10a is connected to the first data line 22.

[0137] In this embodiment, the data writing module 102 provides a data signal to the driving module 101, and the bias module 103 provides a bias signal to the driving module 101, which can easily avoid crosstalk between different signals. In addition, the data writing module 102 and the bias module 103 of the same pixel circuit are connected to different data lines, which can further help avoid crosstalk between the data signal and the bias signal transmitted to the same pixel circuit.

[0138] To facilitate distinguishing the connection relationships between the data writing module and the bias module and the two data lines in the same pixel circuit. Figure 8 In the diagram, the connecting line with an arrow indicates that the data line is connected to the data writing module 102 of the pixel circuit, and the connecting line with a solid dot indicates that the data line is connected to the bias module 103 of the pixel circuit.

[0139] For example, taking the columns containing the first pixel circuit 11 and the third pixel circuit 13 as an example, the first pixel circuit 11 can be located in an odd-numbered row, and the third pixel circuit 13 can be located in an even-numbered row. The data writing module 102 of the first pixel circuit 11 can be connected to the first data line 21 / data1, and the bias module 103 of the first pixel circuit 11 can be connected to the second data line 22 / data3. Similarly, the data writing module 102 of the third pixel circuit 13 can be connected to the second data line 22 / data3, and the bias module 103 of the third pixel circuit 13 can be connected to the first data line 21 / data1.

[0140] Similarly, taking the column containing the second pixel circuit 12 as an example, the data writing module 102 of the second pixel circuit 12 in odd-numbered rows can be connected to the first data line 21 / data2, and the biasing module 103 of the second pixel circuit 12 in odd-numbered rows can be connected to the second data line 22 / data4. The data writing module 102 of the second pixel circuit 12 in even-numbered rows can be connected to the second data line 22 / data4, and the biasing module 103 of the second pixel circuit 12 in even-numbered rows can be connected to the first data line 21 / data2.

[0141] For example, the data signal terminal Source is used to provide a data signal, and the bias signal terminal DVH is used to provide a bias signal. Each data line can be electrically connected to the data signal terminal Source and the bias signal terminal DVH. It can be understood that the data line is connected to the data signal terminal Source through a first gating circuit and to the bias signal terminal DVH through a second gating circuit.

[0142] In some embodiments, where the pixel circuit connects both the first data line and the second data line, and the pixel circuit includes a data writing module 102 and a bias module 103, such as Figure 9 As shown, during the display time of one frame, the operation of the pixel circuit includes a data writing stage, which includes a data writing sub-stage and a first bias sub-stage.

[0143] To facilitate the differentiation of sub-stages in different rows of pixel circuits, Figure 9 In the diagram, the data writing sub-stage d(m) and the first bias sub-stage p1(m) correspond to the m-th row of pixel circuits, the data writing sub-stage d(m+1) and the first bias sub-stage p1(m+1) correspond to the (m+1)-th row of pixel circuits, and the data writing sub-stage d(m+2) and the first bias sub-stage p1(m+2) correspond to the (m+2)-th row of pixel circuits, where m is an integer greater than 0.

[0144] During the data writing sub-stage, the data writing module 102 of the pixel circuit 10 is turned on, and the data signal on the data line can be written to the driving module 101.

[0145] In the first bias sub-stage, the bias module 103 of the pixel circuit 10 can be turned on, and the bias signal on the data line can be written into the driver module 101.

[0146] During the data writing phase, the control signals on the first control signal line mux1 and the second control signal line mux2 are sequentially at the on level.

[0147] As an example, such as Figure 9 As shown, for the same row of pixel circuits, the first bias sub-stage can occur after the data writing sub-stage. For example, for the m-th row of pixel circuits, its first bias sub-stage p1(m) follows the data writing sub-stage d(m). For the (m+1)-th row of pixel circuits, its first bias sub-stage p1(m+1) follows the data writing sub-stage d(m+1). For the (m+2)-th row of pixel circuits, its first bias sub-stage p1(m+2) follows the data writing sub-stage d(m+2).

[0148] The first bias sub-stage of the m-th row pixel circuit and the data writing sub-stage of the (m+2)-th row pixel circuit can at least partially overlap in time.

[0149] Please refer to the reference. Figure 8 , Figure 3 and Figure 9 For three adjacent rows of pixel circuits, the change process of the control signals on the first control signal mux1 and the second control signal line mux2 can include stages a1 to a6. The working process of the display panel can be as follows:

[0150] First, during at least a portion of stage a1, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the m-th row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the m-th row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0151] In the data writing sub-stage d(m), the scan line S2 connected to the m-th row pixel circuit is at the on level, the data writing module 102 of the m-th row pixel circuit is turned on, the data signal data R on the data line data1 is written to the driving module 101 of the first pixel circuit 11 in the m-th row, and the data signal data G on the data line data2 is written to the driving module 101 of the second pixel circuit 12 in the m-th row.

[0152] Next, during at least a portion of stage a2, the signal on the second control signal line mux2 is at the on level. At this time, the second switch T2 and the third switch T3 are simultaneously turned on. The data signal data B provided by the first data signal terminal Source1 to the pixel circuit located in the (m+1)th row can be transmitted to the data line data3 through the second switch T2. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (m+1)th row can be transmitted to the data line data4 through the second switch T2. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data1 and data2 respectively through the third switch T3.

[0153] In the data writing sub-stage d(m+1), the scan line S2 connected to the (m+1)th row pixel circuit is at the on level, the data writing module 102 of the (m+1)th row pixel circuit is turned on, the data signal data B on the data line data3 is written to the driving module 101 of the third pixel circuit 13 of the (m+1)th row, and the data signal data G on the data line data4 is written to the driving module 101 of the second pixel circuit 12 of the (m+1)th row.

[0154] Next, during at least a portion of stage a3, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the (m+2)th row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (m+2)th row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0155] In the data writing sub-stage d(m+2), the scan line S2 connected to the pixel circuit of the (m+2)th row is at the on level, the data writing module 102 of the pixel circuit of the (m+2)th row is turned on, the data signal data R on the data line data1 is written to the driving module 101 of the first pixel circuit 11 of the (m+2)th row, and the data signal data G on the data line data2 is written to the driving module 101 of the second pixel circuit 12 of the (m+2)th row.

[0156] The data writing sub-stage d(m+2) and the first bias sub-stage p1(m) can overlap.

[0157] In the first bias sub-stage p1(m), the scan line SP connected to the m-th row pixel circuit is at the on level, the bias module 103 of the m-th row pixel circuit is turned on, the bias signal on the data line data3 is written into the driving module 101 of the first pixel circuit 11 in the m-th row, and the bias signal on the data line data4 is written into the driving module 101 of the second pixel circuit 12 in the m-th row.

[0158] Next, during at least a portion of stage a4, the signal on the second control signal line mux2 is at the on level. At this time, the second switch T2 and the third switch T3 are simultaneously turned on. The data signal data B provided by the first data signal terminal Source1 to the pixel circuit located in the (m+3)th row can be transmitted to the data line data3 through the second switch T2. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (m+3)th row can be transmitted to the data line data4 through the second switch T2. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data1 and data2 respectively through the third switch T3.

[0159] In the first bias sub-stage p1(m+1), the scan line SP connected to the (m+1)th row pixel circuit is at the on level, the bias module 103 of the (m+1)th row pixel circuit is turned on, the bias signal on the data line data1 is written into the driving module 101 of the third pixel circuit 13 of the (m+1)th row, and the bias signal on the data line data2 is written into the driving module 101 of the second pixel circuit 12 of the (m+1)th row.

[0160] Next, during at least a portion of stage a5, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the (m+4)th row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (m+4)th row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0161] In the first bias sub-stage p1(m+2), the scan line SP connected to the (m+2)th row pixel circuit is at the on level, the bias module 103 of the (m+2)th row pixel circuit is turned on, the bias signal on the data line data3 is written into the driving module 101 of the first pixel circuit 11 in the (m+2)th row, and the bias signal on the data line data4 is written into the driving module 101 of the second pixel circuit 12 in the (m+2)th row.

[0162] And so on. For example, m takes the value 1.

[0163] Figure 9 The timing diagram only shows three rows of pixel circuits. It can be understood that the first bias sub-stage p1(m+1) of the (m+1)th row pixel circuit and the data writing sub-stage d(m+3) of the (m+3)th row pixel circuit can at least partially overlap in time.

[0164] As another example, such as Figure 5 As shown, for the same row of pixel circuits, the first bias sub-stage can precede the data writing sub-stage. For example, for the nth row of pixel circuits, its first bias sub-stage p1(n) precedes the data writing sub-stage d(n). For the (n+1)th row of pixel circuits, its first bias sub-stage p1(n+1) precedes the data writing sub-stage d(n+1). For the (n+2)th row of pixel circuits, its first bias sub-stage p1(n+2) precedes the data writing sub-stage d(n+2). n is an integer greater than 0.

[0165] The data writing sub-stage of the nth row pixel circuit and the first bias sub-stage of the (n+2)th row pixel circuit overlap at least partially in time.

[0166] Please refer to the reference. Figure 8 , Figure 3 and Figure 10 The operation of the display panel can be described as follows:

[0167] First, during at least a portion of stage a1, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the nth row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the nth row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0168] In the first bias sub-stage p1(n), the scan line SP connected to the nth row pixel circuit is at the on level, the bias module 103 of the nth row pixel circuit is turned on, the bias signal on the data line data3 is written into the driving module 101 of the first pixel circuit 11 in the nth row, and the bias signal on the data line data4 is written into the driving module 101 of the second pixel circuit 12 in the nth row.

[0169] Next, during at least a portion of stage a2, the signal on the second control signal line mux2 is at the on level. At this time, the second switch T2 and the third switch T3 are simultaneously turned on. The data signal data B provided by the first data signal terminal Source1 to the pixel circuit located in the (n+1)th row can be transmitted to the data line data3 through the second switch T2. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (n+1)th row can be transmitted to the data line data4 through the second switch T2. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data1 and data2 respectively through the third switch T3.

[0170] In the first bias sub-stage p1(n+1), the scan line SP connected to the (n+1)th row pixel circuit is at the on level, the bias module 103 of the (n+1)th row pixel circuit is turned on, the bias signal on the data line data1 is written into the driving module 101 of the (n+1)th row third pixel circuit 13, and the bias signal on the data line data2 is written into the driving module 101 of the (n+1)th row second pixel circuit 12.

[0171] Next, during at least a portion of stage a3, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the (n+2)th row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (n+2)th row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0172] In the first bias sub-stage p1(n+2), the scan line SP connected to the (n+2)th row pixel circuit is at the on level, the bias module 103 of the (n+2)th row pixel circuit is turned on, the bias signal on the data line data3 is written into the driving module 101 of the first pixel circuit 11 in the (n+2)th row, and the bias signal on the data line data4 is written into the driving module 101 of the second pixel circuit 12 in the (n+2)th row.

[0173] The data writing sub-stage d(n) and the first bias sub-stage p1(n+2) can overlap.

[0174] In the data writing sub-stage d(n), the scan line S2 connected to the nth row pixel circuit is at the on level, the data writing module 102 of the nth row pixel circuit is turned on, the data signal data R on the data line data1 is written to the driving module 101 of the first pixel circuit 11 in the nth row, and the data signal data G on the data line data2 is written to the driving module 101 of the second pixel circuit 12 in the nth row.

[0175] Next, during at least a portion of stage a4, the signal on the second control signal line mux2 is at the on level. At this time, the second switch T2 and the third switch T3 are simultaneously turned on. The data signal data B provided by the first data signal terminal Source1 to the pixel circuit located in the (n+3)th row can be transmitted to the data line data3 through the second switch T2. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (n+3)th row can be transmitted to the data line data4 through the second switch T2. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data1 and data2 respectively through the third switch T3.

[0176] In the data writing sub-stage d(n+1), the scan line S2 connected to the n+1th row pixel circuit is at the on level, the data writing module 102 of the n+1th row pixel circuit is turned on, the data signal data B on the data line data3 is written to the driving module 101 of the third pixel circuit 13 of the n+1th row, and the data signal data G on the data line data4 is written to the driving module 101 of the second pixel circuit 12 of the n+1th row.

[0177] Next, during at least a portion of stage a5, the signal on the first control signal line mux1 is at the on level. At this time, the first switch T1 and the fourth switch T4 are simultaneously turned on. The data signal data R provided by the first data signal terminal Source1 to the pixel circuit located in the (n+4)th row can be transmitted to the data line data1 through the first switch T1. The data signal data G provided by the second data signal terminal Source2 to the pixel circuit located in the (n+4)th row can be transmitted to the data line data2 through the first switch T1. The bias signal provided by the bias signal terminal DVH can be transmitted to the data lines data3 and data4 through the fourth switch T4, respectively.

[0178] In the data writing sub-stage d(n+2), the scan line S2 connected to the n+2nd row pixel circuit is at the on level, the data writing module 102 of the n+2nd row pixel circuit is turned on, the data signal data R on the data line data1 is written to the driving module 101 of the first pixel circuit 11 in the n+2nd row, and the data signal data G on the data line data2 is written to the driving module 101 of the second pixel circuit 12 in the n+2nd row.

[0179] And so on. For example, n can take the value 1.

[0180] Figure 10 The timing diagram only shows three rows of pixel circuits. It can be understood that the data writing sub-stage d(n+1) of the (n+1)th row of pixel circuits and the first bias sub-stage p1(n+3) of the (n+3)th row of pixel circuits overlap at least partially in time.

[0181] Figure 9 or Figure 10 In the illustrated embodiment, the data signal and bias signal can be transmitted to the driver module using two data lines.

[0182] In some embodiments, the data line may no longer be connected to the data signal terminal via a gating circuit. For example... Figure 11 As shown, the two data lines 20 connected to the pixel circuit column 10a include a first data line 21 and a second data line 22.

[0183] The pixel circuits in the odd-numbered rows of pixel circuit column 10a are connected to the first data line 21, and the pixel circuits in the even-numbered rows of pixel circuit column 10a are connected to the second data line 22.

[0184] The first data line 21 and the second data line 22 are connected to different data signal terminals Source of the display panel. The data signal terminals Source can be used to provide data signals and bias signals in a time-division manner.

[0185] In this embodiment, a gating circuit is not required, which facilitates the achievement of a narrow bezel. Furthermore, the data signal terminal Source can be used to provide data and bias signals in a time-division multiplexing manner, reducing the number of signal ports on the driver chip and thus lowering chip costs.

[0186] For example, in two adjacent pixel circuit columns 10a, one pixel circuit column 10a can be connected to the first data signal terminal Source1 via the first data line 21, and can be connected to the second data signal terminal Source2 via the second data line 22. The other pixel circuit column 10a can be connected to the third data signal terminal Source3 via the first data line 21, and can be connected to the fourth data signal terminal Source4 via the second data line 22.

[0187] In some embodiments, where the pixel circuit is connected to one of the first data line and the second data line, different functional modules can be used to transmit the data signal and the bias signal respectively. For example... Figure 3 As shown, the pixel circuit 10 may include a driving module 101, a data writing module 102, and a bias module 103. The data writing module 102 is used to transmit data signals to the driving module 101, and the bias module 103 is used to transmit bias signals to the driving module 101.

[0188] Please refer to Figure 11 and Figure 3 When the pixel circuit is connected to one of the first data line and the second data line, the data writing module 102 and the bias module 103 of the pixel circuit 10 in the odd-numbered rows of the pixel circuit 10 in the pixel circuit column 10a can be connected to the first data line 21, and the data writing module 102 and the bias module 103 of the pixel circuit 10 in the even-numbered rows of the pixel circuit 10 in the pixel circuit column 10a can be connected to the second data line 22.

[0189] In this embodiment, even without the need for a gating circuit, the data writing module 102 can provide data signals to the driving module 101, and the bias module 103 can provide bias signals to the driving module 101, which can easily avoid crosstalk between different signals. Furthermore, the data writing module 102 and the bias module 103 of the same pixel circuit are connected to the same data line, which is beneficial for efficient use of the data line.

[0190] In some embodiments, where no gating circuit is required, the pixel circuit is connected to one of the first data line and the second data line, and the pixel circuit includes a data writing module 102 and a bias module 103, please refer to... Figure 12 During the display time of one frame, the operation of the pixel circuit may include a data writing stage, which may include a data writing sub-stage and a first bias sub-stage.

[0191] During the data writing sub-stage, the data writing module 102 of the pixel circuit 10 is turned on, and the data signal on the data line can be written to the driving module 101.

[0192] In the first bias sub-stage, the bias module 103 of the pixel circuit 10 can be turned on, and the bias signal on the data line can be written into the driver module 101.

[0193] As an example, such as Figure 12 As shown, for the same row of pixel circuits, the first bias sub-stage can be after the data writing sub-stage.

[0194] As another example, such as Figure 13 As shown, for the same row of pixel circuits, the first bias sub-stage can be performed before the data writing sub-stage.

[0195] Figure 12 and Figure 4 Similarities, and Figure 13 and Figure 5 The similarities will not be repeated here; the differences are... Figure 12 and Figure 13 Both the data signal and the bias signal are provided by the data signal terminal.

[0196] in:

[0197] In stage a1, the first data signal terminal Source1 provides the data signal data R, the second data signal terminal Source2 provides the data signal data G, and the third data signal terminal Source3 and the fourth data signal terminal Source4 both provide the bias signal DVH.

[0198] In stage a2, the first data signal terminal Source1 and the second data signal terminal Source2 both provide the bias signal DVH, the third data signal terminal Source3 provides the data signal data B, and the fourth data signal terminal Source4 provides the bias signal DVH.

[0199] In stage a3, the signals provided by each data signal terminal are the same as in stage a1.

[0200] In stage a4, the signals provided by each data signal terminal are the same as in stage a2.

[0201] In some embodiments, without the need for a gating circuit, the same functional module can be used to transmit data signals and bias signals in a time-division manner. For example... Figure 6 As shown, the pixel circuit 10 may include a driving module 101 and a data writing module 102. The data writing module 102 is used to transmit data signals and bias signals to the driving module 101 in a time-division multiplexing manner.

[0202] Please refer to Figure 11 and Figure 6 When the pixel circuit is connected to one of the first data line and the second data line, the data writing module 102 of the odd-numbered row pixel circuit 10 in the pixel circuit column 101a can be connected to the first data line 21, and the data writing module 102 of the even-numbered row pixel circuit 10 in the pixel circuit column 10a can be connected to the second data line 22.

[0203] In this embodiment, without the need for a gating circuit, the data writing module 102 transmits data signals and bias signals to the driving module 101 in a time-division manner, which can reduce the number of functional modules in the pixel circuit and improve the resolution of the display panel.

[0204] In some embodiments, where a gating circuit is provided and the pixel circuit's data writing module 102 is used for time-division multiplexing of data signals and bias signals, please refer to... Figure 14 During the display time of one frame, the operation of the pixel circuit includes a data writing stage, which includes a data writing sub-stage and a first bias sub-stage.

[0205] In the data writing sub-stage, the pixel circuit driving module 101 writes the data signal, and in the first bias sub-stage, the pixel circuit driving module 101 writes the bias signal.

[0206] For example, the pixel circuit may also include a threshold compensation module 104. The threshold compensation module 104 can be turned on or off under the control of the scan line S2, and the data writing module 102 can be turned on or off under the control of the scan line S3.

[0207] During the data writing sub-stage, both the data writing module 102 and the threshold compensation module 104 of the pixel circuit can be turned on, and the data signal can be written to the control terminal of the driving module 101. During the first bias sub-stage, the threshold compensation module 104 is turned off, the data writing module 102 is turned on, and the bias signal can be written to the source or drain of the driving transistor M3 of the driving module 101.

[0208] As an example, such as Figure 14 As shown, for the same row of pixel circuits, the first bias sub-stage can be after the data writing sub-stage. For example, for the k-th row of pixel circuits, its first bias sub-stage p1(k) is after the data writing sub-stage d(k). For the (k+1)-th row of pixel circuits, its first bias sub-stage p1(k+1) is after the data writing sub-stage d(k+1).

[0209] The first bias sub-stage p1(k) of the k-th row pixel circuit and the data writing sub-stage d(k+1) of the (k+1)-th row pixel circuit can at least partially overlap in time.

[0210] Figure 14 and Figure 7 The similarities will not be repeated here; the differences are... Figure 14 Both the data signal and the bias signal are provided by the data signal terminal. Specifically:

[0211] In stage a1, the first data signal terminal Source1 provides the data signal data R, the second data signal terminal Source2 provides the data signal data G, and the third data signal terminal Source3 and the fourth data signal terminal Source4 both provide the bias signal DVH.

[0212] In stage a2, the first data signal terminal Source1 and the second data signal terminal Source2 both provide the bias signal DVH, the third data signal terminal Source3 provides the data signal data B, and the fourth data signal terminal Source4 provides the bias signal DVH.

[0213] In stage a3, the signals provided by each data signal terminal are the same as in stage a1.

[0214] In stage a4, the signals provided by each data signal terminal are the same as in stage a2.

[0215] In some embodiments, the display panel provided in this application may also support a low refresh rate operating mode. For example... Figure 15 As shown, the operation of the pixel circuit may also include a holding phase. During the writing phase, the data signal is written to the control terminal of the driver module. During the holding phase, the data signal is no longer written to the control terminal of the driver module. During the holding phase, the potential of the control terminal of the driver module is maintained at the same level as during the writing phase.

[0216] The holding phase may include at least one second bias sub-phase, in which the pixel circuit driving module 101 writes a bias signal, and the data signal terminal Source connected to the data line 20 is either floating or used to provide the bias signal.

[0217] To facilitate the differentiation of sub-stages in different rows of pixel circuits, Figure 15 In the diagram, the second bias sub-stage p2(i) corresponds to the pixel circuit in the i-th row, and the second bias sub-stage p2(i+1) corresponds to the pixel circuit in the (i+1)-th row.

[0218] In this embodiment, the data line can maintain a bias signal during the holding phase to prevent short circuits.

[0219] For example, in a display panel that includes both data signal terminals and bias signal terminals, during the writing phase, the data signal terminals provide data signals, and the bias signal terminals provide bias signals. During the holding phase, the data signal terminals can be either floating or used to provide bias signals.

[0220] For example, in the case where the data signal terminal of the display panel is used to provide data signals and bias signals in a time-division manner, during the writing phase, the data signal terminal can provide data signals and bias signals in a time-division manner, and during the holding phase, the data signal terminal can continuously provide bias signals.

[0221] It should be noted that, Figure 15The display panel includes a gating circuit, and the pixel circuit includes a data writing module and a bias module. Scan line S2 controls the data writing module, and scan line SP controls the bias module. The first sub-biasing stage occurs after the data writing sub-stage, but this is not intended to limit the scope of this application. It is understood that even without a gating circuit, or when the pixel circuit's data writing module transmits data and bias signals in a time-division multiplexing manner, the pixel circuit's operation may still include a holding stage, which may include at least one second bias sub-stage.

[0222] It should be noted that, in Figure 2 and Figure 11 In the example shown, data line data1 is connected to the first pixel circuit 11 and data line data3 is connected to the third pixel circuit 13. This is not intended to limit the scope of this application. For example, in other examples, data line data1 may be connected to the third pixel circuit 13 and data line data3 may be connected to the first pixel circuit 11.

[0223] exist Figure 8 In the example shown, data line data1 is connected to the data writing module of the first pixel circuit 11 and the bias module of the third pixel circuit 13, and data line data3 is connected to the data writing module of the third pixel circuit 13 and the bias module of the first pixel circuit 11. This is not intended to limit this application. For example, in other examples, data line data1 may be connected to the data writing module of the third pixel circuit 13 and the bias module of the first pixel circuit 11, and data line data3 may be connected to both the data writing module of the first pixel circuit 11 and the bias module of the third pixel circuit 13.

[0224] For example, such as Figure 16 As shown, the display panel may include a display area AA and a non-display area at least partially surrounding the display area AA. The non-display area may include a first non-display area NA1 and a second non-display area NA2 opposite to each other in the column direction Y, with the first non-display area NA1 and the second non-display area NA2 spaced apart from the display area AA. The first non-display area NA1 includes a bonding area BA, which can be used to bond a driver chip.

[0225] As described above, the display panel includes a first gating circuit 31 and a second gating circuit 32.

[0226] As an example, the first gating circuit 31 and the second gating circuit 32 can be set in the first non-display area NA1.

[0227] As another example, one of the first gating circuit 31 and the second gating circuit 32 may be located in the first non-display area NA1, and the other may be located in the second non-display area NA2. For example, the first gating circuit 31 may be located in the first non-display area NA1, and the second gating circuit 32 may be located in the second non-display area NA2.

[0228] For example, such as Figure 3 or Figure 6 As shown, the pixel circuit 10 is connected to the light-emitting element 40. The light-emitting element 40 can be an organic light-emitting diode (OLED).

[0229] For example, the pixel circuit 10 may also include a threshold compensation module 104, a first reset module 105, an emissivity control module 106, a second reset module 107, and a storage capacitor Cst.

[0230] The light emission control module 106 may include transistors M1 and M6, the data writing module 102 may include transistor M2, the driving module 101 may include transistor M3, the threshold compensation module 104 may include transistor M4, the first reset module 105 may include transistor M5, and the second reset module 107 may include transistor M7. If the pixel circuit includes a bias module 103, the bias module 103 may include transistor M8. Additionally, Figure 7 In the diagram, Vref1 represents the first reset signal, Vref2 represents the second reset signal, Emit represents the light emission control signal, PVDD represents the positive power supply signal, and PVEE represents the negative power supply signal. The first reset signal Vref1 can be used to reset the gate of the driving transistor M3, and the second reset signal Vref2 can be used to reset the anode of the light-emitting element 40. The light emission control signal Emit can be used to control the pixel circuit to enter the light emission stage. For the connection relationships of the components in the pixel circuit, see [reference needed]. Figure 3 or Figure 6 This will not be elaborated upon here.

[0231] It should be noted that the signals on scan line S1 are not shown in the timing diagrams provided in the embodiments of this application. It is understood that, for the same row of pixel circuits, the off-level duration of the Emit control signal should cover the on-level duration of scan line S1. For example, using... Figure 3 For example, the conduction level of scan line S1 can precede the conduction level of scan line S2. For the same row of pixel circuits, during the data writing stage, the duration of the cutoff level of the light emission control signal Emit should cover the duration of the conduction level of scan line S1, the duration of the conduction level of scan line S2, and the duration of the conduction level of scan line SP.

[0232] Based on the same inventive concept, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 17 , Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 17 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 17 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0233] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, It includes multiple pixel circuit columns, one of the pixel circuit columns is electrically connected to two data lines, and one of the data lines transmits data signals and bias signals to the pixel circuits in the pixel circuit column in a time-division manner. The two data lines connected to the pixel circuit column include a first data line and a second data line; The display panel further includes a first gating circuit and a second gating circuit. The first gating circuit includes a first switch and a second switch. The first end of the first switch and the first end of the second switch are both connected to the data signal terminal. The second end of the first switch is connected to the first data line, and the second end of the second switch is connected to the second data line. The second gating circuit includes a third switch and a fourth switch. The first end of the third switch and the first end of the fourth switch are both connected to the bias signal terminal. The second end of the third switch is connected to the first data line, and the second end of the fourth switch is connected to the second data line. The first switch and the fourth switch are simultaneously turned on or off under the control of the first control signal line, and the second switch and the third switch are simultaneously turned on or off under the control of the second control signal line. The first switch and the second switch are turned on or off sequentially under the control of the first control signal line and the second control signal line, respectively; The pixel circuits in the odd-numbered rows of the pixel circuit column are connected to the first data line, and the pixel circuits in the even-numbered rows of the pixel circuit column are connected to the second data line.

2. The display panel according to claim 1, characterized in that, Two adjacent pixel circuit columns are connected to different data signal terminals via the data line, and the data signal terminals are used to provide the data signal.

3. The display panel according to claim 1, characterized in that, The two data lines connected to the pixel circuit column include a first data line and a second data line, and the data signal and the bias signal are different signal types. At the same time, the first data line and the second data line connected to the same pixel circuit column transmit different signal types, the first data line connected to two adjacent pixel circuit columns transmits the same signal type, and the second data line connected to two adjacent pixel circuit columns transmits the same signal type.

4. The display panel according to claim 1, characterized in that, The pixel circuit includes a driving module, a data writing module, and a bias module. The data writing module is used to transmit the data signal to the driving module, and the bias module is used to transmit the bias signal to the driving module. In the pixel circuit column, the data writing module and the bias module of the pixel circuit in the odd-numbered rows are all connected to the first data line, and the data writing module and the bias module of the pixel circuit in the even-numbered rows are all connected to the second data line.

5. The display panel according to claim 4, characterized in that, During the display time of one frame, the operation of the pixel circuit includes a data writing stage, which includes a data writing sub-stage and a first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal, and in the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. During the data writing phase, the control signals on the first control signal line and the second control signal line are sequentially at the on level; Wherein, the first bias sub-stage is after the data writing sub-stage, and the first bias sub-stage of the pixel circuit in the i-th row and the data writing sub-stage of the pixel circuit in the (i+1)-th row overlap at least partially in time; Alternatively, before the first bias sub-stage, the data writing sub-stage of the pixel circuit in row j and the first bias sub-stage of the pixel circuit in row j+1 overlap at least partially in time. Both i and j are integers greater than 0.

6. The display panel according to claim 4, characterized in that, The pixel circuit includes a driving module and a data writing module. The data writing module is used to transmit the data signal and the bias signal to the driving module in a time-division manner. The data writing module of the pixel circuit in the odd-numbered row of the pixel circuit column is connected to the first data line, and the data writing module of the pixel circuit in the even-numbered row of the pixel circuit column is connected to the second data line.

7. The display panel according to claim 6, characterized in that, During the display time of one frame, the operation of the pixel circuit includes a data writing stage, which includes a data writing sub-stage and a first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal, and in the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. During the data writing phase, the control signals on the first control signal line and the second control signal line are sequentially at the on level; Wherein, the first bias sub-stage is after the data writing sub-stage, and the first bias sub-stage of the pixel circuit in the k-th row and the data writing sub-stage of the pixel circuit in the (k+1)-th row overlap at least partially in time. k is an integer greater than 0.

8. A display panel, characterized in that, It includes multiple pixel circuit columns, one of the pixel circuit columns is electrically connected to two data lines, and one of the data lines transmits data signals and bias signals to the pixel circuits in the pixel circuit column in a time-division manner. The two data lines connected to the pixel circuit column include a first data line and a second data line; The display panel further includes a first gating circuit and a second gating circuit. The first gating circuit includes a first switch and a second switch. The first end of the first switch and the first end of the second switch are both connected to the data signal terminal. The second end of the first switch is connected to the first data line, and the second end of the second switch is connected to the second data line. The second gating circuit includes a third switch and a fourth switch. The first end of the third switch and the first end of the fourth switch are both connected to the bias signal terminal. The second end of the third switch is connected to the first data line, and the second end of the fourth switch is connected to the second data line. The first switch and the fourth switch are simultaneously turned on or off under the control of the first control signal line, and the second switch and the third switch are simultaneously turned on or off under the control of the second control signal line. The first switch and the second switch are turned on or off sequentially under the control of the first control signal line and the second control signal line, respectively; The two data lines electrically connected to the pixel circuit column include a first data line and a second data line. Each pixel circuit in the pixel circuit array is electrically connected to the first data line and the second data line; The pixel circuit includes a driving module, a data writing module, and a bias module. The data writing module is used to transmit the data signal to the driving module, and the bias module is used to transmit the bias signal to the driving module. The data writing module of the pixel circuit in the odd-numbered row of the pixel circuit column is connected to the first data line, and the bias module of the pixel circuit in the odd-numbered row of the pixel circuit column is connected to the second data line. The data writing module of the pixel circuit in the even-numbered row of the pixel circuit column is connected to the second data line, and the bias module of the pixel circuit in the even-numbered row of the pixel circuit column is connected to the first data line. During the display time of one frame, the operation of the pixel circuit includes a data writing stage, which includes a data writing sub-stage and a first bias sub-stage. In the data writing sub-stage, the driving module of the pixel circuit writes the data signal, and in the first bias sub-stage, the driving module of the pixel circuit writes the bias signal. During the data writing phase, the control signals on the first control signal line and the second control signal line are sequentially at the on level; Wherein, the first bias sub-stage is after the data writing sub-stage, and the first bias sub-stage of the pixel circuit in the m-th row and the data writing sub-stage of the pixel circuit in the (m+2)-th row overlap at least partially in time; Alternatively, before the first bias sub-stage, the data writing sub-stage of the pixel circuit in the nth row and the first bias sub-stage of the pixel circuit in the (n+2)th row overlap at least partially in time. Both m and n are integers greater than 0.

9. The display panel according to claim 1 or 8, characterized in that, The operation of the pixel circuit in the pixel circuit array also includes a holding phase, which includes at least one second bias sub-phase. In the second bias sub-phase, the driving module of the pixel circuit writes the bias signal, and the data signal terminal connected to the data line is either in a floating state or used to provide the bias signal.

10. A display device comprising a display panel according to any one of claims 1 to 9.

Images