Electronic package and method of making the same

Abstract

An electronic package and a method of manufacturing the same, including covering a plurality of field effect transistors (FETs) and conductive pillars with a package body, forming fan-out conductors in the package body to electrically connect the FETs, and electrically connecting the conductive pillars and the fan-out conductors with lines of a line structure, so that the package direction of the FETs can be arbitrarily designed, thereby increasing the flexibility of design or configuration.

Description

Technical Field

[0001] This invention relates to an electronic packaging structure, and more particularly to an electronic package containing multiple field-effect transistors (FETs) and its manufacturing method. Background Technology

[0002] With the development of the electronics industry, today's electronic products are trending towards thinner, smaller, and more functional designs, and semiconductor packaging technology has also developed different packaging forms accordingly.

[0003] Currently, if the function of a semiconductor chip is a vertically connected upper and lower signal series configuration, such as a field-effect transistor (FET) or diode, a conductive frame is used as the carrier.

[0004] like Figure 1 As shown, the existing package structure 1 includes: a clip 14 made of copper, a leadframe 15, and a semiconductor chip 10. The leadframe 15 includes a separate die pad 151 and at least one lead 152. The lower electrode region 101 of the semiconductor chip 10 is disposed on the die pad 151 by solder 11, and the upper electrode region 102 of the semiconductor chip 10 is connected to the clip 14 by solder 12, so that one side of the clip 14 is connected to the lead 152 by solder 13.

[0005] However, the existing packaging structure 1 has the following drawbacks:

[0006] First, since the lower electrode region 101 of the semiconductor chip 10 is disposed on the die pad 151 through the solder material 11, the solder material 11 is prone to overflow during reflow of the solder material 11 because there is no restricted flow area on the die pad 151.

[0007] Secondly, in order to prevent the lead frame 15 from warping, the lead frame 15 needs to have a certain thickness h, which makes it difficult to thin the packaging structure 1.

[0008] Third, after a large current passes through the upper electrode region 102 of the semiconductor chip 10, the solder material 12 is prone to cracking, resulting in poor electrical properties of the package structure 1.

[0009] Fourth, both sides of the lead frame 14 are connected by solder material 12, 13. Therefore, during the reflow of the solder material 12, 13, the lead frame 14 is prone to displacement, which can cause accuracy deviation.

[0010] Therefore, the industry has developed a method that eliminates the need for conductor frames, such as TWI682513, to overcome the above problems.

[0011] However, the package structure disclosed in TWI682513 requires the conductive adhesive (as indicated by reference numeral 23 in its specification) to electrically connect the field-effect transistors (as indicated by reference numerals 24, 24 in its specification) and the circuit layer (as indicated by reference numeral 22 in its specification) through conductive adhesive (as indicated by reference numeral 23 in its specification). Therefore, when these field-effect transistors are placed, they will squeeze the conductive adhesive, causing the conductive adhesive to overflow to all sides, making it easy for adjacent conductive adhesives to connect, thus causing a problem of poor electrical performance due to bridging and short circuit.

[0012] Therefore, overcoming the various problems of the existing technologies has become a pressing issue that the industry urgently needs to address. Summary of the Invention

[0013] In view of the deficiencies in the prior art, the present invention provides an electronic package and its manufacturing method, which can at least partially solve the problems in the prior art.

[0014] The electronic package of the present invention includes: a package body composed of an insulating material having a first surface and a second surface opposite to each other; a circuit structure attached to the package body, comprising a first circuit corresponding to the first surface of the package body and a second circuit corresponding to the second surface of the package body, wherein the first circuit can be electrically connected to a circuit board via a plurality of conductive elements; a plurality of field-effect transistors, which are horizontally embedded in the package body between the first circuit and the second circuit, wherein the field-effect transistors have a first working surface opposite to each other. The second working surface includes a plurality of fan-out conductors on both the first and second working surfaces to electrically connect the first and second lines respectively; and at least one conductive post embedded in the package, wherein the conductive post has a first conductive portion and a second conductive portion, wherein the second conductive portion is cylindrical, and one end of the second conductive portion is electrically connected to the first line, while the first conductive portion is a short conical column, such that the large end face of the first conductive portion is combined with the other end of the second conductive portion, and the small end face of the first conductive portion is electrically connected to the second line.

[0015] The present invention also provides a method for manufacturing an electronic package, comprising: providing a substrate having a metal surface; forming an insulating adhesive layer on the substrate; disposing a plurality of field-effect transistors on the insulating adhesive layer, the field-effect transistors having a first working surface and a second working surface opposite to each other; forming at least one first blind hole on the insulating adhesive layer by laser method to expose a portion of the metal surface of the substrate; electroplating a first conductive portion in the first blind hole in a tapered short column shape by exposure and development method, and then electroplating a second conductive portion in a column shape on the large end face of the first conductive portion to combine the first conductive portion and the second conductive portion to form a conductive column; forming a first insulating layer. A layer is applied to the insulating adhesive layer to cover the plurality of field-effect transistors, the conductive pillar, and the surface of the insulating adhesive layer; a leveling operation is performed to remove part of the first insulating layer and expose one end face of the second conductive portion of the conductive pillar; a plurality of second blind holes are formed on the first insulating layer by laser to expose the first and / or second working surfaces of the plurality of field-effect transistors; a first fan-out conductor is formed by electroplating in the second blind holes by exposure and development method, and a first line is formed by electroplating on the end face of the first fan-out conductor, the exposed end face of the conductive pillar, and the surface of the first insulating layer to electrically connect the first fan-out conductor and the conductive pillar; A second insulating layer is formed on the first insulating layer to cover the first circuit and the surface of the first insulating layer; another leveling operation is performed, removing a portion of the second insulating layer to expose a portion of the first circuit as an electrical connection pad; the substrate and the insulating adhesive layer are removed to expose the first and / or second functional surfaces of the plurality of field-effect transistors, the first conductive portion of the conductive pillar, and the surface of the first insulating layer; a third insulating layer is formed on the exposed surface of the first insulating layer to cover the first and / or second functional surfaces of the plurality of field-effect transistors, the first conductive portion of the conductive pillar, and the exposed surface of the first insulating layer; a leveling operation is then performed. The process involves removing a portion of the third insulating layer to expose the small end face of the first conductive portion of the conductive pillar; forming a plurality of third blind vias on the third insulating layer using a laser to expose the first and / or second working surfaces of the plurality of field-effect transistors; electroplating a second fan-out conductor in the third blind vias using an exposure and development method; then electroplating a second circuit on the end face of the second fan-out conductor, the small end face of the first conductive portion of the conductive pillar, and the surface of the third insulating layer to electrically connect the second fan-out conductor and the conductive pillar; and forming a fourth insulating layer on the third insulating layer to cover the second circuit and the surface of the third insulating layer.

[0016] In a specific embodiment of the aforementioned electronic package and its manufacturing method, the first fan-out conductor is in the shape of a short conical column, and the small end face of the first fan-out conductor is electrically connected to the first working surface and / or the second working surface of the plurality of field-effect transistors, while the large end face of the first fan-out conductor is electrically connected to the first circuit.

[0017] In a specific embodiment of the aforementioned electronic package and its manufacturing method, the second fan-out conductor is in the shape of a short conical column, and the small end face of the second fan-out conductor is electrically connected to the first and / or second working surfaces of the plurality of field-effect transistors, while the large end face of the second fan-out conductor is electrically connected to the second circuit.

[0018] In one specific embodiment of the aforementioned electronic package and its manufacturing method, the plurality of field-effect transistors are disposed on the insulating adhesive layer with the same orientation.

[0019] In one specific embodiment of the aforementioned electronic package and its manufacturing method, the plurality of field-effect transistors are disposed on the insulating adhesive layer with different orientations.

[0020] In one specific embodiment of the aforementioned electronic package and its manufacturing method, a plurality of openings are formed on the surface of the fourth insulating layer by laser, with the exposed portion of the second line serving as an electrical connection pad for flip-chip bonding of a semiconductor chip.

[0021] As can be seen from the above, the electronic package and its manufacturing method of the present invention utilize a large-size package specification at the board level combined with laser drilling technology, electroplated fan-out conductors and conductive pillars to form an effective circuit for each electrode of the multiple field-effect transistors, thereby forming the electronic package. Therefore, the present invention has the following advantages:

[0022] First, compared with existing leadframes and pinframes, the present invention can effectively control the thickness of the package through the packaging process, which is conducive to the miniaturization of the electronic package.

[0023] Secondly, compared to the use of existing solder materials, the present invention uses the fan-out conductor and the conductive post as the electrical connection structure, without the need for solder materials, thus avoiding the quality problem of solder material overflow.

[0024] Third, compared to the use of existing solder materials, the present invention uses the fan-out conductor and the conductive post as the electrical connection structure, without the need for solder materials, thus overcoming the quality problem of gate breakage caused by high current products.

[0025] Fourth, compared with the existing pinout configuration, the present invention embeds the multiple field-effect transistors in the package and then electrically connects the multiple field-effect transistors with the fan-out conductor to avoid displacement of the fan-out conductor, thus avoiding the existing accuracy deviation problem.

[0026] Fifth, through the configuration of the first and second lines, the signals between each field-effect transistor can be interconnected, and the orientation of the chip package can be arbitrarily designed.

[0027] Sixth, compared to the packaging structure disclosed in TWI682513, the present invention forms the second fan-out conductor in these third blind holes without the need for conductive adhesive, thus avoiding electrical defects caused by conductive adhesive overflow. Attached Figure Description

[0028] Figure 1 This is a cross-sectional schematic diagram of the existing packaging structure.

[0029] Figures 2A to 2H This is a cross-sectional schematic diagram illustrating the manufacturing method of the electronic package of the present invention.

[0030] Figure 3A and Figure 3B for Figure 2H Cross-sectional schematic diagrams of different embodiments of subsequent processes.

[0031] Figure 4 This is a cross-sectional schematic diagram of another method for manufacturing the electronic package of the present invention.

[0032] Explanation of key component symbols:

[0033] 1. Packaging Structure

[0034] 10 Semiconductor chips

[0035] 101 Lower electrode region

[0036] 102 Upper electrode region

[0037] 11, 12, 13, 310 solder materials

[0038] 14-pin bracket

[0039] 15 Conductor frame

[0040] 151 Crystal Pad

[0041] 152 guide pins

[0042] 2 Electronic Packages

[0043] 20,40 field-effect transistors

[0044] 20a, 40a first working surface

[0045] 20b, 40b Second Working Surface

[0046] 201 First electrode pad

[0047] 202 Second electrode pad

[0048] 21 Insulating adhesive layer

[0049] 21a Third Insulation Layer

[0050] 210 First blind hole

[0051] 210a First Hole End

[0052] 210b Second Hole End

[0053] 22 First Insulation Layer

[0054] 220 Second blind hole

[0055] 23 Package

[0056] 23a First Surface

[0057] 23b Second Surface

[0058] 230 Third blind hole

[0059] 24 First Route

[0060] 240 First Fan-Out Conductor

[0061] 240a Small end face

[0062] 240b Large end face

[0063] 25 Second Insulation Layer

[0064] 26 conductive pillars

[0065] 26a First end face

[0066] 26b Second end face

[0067] 260 First conductive part

[0068] 261 Second conductive part

[0069] 27 Second Fan-Out Conductor

[0070] 27a Large end face

[0071] 27b Small end face

[0072] 270 Second Line

[0073] 28. Add-on structure

[0074] 280 column wiring

[0075] 281 Dielectric layer

[0076] 29 Fourth Insulation Layer

[0077] 290 Opening

[0078] 30 circuit boards

[0079] 31 Semiconductor Chips

[0080] 300 conductive elements

[0081] 9 substrate

[0082] 9a Metal surface

[0083] h thickness

[0084] d1, d2 aperture

[0085] S large end face

[0086] Widths w1, w2, R2 Detailed Implementation

[0087] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and technical effects of the present invention from the content disclosed in this specification.

[0088] It should be understood that the structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for illustrative purposes and to facilitate understanding and reading by those skilled in the art. They are not intended to limit the conditions under which the invention can be implemented and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the technical effects and objectives achieved by the invention, should still fall within the scope of the technical content disclosed in this invention. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0089] Figures 2A to 2H This is a cross-sectional schematic diagram of the manufacturing method of the electronic package 2 of the present invention.

[0090] like Figure 2A As shown, a substrate 9 with a metal surface 9a is provided, and an insulating adhesive layer 21 is formed on the metal surface 9a of the substrate 9, and a plurality of field-effect transistors 20 arranged at intervals are disposed on the insulating adhesive layer 21.

[0091] In this embodiment, the substrate 9 may be a copper foil substrate.

[0092] Furthermore, the field-effect transistor 20, such as a metal-oxide-semiconductor field-effect transistor (FET), functions as a vertically coupled upper and lower signal series connection. For example, the FET 20 has a first working surface 20a and a second working surface 20b, the first working surface 20a having at least one first electrode pad 201, and the second working surface 20b having at least one second electrode pad 202, and is bonded to the insulating adhesive layer 21 via the second working surface 20b.

[0093] Furthermore, the three pins (or electrodes) of the field-effect transistor 20, namely the gate (G), drain (D), and source (S), can be configured on the first operating surface 20a and the second operating surface 20b as needed. For example, the electrodes of the two field-effect transistors 20 can be configured as needed, as shown in the following table:

[0094]

[0095]

[0096]

[0097]

[0098]

[0099] It should be understood that there are many different configurations of the electrodes of the multiple field-effect transistors 20, and they are not limited to those described above.

[0100] Furthermore, the plurality of field-effect transistors 20 are disposed on the insulating adhesive layer 21 with the same orientation (i.e., the orientation of the first active surface 20a and the second active surface 20b). Or, as Figure 4 As shown, the orientations of the plurality of field-effect transistors 20, 40 on the insulating adhesive layer 21 (i.e., the orientations of the first working surfaces 20a, 40a and the second working surfaces 20b, 40b) may be different.

[0101] like Figure 2B As shown, at least one first blind hole 210 is formed on the insulating adhesive layer 21 by laser to expose a portion of the metal surface 9a of the substrate 9. The first blind hole 210 has a first hole end 210a and a second hole end 210b. The first hole end 210a communicates with the carrier 9. The diameter d1 of the first hole end 210a is smaller than the diameter d2 of the second hole end 210b, so that the first blind hole 210 has an "inverted cone" shape.

[0102] like Figure 2C As shown, a first conductive portion 260 in the shape of a short, conical column is formed by electroplating in the first blind hole using an exposure and development method. Then, a second conductive portion 261 in the shape of a column is formed by electroplating on the large end face S of the first conductive portion 260. The first conductive portion 260 and the second conductive portion 261 are combined to form a conductive column 26, and the conductive column 26 protrudes from the insulating adhesive layer 21.

[0103] In this embodiment, the conductive post 26 has a first end face 26a and a second end face 26b. The first end face 26a is located on the side of the first hole end 210a of the first blind hole 210 to connect with the metal surface 9a of the substrate 9, and the width w1 of the first end face 26a is smaller than the width R2 of the second end face 26b.

[0104] Furthermore, the conductive post 26 is formed of a columnar structure made of copper, gold, alloy, silver, aluminum or other suitable conductive materials, and the conductive post 26 is made using a patterned electroplating process, so that the conductive post 26 extends upward from the first blind hole 210 to form the insulating adhesive layer 21.

[0105] Furthermore, the first conductive portion 260 is in the shape of an inverted cone, and the first conductive portion 260 260 defines a small end face as the first end face 26a and a large end face S opposite to the first end face 26a (which is the interface between the first conductive portion 260 and the second conductive portion 261 and corresponds to the second hole end 210b of the first blind hole 210), such that the width w2 of the large end face S of the first conductive portion 260 is greater than the width w1 of its small end face (the first end face 26a), and less than or equal to the width R2 (i.e., w1) of the second end face 26b. <w2≦R2)。

[0106] like Figure 2D As shown, a first insulating layer 22 is formed on the insulating adhesive layer 21 to cover the plurality of field-effect transistors 20, the conductive pillars 26, and the surface of the insulating adhesive layer 21. Next, a leveling operation is performed to remove a portion of the first insulating layer 22 and expose the second end face 26b of the conductive pillars 26. Then, a plurality of second blind vias 220 are formed on the first insulating layer 22 using a laser to expose the first working surface 20a of the plurality of field-effect transistors 20.

[0107] In this embodiment, the first insulating layer 22 is formed on the substrate 9 by molding, coating or lamination, and the material forming the first insulating layer 22 is a dielectric material, which may be epoxy resin, and the epoxy resin may also contain molding compound or primer, such as epoxy molding compound (EMC), wherein the epoxy molding resin contains filler, and the filler content is 70 to 90 wt%.

[0108] Furthermore, the first insulating layer 22 can first cover the plurality of field-effect transistors 20 and the conductive pillar 26, and then perform a leveling operation by grinding to remove the upper part of the material of the first insulating layer 22, so that the surface of the first insulating layer 22 is flush with the second end face 26b of the conductive pillar 26.

[0109] like Figure 2E As shown, a first fan-out conductor 240 is formed by electroplating in the second blind hole 220 using an exposure and development method. Then, a first line 24 is formed by electroplating on the end face of the first fan-out conductor 240, the exposed second end face 26b of the conductive post 26, and the surface of the first insulating layer 22, so that the first line 24 electrically connects the first fan-out conductor 240 and the conductive post 26.

[0110] In this embodiment, the first fan-out conductor 240 is a short conical column, and the small end face 240a of the first fan-out conductor 240 is electrically connected to the first working surface 20a of the plurality of field-effect transistors 20, while the large end face 240b of the fan-out conductor 240 is electrically connected to the first line 24.

[0111] like Figure 2F As shown, a second insulating layer 25 is formed on the first insulating layer 22 to cover the first circuit 24 and the surface of the first insulating layer 22. Next, another leveling operation is performed, removing a portion of the second insulating layer 25 to expose a portion of the first circuit 24 as an electrical connection pad. Afterwards, the substrate 9 and the insulating adhesive layer 21 are removed to expose the second working surface 20b of the plurality of field-effect transistors 20, the first conductive portion 260 (or first end face 26a) of the conductive pillar 26, and the surface of the first insulating layer 22.

[0112] like Figure 2GAs shown, a third insulating layer 21a is formed on the exposed surface of the first insulating layer 22 to cover the second working surface 20b of the plurality of field-effect transistors 20, the first conductive portion 260 of the conductive post 26, and the exposed surface of the first insulating layer 22. Next, a leveling operation is performed to remove part of the third insulating layer 21a to expose the small end face (first end face 26a) of the first conductive portion 260 of the conductive post 26. Then, a plurality of third blind holes 230 are formed on the third insulating layer 21a by laser to expose the second working surface 20b of the plurality of field-effect transistors 20.

[0113] In this embodiment, the third blind hole 230 is in a "conical" shape.

[0114] like Figure 2H As shown, a second fan-out conductor 27 is electroplated in the third blind hole 230 using an exposure and development method. Then, a second circuit 270 is electroplated on the large end face 27a of the second fan-out conductor 27, the small end face (first end face 26a) of the first conductive portion 26 of the conductive post 26, and the surface of the third insulating layer 21a, so that the second circuit 270 electrically connects the second fan-out conductor 27 and the conductive post 26. Next, a fourth insulating layer 29 is formed on the third insulating layer 21a to cover the second circuit 270 and the surface of the third insulating layer 21a.

[0115] In this embodiment, the second fan-out conductor 27 is a short conical column, and the small end face 27b of the second fan-out conductor 27 is electrically connected to the second working surface 20b of the plurality of field-effect transistors 20, while the large end face 27a of the second fan-out conductor 27 is electrically connected to the second line 270.

[0116] Furthermore, an add-on structure 28 can be formed on the second insulating layer 25 and the first circuit 24 as needed. The add-on structure 28 includes a plurality of columnar wirings 280 disposed on the first circuit 24 and a dielectric layer 281 covering the columnar wirings 280. For example, the dielectric layer 281 can first cover the columnar wirings 28, and then, through a leveling process, such as grinding, remove the upper portion of the dielectric layer 281 so that the surface of the dielectric layer 281 is flush with the end face of the columnar wirings 280. It should be understood that multiple dielectric layers 281 can be configured as needed to arrange the required circuitry.

[0117] In addition, the third insulating layer 21a, the first insulating layer 22, the second insulating layer 25 and the fourth insulating layer 29 (and even the dielectric layer 281) form a package 23, which has a first surface 23a and a second surface 23b opposite to each other, such that the outer surface of the second insulating layer 25 (or the dielectric layer 281) serves as the first surface 23a and the outer surface of the fourth insulating layer 29 serves as the second surface 23b.

[0118] In addition, in subsequent processes, such as Figure 3A As shown, the electronic package 2 connects to an electronic device, such as a circuit board 30, via its columnar wiring 280 (or first line 24) through a plurality of conductive elements 300 containing solder material; or, as shown Figure 3B As shown, multiple openings 290 can also be formed on the surface of the fourth insulating layer 29 by laser, with the exposed portion of the second line 270 serving as an electrical connection pad, so that the electronic package 2 can connect a semiconductor chip 31 to the second line 270 via solder material 310 in a flip-chip manner.

[0119] Therefore, the manufacturing method of the present invention utilizes a large-size panel-level package specification combined with laser drilling technology, electroplated double-sided fan-out circuit structure (such as the first line 24, the second line 270, and even the columnar wiring 280) and conductive pillars 26 to form an effective circuit for each electrode of the MOSFET type field-effect transistor 20, thereby forming the electronic package 2. The shape of the third blind hole 230 connecting the field-effect transistor 20 is a "cone" shape with a smaller top and a larger bottom, while the shape of the second blind hole 220 connecting the field-effect transistor 20 and the shape of the first blind hole 210 forming the conductive pillar 26 are "inverted cones" with a larger top and a smaller bottom. This allows for arbitrary design of the packaging direction of each field-effect transistor 20 when the first working surface 20a and the second working surface 20b of each field-effect transistor 20 are interconnected, thereby increasing the flexibility of design or configuration. Thus, by having the structural shapes of the first conductive part 260 and the second fan-out conductor 27 in an inverted or complementary state, stress distribution is dispersed to avoid problems such as warping or cracking caused by stress concentration.

[0120] The present invention also provides an electronic package 2, comprising: a package body 23 composed of an insulating material, a circuit structure coupled to the package body 23, a plurality of field-effect transistors 20, and at least one conductive post 26.

[0121] The package 23 has a first surface 23a and a second surface 23b opposite to each other.

[0122] The circuit structure includes a first line 24 corresponding to the first surface 23a side of the package 23 and a second line 270 corresponding to the second surface 23b side of the package 23, and the first line 24 can be electrically connected to a circuit board 30 through a plurality of conductive elements 300.

[0123] The field-effect transistors 20 are horizontally embedded in the package 23 between the first line 24 and the second line 270, and the field-effect transistors 20 have opposing first working surfaces 20a and second working surfaces 20b, wherein the first working surfaces 20a and the second working surfaces 20b are respectively provided with a plurality of first and second fan-out conductors 240, 27 to electrically connect the first line 24 and the second line 270 respectively.

[0124] The conductive post 26 is embedded in the package 23, and the conductive post 26 has a first conductive part 260 and a second conductive part 261, and is separated from the plurality of field-effect transistors 20. The second conductive part 261 is cylindrical, and one end of the second conductive part 261 is electrically connected to the first line 24. The first conductive part 260 is a short conical column, such that the large end face S of the first conductive part 260 is combined with the other end of the second conductive part 261, and the small end face of the first conductive part 260 is electrically connected to the second line 270.

[0125] In one embodiment, the first and second fan-out conductors 240 and 27 are in the shape of short conical columns, and the large end faces 240b and 27a of the first and second fan-out conductors 240 and 27 are electrically connected to the first line 24 and the second line 270, respectively, while the small end faces 240a and 27b of the first and second fan-out conductors 240 and 27 are electrically connected to the first working surface 20a and the second working surface 20b of the field-effect transistor 20, respectively.

[0126] In one embodiment, the plurality of field-effect transistors 20 are embedded in the package 23 with the same configuration orientation. Alternatively, the plurality of field-effect transistors 20, 40 are embedded in the package 23 with different configuration orientations.

[0127] In one embodiment, a plurality of openings 290 are formed on the second surface 23b of the package 23 to expose a portion of the second line 270 as an electrical connection pad for bonding a semiconductor chip 31 via a flip-chip method.

[0128] In summary, the electronic package 2 and its manufacturing method of the present invention have the following advantages:

[0129] First, compared with existing leadframes and pinframes, the present invention can effectively control the thickness of the package 23 through the packaging process, which is beneficial to the miniaturization of the electronic package 2.

[0130] Secondly, compared to the use of existing solder materials, the present invention uses the first and second fan-out conductors 240, 27 and the conductive post 26 as the electrical connection structure, without the need to use solder materials such as solder paste, thus avoiding the quality problem of solder material overflow.

[0131] Third, compared to the use of existing solder materials, the present invention uses the first and second fan-out conductors 240, 27 and the conductive post 26 as the electrical connection structure, without the need for solder materials, thus overcoming the quality problem of gate breakage caused by high current products.

[0132] Fourth, compared with the existing pin frame 14 configuration, the present invention embeds the field effect transistors 20, 40 in the package 23 and then electrically connects the field effect transistors 20, 40 with the first and second fan-out conductors 240, 27 to avoid displacement of the first and second fan-out conductors 240, 27, thus avoiding the existing accuracy deviation problem.

[0133] Fifth, through the configuration of the first line 24 and the second line 270, the signals between each field-effect transistor 20, 40 can be interconnected, and the orientation of the chip package can be arbitrarily designed.

[0134] Sixth, compared to the packaging structure disclosed in TWI682513, the present invention forms a second fan-out conductor 27 in these third blind vias 230 without the need for conductive adhesive, thus avoiding the problem of poor bridging electrical properties caused by conductive adhesive overflow.

[0135] The above embodiments are merely illustrative of the principles and technical effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. An electronic package, comprising: An encapsulation made of insulating material, having a first surface and a second surface opposite to each other; A circuit structure incorporating the package includes a first circuit corresponding to a first surface side of the package and a second circuit corresponding to a second surface side of the package, wherein the first circuit can be electrically connected to a circuit board via a plurality of conductive elements. Multiple field-effect transistors (FETs) are horizontally arranged and embedded in a package between a first line and a second line. Each FET has a first working surface and a second working surface, each having multiple fan-out conductors for electrically connecting to the first line and the second line, respectively. At least one conductive post is embedded in the package body, and the conductive post has a first conductive portion and a second conductive portion. The second conductive portion is cylindrical, and one end of the second conductive portion is electrically connected to the first circuit. The first conductive portion is a short conical column, such that the large end face of the first conductive portion is combined with the other end of the second conductive portion, and the small end face of the first conductive portion is electrically connected to the second circuit.

2. The electronic package as claimed in claim 1, wherein, The fan-out conductor is in the shape of a short, tapered column, and its large end face is electrically connected to the first line and the second line, while its small end face is electrically connected to the first and second working surfaces of the field-effect transistor.

3. The electronic package as described in claim 1, wherein, The multiple field-effect transistors embedded in the package are configured with the same orientation.

4. The electronic package as claimed in claim 1, wherein, The multiple field-effect transistors are embedded in the package with different orientations.

5. The electronic package as claimed in claim 1, wherein, The second surface of the package has multiple openings to expose portions of the second circuit as electrical connection pads for flip-chip bonding of a semiconductor chip.

6. A method for manufacturing an electronic package, comprising: A substrate with a metallic surface is provided; An insulating adhesive layer is formed on the substrate; Multiple field-effect transistors are disposed on the insulating adhesive layer, and the field-effect transistors have a first working surface and a second working surface opposite to each other. At least one first blind hole is formed on the insulating adhesive layer by laser to expose a portion of the metal surface of the substrate; A first conductive part in the shape of a short, conical column is formed by electroplating in the first blind hole using an exposure and development method. Then, a second conductive part in the shape of a column is formed by electroplating on the large end face of the first conductive part, so that the first conductive part and the second conductive part are combined to form a conductive column. A first insulating layer is formed on the insulating adhesive layer to cover the plurality of field-effect transistors, the conductive pillars, and the surface covering the insulating adhesive layer; Perform a leveling operation to remove part of the first insulating layer and expose one end face of the second conductive part of the conductive post; Multiple second blind holes are formed on the first insulating layer by laser to expose the first and / or second working surfaces of the multiple field-effect transistors; A first fan-out conductor is formed by electroplating in the second blind hole using an exposure and development method. Then, a first line is formed by electroplating on the end face of the first fan-out conductor, the exposed end face of the conductive post, and the surface of the first insulating layer, so that the first line electrically connects the first fan-out conductor and the conductive post. A second insulating layer is formed on the first insulating layer to cover the surface of the first circuit and the first insulating layer; Perform another leveling operation to remove part of the second insulation layer to expose part of the first line as an electrical connection pad; Remove the substrate and the insulating adhesive layer to expose the first and / or second working surfaces of the plurality of field-effect transistors, the first conductive portion of the conductive pillar, and the surface of the first insulating layer; A third insulating layer is formed on the exposed surface of the first insulating layer to cover the first and / or second working surfaces of the plurality of field-effect transistors, the first conductive portion of the conductive pillar, and the exposed surface of the first insulating layer. Perform a leveling operation to remove part of the third insulating layer to expose the small end face of the first conductive part of the conductive post; Multiple third blind holes are formed on the third insulating layer by laser to expose the first and / or second working surfaces of the multiple field-effect transistors; A second fan-out conductor is formed by electroplating in the third blind hole using an exposure and development method. Then, a second line is formed by electroplating on the end face of the second fan-out conductor, the small end face of the first conductive part of the conductive post, and the surface of the third insulating layer, so that the second line electrically connects the second fan-out conductor and the conductive post. as well as A fourth insulating layer is formed on the third insulating layer to cover the second circuit and the surface of the third insulating layer.

7. The method for manufacturing an electronic package as described in claim 6, wherein, The first fan-out conductor is a short, tapered column, and the small end face of the first fan-out conductor is electrically connected to the first and / or second working surfaces of the plurality of field-effect transistors, while the large end face of the first fan-out conductor is electrically connected to the first circuit.

8. The method for manufacturing an electronic package as described in claim 6, wherein, The second fan-out conductor is in the shape of a short conical column, and the small end face of the second fan-out conductor is electrically connected to the first and / or second working surfaces of the plurality of field-effect transistors, while the large end face of the second fan-out conductor is electrically connected to the second circuit.

9. The method for manufacturing an electronic package as described in claim 6, wherein, The multiple field-effect transistors are arranged on the insulating adhesive layer with the same orientation.

10. The method for manufacturing an electronic package as described in claim 6, wherein, The multiple field-effect transistors are arranged on the insulating adhesive layer with different orientations.

11. The method for manufacturing an electronic package as described in claim 6, wherein, The manufacturing method also includes forming multiple openings on the surface of the fourth insulating layer by laser, with the exposed portion of the second line serving as an electrical connection pad for flip-chip bonding of a semiconductor chip.

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