Memory structure and method of forming the same

Abstract

A memory structure includes a substrate, a first word line trench, and a first word line formed in the first word line trench. The substrate has a plurality of active regions and isolation structures surrounding the active regions. The first word line trench is formed across a first active region of the active regions and the isolation structures. The first word line trench includes a first slot and a first slot body. The first slot is recessed from a top surface of the substrate. The first slot body extends from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first slot body. The first word line includes a gate dielectric conformally formed on the first slot body and the first slot. Thus, leakage current due to unintended element overlap issues can be avoided.

Description

Technical Field

[0001] This disclosure relates to memory structures and methods for forming memory structures. Background Technology

[0002] In advanced memory technologies, the retention performance of memory devices is primarily determined by various leakage effects. Gate-induced drain leakage (GIDL) is one of the main leakage effects affecting retention performance. For example, a high cutoff-state electric field will generate a poor GIDL effect, resulting in poor retention performance of the memory device. Furthermore, the small landing area of ​​the memory device will cause high cell contact resistance and is prone to unintended overlap problems, thus also leading to poor retention performance of the memory device.

[0003] Therefore, how to provide a solution to reduce the occurrence of GIDL effect and insufficient landing area, thereby improving the storage performance of memory, is one of the issues that those skilled in the art want to solve. Summary of the Invention

[0004] This disclosure relates to a memory structure.

[0005] According to one embodiment of this disclosure, a memory structure includes a substrate, a first word line trench, and a first word line formed in the first word line trench. The substrate has a plurality of active regions and an isolation structure surrounding the active regions. The first word line trench is formed across the first active region and the isolation structure. The first word line trench includes a first slot and a first trench body. The first slot is recessed from the top surface of the substrate. The first trench body extends from the bottom of the first slot. A first sidewall is connected between the bottom of the first slot and the top of the first trench body. The first word line includes a gate dielectric conformally formed on the first trench body and the first slot.

[0006] In one or more embodiments disclosed herein, the first sidewall is inclined relative to the top surface of the substrate.

[0007] In one or more embodiments disclosed herein, the thickness of the gate dielectric on the first sidewall is greater than the thickness of the gate dielectric on the first slot or the first trench body.

[0008] In one or more embodiments disclosed herein, the top of the first active region is implanted as a source / drain implantation region, and the source / drain implantation region overlaps with the first groove of the first character line trench.

[0009] In some implementations, the first sidewall of the first character line trench in the first active region is part of the source / drain implantation region.

[0010] In one or more embodiments disclosed herein, the memory structure further includes a second word line and a bit line structure. The second word line is formed across the first active region and the isolation structure. The bit line structure is formed on a portion of the first active region located between the first word line and the second word line.

[0011] In one or more embodiments disclosed herein, the memory structure further includes a third word line and a capacitor structure. The third word line crosses a second active region and an isolation structure formed across the active region. The capacitor structure is formed on a portion of the first active region located between the first word line and the third word line.

[0012] In one or more embodiments disclosed herein, the first word line further includes a gate structure and a dielectric cap. The gate structure is formed on the gate dielectric and fills the bottom of the first trench and the first slot. The dielectric cap fills the first slot and covers the gate structure.

[0013] This disclosure relates to a memory structure.

[0014] According to one embodiment of this disclosure, a memory structure includes a substrate, a plurality of word lines, a bit line structure, and a capacitor structure. The substrate has a plurality of active regions and an isolation structure surrounding the active regions. Each word line has an extending bottle shape in a cross-section perpendicular to a first direction in which the word line extends. The word lines include a first word line, a second word line, and a third word line. The first and second word lines cross the first active region and the isolation structure. The third word line crosses the second active region and the isolation structure. The bit line structure is formed on a portion of the first active region located between the first and second word lines. The capacitor structure is formed on a portion of the first active region between the first and third word lines.

[0015] In one or more embodiments disclosed herein, character lines are formed in a plurality of character line trenches extending along a first direction. Each character line trench includes a slot, a groove body, and a sidewall. The slot extends downward from the upper surface of the substrate. The groove body extends from the bottom of the slot. The width of the slot in cross-section is smaller than the width of the groove body in cross-section. The sidewall connects the bottom of the slot and the top of the groove body.

[0016] In some implementations, the sidewalls of the character line trench are parallel to the first direction and inclined relative to the top surface of the substrate.

[0017] In some embodiments, each word line formed in the word line trench includes a gate dielectric. The gate dielectric is conformally formed on the slot, tank body, and sidewall of a corresponding word line trench. The thickness of the gate dielectric on the sidewall of the corresponding word line trench is greater than the thickness of the gate dielectric on the slot or tank body of the corresponding word line trench.

[0018] In some embodiments, the gate dielectric on the sidewall of the word line trench in the active region includes an oxidized active region, and the gate dielectric on the sidewall of the word line trench in the isolation structure includes an oxidized isolation structure.

[0019] This disclosure relates to a method for manufacturing a memory device.

[0020] According to one embodiment of this disclosure, a method of manufacturing a memory device includes the following steps: Forming a hard mask on a plurality of active regions and an isolation structure surrounding the active regions on a substrate, wherein the hard mask has a first patterned trench extending over the first active region and the isolation structure. Etching the first active region and the isolation structure based on the first patterned trench of the hard mask to form a first slot within the first active region and the isolation structure. Forming a selection layer covering the active regions, the isolation structure, and the first slot. Etching a portion of the selection layer located at the bottom of the first slot to expose the first active region and the isolation structure located at the bottom of the first slot. Etching the first active region and the isolation structure exposed at the bottom of the first slot to form a first trench body, wherein the width of the first trench body is greater than the width of the first slot, and the first slot and the first trench body form a first word line trench. Removing the selection layer. Forming a first word line in the first word line trench.

[0021] In one or more embodiments of this disclosure, forming the first character line further includes the following steps: A gate dielectric is conformally formed on the first slot and the first slot body. A portion of the gate dielectric between the first slot and the first slot body is thickened such that a first sidewall is formed between the bottom and the top of the first slot, wherein the first sidewall is inclined relative to the horizontal direction.

[0022] In some embodiments, the gate dielectric is an oxide layer. Thickening the gate dielectric further includes the following process: Oxidizing a portion of the first active region exposed from the first trench.

[0023] In some embodiments, forming the first word line further includes the following steps: forming a gate structure on the gate dielectric; forming a dielectric cap on top of the first slot; and forming the gate structure further includes the following steps: conformally forming a conductive layer on the gate dielectric; forming a conductive material over the conductive layer, wherein the conductive material fills the first slot and the first trench; and recessing the conductive layer and conductive material from the first slot to expose the top of the first slot, wherein the recessed conductive layer and conductive material form the gate structure.

[0024] In one or more embodiments disclosed herein, the top of the first active region is implanted as a source / drain implantation region, and the depth of the first slot is less than the depth of the source / drain implantation region.

[0025] In one or more embodiments disclosed herein, the method of manufacturing a memory device further includes the following steps: forming a second word line spanning a first active region and an isolation structure; and forming a bit line structure on a portion of the first active region between the first word line and the second word line.

[0026] In one or more embodiments disclosed herein, the method of manufacturing a memory device further includes the following steps: forming a second active region spanning an active region and a third word line of an isolation structure; forming a capacitor structure on a portion of the first active region between the first word line and the third word line.

[0027] In summary, memory structures with improved word line structures can provide a large landing area for setting conductive pads. The gate dielectric of the word line structure has a considerable thickness at the corners, which can improve gate control capability, suppress the off-state electric field in the depletion region, and further suppress the GIDL phenomenon.

[0028] The above description is only used to illustrate the problem to be solved by this disclosure, the technical means to solve the problem, and the effects produced, etc. The specific details of this disclosure will be described in detail in the following implementation method and related drawings. Attached Figure Description

[0029] The advantages and accompanying drawings of this disclosure should be better understood through the following description of the embodiments, with reference to the accompanying drawings. The description of these drawings is merely illustrative of the embodiments and should not be construed as limiting the specific embodiments or the scope of the invention claims.

[0030] Figure 1A A partial schematic top view of the memory structure disclosed herein;

[0031] Figure 1B Drawing along Figure 1A A schematic cross-sectional view of line segment AA;

[0032] Figures 2 to 13A Several schematic cross-sectional views of a memory structure forming the present disclosure are shown at different stages;

[0033] Figure 13B schematically drawn in Figure 13A A partial cross-sectional view of the Chinese character's central line; and

[0034] Figure 14 A flowchart illustrating a method for forming a memory structure disclosed herein is provided. Detailed Implementation

[0035] The following detailed description includes embodiments in conjunction with the accompanying drawings. However, the provided embodiments are not intended to limit the scope of this disclosure, and the description of the structural operation is not intended to limit the order of execution. Any structure resulting from the recombination of elements and producing an apparatus with equivalent functionality is within the scope of this disclosure. Furthermore, the accompanying drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same or similar elements will be designated with the same symbols in the following description.

[0036] Furthermore, unless otherwise specified, the terms used throughout this specification and claims generally have their ordinary meaning in the context of this art, the content of this disclosure, and the specific content. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing this disclosure.

[0037] In this document, terms such as "first," "second," etc., are used only to distinguish elements or methods of operation that have the same technical terminology, and are not intended to indicate order or limit this disclosure.

[0038] In addition, terms such as “include,” “including,” and “provide” are all open-ended restrictions in this article, meaning that they include but are not limited to.

[0039] Furthermore, in this document, unless otherwise specified in the text, “a” and “the” may refer to one or more. It will be further understood that the terms “comprising,” “including,” “having,” and similar words as used herein specify the features, regions, integers, steps, operations, elements, and / or components described herein, but do not exclude one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof described or additionally described herein.

[0040] The retention performance of memory devices is affected by leakage current. Leakage current can be caused by, for example, subthreshold leakage, gate-induced drain leakage (GIDL), junction leakage, and / or cell leakage. Among these leakage effects, gate-induced drain leakage has a significant impact on the retention performance of memory devices. For example, the high electric field between the gate and drain of a transistor formed in a memory cell during the off-state can generate an undesirable GIDL effect, leading to poor retention time. Furthermore, a small landing area between the gate and source or drain of a transistor formed in a memory cell can lead to higher contact resistance and unintended cell overlap problems, thus affecting the retention performance of the memory cell.

[0041] To improve the retention performance of memory devices, this disclosure provides an improved memory structure and a method for forming such an improved memory structure, such that leakage current generated by the high electric field between the gate and drain of the transistor formed in the memory cell in the off state can be reduced, and a large landing area can be provided in the formed memory structure.

[0042] Please refer to Figure 1A and Figure 1B . Figure 1A A partial schematic top view of the memory structure disclosed herein is shown. Figure 1B Drawing along Figure 1A A schematic cross-sectional view of line segment AA.

[0043] In this embodiment, the memory structure 100 includes a substrate 110, a plurality of active regions 120 formed on the substrate 110, an isolation structure 130 formed around the active regions 120, and a plurality of word lines 140 formed above the isolation structure 130. Figure 1A In the partial top view shown, character line 140 includes character line 143, character line 146, character line 149, character line 152, character line 155, character line 158 and character line 161.

[0044] It should be noted that, for the sake of simplicity, some components of memory structure 100 have been omitted. For example, the bit line structure and capacitor structure in memory structure 100 are not shown. Figure 1A It is shown in the drawing.

[0045] Figure 1B A schematic cross-sectional view of an isolation structure 130 and two active regions 121 and 122 is shown, wherein two character lines 143 and 146 extend across active region 121, and two character lines 155 and 158 extend across active region 122.

[0046] In this embodiment, the isolation structure 130 is formed in the isolation trench 112, which is recessed from the substrate 110 and surrounds the active region 120. For example... Figure 1A and Figure 1B As shown, the isolation structure 130 surrounds active regions 121 and 122, isolating them from each other. In other words, the isolation structure 130 formed in the isolation trench 112 defines a plurality of active regions 120, isolating them from each other. Figure 1B In the illustrated cross-sectional view, the isolation structure 130 is located on both sides of the active region 121 or the active region 122, thereby isolating the active region 121 and the active region 122 from each other.

[0047] In some embodiments, the isolation structure 130 is used as an electrical insulator to prevent unintended leakage current from one of the active regions 120 to the other active regions 120. In some embodiments, the isolation structure 130 includes a dielectric material deposited in the isolation trench 112. In some embodiments, the isolation structure 130 includes an oxide material. The isolation structure 130 may be considered, for example, as a shallow trench isolation (STI).

[0048] Back Figure 1A In this embodiment, the character line 140 extends along the X direction. The active area 120 is arranged along directions other than the X and Y directions. Figure 1A As shown, two character lines 140 extend through one of the active regions 120. For example, two character lines 143 and 146 extend over one of the active regions 121. On the other hand, two character lines 155 and 158 extend over one of the active regions 122.

[0049] In this embodiment, each character line 140 (e.g., character lines 143, 146, 149, 152, 155, 158, and 161) has a bottle shape in a cross-sectional view, such as... Figure 1B As shown. For example, in Figure 1BIn this configuration, each character line 140 is formed within a corresponding character line groove 131 recessed from the top surface of the isolation structure 130 or a character line groove 111 recessed from the top surface of the active regions 121 / 122. Each character line groove 111 and character line groove 131 is bottle-shaped, with a narrow slot extending to the top surface of the isolation structure 130 or the active regions 121 and 122, and a wide slot extending from the bottom of the corresponding narrow slot. In other words, only a small portion of each character line is exposed from the top surface of the isolation structure 130 or the active regions 121 and 122, thus reducing the area occupied by the character lines 140 (e.g., character lines 143, 146, 149, 152, 155, 158, and 161). This increases the area available for landing pads or other structures.

[0050] In this embodiment, each character line 140 has a gate dielectric, a gate structure, and a dielectric cap (or dielectric cover) covering the gate structure. For example, in Figure 1B In the active region 121, a word line 143 is formed in a word line trench 111, and the word line 143 includes a gate dielectric 143gd, a gate structure 143g, and a dielectric cap 143dc. The gate dielectric 143gd is conformally formed above the word line trench 111. The gate structure 143g is formed above the gate dielectric 143gd. The dielectric cap 143dc fills the word line trench 111 and covers the gate structure 143g. Similar to word line 143, word line 146 includes a gate dielectric 146gd, a gate structure 146g, and a dielectric cap 146dc.

[0051] In some embodiments, the gate dielectric of word line 140 (e.g., gate dielectric 143gd and gate dielectric 146gd) is an oxide material. In some embodiments, the dielectric cap (or dielectric cover, e.g., dielectric cap 143dc and dielectric cap 146dc) of word line 140 is also an oxide material. In some embodiments, the material of the gate dielectric (e.g., gate dielectric 143gd and gate dielectric 146gd) is the same as the material of the dielectric cap (e.g., dielectric cap 143dc, dielectric cap 146dc, dielectric cap 149dc and / or dielectric cap 152dc).

[0052] Character lines 149 and 152 also have a structure similar to that of character lines 143 and 146. Figure 1BIn the cross-sectional view, word lines 149 and 152 are formed in word line trenches 131, and each word line trench 131 extends into the isolation structure 130. A gate dielectric 149gd is formed above the isolation structure 130. Similarly, the gate structure 149g and dielectric cap 149dc of word line 149 are formed above the gate dielectric 149gd within the word line trench 131. Likewise, word line 152 includes a gate dielectric 152gd, a gate structure 152g, and a dielectric cap 152dc formed within the word line trench 131.

[0053] like Figure 1B As shown, in this embodiment, character lines 155 and 158 in the active region 122 have a structure similar to that of character lines 143 and 146, while character line 161 has a structure similar to that of character lines 149 and 152.

[0054] In this embodiment, the top of the substrate 110 is implanted. Specifically, in this embodiment, the substrate 110 is a semiconductor substrate, the top of the active region 121 is implanted as a source / drain implantation region 1211, and the top of the active region 122 is implanted as a source / drain implantation region 1221. The source / drain implantation regions 1211 and 1221 can each be part of a transistor in a memory cell used for storing information.

[0055] For example, a first transistor is formed by the source / drain implantation region 1211 located at the top of the active region 121 between word lines 143 and 146, the word line 143, and the portion of the active region 121 between word line 143 and the isolation structure 130. A second transistor is formed by the source / drain implantation region 1221 located at the top of the active region 122 between word lines 143 and 146, the word line 146, and the portion of the active region 121 between word line 146 and the isolation structure 130. The first transistor with the gate structure 143g of the word line 143 and the second transistor with the gate structure 146g of the word line 146 form a common-source structure.

[0056] In addition, such as Figure 1B As shown, each word line trench has sidewalls that are inclined relative to the top surface of the substrate 110. For example, for word line 143, gate dielectric 143gd is conformally formed on word line trench 111, and word line trench 111 has sidewalls that are inclined relative to the top surface of the substrate 110.

[0057] In addition, such as Figure 1BIn the illustrated cross-section, the thickness of the gate dielectric 143gd on the inclined sidewall of the word line trench 111 is greater than the thickness of the gate dielectric 143gd in other parts of the word line trench 111, which reduces the electric field between the drain of the transistor (e.g., the active region 121 portion between the word line 143 and the isolation structure 130) and the gate of the transistor (e.g., the gate structure 143g of the word line 143), thereby improving the GIDL effect.

[0058] exist Figure 1B In the active region 121, multiple bit line structures 170 and multiple capacitor structures 180 are formed on the top surfaces of the active regions 121 and 122. Specifically, for the bit line structure 170 and capacitor structure 180 formed on the active region 121, one capacitor structure 180 is formed in a portion of the active region 121 between word lines 143 and 149, wherein word line 149 extends across another active region 122 and an isolation structure 130 adjacent to the active region 121. Bit line structure 170 is formed in a portion of the active region 121 between word lines 143 and 146. A capacitor structure 180 and a transistor in the active region 121 form a 1T1C memory cell, which is connected to a corresponding bit line of the memory device. In some embodiments, the memory device is, for example, a DRAM device. The transistor in the memory cell is a structure used to control memory operations. In some embodiments of the 1T1C memory cell, the capacitor structure 180 is applied with a ground potential, and the bit line structure 170 is applied with a charging potential.

[0059] Specifically, one of the capacitor structures 180 is formed in the active region 121 portion between word lines 143 and 149, with word line 149 extending across active region 121 and another active region 1202 outside of active region 120, as well as the isolation structure 130 adjacent to active region 121. A bit line structure 170 is formed on the active region 121 portion between word lines 143 and 146. A capacitor structure 180 and a transistor in the active region 121 form a 1T1C memory cell, which is connected to a corresponding bit line structure 170 in a DRAM device. The transistor in the memory cell is a structure used to control memory operations. In some embodiments of the 1T1C memory cell, the capacitor structure 180 is applied a ground potential, and the bit line structure 170 is applied a charging potential.

[0060] In some embodiments, each bit line structure 170 includes a bit line contact and other additional connection structures, and the bit line contact may be a landing pad disposed above the substrate 110. In some embodiments, each capacitor structure 180 includes a cell contact and a capacitor formed on the cell contact, and the cell contact may be a landing pad disposed above the substrate 110. Since the occupation area of word lines 140 on the upper surface of the substrate 110 is reduced, the landing pads of the bit line structure 170 and the capacitor structure 180 can have a larger area for arrangement for connection, thereby avoiding unexpected overlapping problems.

[0061] Please refer to Figures 2 to 13B . Figures 2 to 13A which illustrate a plurality of schematic cross-sectional views of the memory structure of the present disclosure at different stages. Figure 13B schematically illustrates a partial cross-sectional view of word lines in Figure 13A .

[0062] In Figure 2 , a substrate 110 is provided, and the substrate 110 has active regions 121, an active region 122 and isolation structures 130 surrounding the active regions 121 and the active region 122. The isolation structures 130 are formed in isolation trenches 112 recessed from the top surface of the substrate 110.

[0063] In this embodiment, the top of the active region 121 is implanted to form source / drain implantation regions 1211, and the top of the active region 122 is implanted to form source / drain implantation regions 1221. As mentioned above, the source / drain implantation regions 1211 and the source / drain implantation regions 1221 can be used as source / drain in subsequent processes.

[0064] Subsequently, a hard mask layer 210 is formed on the active region 121, the active region 122 and the isolation structures 130 of the substrate 110. In some embodiments, the hard mask layer 210 is a nitride layer formed on the active region 121, the active region 122 and the isolation structures 130 of the substrate 110.

[0065] Continuing from Figure 2 , in Figure 3 , a photoresist layer 220 is formed on the hard mask layer 210. The photoresist layer 220 has a pattern including a plurality of slots 221. The slots 221 are used to pattern the hard mask layer 210. In this embodiment, the slots 221 have the same width.

[0066] In Figure 4 , the hard mask layer 210 is patterned based on the slots 221 of the photoresist layer 220, and a plurality of patterned trenches 211 are formed in the slots 221.

[0067] After forming the patterned trench 211, the active regions 121 and 122 and the isolation structure 130 are etched based on the patterned trench 211 of the slot 221 to form a plurality of slots 111s recessed from the active regions 121 and 122, and a plurality of slots 131s recessed from the isolation structure 130. In this embodiment, the formed slots 111s and slots 131s extend along the X direction and respectively span the isolation structure 130 and one or more active regions 120. Figure 4 As shown, in this embodiment, each of slots 111s and 131s has a depth D, which is the depth from the top surface of the substrate 110 or the isolation structure 130 to its own bottom. In this embodiment, the depth D of slots 111s and 131s is less than the depth of the source / drain implantation region 1211 of the active region 121 or the source / drain implantation region 1221 of the active region 122.

[0068] exist Figure 5 In the process of forming slots 111s and 131s, the photoresist layer 220 is removed. Subsequently, a selectable layer 230 is conformally formed on the hard mask layer 210 and slots 111s and 131s. In some embodiments, the selectable layer 230 is formed by a deposition process. The deposition process used to form the selectable layer 230 includes chemical vapor deposition (CVD) or other suitable deposition processes.

[0069] exist Figure 6 In this process, the selectable layer 230 is etched, exposing the top surface of the hard mask layer 210 and the bottom of the slots 111s and 131s. In this embodiment, the selectable layer 230 is etched using an anisotropic etching process, such that a portion of the selectable layer 230 remains on the sidewalls of the patterned trenches 211 of the hard mask layer 210 and the sidewalls of the slots 111s and 131s.

[0070] exist Figure 7 In the middle, a plurality of wide grooves 111gr are formed and extend from the bottom exposed by the slot 111s, and a plurality of wide grooves 131gr are formed and extend from the bottom exposed by the slot 131s. Each of the grooves 111gr and 131gr extends along the X direction and spans the isolation structure 130 and one or more active regions 120.

[0071] like Figure 7As shown, since some selection layers 230 remain on the sidewalls of the patterned trenches 211 of the hard mask layer 210 and on the sidewalls of slots 111s and 131s, the sidewall portions of the active regions 121 and 122, as well as the sidewall portions of the isolation structure 130, are covered by the selection layers 230 and are retained after etching. Outside the remaining selection layers 230, the slots 111gr and 131gr further extend from the bottom of slots 111s and 131s, respectively, such that the width of each slot 111gr is greater than the width of the corresponding slot 111s, and the width of each slot 131gr is greater than the width of the corresponding slot 131s.

[0072] exist Figure 8 In the middle, the remaining selection layer 230 is removed, thereby exposing the slots 111s, 131s and the grooves 111gr, 131gr.

[0073] exist Figure 9 In this process, after removing the selection layer 230, the hard mask layer 210 is removed, and oxide layers 111o are formed in slots 111s and grooves 111gr, and oxide layers 131o are formed in slots 131s and grooves 131gr. In some embodiments, each oxide layer 111o is conformally formed in its corresponding slot 111s and corresponding groove 111gr, and oxide layers 131o are conformally formed in their respective slots 131s and corresponding grooves 131gr. In this embodiment, oxide layers 111o and 131o are formed by an oxidation process.

[0074] exist Figure 10 In this process, the oxide layer 111o and the oxide layer 131o are thickened so that the oxide layer 111o and the oxide layer 131o can be used as gate dielectrics formed in the word line trench 111 and the word line trench 131.

[0075] Please focus on the active region 121 and the area near the active region 121. In this embodiment, the oxide layer 111o and the oxide layer 131o are thickened by an oxidation process. Please focus on the oxide layer 111o. After the oxide layer 111o is formed on the slot 111s and the tank body 111gr, a further oxidation process is performed to oxidize the portions of the slot 111s and the tank body 111gr where the oxide layer 111o is formed. This oxidizes a portion of the slot 111s and also oxidizes portions of the slot 111s near the oxide layer 111o, all of which become part of the oxide layer 111o. Thus, the oxide layer 111o is thickened to serve as the gate dielectric (e.g., gate dielectrics 143gd and 146gd).

[0076] In addition, such as Figure 10 As shown, the portion connecting the slot 111s and the groove 111gr and covered by the oxide layer 111o is reduced, thereby forming a sidewall 111w inclined relative to the top surface of the substrate 110. In this embodiment, the slot 111s, the groove 111gr, and the sidewall 111w connecting the corresponding slot 111s and the corresponding groove 111gr form a character line groove 111.

[0077] In this embodiment, the sidewalls 111w of the word line trenches 111 in each active region 121 and active region 122 are formed in the source / drain implantation regions 1211 and 1221, and the gate dielectric 143gd and gate dielectric 146gd at the sidewalls 111w will include the oxidized material portions of the source / drain implantation regions 1211 and 1221.

[0078] For word line 143, since the portion connected between slot 111s and trench 111gr and covered by oxide layer 111o is oxidized to the gate dielectric 143gd, the thickness of the gate dielectric 143gd in the inclined sidewall 111w of word line trench 111 will be greater than the thickness of the gate dielectric 143gd in other portions of word line trench 111. In other words, the gate dielectric 143gd near the source / drain implantation region 1211 can have a larger thickness, thereby suppressing the electric field near the cutoff state of the source / drain implantation region 1211, and thus suppressing the GIDL effect in the memory structure.

[0079] In some embodiments, the gate dielectric 143gd in the trench 111gr below the source / drain implantation region 1211 can be designed to have a thin thickness. Since the trench 111gr is used to accommodate the gate structure of each word line, having a thin gate dielectric 143gd in the trench 111gr can improve gate control capability.

[0080] For the word line trench 131 in the isolation structure 130, the oxide layer 131o can also be thickened using a similar oxidation process, thereby forming gate dielectric 149gd and gate dielectric 152gd with increased thickness at the corners of the word line trench 131. The increased thickness of the gate dielectric 149gd and gate dielectric 152gd includes the oxide material of the isolation structure 130. Please refer to the subsequent discussion for details.

[0081] In this embodiment, the slot 111s, the groove 111gr, and the sidewall 111w connecting the slot 111s and the groove 111gr form a bottle-shaped character line groove 111, such that the character line groove 111 has a narrow top extending from the top surface of the substrate 110 and a wide bottom extending inside the substrate 110. Since the character line groove 111 extends along the X direction, the inclined sidewall 111w will also extend parallel to the X direction.

[0082] Similarly, for one of the character line grooves 131, the slot 131s, the groove body 131gr, and the sidewall 131w connecting the slot 131s and the groove body 131gr form a bottle-shaped character line groove 131, such that the character line groove 131 has a narrow top extending from the top surface of the substrate 110 and a wide bottom extending inside the substrate 110. Since the character line groove 131 extends along the X direction, the inclined sidewall 131w also extends substantially parallel to the X direction.

[0083] The character line trench 111 in the active region 122 and the character line trench 131 in the isolation structure 130 adjacent to the active region 122 can be provided through the same manufacturing process, and the oxide layer 111o on the character line trench 111 in the active region 122 and the oxide layer 131o on the character line trench 131 in the isolation structure 130 can be further thickened.

[0084] In this embodiment, the thickened oxide layer 111o and oxide layer 131o can be carried out in the same process to thicken the oxide layer 111o and oxide layer 131o as gate dielectric.

[0085] exist Figure 11 In the middle, multiple character lines 140 are formed in the bottle-shaped character line grooves 111 and 131.

[0086] As previously described, the source / drain implantation regions 1211 and 1221 can be part of a transistor in a memory cell used for storing information. In this embodiment, the source / drain implantation region 1211 located at the top of the active region 121 between word lines 143 and 146, and the portion of the active region 121 between word line 143 and isolation structure 130 form a first transistor. The source / drain implantation region 1221 located at the top of the active region 122 between word lines 143 and 146, the word line 146, and the portion of the active region 121 between word line 146 and isolation structure 130 form a second transistor. The first transistor with gate structure 143g having word line 143 and the second transistor with gate structure 146g having word line 146 form a common-source structure.

[0087] exist Figure 11In the middle, the gate structure and the dielectric cap covering the gate structure are formed in the corresponding word line trench 111 and word line trench 131, respectively, thereby forming word line 143, word line 146, word line 149, word line 152, word line 155, word line 158 and word line 161.

[0088] Please pay attention to active area 121. In some embodiments, after depositing gate dielectric 143gd, gate dielectric 146gd, gate dielectric 149gd, and gate dielectric 152gd, gate structures 143g, 146g, 149g, and 152g are deposited on top of their respective gate dielectrics 143gd, 146gd, 149gd, and 152gd, and dielectric caps 14 are deposited respectively. 3dc, dielectric cap 146dc, dielectric cap 149dc and dielectric cap 152dc are on the corresponding gate structures 143g, 146g, 149g and 152g, such that the gate structures 143g, 146g, 149g and 152g are covered by the corresponding dielectric caps 143dc, 146dc, 149dc and 152dc, respectively.

[0089] In this embodiment, character lines 155 and 158 in the active region 122 have a structure similar to that of character lines 143 and 146, and character line 161 has a structure similar to that of character lines 149 and 152. Therefore, character lines 155, 158, and 161 can be formed by a process similar to that described above.

[0090] In some implementations, after forming character lines 143, 146, 149, 152, 155, 158, and 161, a polishing process is performed to planarize them, so that the top surfaces of character lines 143, 146, 149, 152, 155, 158, and 161 are coplanar.

[0091] In some embodiments, the gate structure (e.g., gate structure 143g, gate structure 146g, gate structure 149g, and gate structure 152g) is made of a conductive material. In some embodiments, the conductive material of the gate structure includes tungsten.

[0092] In some embodiments, for each gate dielectric, the gate dielectric in the trench 111gr (e.g., gate dielectric 143gd) can be designed to have a thinner thickness relative to the thickness of the gate dielectric 143gd at the sidewall 111w, such that the thickness of the gate dielectric 143gd around the gate structure 143g is less than the thickness of the gate dielectric 143gd at the sidewall 111w. This thin gate dielectric around the gate structure 143g improves gate control capability to achieve a good on / off ratio.

[0093] In some embodiments, the gate structure of the word line is formed through the following process. For the formation of the gate structure 143g, a thin conductive layer is conformally formed over the gate dielectric 143gd. The thin conductive layer over the gate dielectric 143gd can form gaps in the corresponding word line trench 111. After forming the thin conductive layer, a conductive material is further formed over the thin conductive layer and fills the gaps formed by the thin conductive layer. For the corresponding word line trench 111, the conductive material fills the slots 111s and the grooves 111gr of the corresponding word line trench 111. The conductive material and the thin conductive layer form the gate structure 143g of the word line 143. In this case, the thin conductive layer can be regarded as a seed layer.

[0094] After the conductive material is filled, the conductive material and a thin conductive layer are recessed from the slots 111s of the corresponding word line trench 111, thereby providing space for accommodating the dielectric cap 143dc, so that the gate structure 143g covers the dielectric cap 143dc. After the dielectric cap 143dc is deposited on top of the gate structure 143g, the formation of the word line 143 is completed.

[0095] successor Figure 11 ,exist Figure 12 In the cross-sectional view, one bit line structure 170 is formed on the active region 121 portion between word line 143 and word line 146. Another bit line structure 170 is formed on the active region 122 portion between word line 155 and word line 158.

[0096] In some implementations, each bitline structure 170 includes bitline contacts and other additional connection structures, wherein the bitline contacts may be landing pads above the substrate 110.

[0097] In Figure 13A, a capacitor structure 180 is formed on the substrate 110. One of the capacitor structures 180 is formed between a portion of word line 143 and word line 149, extending across another active region 122 and an isolation structure 130 adjacent to the active region 121. As previously described, one of the transistors in the capacitor structure 180 and the active region 121 forms a 1T1C memory cell connected to the corresponding word line of the DRAM device. The transistor in the memory cell is a structure used to control memory operations.

[0098] In some embodiments, each capacitor structure 180 includes a unit contact and a capacitor body formed on the unit contact, wherein the unit contact may be a landing pad above the substrate 110.

[0099] Because the area occupied by the character line 140 on the top surface of the substrate 110 is reduced, more area can be provided on the top surface of the substrate 110 for the bit line structure 170 and the capacitor structure 180, thus avoiding the overlap problem caused by unintended connections between the bit line structure 170 and the capacitor structure 180. Figure 13A As shown, the projection of one of the capacitor structures 180 can overlap with the gate structure 143g of the word line 143 in the groove 131gr of the word line trench 111.

[0100] Reference Figure 13B . Figure 13B A schematic partial cross-sectional view of character line 143 in Figure 13 is shown. For simplicity, some components are... Figure 13B This was overlooked. For example, a portion of the corresponding capacitor structure 180 was not included. Figure 13B It is shown in the figure.

[0101] like Figure 13B As shown, in this embodiment, the character line 143 formed in the character line groove 111 is bottle-shaped, and the character line groove 111 has a narrow slot 111s, a wide groove body 111gr, and an inclined sidewall 111w. In other words, along the horizontal direction perpendicular to the Z direction, the slot 111s has a width W1, the groove body 111gr has a width W2, and the width W1 is smaller than the width W2.

[0102] In this embodiment, the gate dielectric 143gd has different segments conformally formed on the slot 111s, sidewall 111w, and tank body 111gr, each segment having a different thickness. Figure 13BIn this embodiment, the portion of the gate dielectric 143gd on the slot 111s has a thickness T1, and the portion of the gate dielectric 143gd on the inclined sidewall 111w has a thickness T2. Thickness T2 is greater than thickness T1. As previously described, in some embodiments, the portion of the gate dielectric 143gd on the sidewall 111w can be further thickened, such that the gate dielectric 143gd has an increased thickness T2 above the sidewall 111w, wherein the gate dielectric 143gd with the increased thickness T2 above the sidewall 111w is a portion of the source / drain implantation region 1211 located between the gate structure 143g and the capacitor structure 180, and is capable of suppressing GIDL current.

[0103] In this embodiment, at Figure 13B In the illustrated cross-sectional view, the gate dielectric 143gd has a thickness thinner than the thickness T2 at the trench 111gr. As previously described, in some embodiments, the gate dielectric 143gd in the trench 111gr can be designed to be thinner than the thickness T2 of the gate dielectric 143gd at the sidewall 111w, such that the thickness of the gate dielectric 143gd at the adjacent gate structure 143g is less than the thickness of the gate dielectric 143gd at the sidewall 111w. A thinner gate dielectric 143gd around the gate structure 143g can improve gate control capability to achieve a good on / off ratio.

[0104] Please refer to Figures 2 to 13B as well as Figure 14 . Figure 14 A flowchart illustrating a method 300 for forming a memory structure disclosed herein is provided. Method 300 includes processes 301 to 311, which summarize an exemplary method for forming the memory disclosed herein.

[0105] Reference Figure 2 In process 301, a hard mask layer 210 is formed on the active regions 121 and 122 of the substrate 110, and an isolation region is formed around the active regions 121 and 122, the isolation region including an isolation structure 130.

[0106] Reference Figure 3 In process 302, a photoresist layer 220 is formed on the hard mask layer 210, wherein the photoresist layer 220 has a pattern for patterning the hard mask layer 210.

[0107] Reference Figure 4 In process 303, a hard mask layer 210 is patterned based on the photoresist layer 220, and active regions 121 and 122 are etched based on the patterned hard mask layer 210 to form slots 111s and 131s on the active regions 121, 122 and isolation structure 130.

[0108] Reference Figure 5 In process 304, the photoresist layer 220 is removed and a selection layer 230 is formed that conformally overlaps the active regions 121, 122, isolation structure 130, and slots 111s and 131s.

[0109] Reference Figure 6 In process 305, the selection layer 230 is etched to expose the bottom of slots 111s and 131s.

[0110] Reference Figure 7 In process 306, active regions 121 and 122 and isolation structure 130 exposed from the bottom of slots 111s and 131s are etched to form trenches 111gr and 131gr, wherein each trench 111gr extends from the bottom of the corresponding slot 111s and each trench 131gr extends from the bottom of the corresponding slot 131s.

[0111] Reference Figure 8 In process 307, remove selection layer 230.

[0112] Reference Figure 9 In process 308, gate dielectrics (i.e., oxide layers 111o and 131o) are formed in slots 111s, slots 131s and tanks 111gr and 131gr.

[0113] Reference Figure 10 In process 309, the gate dielectric is thickened. The thickened gate dielectric serves as the gate dielectric for each subsequently formed word line (e.g., gate dielectric 143gd, gate dielectric 146gd, gate dielectric 149gd, and gate dielectric 152gd). In the active region 121, active region 122, and isolation structure 130, slots 111s and 131s, trenches 111gr and 131gr, and sidewalls 111w connecting the slots 111s, 131s, and trenches 111gr and 131gr form multiple word line trenches 111 and 131. Thus, each formed word line trench 111 and word line trench 131 is bottle-shaped with a narrow top and a wide bottom.

[0114] Reference Figure 11In process 310, gate structures (e.g., gate structures 143g, 146g, 149g, and 152g) and dielectric caps (e.g., dielectric caps 143dc, 146dc, 149dc, and 152dc) covering the gate structures are deposited. Thus, word lines (e.g., word lines 143, 146, 149, 152, 155, 158, and 161) are formed within word line trenches 111 and 131.

[0115] Reference Figure 12 , Figure 13A and Figure 13B In process 311, bit line structure 170 and capacitor structure 180 are formed on substrate 110.

[0116] In summary, this disclosure provides a memory structure primarily featuring an improved word line structure. One such improved word line structure has a bottle shape with a narrow top and a wide bottom, thereby reducing the area occupied by the word lines on the top surface of the substrate and increasing the area available on the top surface of the substrate for other landing structures (such as conductive pads or contacts). Furthermore, the thickness of the gate dielectric portion between the narrow top and the wide bottom can be increased to suppress the electric field between the gate and drain in the off state. Further, a thinner gate dielectric can be provided around the gate structure of the word lines, thereby improving gate controllability.

[0117] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the claims.

[0118] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the embodiments disclosed herein without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations of the invention, provided they fall within the appended scope of protection.

[0119] [Symbol Explanation]

[0120] 100: Memory Structure

[0121] 110:Substrate

[0122] 111: Character line groove

[0123] 111o: Oxide layer

[0124] 111s: slot

[0125] 111gr: Tank

[0126] 111w: Sidewall

[0127] 112: Isolation trench

[0128] 120: Active Zone

[0129] 121: Active Zone

[0130] 1211: Source / Drain Implantation Region

[0131] 122: Active Zone

[0132] 1221: Source / Drain Implantation Region

[0133] 130: Isolation Structure

[0134] 131: Character line groove

[0135] 131o: Oxide layer

[0136] 131s: slot

[0137] 131gr: Tank

[0138] 131w: Sidewall

[0139] 140, 143, 146, 149, 152, 155, 158, 161: Character lines

[0140] 143gd, 146gd, 149gd, 152gd: Gate dielectric

[0141] 143g, 146g, 149g, 152g: Gate structure

[0142] 143dc, 146dc, 149dc, 152dc: Dielectric cap body

[0143] 170: Bitline Structure

[0144] 180: Capacitor Structure

[0145] 210: Hard mask layer

[0146] 211: Patterned Grooves

[0147] 220: Photoresist layer

[0148] 221: Slot

[0149] 230: Select Layer

[0150] 300: Method

[0151] 301-311: Process

[0152] AA: Line segment

[0153] D: Depth

[0154] T1, T2: Thickness

[0155] X, Y, Z: Direction.

Claims

1. A memory structure, characterized in that, include: The substrate has a plurality of active regions and an isolation structure surrounding the active regions; A first character line groove, spanning the first active region and the isolation structure, wherein the first character line groove includes: The first slot is recessed from the top surface of the substrate; A first groove extends from the bottom of the first slot, wherein a first sidewall is connected between the bottom of the first slot and the top of the first groove, and in a cross-section perpendicular to the first direction of the extension of the first character line, the first character line groove is bottle-shaped in both the first active area and the isolation structure, and the width of the first groove is greater than the width of the first slot. A first character line is formed in the first character line trench, wherein the first character line includes a gate dielectric conformally formed on the first trench body and the first slot.

2. The memory structure according to claim 1, characterized in that, The first sidewall is inclined relative to the top surface of the substrate.

3. The memory structure according to claim 1, characterized in that, The thickness of the gate dielectric on the first sidewall is greater than the thickness of the gate dielectric on the first slot or the first trench body.

4. The memory structure according to claim 1, characterized in that, The top of the first active region is implanted as a source / drain implantation region, and the source / drain implantation region overlaps with the first groove of the first character line trench.

5. The memory structure according to claim 4, characterized in that, The first sidewall of the first character line trench in the first active region is part of the source / drain implantation region.

6. The memory structure according to claim 1, characterized in that, Further includes: The second character line crosses the first active area and forms the isolation structure; as well as The bit line structure is formed on a portion of the first active region located between the first bit line and the second bit line.

7. The memory structure according to claim 1, characterized in that, Further includes: The third character line, which spans the second active region across these active regions, forms with the isolation structure; as well as A capacitor structure is formed on a portion of the first active region located between the first character line and the third character line.

8. The memory structure according to claim 1, characterized in that, The first character line further includes: A gate structure is formed on the gate dielectric and fills the bottom of the first trench and the first slot; and The dielectric cap fills the first slot and covers the gate structure.

9. A memory structure, characterized in that, include: The substrate has a plurality of active regions and an isolation structure surrounding the active regions; A plurality of character lines, each of which has an extending bottle shape in a cross-section perpendicular to a first direction in which the character line extends, the character line including a first character line, a second character line, and a third character line, the first character line and the second character line forming a first active region across the active regions and the isolation structure, the third character line forming a second active region across the active regions and the isolation structure, the character lines being formed in a plurality of character line grooves extending along the first direction, each character line groove including: A slot extends downward from the upper surface of the substrate; and The groove extends from the bottom of the slot, wherein in a cross-section perpendicular to the first direction of the extension of the character line, each character line groove has an extending bottle shape in the corresponding active areas and the isolation structure, and the width of the slot is smaller than the width of the groove. The bit line structure is formed on a portion of the first active region located between the first bit line and the second bit line; and A capacitor structure is formed on a portion of the first active region between the first character line and the third character line.

10. The memory structure according to claim 9, characterized in that, The character lines are formed in a plurality of character line grooves extending along the first direction, each character line groove further comprising: The sidewall connects the bottom of the slot to the top of the slot body.

11. The memory structure according to claim 10, characterized in that, The sidewall of each character line groove is parallel to the first direction and inclined relative to the top surface of the substrate.

12. The memory structure according to claim 10, characterized in that, Each character line formed in the character line groove includes: A gate dielectric is conformally formed on the slot, the tank body, and the sidewall of a corresponding one of the word line trenches, wherein the thickness of the gate dielectric on the corresponding sidewall of the word line trench is greater than the thickness of the gate dielectric on the corresponding slot or the tank body of the word line trench.

13. The memory structure according to claim 12, characterized in that, The gate dielectrics on the sidewalls of the word line trenches in the active regions include the oxidized active regions, and the gate dielectrics on the sidewalls of the word line trenches in the isolation structure include the oxidized isolation structure.

14. A method for forming a memory structure, characterized in that, include: A hard mask is formed on a plurality of active regions of a substrate and an isolation structure surrounding the active regions, wherein the hard mask has a first patterned trench extending above a first active region of the active regions and the isolation structure. Based on the hard mask, the first patterned trench is etched to form the first active region and the isolation structure to form a first slot within the first active region and the isolation structure; A selection layer is formed covering the active regions, the isolation structure, and the first slot; Etch a portion of the selective layer located at the bottom of the first slot to expose the first active region and the isolation structure located at the bottom of the first slot; The first active region and the isolation structure exposed at the bottom of the first slot are etched to form a first groove, the first slot and the first groove form a first character line groove, the first character line groove is bottle-shaped in both the first active region and the isolation structure in a cross-section perpendicular to the first direction of the extension of the first character line, and the width of the first groove is greater than the width of the first slot. Remove the selected layer; and The first character line is formed in the first character line groove.

15. The method according to claim 14, characterized in that, The formation of the first character line includes: A gate dielectric is conformally formed on the first slot and the first slot body; and The portion of the gate dielectric between the first slot and the first slot body is thickened, such that a first sidewall is formed between the bottom and the top of the first slot, wherein the first sidewall is inclined relative to the horizontal direction.

16. The method according to claim 15, characterized in that, The gate dielectric is an oxide layer, and thickening the gate dielectric includes: Oxidation occurs in the portion of the first active region exposed from the first slot.

17. The method according to claim 15, characterized in that, The formation of this first character line further includes: A gate structure is formed on the gate dielectric, wherein forming the gate structure includes: A conductive layer is conformally formed on the gate dielectric; A conductive material is formed above the conductive layer, wherein the conductive material fills the first groove and the first slot; and A conductive layer and conductive material are recessed from a first slot to expose the top of the first slot, wherein the recessed conductive layer and conductive material form the gate structure; and A dielectric cap is formed at the top of the first slot.

18. The method according to claim 14, characterized in that, The top of the first active region is implanted as the source / drain implantation region, and the depth of the first slot is less than the depth of the source / drain implantation region.

19. The method according to claim 14, characterized in that, Further includes: A second character line is formed, spanning the first active region and the isolation structure; as well as A bit line structure is formed on a portion of the first active region between the first bit line and the second bit line.

20. The method according to claim 14, characterized in that, Further includes: A second active region spanning these active regions and a third character line forming the isolation structure are created; as well as A capacitor structure is formed on a portion of the first active region between the first character line and the third character line.

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