Display substrate and manufacturing method thereof, display panel, and display device

Abstract

The present disclosure provides a display substrate and a preparation method thereof, a display panel, and a display device. The display substrate provided by the embodiment of the present disclosure includes: a first base substrate; a plurality of scan lines, located on one side of the first base substrate, extending along a first direction and arranged along a second direction; the first direction and the second direction intersect; a plurality of data lines, located on the same side of the first base substrate as the scan lines and located on a different layer from the scan lines, extending along the second direction and arranged along the first direction; the plurality of scan lines and the plurality of data lines divide a plurality of sub-pixels; a common electrode layer, located on the side of the scan lines and the data lines away from the first base substrate; a first light shielding layer, in contact with the common electrode layer, including a plurality of first light shielding portions extending along the second direction; the first light shielding portions are located in the area between adjacent sub-pixels in the first direction.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, a display panel, and a display device. Background Art

[0002] Liquid Crystal Display (LCD) has attracted much attention in the industry due to its advantages such as small size, low power consumption, and no radiation. Due to the above advantages of LCD, most of the current high pixel density (PPI) virtual reality products use LCD technology. In order to provide a better immersive experience and reduce the screen door effect during VR use, the PPI of virtual reality products has been continuously improved. As the PPI continues to increase, the pixel pitch of display products has also been continuously compressed, and accordingly, the size of the black matrix has also been compressed. Affected by the process capabilities of the alignment equipment, when the alignment of the array substrate and the opposing substrate fluctuates, the black matrix cannot effectively block the light leakage of adjacent pixels, resulting in product color cross-talk, affecting the display effect and user experience. Summary of the Invention

[0003] An embodiment of the present disclosure provides a display substrate, the display substrate comprising:

[0004] a first substrate;

[0005] A plurality of scanning lines are located on one side of the first substrate, extending along a first direction and arranged along a second direction; the first direction and the second direction intersect;

[0006] A plurality of data lines are located on the same side of the first substrate as the scan lines and on different layers from the scan lines, extend along the second direction, and are arranged along the first direction; the plurality of scan lines and the plurality of data lines divide the plurality of sub-pixels;

[0007] The common electrode layer is located on a side of the scan lines and the data lines facing away from the first substrate;

[0008] The first light shielding layer contacts the common electrode layer and includes a plurality of first light shielding portions extending along the second direction; the first light shielding portions are located in the region between adjacent sub-pixels in the first direction.

[0009] In some embodiments, the orthographic projection of the data line on the first base substrate falls within the orthographic projection of the first light shielding portion on the first base substrate.

[0010] In some embodiments, the common electrode layer is located on a side of the first light shielding portion facing away from the first base substrate;

[0011] The orthographic projection of the first light shielding portion on the first base substrate falls within the orthographic projection of the common electrode layer on the first base substrate, and the common electrode layer covers the side surfaces of the first light shielding portion.

[0012] In some embodiments, the first light shielding portion is located on a side of the common electrode layer away from the first base substrate; an orthographic projection of the common electrode layer on the first base substrate and an orthographic projection of the first light shielding portion on the first base substrate have a substantially overlapping area.

[0013] In some embodiments, the common electrode layer includes: a groove group corresponding to each sub-pixel; the groove group includes at least one groove extending along the second direction and penetrating the thickness of the common electrode layer;

[0014] An orthographic projection of the first light shielding portion on the first base substrate and an orthographic projection of the groove on the first base substrate do not overlap with each other.

[0015] In some embodiments, when the first light shielding portion is located on a side of the common electrode layer away from the first base substrate, the groove group includes a plurality of grooves.

[0016] In some embodiments, when the common electrode layer is located on a side of the first light shielding portion facing away from the first base substrate, the groove group includes only one groove.

[0017] In some embodiments, the thickness of the first light shielding layer is greater than or equal to 300 angstroms and less than or equal to 1000 angstroms.

[0018] In some embodiments, the material of the first light-shielding layer includes molybdenum.

[0019] In some embodiments, the first light-shielding layer further includes a plurality of second light-shielding portions extending along the first direction; the second light-shielding portions are located between adjacent sub-pixels in the second direction.

[0020] In some embodiments, the display substrate further comprises:

[0021] The pixel electrode layer is located between the common electrode layer and the data line; the orthographic projection of the first light shielding portion on the first base substrate and the orthographic projection of the pixel electrode layer on the first base substrate do not overlap each other.

[0022] In some embodiments, the data line is located on a side of the scan line away from the first substrate;

[0023] The sub-pixel includes a thin film transistor; the gate of the thin film transistor is arranged in the same layer as the scan line and is electrically connected; the source of the thin film transistor is arranged in the same layer as the data line and is electrically connected; the drain of the thin film transistor is located on the side of the source away from the first substrate.

[0024] An embodiment of the present disclosure provides a method for preparing a display substrate, the method comprising:

[0025] A pattern of multiple scan lines and a pattern of multiple data lines are formed on one side of the first base substrate; the multiple scan lines extend along a first direction and are arranged along a second direction; the multiple data lines extend along the second direction and are arranged along the first direction; the first direction and the second direction intersect; the multiple scan lines and the multiple data lines divide a plurality of sub-pixels;

[0026] A pattern of a common electrode layer and a first light-shielding layer is formed on a side of a plurality of data lines and a plurality of scan lines away from the first base substrate; the first light-shielding portion is in contact with the common electrode layer, and the first light-shielding layer includes a plurality of first light-shielding portions extending along the second direction; the first light-shielding portions are located in an area between adjacent sub-pixels in the first direction.

[0027] In some embodiments, forming a pattern of a common electrode layer and a first light shielding layer on a side of the plurality of data lines and the plurality of scan lines facing away from the first base substrate specifically includes:

[0028] forming a common electrode layer on a side of the plurality of data lines and the plurality of scan lines away from the first base substrate;

[0029] forming a first light shielding layer on a side of the common electrode layer away from the pixel electrode layer;

[0030] The light shielding layer and the common electrode layer are processed by a graphic process to form a pattern of the first light shielding layer and a pattern of the common electrode layer.

[0031] In some embodiments, a patterning process is used to process the first light shielding layer and the common electrode layer to form a pattern of the first light shielding layer and a pattern of the common electrode layer, specifically including:

[0032] Coating photoresist on the side of the first light shielding layer away from the common electrode layer, and forming a first pattern through exposure and development processes;

[0033] forming a second pattern corresponding to the first pattern on the light shielding layer and the common electrode layer by an etching process;

[0034] Stripping the photoresist and performing an annealing process on the common electrode layer to crystallize the common electrode layer;

[0035] forming a photoresist on a side of the first light shielding layer away from the common electrode layer, and forming a third pattern by using an exposure and development process; the third pattern covers a portion of the first light shielding layer;

[0036] removing the first light shielding layer not covered by the third pattern by an etching process;

[0037] Remove the photoresist.

[0038] In some embodiments, forming a pattern of a common electrode layer and a first light shielding layer on a side of the plurality of data lines and the plurality of scan lines facing away from the first base substrate specifically includes:

[0039] forming a first light shielding layer on a side of the plurality of data lines and the plurality of scan lines away from the first base substrate, and forming a pattern of the first light shielding portion by a patterning process;

[0040] A common electrode layer is formed on a side of the first light shielding layer away from the plurality of data lines and the plurality of scanning lines, and a patterning process is adopted to form a pattern of the common electrode layer.

[0041] An embodiment of the present disclosure provides a display panel, comprising:

[0042] The display substrate provided by the embodiment of the present disclosure;

[0043] The opposite substrate is arranged opposite to the display substrate; it includes a second light shielding layer; the second light shielding layer includes a plurality of opening areas; the orthographic projection of the first light shielding layer on the first base substrate falls within the orthographic projection of the second light shielding layer on the first base substrate;

[0044] The liquid crystal layer is located between the opposite substrate and the display substrate.

[0045] A display device provided by an embodiment of the present disclosure includes the display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0048] Figure 2 The embodiment of the present disclosure provides Figure 1 Cross-sectional view of AA';

[0049] Figure 3 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0050] Figure 4 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0051] Figure 5 The embodiment of the present disclosure provides Figure 2 Cross-section of middle BB';

[0052] Figure 6 A schematic flow chart of a method for preparing a display substrate provided in an embodiment of the present disclosure;

[0053] Figure 7 A schematic flow chart of another method for preparing a display substrate provided in an embodiment of the present disclosure;

[0054] Figure 8 A schematic flow chart of another method for preparing a display substrate provided in an embodiment of the present disclosure;

[0055] Figure 9 A schematic structural diagram of a display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. And in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0057] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meaning understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0058] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the contents of this application. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0059] The present disclosure provides a display substrate, such as Figure 1 、 Figure 2 As shown, the display substrate includes:

[0060] A first substrate 1;

[0061] A plurality of scanning lines 6 are located on one side of the first base substrate 1, extending along a first direction X and arranged along a second direction Y; the first direction X and the second direction Y intersect;

[0062] A plurality of data lines 7 are located on the same side of the first base substrate 1 as the scan lines 6 and on different layers from the scan lines 7, extending along the second direction Y and arranged along the first direction X; the plurality of scan lines 6 and the plurality of data lines 7 divide a plurality of sub-pixels 8;

[0063] The common electrode layer 10 is located on a side of the scan line 6 and the data line 7 facing away from the first base substrate 1;

[0064] The first light shielding layer 5 contacts the common electrode layer 10 and includes a plurality of first light shielding portions 9 extending along the second direction Y. The first light shielding portions 9 are located in a region between adjacent sub-pixels 8 in the first direction Y.

[0065] In the display substrate provided by the embodiments of the present disclosure, a first light shielding portion is provided in the region between adjacent sub-pixels in a first direction. This first light shielding portion can block light leakage from adjacent sub-pixels, preventing crosstalk between adjacent sub-pixels in the first direction. This can improve display quality and enhance user experience.

[0066] It should be noted that Figure 1 In the example, the first direction X and the second direction Y are perpendicular to each other. Figure 2 for Figure 1 Cross-sectional view along line AA'.

[0067] It should be noted that in order to clearly show the relationship between the orthographic projections of the various film layers in the substrate, Figure 1 The pattern of the first light shielding layer and the pattern filling of the common electrode layer are not shown. Figure 1 The area surrounded by the dotted line represents the pattern of the first light shielding portion 9 , and the area surrounded by the solid line represents the pattern of the common electrode layer 10 .

[0068] In some embodiments, the display substrate has a pixel density (PPI) range greater than or equal to 800.

[0069] That is, the display substrate provided by the embodiment of the present disclosure can be applied to a high PPI display panel. The PPI of the display substrate can be, for example, 800 PPI to 1700 PPI.

[0070] It should be noted that the display substrate provided in the embodiments of the present disclosure can be applied to a liquid crystal display panel, which also includes a counter substrate disposed opposite the display substrate. The counter substrate includes, for example, a second base substrate, a second light-shielding layer on the side of the second base substrate facing the display substrate, and color resists. The second light-shielding layer has openings corresponding one-to-one to each sub-pixel, and the color resists are located within the openings. In a specific implementation, the display substrate and the counter substrate are aligned using a cell-to-cell process, but process conditions may cause alignment deviation between the display substrate and the counter substrate. For high-PPI display panels, the pixel pitch in the first direction is typically small, and the distance between sub-pixels is small. When the display substrate and the counter substrate are misaligned, the second light-shielding layer cannot effectively block light leakage from adjacent sub-pixels, which can easily lead to color crosstalk in the display product. In the display substrate provided in the embodiments of the present disclosure, since the first light-shielding portion is disposed between adjacent sub-pixels in the first direction, even if the display substrate and the counter substrate are misaligned, the first light-shielding portion can still block light leakage from adjacent sub-pixels, preventing crosstalk between adjacent sub-pixels in the first direction X.

[0071] In some embodiments, as Figure 3 As shown, the first light shielding layer 5 further includes a plurality of second light shielding portions 31 extending along the first direction X; the second light shielding portions 31 are located between adjacent sub-pixels 8 in the second direction Y. In other words, light shielding portions may be provided between adjacent sub-pixels in the second direction. In a specific implementation, when alignment deviation between the display substrate and the opposing substrate easily causes light leakage from adjacent sub-pixels in the second direction, second light shielding portions are provided between adjacent sub-pixels in the second direction to prevent crosstalk between adjacent sub-pixels in the second direction.

[0072] It should be noted that Figure 3 The common electrode layer is not shown in the figure. In order to clarify the relationship between the orthographic projections of the various film layers in the schematic display substrate, Figure 2 The area surrounded by the dotted line in FIG represents the pattern of the first light shielding portion 9 and the second light shielding portion 31.

[0073] In specific implementation, it can be as follows Figure 3 As shown, the first light shielding portion 9 is connected to the second light shielding portion 31. For example, the first light shielding portion and the second light shielding portion are connected as one body.

[0074] Alternatively, in a specific implementation, the first light shielding portion 9 and the second light shielding portion 31 may be disconnected from each other.

[0075] In some embodiments, the material of the first light-shielding layer includes light-shielding metal.

[0076] In a specific implementation, the common electrode layer is provided on the entire surface, that is, the regional common electrode layers corresponding to each sub-pixel are connected as a whole. Therefore, even if the common electrode layer contacts the first light-shielding layer, there will be no problem of electrode short circuit between different sub-pixels. Therefore, there is no need to set an insulating layer between the first light-shielding layer and the common electrode layer. While realizing that the first light-shielding layer blocks light leakage from adjacent sub-pixels, it can avoid increasing the thickness of the display substrate and avoiding increasing the production process of the display substrate.

[0077] In some embodiments, the material of the first light-shielding layer includes molybdenum.

[0078] In some embodiments, as Figure 1 、 Figure 2 As shown, the display substrate further includes:

[0079] The pixel electrode layer 4 is located between the common electrode layer 10 and the data line 7 ; the orthographic projection of the first light shielding portion 9 on the first base substrate 1 does not overlap with the orthographic projection of the pixel electrode layer 4 on the first base substrate 1 .

[0080] In specific implementation, Figure 1 、 Figure 2 As shown, the pixel electrode layer 4 includes a plurality of pixel electrodes 11. The pixel electrodes 11 correspond one to one with the sub-pixels 8. The orthographic projection of the pixel electrodes 11 on the first base substrate 1 falls within the sub-pixels 8.

[0081] In a specific implementation, for a high-PPI display substrate, due to the small pixel pitch, the distance between adjacent sub-pixels in the first direction is small to ensure the sub-pixel aperture ratio. Consequently, the distance between adjacent pixel electrodes in the first direction is also small. In the display substrate provided by the disclosed embodiments, the first light-shielding layer and the pixel electrode are located in different film layers. This not only blocks light leakage from adjacent sub-pixels, but also prevents the pixel electrode from short-circuiting due to being located in the same layer as the pixel electrode.

[0082] In some embodiments, when the first light-shielding layer further includes a second light-shielding portion, an orthographic projection of the second light-shielding portion on the first base substrate overlaps with an orthographic projection of the pixel electrode layer on the first base substrate.

[0083] In a specific implementation, both the pixel electrode layer and the common electrode layer are transparent electrode layers, and the material of the transparent electrode layer includes, for example, indium tin oxide (ITO).

[0084] In the display substrate provided by the embodiment of the present disclosure, the common electrode layer is located on the side of the pixel electrode layer facing away from the first base substrate, thereby improving the transmittance of the display substrate.

[0085] In some embodiments, as Figure 1 As shown, the orthographic projection of the data line 7 on the first base substrate overlaps with the orthographic projection of the first light shielding portion 9 on the first base substrate.

[0086] In some embodiments, as Figure 1 As shown, the orthographic projection of the data line 7 on the first substrate falls within the orthographic projection of the first light shielding portion 9 on the first substrate, that is, the first light shielding portion shields the data line.

[0087] In some embodiments, as Figure 1 、 Figure 2 、 Figure 4 、 Figure 5 As shown, the orthographic projection of the common electrode layer 10 on the first base substrate 1 covers the orthographic projection of the first light shielding portion 9 on the first base substrate 1 .

[0088] It should be noted that Figure 5 For example, it can be along Figure 4 Cross-sectional view of BB'.

[0089] In some embodiments, as Figure 2 As shown, the first light shielding portion 9 is located on the side of the common electrode layer 10 facing away from the first base substrate 1 .

[0090] Alternatively, in some embodiments, Figure 5 As shown, the common electrode layer 10 is located on a side of the first light shielding portion 9 facing away from the first base substrate 1 .

[0091] In some embodiments, as Figure 1 、 Figure 2 、 Figure 4 、 Figure 5 As shown, the common electrode layer 10 includes: a groove group 22 corresponding to each sub-pixel 8; the groove group 22 includes at least one groove 23 extending along the second direction Y and penetrating the thickness of the common electrode layer 10;

[0092] The orthographic projection of the first light shielding portion 9 on the first base substrate 1 and the orthographic projection of the groove 23 on the first base substrate 1 do not overlap with each other.

[0093] In some embodiments, Figure 1 、 Figure 2 As shown, when the first light shielding portion 9 is located on the side of the common electrode layer 10 away from the first base substrate 1 , the orthographic projection of the common electrode layer 10 on the first base substrate 1 and the orthographic projection of the first light shielding portion 9 on the first base substrate 1 have a substantially overlapping area.

[0094] It should be noted that the area where the orthographic projection of the common electrode layer on the first base substrate and the orthographic projection of the first light-shielding portion on the first base substrate have a substantial overlap means that within a reasonable process error range, the orthographic projection of the common electrode layer on the first base substrate and the orthographic projection of the first light-shielding portion on the first base substrate may have non-overlapping parts.

[0095] In some embodiments, as Figure 1 As shown, groove set 22 includes a plurality of grooves 23 . Figure 1 In the description, the groove group 22 including two grooves 23 is taken as an example.

[0096] In a specific implementation, when the groove group includes multiple grooves, the width between the grooves adjacent to and respectively located in two adjacent sub-pixels in the first direction is smaller, so that the width between the grooves adjacent to and respectively located in two adjacent sub-pixels in the first direction can be equal to the width of the first light shielding portion. When the first light shielding portion is located on the side of the common electrode layer facing away from the first base substrate, during the preparation process of the display substrate, the common electrode layer and the first light shielding layer can be formed in sequence before performing a patterning process. This can achieve self-alignment between the first light shielding layer and the common electrode, and there is no alignment offset between the first light shielding layer and the common electrode. This can improve the shielding effect of the first light shielding layer and avoid the problem of inconsistent transmittance caused by uneven opening areas corresponding to the common electrode grooves in adjacent sub-pixels. This can improve the optical effect of the display substrate and enhance the display effect.

[0097] Of course, in a specific implementation, when the groove group includes a plurality of grooves, the common electrode layer may also be located on a side of the first light shielding portion away from the first base substrate.

[0098] In some embodiments, as Figure 4 、 Figure 5 As shown, when the common electrode layer 10 is located on the side of the first light shielding portion 9 facing away from the first base substrate 1, the orthographic projection of the first light shielding portion 9 on the first base substrate 1 falls within the orthographic projection of the common electrode layer 10 on the first base substrate 1, and the common electrode layer 10 covers the side surface of the first light shielding portion.

[0099] In some embodiments, as Figure 4 As shown, groove set 22 includes only one groove 23 .

[0100] In the display substrate provided by the embodiments of the present disclosure, when the groove group includes only one groove, the width between adjacent grooves in the first direction is generally greater than the width between adjacent sub-pixels. That is, the width between adjacent grooves in the first direction is generally greater than the width of the first light shielding portion. In this case, the common electrode layer is located on the side of the first light shielding portion facing away from the first base substrate, allowing the common electrode layer to cover the first light shielding portion and its side surfaces. The patterning process of the common electrode layer does not damage the pattern of the first light shielding layer.

[0101] In some embodiments, the thickness of the first light shielding layer is greater than or equal to 300 angstroms and less than or equal to 1000 angstroms.

[0102] In some embodiments, as Figures 1 to 4 As shown, the data line 7 is located on the side of the scanning line 6 away from the first substrate 1;

[0103] The sub-pixel 8 includes a thin film transistor; the gate G of the thin film transistor is arranged on the same layer as the scanning line 6 and is electrically connected; the source S of the thin film transistor is arranged on the same layer as the data line 7 and is electrically connected; the drain D of the thin film transistor is located on the side of the source S away from the first base substrate 1; the drain D of the thin film transistor is electrically connected to the pixel electrode 11.

[0104] In the display substrate provided by the embodiment of the present disclosure, the drain electrode and the data line of the thin film transistor are arranged on different layers. In this way, even if the distance between the edge of the orthographic projection of the drain electrode on the first base substrate and the edge of the orthographic projection of the data line on the first base substrate is reduced, a short circuit between the drain electrode of the thin film transistor and the data line will not occur, which can simplify the design difficulty of the display substrate layout.

[0105] In specific implementation, the thin film transistor can be a bottom gate structure or a top gate structure. The following description takes the thin film transistor as an example of a top gate structure. In some embodiments, Figure 2 、 Figure 5 As shown, the display panel further includes: a third light-shielding layer 12 located between the first base substrate 1 and the gate G; a buffer layer 13 located between the third light-shielding layer 12 and the gate G; an active layer 14 located between the buffer layer 13 and the gate G; a gate insulating layer 15 located between the active layer 14 and the gate G; a first interlayer insulating layer 16 located between the gate G and the source S; a second interlayer insulating layer 17 located between the source S and the drain D; a planarizing layer 19 located between the drain D and the pixel electrode layer 4; and a passivation layer 20 located between the pixel electrode layer 4 and the common electrode layer 10. The third light-shielding layer 12 includes a pattern of multiple third light-shielding portions 21, and the orthographic projection of the active layer 14 on the first base substrate 1 falls within the orthographic projection of the third light-shielding portions 21 on the first base substrate. The source electrode S contacts the active layer 14 through a via hole penetrating the first interlayer insulating layer 16 and the gate insulating layer 15. The drain electrode D contacts the active layer 14 through a via hole penetrating the second interlayer insulating layer 17, the first interlayer insulating layer 16, and the gate insulating layer 15. The pixel electrode 11 contacts the drain electrode D through a via hole penetrating the planarization layer 19.

[0106] Based on the same inventive concept, the present disclosure also provides a method for preparing a display panel. Figure 6 Shown, including:

[0107] S101, forming a pattern of multiple scan lines and a pattern of multiple data lines on one side of a first substrate; the multiple scan lines extend along a first direction and are arranged along a second direction; the multiple data lines extend along the second direction and are arranged along the first direction; the first direction and the second direction intersect; the multiple scan lines and the multiple data lines divide a plurality of sub-pixels;

[0108] S102. A pattern of a common electrode layer and a first light-shielding layer is formed on a side of the plurality of data lines and the plurality of scan lines away from the first base substrate; the first light-shielding portion is in contact with the common electrode layer, and the first light-shielding layer includes a plurality of first light-shielding portions extending along the second direction; the first light-shielding portions are located in an area between adjacent sub-pixels in the first direction.

[0109] In some embodiments, before step S101 forms a pattern of multiple scan lines and a pattern of multiple data lines on one side of the first base substrate, the step further includes:

[0110] forming a pattern of a third light shielding layer on the first base substrate;

[0111] forming a buffer layer pattern on a side of the third light-shielding layer facing away from the first base substrate;

[0112] forming a pattern of an active layer on a side of the buffer layer away from the third light shielding layer;

[0113] forming a pattern of a gate insulating layer on a side of the active layer away from the third light shielding layer;

[0114] Step S101 forms a pattern of multiple scan lines and a pattern of multiple data lines on one side of a first base substrate, specifically comprising:

[0115] forming a first conductive layer on a side of the gate insulating layer away from the active layer, and forming a pattern of a scanning line and a pattern of a gate of a thin film transistor by a patterning process;

[0116] forming a pattern of a first interlayer insulating layer on a side of the first conductive layer facing away from the active layer;

[0117] A second conductive layer is formed on a side of the first interlayer insulating layer away from the first conductive layer, and a pattern of a data line and a pattern of a source electrode of a thin film transistor are formed by a graphic process.

[0118] In some embodiments, after forming a pattern of multiple scan lines and a pattern of multiple data lines on one side of the first base substrate, and before forming a pattern of a common electrode layer and a first light shielding layer on a side of the multiple data lines and the multiple scan lines facing away from the first base substrate, the method further includes:

[0119] forming a pattern of a second interlayer insulating layer on a side of the second conductive layer away from the first interlayer insulating layer;

[0120] forming a third conductive layer on a side of the second interlayer insulating layer away from the second conductive layer, and forming a pattern of a drain electrode of the thin film transistor by a patterning process;

[0121] forming a pattern of a planarization layer on a side of the third conductive layer facing away from the second interlayer insulating layer;

[0122] forming a pixel electrode layer on a side of the planarization layer away from the third conductive layer, and forming a pattern of the pixel electrode by a patterning process;

[0123] A pattern of a passivation layer is formed on a side of the pixel electrode away from the planarization layer.

[0124] In some embodiments, step S102 forms a pattern of a common electrode layer and a first light shielding layer on a side of the plurality of data lines and the plurality of scan lines facing away from the first base substrate, specifically comprising:

[0125] S1021, forming a common electrode layer on a side of the plurality of data lines and the plurality of scan lines facing away from the first base substrate;

[0126] S1022, forming a first light shielding layer on a side of the common electrode layer facing away from the first base substrate;

[0127] S1023 , processing the first light shielding layer and the common electrode layer by a patterning process to form a pattern of the first light shielding layer and a pattern of the common electrode layer.

[0128] In a specific implementation, forming a common electrode layer on a side of the plurality of data lines and the plurality of scan lines away from the first base substrate specifically includes:

[0129] A common electrode layer is formed on a side of the passivation layer away from the pixel electrode layer.

[0130] In some embodiments, as Figure 7 As shown, step S1023 uses a patterning process to process the first light shielding layer and the common electrode layer to form a pattern of the first light shielding layer and a pattern of the common electrode layer, specifically including:

[0131] S1023-1, coating a photoresist 24 on the side of the first light shielding layer 5 facing away from the common electrode layer 10, and forming a first pattern 25 by exposure and development processes;

[0132] S1023-2, forming a second pattern corresponding to the first pattern 25 on the first light shielding layer 5 and the common electrode layer 10 by an etching process;

[0133] S1023-3, stripping the photoresist 24, and performing an annealing process on the common electrode layer 10 to crystallize the common electrode layer 10;

[0134] S1023-4, forming a photoresist 24 on the side of the first light shielding layer 5 away from the common electrode layer 10, and forming a third pattern 26 by exposure and development processes; the third pattern 26 covers a portion of the first light shielding layer 5;

[0135] S1023-5, removing the first light shielding layer 5 not covered by the third pattern 26 by an etching process;

[0136] S1023-6. Remove the photoresist 24.

[0137] The method for preparing a display substrate provided by the embodiment of the present disclosure sequentially forms a common electrode layer and a first light-shielding layer before performing a patterning process. This can achieve self-alignment between the first light-shielding layer and the common electrode, eliminating alignment offset between the first light-shielding layer and the common electrode. This can improve the shielding effect of the first light-shielding layer and avoid the problem of inconsistent transmittance caused by uneven opening areas corresponding to common electrode grooves in adjacent sub-pixels. This can improve the optical effect of the display substrate and the display effect. Furthermore, after forming the second pattern and glass photoresist, the common electrode layer is annealed to crystallize the common electrode layer. In this way, when the first light-shielding layer not covered by the third pattern is subsequently removed by an etching process, the crystallized common electrode layer will not be removed, thereby avoiding damage to the common electrode layer.

[0138] It should be noted that, in a specific implementation, when the material of the common electrode layer includes ITO and the material of the first light-shielding layer includes molybdenum, the etching process is, for example, a wet etching process, and conventional etching solutions for ITO and molybdenum both contain nitric acid components, and conventional etching solutions for ITO can be used to complete the synchronous etching of the first light-shielding layer and the common electrode layer. Conventional etching solutions for ITO include nitric acid (HNO3), acetic acid (CH3COOH), and phosphoric acid (H3PO4). After the common electrode layer is subjected to an annealing process, a conventional etching solution for molybdenum can be used to remove the first light-shielding layer that is not covered by the third pattern, and the crystallized common electrode layer will not be etched by the conventional etching solution for molybdenum. Conventional etching solutions for molybdenum include HNO3 and sulfuric acid (H2SO4).

[0139] It should be noted that if Figure 7 As shown, the common electrode layer 10 is patterned to form a groove 23. Figure 7 In the figure, the groove group 22 includes two grooves 23 as an example for illustration.

[0140] In specific implementation, Figure 7 As shown, the third pattern 26 formed in step S1023 - 4 also covers the side surface of the first light shielding layer 5 , thereby preventing the side surface of the first light shielding layer that needs to be retained from being etched.

[0141] In some embodiments, step S102 forms a pattern of a common electrode layer and a first light shielding layer on a side of the plurality of data lines and the plurality of scan lines facing away from the first base substrate, specifically comprising:

[0142] S1021′, forming a first light shielding layer on a side of the plurality of data lines and the plurality of scan lines away from the first base substrate, and forming a pattern of the first light shielding portion by a patterning process;

[0143] S1022′: forming a common electrode layer on a side of the first light shielding layer away from the plurality of data lines and the plurality of scan lines, and forming a pattern of the common electrode layer by using a patterning process.

[0144] In specific implementation, Figure 8 As shown, a first light shielding layer is formed on the side of the plurality of data lines and the plurality of scan lines away from the first base substrate, and a patterning process is used to form a pattern of the first light shielding portion, specifically including:

[0145] S1021'-1: forming a first light shielding layer 5 on the side of the passivation layer 20 away from the pixel electrode layer, and forming a photoresist 24 on the side of the first light shielding layer 5 away from the passivation layer 20, and forming a pattern of the photoresist 24 by exposure and development processes;

[0146] S1021′-2, etching the first light shielding layer 5 using an etching process to form a pattern of the first light shielding portion 9;

[0147] S1021'-3, stripping the photoresist 24;

[0148] A common electrode layer is formed on a side of the first light shielding layer away from the plurality of data lines and the plurality of scan lines, and a patterning process is used to form a pattern of the common electrode layer, specifically including:

[0149] S1022′-1, forming a common electrode layer 10 on a side of the first light shielding layer 5 away from the passivation layer 20, and forming a photoresist 24 on a side of the common electrode layer 10 away from the first light shielding layer 5, and forming a pattern of the photoresist 24 by exposure and development processes;

[0150] S1022'-2, etching the common electrode layer 10 using an etching process to form a pattern of the common electrode layer 10;

[0151] S1022′-3, stripping the photoresist 24.

[0152] It should be noted that if Figure 8 As shown, the common electrode layer 10 is patterned to form a groove 23. Figure 8 In the figure, the groove group 22 includes one groove 23 as an example for illustration.

[0153] In the method for preparing a display substrate provided by an embodiment of the present disclosure, when the width between adjacent grooves in the first direction is greater than the width of the first light-shielding portion, the pattern of the first light-shielding portion is first formed, and then the pattern of the common electrode layer is formed. The common electrode layer covers the first light-shielding portion and its sides, and the patterning process of the common electrode layer will not cause damage to the pattern of the first light-shielding layer.

[0154] The embodiment of the present disclosure provides a display panel, such as Figure 9 Shown, including:

[0155] The display substrate 2 provided in the embodiment of the present disclosure;

[0156] The opposite substrate 3 is disposed opposite to the display substrate 2; it includes a second light shielding layer 18; the second light shielding layer 18 includes a plurality of opening areas 27; the orthographic projection of the first light shielding layer 9 on the first base substrate falls within the orthographic projection of the second light shielding layer 18 on the first base substrate;

[0157] The liquid crystal layer 28 is located between the counter substrate 3 and the display substrate 2 .

[0158] The display panel provided by the embodiments of the present disclosure includes a display substrate in which a first light shielding portion is provided in the region between adjacent sub-pixels in a first direction, and an opposing substrate includes a second light shielding layer. The first light shielding layer and the second light shielding layer provide dual shielding, thereby improving shielding between sub-pixels and preventing crosstalk between adjacent sub-pixels in the first direction. This can enhance display quality and user experience.

[0159] In some embodiments, as Figure 9 As shown, the counter substrate 3 further includes a second base substrate 29 and color resists 30 . The second light shielding layer 18 is located on the side of the second base substrate 29 facing the liquid crystal layer 28 , and the color resists 30 are located in the opening area 27 .

[0160] In a specific implementation, the opening area of ​​the second light-shielding layer corresponds one-to-one with the sub-pixels, and the opening area of ​​the second light-shielding layer is the opening area of ​​the sub-pixel. The sub-pixels include, for example, a red sub-pixel, a blue sub-pixel, and a green sub-pixel. The color resist includes a red color resist located in the red sub-pixel, a blue color resist located in the blue sub-pixel, and a green color resist located in the green sub-pixel.

[0161] Next, taking the example of a groove group in the common electrode layer including only one groove, the color crosstalk of the display panel provided by the embodiment of the present disclosure and the display panel in the related art where the first light shielding layer is not provided on the display substrate are compared. In the first direction, the pixel pitch is 6.0 microns, the data line width is 1.4 microns, the width of the second light shielding layer is 2.5 microns, the width between adjacent grooves is 3.5 microns, and the width of the pixel electrode is 3.5 microns. The color difference comparison of the display panel a1 provided with the first light shielding layer and the display panel a2 not provided with the first light shielding layer is shown in Table 1. The color crosstalk of display products is generally marked as a color difference △uv less than 0.015. According to Table 1, it can be seen that in the display panel a2 in the related art where the first light shielding layer is not provided on the display substrate, each sub-pixel does not meet the color crosstalk standard, and each sub-pixel in the display panel a1 provided with the first light shielding layer meets the color crosstalk standard. The display panel provided by the embodiment of the present disclosure can significantly improve the color crosstalk of the display panel and improve the display effect.

[0162] Table 1

[0163] sub-pixel Color difference of display panel a1 Color difference of display panel a2 Red sub-pixel 0.014 0.033 Green sub-pixel 0.002 0.035 Blue sub-pixel 0.006 0.016

[0164] A display device provided by an embodiment of the present disclosure includes the display panel provided by an embodiment of the present disclosure.

[0165] In some embodiments, the display device further includes a backlight module; the display panel is located on the light-emitting side of the backlight module.

[0166] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the aforementioned embodiments of the display substrate and display panel, and any repetitive details will not be repeated.

[0167] In summary, the display substrate and its manufacturing method, display panel, and display device provided by the embodiments of the present disclosure include a first light shielding portion disposed between adjacent sub-pixels in a first direction. This first light shielding portion can block light leakage from adjacent sub-pixels, preventing crosstalk between adjacent sub-pixels in the first direction. This can improve display quality and enhance user experience.

[0168] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0169] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display panel, wherein: The display panel includes: display substrate; an opposite substrate, arranged opposite to the display substrate; a liquid crystal layer, located between the counter substrate and the display substrate; The display substrate comprises: a first substrate; A plurality of scanning lines are located on one side of the first substrate, extending along a first direction and arranged along a second direction; the first direction and the second direction intersect; a plurality of data lines, located on the same side of the first substrate as the scan lines and on different layers from the scan lines, extending along the second direction and arranged along the first direction; the plurality of scan lines and the plurality of data lines dividing a plurality of sub-pixels; a common electrode layer, located on a side of the scan line and the data line facing away from the first substrate; a first light shielding layer, contacting the common electrode layer, and comprising a plurality of first light shielding portions extending along the second direction; the first light shielding portions being located in a region between the adjacent sub-pixels in the first direction; The common electrode layer is located on a side of the first light shielding portion facing away from the first base substrate; The orthographic projection of the first light shielding portion on the first base substrate falls within the orthographic projection of the common electrode layer on the first base substrate, and the common electrode layer covers the side surface of the first light shielding portion; The display substrate further includes: a pixel electrode layer, wherein an orthographic projection of the first light shielding portion on the first base substrate and an orthographic projection of the pixel electrode layer on the first base substrate do not overlap with each other; The data line is located on a side of the scan line away from the first substrate; The sub-pixel includes a thin film transistor; the gate of the thin film transistor is provided in the same layer as the scan line and is electrically connected; the source of the thin film transistor is provided in the same layer as the data line and is electrically connected; the drain of the thin film transistor is located on a side of the source away from the first substrate; The thickness of the first light shielding layer is greater than or equal to 300 angstroms and less than or equal to 1000 angstroms; The counter substrate includes a second light-shielding layer; the second light-shielding layer includes a plurality of opening areas; the orthographic projection of the first light-shielding layer on the first base substrate falls within the orthographic projection of the second light-shielding layer on the first base substrate; The material of the first light-shielding layer includes light-shielding metal.

2. The display panel according to claim 1, wherein An orthographic projection of the data line on the first base substrate falls within an orthographic projection of the first light shielding portion on the first base substrate.

3. The display panel according to claim 1 or 2, wherein: The common electrode layer comprises: a groove group corresponding to each of the sub-pixels; the groove group comprises at least one groove extending along the second direction and penetrating the thickness of the common electrode layer; An orthographic projection of the first light shielding portion on the first base substrate and an orthographic projection of the groove on the first base substrate do not overlap with each other.

4. The display panel according to claim 3, wherein: When the common electrode layer is located on a side of the first light shielding portion away from the first base substrate, the groove group includes only one groove.

5. The display panel according to any one of claims 1 to 2, wherein: The material of the first light shielding layer includes molybdenum.

6. The display panel according to any one of claims 1 to 2, wherein: The first light shielding layer further includes a plurality of second light shielding portions extending along the first direction; the second light shielding portions are located between adjacent sub-pixels in the second direction.

7. The display panel according to any one of claims 1 to 2, wherein: The pixel electrode layer is located between the common electrode layer and the data line.

8. A method for preparing a display substrate, wherein: The method comprises: A pattern of multiple scan lines and a pattern of multiple data lines are formed on one side of a first base substrate; the multiple scan lines extend along a first direction and are arranged along a second direction; the multiple data lines extend along the second direction and are arranged along the first direction; the first direction and the second direction intersect; the multiple scan lines and the multiple data lines divide a plurality of sub-pixels; A pattern of a common electrode layer and a first light shielding layer is formed on a side of the plurality of data lines and the plurality of scan lines away from the first base substrate; the first light shielding layer is in contact with the common electrode layer, and the first light shielding layer includes a plurality of first light shielding portions extending along the second direction; the first light shielding portions are located in a region between the adjacent sub-pixels in the first direction; Also includes: forming a pixel electrode layer; Wherein, the common electrode layer is located on a side of the first light shielding portion away from the first base substrate; The orthographic projection of the first light-shielding portion on the first substrate falls within the orthographic projection of the common electrode layer on the first substrate, and the common electrode layer covers a side surface of the first light-shielding portion; the data line is located on a side of the scan line away from the first substrate; the sub-pixel includes a thin film transistor; the orthographic projection of the first light-shielding portion on the first substrate and the orthographic projection of the pixel electrode layer on the first substrate do not overlap with each other; the gate of the thin film transistor is provided on the same layer as the scan line and is electrically connected; the source of the thin film transistor is provided on the same layer as the data line and is electrically connected; the drain of the thin film transistor is located on a side of the source away from the first substrate; The thickness of the first light-shielding layer is greater than or equal to 300 angstroms and less than or equal to 1000 angstroms; the orthographic projection of the first light-shielding layer on the first base substrate falls within the orthographic projection of the second light-shielding layer of the opposite substrate corresponding to the display substrate on the first base substrate.

9. The method according to claim 8, wherein The method further comprises forming a pattern of a common electrode layer and a first light shielding layer on a side of the plurality of data lines and the plurality of scan lines facing away from the first base substrate, specifically comprising: forming a first light shielding layer on a side of the plurality of data lines and the plurality of scan lines away from the first base substrate, and forming a pattern of the first light shielding portion by a patterning process; The common electrode layer is formed on a side of the first light shielding layer away from the plurality of data lines and the plurality of scan lines, and a patterning process is used to form a pattern of the common electrode layer.

10. A display device, wherein: The display panel comprises the display panel according to any one of claims 1 to 7.

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